JP2002083784A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally the interval of semiconductor chips will not become completely uniform, when a sheet is extended after dicing in a conventional address system, deviation occurs between an address in MPC, and the position of the chip after dicing and this deviation becomes greater as the chip becomes fine, in an address system for selecting and assembling the chip of a requested rank in the case of assembly. SOLUTION: By providing a large number of alignment target chips on a wafer, even if the position deviation occurs after dicing, the position is corrected and mapping data are re-prepared. Since characteristic data and the semiconductor chip can be made to correspond exactly, even in the case of fine chip, the required characteristic rank can be selected and assembled by the address system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device capable of accurately associating characteristic data with individual semiconductor elements by providing a large number of target chips for position correction on a wafer. The present invention relates to a device manufacturing method.

[0002]

2. Description of the Related Art In a manufacturing process of a semiconductor device, a semiconductor element on a wafer on which a pattern has been formed is processed by a process.
The electrical characteristics are measured using a bar. There are a marking method and an address method as a method of measuring the semiconductor chip on the wafer.

[0003] In the marking method, the electrical characteristics of each semiconductor chip formed on a wafer are measured by MPC, and good / defective is determined based on a required characteristic rank. This is a marking method.
Since wafers with many required ranks (non-defective products) are delivered to the assembling process, and only unmarked semiconductor chips are assembled, wafer out due to hFE rank deviation or out-of-rank defect in the wafer occurs, resulting in low yield. The drop was a problem.

On the other hand, in the address method, each semiconductor chip on a wafer on which ID data is printed is measured by MPC, the obtained characteristic data and the position data of the semiconductor chip are managed and transferred to an assembling process, and the ID data is transferred. This is a method in which characteristic data can be obtained for each wafer and each chip by recognizing it. As a result, only semiconductor chips having necessary characteristic data can be selected at the time of assembling, so that man-hours can be reduced by eliminating marking of defective chips, and reduction in yield due to rank shift failure can be prevented.

FIGS. 4 and 6 show a method of manufacturing a semiconductor device in which measurement is performed by the address method.

FIG. 4 shows the wafer after pattern formation.
The wafer 11 is laser-marked with a wafer ID before pattern formation. Further, in order to make the electrical characteristics of the individual semiconductor chips 13 correspond to the position data, the wafer 11
An alignment target chip 15 is provided thereon. Since this alignment target chip 15 is also used for mask alignment, usually two alignment target chips 15 are formed.

FIG. 5 shows a semiconductor chip based on the address method.
13 check processes are shown. The wafer ID 12 printed on the orientation flat portion of the wafer 11 and the chip ID 14 of each semiconductor chip 13 are recorded in the order of measurement. Then the probe needle 17
In contact with the electrode pads of each semiconductor chip 13. In this state, a pre-programmed input signal waveform is input from the input electrode pad, a constant signal waveform output from the output terminal is read by a tester, and the inspection result and the position data of the semiconductor chip 13 are assembled as map data. Deliver to the process. As map data, for example, wafer I
In the case of D12, chip ID14, good or bad, and good product, the characteristic rank is managed. Also, alignment target chip
It is noted that 15 is an alignment target chip.

Also, the measurement results of the entire wafer 11 are managed as data such as rank yield, yield, and the defect rate of each defect. Further, no defective product is marked on the wafer 11, and the wafer 11 is transferred to the assembly process together with the measurement data.

FIG. 6 shows a semiconductor chip diced in the assembling process. Individual semiconductor chips 13 after dicing
In order to facilitate vacuum chucking, the sheet 16 on the back surface of the wafer 11 is stretched and cut off so that there is a gap between the individual semiconductor chips 13. Only the semiconductor chips 13 of a required rank are die-bonded by a vacuum chuck in accordance with the transferred data and individually assembled.

[0010]

In the conventional method of manufacturing a semiconductor device by the address method, when the sheet 16 on the back surface of the wafer 11 is stretched after dicing, the intervals between the semiconductor chips 13 are not completely equal. Furthermore, since there are only two alignment target chips 15, there is a deviation from the address data at the time of MPC measurement. In the case of a microchip such as a transistor, the influence of the variation in the chip interval is large, and there has been a problem that the position of the semiconductor chip 13 on the wafer and the managed position data and characteristic data cannot be accurately corresponded.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and individually measures semiconductor elements patterned on a wafer, and obtains characteristic data obtained and the individual semiconductor elements. In a method for manufacturing a semiconductor device in which element position data is managed and assembled according to characteristics after dicing, three or more target chips are provided on the wafer. Thereby, the difference between the position data of the target chip at the time of MPC and the position after dicing is recognized, and correction is made based on the data to re-create the map data on the wafer, thereby obtaining the characteristic data and the position data and the chip on the wafer. And a method of manufacturing a semiconductor device that can accurately correspond to the position of the semiconductor device.

[0012]

Embodiments of the present invention will be described below in detail.

[0013] A method of manufacturing a semiconductor device comprises the steps of individually measuring semiconductor elements pattern-formed on a wafer, managing the obtained characteristic data and the position data of the individual semiconductor elements, and assembling the semiconductor elements according to characteristics after dicing. In the above method, three or more target chips are provided on the wafer.

FIG. 1 shows a wafer after pattern formation, which is a feature of the present invention. The wafer ID2 is laser-marked on the orientation flat portion of the wafer 1 before pattern formation. Further, a chip ID 4 is assigned to each semiconductor chip 3.

On the wafer 1, the electrical characteristics and the position data of the semiconductor chip 3 and the wafer 1 of the semiconductor chip 3
A number of alignment target chips 5 are provided to correspond the upper positions. The number of the alignment target chips 5 is about 0.1% of the theoretical wafer yield. For example, if the theoretical yield is 30,000, the number of alignment target chips 5 is about 30.

Thus, even if the intervals between the semiconductor chips 3 are not uniform when the sheet is stretched after dicing, M
The deviation between the position of the alignment target chip 5 at the time of PC and the position after dicing can be recognized, and correction can be performed based on the data to re-create the map on the wafer 1.

FIG. 2 shows a step of checking a semiconductor chip by an address method. First, a wafer ID 2 serving as an index of data to be managed and a semiconductor chip ID 4 of each semiconductor chip 3 are recorded in a measurement order on a recording medium such as a floppy (registered trademark) disk for data transfer. Thereafter, the probe needle 7 is brought into contact with the electrode pad of each semiconductor chip 3. In this state, a pre-programmed input signal waveform is input from the input electrode pad, and a constant signal waveform output from the output terminal is read by the tester.

The inspection result and the position data of the semiconductor chip 3 are recorded as map data and delivered to the assembling process.
As the map data, for example, wafer ID2, chip I
D4, good or bad, in the case of non-defective product to manage, such as characteristic ranks of such VCBO and h _FE. In addition, it is made to recognize that the alignment target chip 5 is an alignment target chip.

The measurement result of the entire wafer 1 also manages the rank yield, the yield, the defect rate of each defect, and the like as data. Further, the wafer 1 is not marked with a defective product, and all the wafers 1 are transferred to the assembling process together with the measurement data.

FIG. 6 shows a semiconductor chip diced in the assembling process. Individual semiconductor chips 3 after dicing
In order to facilitate vacuum chucking, the sheet 5 on the back surface of the wafer 1 is stretched and separated so as to leave a gap between the individual semiconductor chips 3. At this time, the intervals between the chips 3 are not completely equal, which may cause deviation from the mapping data at the time of MPC. However, a large number of alignment target chips 5 (about 0.1% of the theoretical wafer yield) must be provided. Accordingly, position correction becomes possible, and even in the case of a microchip such as a transistor, the managed position data and characteristic data can accurately correspond to the position of the semiconductor chip 3 on the wafer 1.

First, the transferred management data is read, and the wafer ID 2, the chip ID 4, and the characteristic data of the chip 3 are recognized. When data of a required rank is given at the time of die bonding, only chips 3 of that rank are selected and assembled. The position of the alignment target chip 5 is confirmed by the pattern recognition camera, the deviation between the position of the target chip at the time of MPC and the position after dicing is recognized, and correction is made based on the data to re-create the map on the wafer 1.

As a result, the position data and characteristic data of each semiconductor chip 3 and the position of the chip 3 on the wafer 1 can accurately correspond to each other.
Only the semiconductor chips 3 are assembled by die bonding using a vacuum chuck.

A feature of the present invention resides in that a number of alignment target chips 5 are formed on the wafer 1. Thus, even if the distance between the chips 3 is not uniform due to the stretching of the sheet 6 on the back surface of the wafer 1 after the dicing, the position of the alignment target chip 5 is confirmed by the pattern recognition camera, and the position of the target chip at the time of MPC and after the dicing , And a correction can be made based on the data to recreate the map on the wafer 1. This results in individual semiconductor chips 3
Position data and characteristic data can accurately correspond to the position of the semiconductor chip 3 on the wafer 1, so that even a small chip that has been difficult in the past, only a chip of a required rank is assembled by an address method. It becomes possible.

As a result, it is possible to significantly reduce wafer outs and out-of-rank defects in the wafer, and to reduce man-hours by eliminating marking.

Further, by managing data of individual chips, production control and quality control can be easily performed.

[0026]

According to the present invention, there is provided a method for forming a large number of alignment target chips on a wafer.
This enables the pattern recognition camera to confirm the position of the alignment target chip even if the chip spacing is not uniform due to the stretching of the sheet after dicing.
The deviation between the position of the target chip at the time of MPC and the position after dicing is recognized, and a correction can be made based on the data to recreate a map on the wafer. As a result, the position data and characteristic data of each semiconductor chip can accurately correspond to the position of the semiconductor chip on the wafer. Can be assembled only.

As a result, it is possible to significantly reduce wafer outs and out-of-rank defects in the wafer, and to reduce the number of steps by eliminating marking.

Further, by managing data of individual chips, production control and quality control can be easily performed.

[Brief description of the drawings]

FIG. 1 is a top view for explaining a manufacturing method of the present invention.

FIG. 2 is a top view for explaining the manufacturing method of the present invention.

FIG. 3 is a top view for explaining the manufacturing method of the present invention.

FIG. 4 is a top view for explaining a conventional manufacturing method.

FIG. 5 is a top view for explaining a conventional manufacturing method.

FIG. 6 is a top view for explaining a conventional manufacturing method.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: individually measuring semiconductor elements patterned on a wafer; managing obtained characteristic data and position data of the individual semiconductor elements; and assembling according to characteristics after dicing. A method for manufacturing a semiconductor device, comprising providing three or more target chips on the wafer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the position data of each of the semiconductor elements is accurately corrected by performing position correction using the target chip.