JP2945488B2 - Lead frame and semiconductor device burn-in method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and, more particularly, to a lead frame for performing burn-in during a semiconductor device manufacturing process.

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated and higher in density, they have become larger and have finer patterns. Therefore, burn-in execution has become an essential condition for removing the initial failure mode, and it is desired that burn-in execution can be easily performed. Therefore, it is necessary to perform burn-in not during the completion of the semiconductor device but during the manufacturing process.

[0003]

2. Description of the Related Art In general, burn-in of a semiconductor device involves applying time and stress to obtain a quality and reliability level of a finished product, and a semiconductor device having an inherent defect or a device causing a failure due to manufacturing variations. Implemented to eliminate.

In the conventional burn-in, a signal or a power supply voltage is applied to each package in a state of a finished product. For this purpose, a burn-in board having a socket and wiring on a printed board is used. That is, the semiconductor device is mounted on the socket of the burn-in board, a signal and a power supply voltage are applied, and the burn-in operation is performed under a high temperature condition.

[0005]

However, when performing burn-in in a completed state of a semiconductor device, it is necessary to develop a socket suitable for a package, to prepare a burn-in board (printed board), and to prepare a burn-in device. In particular, the development of sockets must be performed for each package outline. For the same type of gate array or the like that requires various packages, it is necessary to develop each socket and each burn-in board, which requires time and cost. There is a problem that requires.

The present invention has been made in view of the above problems, and has as its object to provide a lead frame that performs burn-in in an unfinished state to reduce time and cost. Another object of the present invention is to provide a burn-in method using the lead frame.

[0007]

The object of the present invention is to provide a lead frame in which a resistance member is interposed at a predetermined intermediate position between the outer leads, or an insulating material having a thickness smaller than the outer lead at a predetermined intermediate position between the outer leads. The problem can be solved by using a lead frame provided with a member and a resistance member adjacent to each other, mounting the semiconductor device on the lead frame, performing packaging, and then using the exposed outer leads for burn-in.

[0008]

As described above, the resistance member is interposed between the predetermined outer leads. That is, the burn-in of the power supply system and the signal system is performed by applying a voltage to the support frame with the resistance member interposed between the external leads other than the power supply.

An insulating member and a resistance member having a thickness smaller than that of the outer lead are provided adjacent to an intermediate position of the predetermined outer lead. Then, by cutting a predetermined position of the outer lead, the voltage applied to the support frame can be applied directly to the power supply lead, or can be insulated with an insulating member interposed, or a signal system can be interposed with a resistive member. Burn-in is performed by selecting whether to apply a signal level voltage to the lead.

Therefore, it is possible to perform burn-in in an unfinished state of the semiconductor device before cutting the outer leads from the support frame, thereby eliminating the need for a socket or the like and reducing burn-in time and cost. .

[0011]

FIG. 1 shows a configuration diagram of a first embodiment of the present invention. The lead frame 1 in FIG.
The same package 3 is connected in a straight line direction in units of several to several hundreds between b. Although not shown, the package 3 is formed by mounting a chip on a die pad of the lead frame 1, connecting the chip and inner leads by wire bonding, and performing resin molding.

A predetermined number of outer leads 4 exposed by packaging are integrally formed on the support frames 2a and 2b. In this case, the insulating member 5 is interposed at a predetermined position of the outer lead 4 extending from terminals other than the positive power supply terminal + V and the negative power supply terminal -V of the package 3 in the outer lead 4 group. That is, the burn-in target is determined by whether or not the corresponding outer lead 4 is made conductive depending on whether or not the insulating member 5 is interposed.

In such an unfinished semiconductor device, a positive power supply voltage is applied to the support frame 2a, a negative power supply voltage is applied to the support frame 2b, and the semiconductor device is left in a high-temperature atmosphere. ) Burn-in is performed. In this case, only the power supply terminals + V and -V are driven, and the other terminals are in an electrically floating state. Therefore, a semiconductor device that performs such burn-in is not affected by static electricity or the like. Selected.

Therefore, in the semiconductor device affected by static electricity or the like, burn-in is performed by interposing the resistance member 6 instead of the insulating member 5 interposed between the outer leads 4. That is, burn-in is performed by always applying a positive or negative level to terminals other than the power supply terminals + V and -V. Such burn-in is for forming the lead frame 1 in a unique pattern, and is performed for a highly versatile semiconductor device common to power supplies. Note that the resistance value of the resistance member 6 is appropriately set according to the characteristics of the semiconductor device performing the burn-in.

Here, the insulating member 5 or the resistance member 6 interposed between the outer leads 4 is provided with a conductive adhesive at a portion where a predetermined position of the predetermined outer lead 4 is punched with a predetermined width by press working after packaging. It is made to adhere by. Note that the insulating member 5 or the resistance member 6 may be interposed in the outer lead 4 by photo etching or the like. After the burn-in is completed, the non-defective products are replaced with broken lines A ₁ and A ₂
The semiconductor device is completed by cutting the outer leads 4 at the portions. Next, FIG. 2 shows a configuration diagram of a second embodiment of the present invention. The semiconductor device shown in FIG. 2 is mainly for performing burn-in for each product requiring a high level, a low level, and a power supply voltage by a terminal.

FIGS. 2A and 2B are diagrams showing the configuration of a second embodiment of the present invention, and FIG. 2B is a broken line of B and B 'in FIG. 2A. FIG. 3 is a sectional view of the outer lead 4 in the section shown. In the lead frame 1 shown in FIGS. 2A and 2B, an insulating member 5a having a thickness smaller than that of the outer lead 4 is provided at an intermediate position between the outer leads 4 as shown in FIG. The resistance member 6a is interposed adjacent to the outer lead 4 in the length direction. The outer lead 4a is connected to the support frame 10a, and the outer lead 4b is connected to the support frame 1a.
0b. That is, the support frames 10a and 10b
Has a structure in which the insulating member 5a is sandwiched vertically. Further, the outer leads 4a and 4b and the support frames 10a and 1
An insulating member 5a is interposed between Ob (or 10c and 10d) to maintain electrical insulation. Here, FIG.
The structure of the outer lead 4 shown in (B) is formed, for example, as follows. First, after a film is formed by a vapor deposition method (for example, a vacuum deposition method, a physical vapor deposition method or a chemical vapor deposition method), patterning by photoetching is performed to form the outer leads 4a and the support frame 10a ( Or 10c)
Are simultaneously formed. Next, a metal oxide film is grown on the surfaces of the outer leads 4a and the support frame 10a by annealing, or an insulating layer is formed by a vapor phase growth method, and then patterned by photoetching to form an insulating member 5a.
Is formed at a predetermined position in FIG. 2B, that is, at a portion of the outer lead 4a facing the outer lead 4b and on the surface of the support frame 10a. Subsequently, similarly, a resistive member 6a is formed at a predetermined position in FIG. 2B by film formation by a vapor deposition method and patterning by photoetching. Finally, the outer leads 4b and the support frame 10b (or 10d) are formed by film formation by a vapor phase growth method and patterning by photoetching to form outer leads 4a whose surfaces are partially covered with an insulating member and a resistance member, and 2B by simultaneously forming the support frame 10a whose surface is covered with an insulating member.
Can be obtained.

FIG. 3 is a diagram for explaining the outer leads shown in FIG. Here, a positive power supply voltage + V is applied to the outer lead 4a divided by the insulating member 5a, and a negative power supply voltage -V is applied to the outer lead 4b. First, based on the capabilities of the package 3 terminals, when applying a positive supply voltage + V to the terminal disconnects the outer leads 4b of the lateral portion C ₁ of the insulating member 5a. As a result, the positive power supply voltage + V is directly applied to the terminal (see FIG. 3).
(A)). Further, in the case of applying a negative power supply voltage -V is by cutting the lateral portion C ₂ of the insulating member 5a of the outer leads 4a, a negative power supply voltage -V is applied directly to the terminals (FIG. 3 (B)).

Meanwhile, in the case of applying a positive level to the terminal, as well as to cut the horizontal portion C ₃ of the resistance member 6a of the outer leads 4a, cutting the transverse portion C ₄ of the insulating member 5a of the outer leads 4b As a result, a positive power supply voltage + V is applied to the terminal via the resistance member 6a at a predetermined level (FIG. 3).
(C)). Further, in the case of applying a negative level to the terminal, as well as to cut the horizontal portion C ₅ of the insulating member 5a of the outer leads 4a, by cutting the lateral portions C ₆ of the resistance member 6a of the outer leads 4b, the A negative power supply voltage -V is applied to the terminal at a predetermined level via the resistance member 6a (FIG. 3D).

That is, by appropriately setting the cutting position, the positive or negative power supply voltage ±
V, a positive or negative level is applied. As a result, burn-in can be performed on many types of semiconductor devices at the same time. Processing of the insulating member 5a and the like and cutting of the outer lead 4 after burn-in are the same as those in FIG.

FIG. 4 shows an example of the bias application in FIGS. 2 and 3. FIG. 4 shows an equivalent circuit, in which a positive or negative constant level is applied to the input / output terminals of the package 3 from the positive or negative power supply (± V) via the resistance member 6a. In this case, a fixed level is applied to an input terminal (not shown), and a level may be applied to the input terminal at a predetermined frequency in order to make the driving more similar to actual driving.

As described above, the burn-in of the semiconductor device can be performed before cutting the outer leads 4 and without changing the flow of the conventional manufacturing process. As a result, it is not necessary to prepare a socket or a burn-in board as in the related art, and the burn-in time and cost can be reduced. In addition, burn-in can be performed while an actual stress is applied to the semiconductor device. For example, it is possible to avoid that stress such as resin filling is not applied in burn-in performed on a wafer. Further, since the burn-in is performed in a high-temperature atmosphere, for example, if a process such as marking is performed on the package 3 before the burn-in, the conventional heating process for drying the stamp can be performed also as the burn-in. The process can be reduced.

[0022]

As described above, according to the present invention, a semiconductor device is provided by interposing a resistance member at an intermediate position of an outer lead or by providing an insulating member and a resistance member having a thickness smaller than that of the outer lead adjacent to each other. Burn-in can be performed in an unfinished state of the device and without changing the conventional assembling process, and burn-in time and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the present invention.

FIG. 3 is a view for explaining outer leads in FIG. 2;

FIG. 4 is a diagram illustrating an example of bias application in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead frame 2a, 2b, 10a-10d Support frame 3 Package 4 Outer lead 5, 5a Insulation member 6, 6a Resistance member

Claims (3)

(57) [Claims] 1. A die pad on which a semiconductor device can be mounted; a support frame made of a conductive material; an inner lead made of a conductive material disposed close to the die pad; An outer lead made of a conductive material connected at a second end to the inner lead; and an outer lead interposed at an intermediate position between the first end and the second end of the outer lead. And a conductive resistance member having a higher resistance value than the support frame, the inner lead and the outer lead. 2. A die pad on which a semiconductor device can be mounted; a support frame formed by sequentially laminating a first conductive member, a first insulating member, and a second conductive member; A lead frame comprising: an inner lead made of a conductive material; and an outer lead connected to the support frame at a first end and connected to the inner lead at a second end. An outer lead, a second insulating member connected to the first insulating member at the first end, a conductive resistance member disposed in contact with the second insulating member, A second insulating member and the conductive resistance member interposed therebetween; a first end connected to the first conductive member and the second conductive member; a second end At the third conductivity connected to the inner lead And a timber, the conductive resistance 1 resistance the first member, the second and third
A conductive member, and a lead frame having a resistance value larger than a resistance value of the inner lead. 3. The semiconductor device according to claim 1, wherein a semiconductor device is mounted on the die pad, each terminal of the semiconductor device is connected to the inner lead, and the semiconductor device is molded with a resin. Performing a burn-in while inputting an electrical signal to each terminal of the semiconductor device through the support frame, the outer lead, and the inner lead. Device burn-in method.