JPH04298070A - Semiconductor process - Google Patents
Semiconductor processInfo
- Publication number
- JPH04298070A JPH04298070A JP6302891A JP6302891A JPH04298070A JP H04298070 A JPH04298070 A JP H04298070A JP 6302891 A JP6302891 A JP 6302891A JP 6302891 A JP6302891 A JP 6302891A JP H04298070 A JPH04298070 A JP H04298070A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- lead
- lead frame
- rims
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title description 3
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 238000007789 sealing Methods 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体の検査効率の改良
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving semiconductor inspection efficiency.
【０００２】0002
【従来の技術】従来の半導体製造方法を図２に示す。半
導体はリードフレームに半導体素子７２を実装し、樹脂
５３により封止され、ダムバー５４、５５を切断し、リ
ード端子５８〜７１を曲げ加工し、完成品となる。また
半導体の検査は完成品になってから一つ一つ行っていた
。2. Description of the Related Art A conventional semiconductor manufacturing method is shown in FIG. A semiconductor element 72 is mounted on a lead frame, sealed with resin 53, dam bars 54 and 55 are cut, and lead terminals 58 to 71 are bent to form a finished product. Additionally, semiconductors were inspected one by one after they were completed.
【０００３】0003
【発明が解決しようとする課題】しかし、従来の技術で
は、完成品になってから一つ一つ半導体を検査する為、
手間、時間がかかり検査効率が悪くなるという問題点を
有していた。又、リードフレームから半導体を切り離し
ていない状態で検査をするとショートしてしまう。そこ
でダムバーを切断し、リード端子間、及び、リード端子
と外枠がショートしない状態で検査すると、半導体が外
枠に固定されず、前記半導体と前記外枠が切り離れてし
まう。[Problem to be solved by the invention] However, in the conventional technology, each semiconductor is inspected one by one after it becomes a finished product.
This method has the problem of being labor intensive and time consuming, resulting in poor inspection efficiency. Furthermore, if the semiconductor is inspected without being separated from the lead frame, a short circuit will occur. Therefore, if the dam bar is cut and inspected without shorting between the lead terminals or between the lead terminals and the outer frame, the semiconductor will not be fixed to the outer frame, and the semiconductor and the outer frame will be separated.
【０００４】そこで本発明はこのような問題点を解決す
るもので、半導体をリードフレームの外枠に固定したま
ま一度に多くの半導体を検査できることを目的とする。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and aims to enable inspection of many semiconductors at once while the semiconductors are fixed to the outer frame of a lead frame.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体製造方法
は、少なくともリードフレームに半導体素子を実装し、
樹脂により封止される半導体の製造方法において、封止
後、一対のリードフレーム外枠間にリード端子を介して
絶縁部材を貼ることを特徴とする。[Means for Solving the Problems] A semiconductor manufacturing method of the present invention includes mounting a semiconductor element on at least a lead frame,
A method of manufacturing a semiconductor sealed with resin is characterized in that after sealing, an insulating member is pasted between the outer frames of a pair of lead frames via lead terminals.
【０００６】[0006]
【実施例】本発明の半導体製造方法を図面を用いて詳細
に説明する。図１は、本発明の半導体製造方法の一実施
例を示す平面図である。半導体はリードフレームに半導
体素子２２を実装し、前記半導体素子２２、前記リード
フレームの一部を残し樹脂３により封止され、一対のリ
ードフレームの外枠６、７間にリード端子８〜１４、１
５〜２１を介し前記リード端子８〜２１の一部に絶縁部
材としてポリイミドテープ等の絶縁テープ１、２をダム
バー４、５（図中点線で示す）に接しないようにそれぞ
れ貼り、各前記リード端子間８〜２１、及び前記外枠６
、７とそれぞれ隣接されたリード端子８、１４、１５、
２１との間の前記ダムバー４、５を切断し、前記外枠６
、７と前記半導体が電気的接続されないようにする。前
記半導体は、前記絶縁テープ１、２により前記リードフ
レームの外枠６、７に機械的に接続され、前記の状態で
半導体を作動させ、検査を行う。DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor manufacturing method of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a plan view showing an embodiment of the semiconductor manufacturing method of the present invention. A semiconductor element 22 is mounted on a lead frame, and the semiconductor element 22 and a part of the lead frame are sealed with resin 3, and lead terminals 8 to 14 are placed between the outer frames 6 and 7 of the pair of lead frames. 1
Insulating tapes 1 and 2 such as polyimide tape are applied as insulating members to some of the lead terminals 8 to 21 via the leads 5 to 21 so as not to contact the dam bars 4 and 5 (indicated by dotted lines in the figure). Between the terminals 8 to 21 and the outer frame 6
, 7 and adjacent lead terminals 8, 14, 15, respectively.
The dam bars 4 and 5 between the outer frame 6 and the outer frame 6 are cut.
, 7 and the semiconductor are not electrically connected. The semiconductor is mechanically connected to the outer frames 6 and 7 of the lead frame by the insulating tapes 1 and 2, and the semiconductor is operated and inspected in the above state.
【０００７】尚、前記ダムバー４、５を切断する際、前
記半導体素子２２と電気的接続されていないリード端子
のダムバーは切断しても、切断しなくても良いが、切断
しなければ前記リードフレームの外枠６、７と前記半導
体間の機械的接続の強度を補強することができる。When cutting the dam bars 4 and 5, the dam bars of the lead terminals that are not electrically connected to the semiconductor element 22 may or may not be cut, but if they are not cut, the leads The strength of the mechanical connection between the outer frames 6 and 7 of the frame and the semiconductor can be reinforced.
【０００８】以上本例では、半導体について説明したが
、ＩＣ、抵抗、コンデンサー等を複合させたハイブリッ
トＩＣや、ＩＣ、圧電振動子等を複合させた圧電発振器
等においても同等の効果が得られる。また、本実施例で
は、２本の絶縁テープにより半導体とリードフレームの
外枠を固定したが、前記リードフレームの外枠をＧＮＤ
とし、外部接続端子のＧＮＤ端子と前記リードフレーム
の外枠間のダムバーを切断しないで残して前記リードフ
レームの外枠と半導体間の機械的接続の強度を補強する
方法の実施も可能である。また、本実施例では、絶縁テ
ープを一方の面に貼ったが絶縁テープを両面に貼り、リ
ードフレームの外枠と半導体間の機械的接続の強度を増
加させるという方法の実施も可能である。[0008] In this example, a semiconductor has been described above, but the same effect can be obtained with a hybrid IC that combines an IC, a resistor, a capacitor, etc., or a piezoelectric oscillator that combines an IC, a piezoelectric vibrator, etc. In addition, in this embodiment, the semiconductor and the outer frame of the lead frame were fixed with two insulating tapes, but the outer frame of the lead frame was connected to GND.
It is also possible to implement a method of reinforcing the strength of the mechanical connection between the outer frame of the lead frame and the semiconductor by leaving the dam bar between the GND terminal of the external connection terminal and the outer frame of the lead frame uncut. Further, in this embodiment, the insulating tape was applied to one side, but it is also possible to apply an insulating tape to both sides to increase the strength of the mechanical connection between the outer frame of the lead frame and the semiconductor.
【０００９】また以上の実施例において、絶縁部材とし
て、ポリイミドテープ等の表面に粘着剤の付着した絶縁
テープを用いたが、本発明は、これに限るものでなく、
樹脂やセラミック等の絶縁材や、表面に絶縁処理を施し
た金属等の部材に、接着剤を塗布して貼っても良い。Further, in the above embodiments, an insulating tape such as a polyimide tape with an adhesive attached to the surface was used as the insulating member, but the present invention is not limited to this.
An adhesive may be applied and attached to an insulating material such as resin or ceramic, or a member such as metal whose surface has been subjected to insulation treatment.
【００１０】0010
【発明の効果】以上述べたように本発明によれば、少な
くともリードフレームと半導体素子と樹脂により構成さ
れる半導体において、樹脂による封止の後、一対のリー
ドフレームの外枠間にリード端子を介して絶縁テープを
貼ることにより、ダムバー切断を行っても、前記リード
フレームの外枠と前記半導体が機械的に接続される為前
記リードフレームの外枠に前記半導体を機械的に接続し
たまま一度に多くの半導体を検査できるという効果を得
られる。As described above, according to the present invention, in a semiconductor composed of at least a lead frame, a semiconductor element, and a resin, after sealing with resin, a lead terminal is inserted between the outer frames of a pair of lead frames. By pasting insulating tape through the lead frame, even if the dam bar is cut, the semiconductor is mechanically connected to the outer frame of the lead frame. The effect is that many semiconductors can be inspected.
【図１】本発明の一実施例を示す平面図。FIG. 1 is a plan view showing one embodiment of the present invention.
【図２】従来例を示す平面図。FIG. 2 is a plan view showing a conventional example.
１、２ 絶縁テープ ３ 樹脂 ４、５ ダムバー ６、７ 外枠 ８〜２１ リード端子 ２２ 半導体素子 1, 2 Insulating tape 3 Resin 4, 5 Dam bar 6, 7 Outer frame 8-21 Lead terminal 22 Semiconductor element
Claims (1)
実装し、樹脂により封止される半導体の製造方法におい
て、封止後、一対のリードフレームの外枠間にリード端
子を介して絶縁部材を貼ることを特徴とする半導体製造
方法。Claim 1: A semiconductor manufacturing method in which a semiconductor element is mounted on at least a lead frame and sealed with a resin, wherein after sealing, an insulating member is pasted between the outer frames of a pair of lead frames via lead terminals. A semiconductor manufacturing method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6302891A JPH04298070A (en) | 1991-03-27 | 1991-03-27 | Semiconductor process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6302891A JPH04298070A (en) | 1991-03-27 | 1991-03-27 | Semiconductor process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04298070A true JPH04298070A (en) | 1992-10-21 |
Family
ID=13217468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6302891A Pending JPH04298070A (en) | 1991-03-27 | 1991-03-27 | Semiconductor process |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04298070A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016092040A (en) * | 2014-10-29 | 2016-05-23 | タツタ電線株式会社 | Printed circuit board, manufacturing method of printed circuit board, and joining method for conductive member |
-
1991
- 1991-03-27 JP JP6302891A patent/JPH04298070A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016092040A (en) * | 2014-10-29 | 2016-05-23 | タツタ電線株式会社 | Printed circuit board, manufacturing method of printed circuit board, and joining method for conductive member |
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