JPH08204119A - Semiconductor device - Google Patents

Abstract

PURPOSE: To mount respectively semiconductor chips on both surfaces of a die pad without generating defective connection and short circuit and making short bonding wires by a method wherein a lead frame is provided with the chips, which are respectively mounted on the first and second surfaces of a semiconductor chip mounting part and are respectively connected electrically with first and second circuit patterns. CONSTITUTION: A semiconductor device has a lead frame 6 which is provided with a die pad 1 with first and second circuit patterns 3a and 3b formed radially on the peripheral edge parts of the surface and rear thereof and a plurality of inner leads 7 extended so as to connect with the upper part of the pattern 3a formed on the peripheral edge of the surface of this pad 1. Moreover, the lead frame 6 is provided with a first semiconductor chip 2a which is mounted on the surface of the pad 1 and is used as a memory chip, and a second semiconductor chip 2b which is mounted on the rear of the pad 1 and is used as a logic chip larger than the pad 1. The chips 2a and 2b are respectively connected with the inward ends of the patterns 3a and 3b via bonding wires 4a and 4b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a double-sided mounting type semiconductor device in which semiconductor chips are mounted on both sides of a lead frame.

[0002]

2. Description of the Related Art Usually, a semiconductor device has a semiconductor chip mounted on a die pad (semiconductor element mounting portion) of a lead frame, and a bonding pad and a lead of the semiconductor chip.
Connect the inner frame of the d-frame with a bonding wire, etc., and further seal them with a sealing material such as resin or ceramic, cut the tie bar and side bar, and obtain the outer lead. It can be completed by bending it in the shape of.

By the way, in recent years, the demand for higher density and thinner semiconductor devices is increasing, and in preparation for this demand,
It has been proposed that semiconductor chips are mounted on both front and back surfaces of a lead frame (for example, Japanese Patent Laid-Open No. 5-121462).
issue). As described above, in the case where the semiconductor chips are mounted on both sides, the number of input / output pins can be increased, but the inner leads of the lead frame to be connected are fine in width pitch and easily deformed, which may cause a short circuit. .
In such a semiconductor device, semiconductor chips of the same size are usually mounted on the front surface and the back surface of the die pad.

Further, since the bonding wire is used from both sides of the pad, it is difficult to shorten the bonding wire, and there are problems such as increase in impedance and regulation of high speed signal transmission.
Further, since the temperature becomes high during use, there is a risk of inducing crosstalk.

[0005]

By the way, in response to the increasing demand for multi-functionalization and multi-use of semiconductor devices, in order to meet this demand, semiconductor chips having different integration levels or semiconductor chips having different functions are being provided. It is also necessary to mount the same die pad on both sides. Further, semiconductor chips having different degrees of integration and functions often have different sizes.
When semiconductor chips of different sizes are mounted on both sides of the same die pad in this way, the smaller semiconductor chip has a larger distance from the tip of the inner lead, which lengthens the bonding wire, making the bonding operation difficult and making the bonding wire difficult. It causes problems such as short circuit. Furthermore, if the bonding wire becomes long, the signal transfer time becomes long, and there is a problem that high-speed processing is difficult.

Furthermore, as the integration of semiconductor chips increases, the number of pins also increases, and the inner lead tips are particularly fine and deformable in both the lead width and the lead spacing, which easily causes short circuits and connection failures. This may have caused a decrease in reliability.

The present invention has been made in view of the above circumstances, and it is possible to mount the bonding wires on both surfaces of the die pad without causing a defective connection or a short circuit and shortening the bonding wires. It is an object of the present invention to provide a highly reliable semiconductor device structure capable of preventing and increasing the number of pins.

[0008]

Therefore, the semiconductor device of the present invention is characterized in that it is connected to the peripheral portions of the first surface and the second surface at least at one place thereof through through holes. A semiconductor chip mounting portion made of an insulating substrate having first and second circuit patterns, and a plurality of inner ends having tips connected to outer ends of the first or second circuit patterns of the semiconductor chip mounting portion. A lead frame having a lead and an outer lead connected to each inner lead; and a lead frame mounted on the first surface and the second surface of the semiconductor chip mounting portion, respectively. The first and second circuit patterns are provided with the first and second semiconductor chips electrically connected to each other. Note that this electrical connection can be applied to a wire bonding method using a bonding wire, as well as a direct bonding method in which a bonding pad of a semiconductor chip and a circuit pattern are directly connected via a bump or the like.

Preferably, the insulating substrate is a ceramic plate.

Further, preferably, the first circuit pattern has an inner end located more inward than the second circuit pattern, and the first semiconductor chip is more than the second semiconductor chip. Characterized by being small.

[0011]

According to the above structure, the tip of the inner lead is superposed and connected on the circuit pattern formed on any surface of the insulating substrate, so that reliable connection can be achieved. Further, since the circuit pattern of the semiconductor element mounting portion is fixed, the tip can be reliably brought close to the peripheral edge of the first or second semiconductor chip without positional deviation. In addition, even if the lengths of the circuit patterns are changed, even if the chip sizes of the first and second semiconductor chips are greatly different, it is possible to achieve electrical connection without lengthening the bonding wires. There is no risk of short circuit or poor connection.

Further, since the bonding wire can be shortened, it is possible to provide a highly reliable semiconductor device without being deformed by the weight of the resin when the resin is sealed.

Further, when the sizes of the first and second semiconductor chips are different, the length of the circuit pattern may be adjusted so that the inner end of the circuit pattern is as close as possible to the respective semiconductor chips. Appropriate implementation is possible.

Further, when the connection method by direct bonding is used, the reliable connection can be easily made by extending the inner end of the circuit pattern to directly below the bonding pads of the first and second semiconductor chips. It is possible.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view of this semiconductor device, FIG. 2 is an explanatory view of the same top surface (sealing resin and circuit pattern are omitted), and FIGS. 3 (a) and 3 (b) show circuit patterns on the front and back sides. Indicates. This semiconductor device is made of alumina ceramic, and has a die pad 1 formed by forming first and second circuit patterns 3a and 3b in a radial shape on the peripheral portions of the front and back surfaces, and a first circuit pattern on the peripheral edge. 3a, a lead frame 6 having a plurality of inner leads 7 extending so as to be connected to the 3a, a first semiconductor chip 2a as a memory chip mounted on the front surface of the die pad 1, and a back surface of the die pad 1. A second semiconductor chip 2b mounted as a logic chip and formed larger than the die pad 1;
Of the semiconductor chip is connected to the inner ends of the first and second circuit patterns through the first and second bonding wires 4a and 4b, and the first circuit pattern 3a is further connected through the through hole 5. Two circuit patterns 3b, and the tips of the inner leads 7 are fixed near the outer ends of the second circuit patterns 3b, respectively, to achieve electrical connection. Further, resin sealing is performed by the sealing resin 8. Here, although the first semiconductor chip 2a is smaller than the second semiconductor chip 2b on the back surface side,
As shown in (a) and (b), the first circuit pattern 3a
Has reached inward of the second circuit pattern 3b and is formed so as to be closer to the first semiconductor chip 2a.

Here, the inner lead 7 is integrally supported by a tie bar 10. Here, the first circuit pattern connected to the power supply line or the ground line or the first circuit pattern connected to a part of the signal line is
Connected to the second circuit pattern through the through hole,
The first and second semiconductor chips are commonly connected to the inner leads 7 one by one. Also the second
A part of the circuit pattern of No. 2 is not connected to the second semiconductor chip and may be used only for extracting the signal line of the first semiconductor chip connected through the through hole.

Further, the signal line of the first semiconductor chip corresponds to the inner lead 7 through the through hole and, as shown in FIG. 4, the bonding pad BP formed on the second surface. May be connected to. Alternatively, as shown in FIG. 5, an auxiliary pattern 3Q used only for connection with the first circuit pattern may be formed on the second surface.

Next, a method of manufacturing this semiconductor device will be described.

First, a strip material or the like made of a 4-2 alloy is used as a starting material, a shape process is performed by an ordinary press working method, and then a lead frame 6 is subjected to a plating process if necessary.
To form. Gold bumps (not shown) are formed at the tips of the inner leads of the lead frame 6.

A through hole serving as a through hole H is formed in a predetermined area of the alumina ceramic substrate 1, and
First and second circuit patterns 3a and 3b made of a gold pattern are formed on the front and back surfaces by screen printing or a thin film process.

Then, the lead frame 6 and the second circuit pattern 3b are aligned and heated and fixed. Further, on the front surface and the back surface side of the die pad 1, a first semiconductor chip 2 and a second semiconductor chip 2 are provided via an insulating paste.
a and 2b are mounted.

After the bonding is performed through the first and second bonding wires 4a and 4b, the back surface side and the front surface side are sealed with resin 8.

Finally, the tie bar 10 is cut off and the lead frame is molded to complete the semiconductor device of the present invention.

In this way, a high-density mounting type thin semiconductor device is completed, but since the tip of the circuit pattern is close to the chip, electrical connection can be made without lengthening the bonding wire. Therefore, there is no possibility of short circuit or poor connection. Although the first semiconductor chip 2a is smaller than the second semiconductor chip 2b, the first circuit pattern extends to a very close position, and the bonding wire is formed shorter. .

As described above, in accordance with the high integration of the semiconductor device, even if the lead width and the lead interval are miniaturized, the semiconductor device can be protected well without being deformed. Further, the bonding wire can be further shortened, and neither short circuit nor poor connection will occur. In addition, it is possible to provide a highly reliable semiconductor device without being deformed by the weight of the resin even when the resin is sealed.

In the above-mentioned embodiment, the connection between the first and second circuit patterns and the first and second semiconductor chips was made by wire bonding, but as shown in FIG.
Needless to say, direct bonding may be used. In this case, the tip of the circuit pattern may be extended to just below the bonding pad of the semiconductor chip, and bumps may be formed if necessary.

Furthermore, as shown in FIG. 7, the insulating substrate is a multilayer structure substrate (1A, 1B) made of a green sheet or the like, and the wiring layer pattern 3S interposed between the multilayers is adjusted. The pattern positions on the front and back sides can be freely selected and connected, and the pattern can be taken out from the inner lead 7.

In addition, although the memory and the logic circuit are mounted on the front surface and the back surface in the above embodiment, the memories having the same shape may be stacked. In this case, since the pad position of the semiconductor chip is reversed, the multilayer wiring as shown in FIG. 7 may be used for connection and the signal may be taken out by one lead. Further, if the chips on one side are connected face down by the direct bonding method, as a result, the first and second semiconductor chips are mounted so as to face the same direction, and the first and second semiconductor chips are mounted. The circuit pattern positions can be connected without reversing.

Further, since they are in close contact with each other via the die pad, heat dissipation is also improved, and the temperatures of the first and second semiconductor chips can be kept the same through the die pad. In particular, when semiconductor chips having different temperature characteristics are used, the characteristic variation can be reduced, which is effective.

In the above embodiment, the alumina ceramic substrate is used as the insulating substrate, but the insulating substrate is not limited to this and can be appropriately selected. Although 4-2 alloy is used as the starting material of the lead frame, other materials such as copper material may be used, and the molding method is not limited to the pressing method, and other methods such as etching method may be used. Needless to say, it may be used.

[0032]

As described above, according to the present invention, it is possible to provide a double-sided chip-mounted semiconductor device which is multi-pin, high-speed and excellent in reliability.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an explanatory top view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is an explanatory view showing a circuit pattern on the front surface and the back surface of the semiconductor device of the embodiment of the present invention.

FIG. 4 is a diagram showing a modification of the present invention.

FIG. 5 is a diagram showing a modified example of the present invention.

FIG. 6 is a diagram showing a modification of the present invention.

FIG. 7 is a diagram showing a modification of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Die pad 1A, 1B Multilayer substrate 2a First semiconductor chip 2b First semiconductor chip 3a First circuit pattern 3b First circuit pattern 4a First bonding wire 4b Second bonding wire 5 Through hole 6 Lead frame 7 Inner lead 8 Resin 10 Tie bar

Claims (3)

[Claims] 1. An insulating substrate having first and second circuit patterns, which are connected to each other through a through hole at at least one of the peripheral portions of the first surface and the second surface. A semiconductor chip mounting portion, a plurality of inner leads whose ends are connected to the outer ends of the first or second circuit patterns of the semiconductor chip mounting portion, and the inner leads are connected to each inner lead. A lead frame provided with an outer lead; and a lead frame mounted on the first surface and the second surface of the semiconductor chip mounting portion, respectively, and electrically connected to the first and second circuit patterns. A semiconductor device comprising: a first semiconductor chip and a second semiconductor chip. 2. The semiconductor device according to claim 1, wherein the insulating substrate is a ceramic plate. 3. The first circuit pattern has an inner end located more inward than the second circuit pattern, and the first semiconductor chip is smaller than the second semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.