JP2617870B2 - Alignment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment method for a dicing apparatus or the like.

[0002]

2. Description of the Related Art Generally, a wafer on which a plurality of chips such as ICs are formed is divided into individual chips by a dicing device. Prior to this division, alignment is performed in which a cutting line (referred to as a street) that divides chips formed on the wafer and a cutting direction of the blade are matched with each other. As this alignment method, the first area and the second area, which are spaced apart from each other by a predetermined distance on the wafer, are detected by pattern matching, and the coordinate shift is calculated based on the detected value to calculate the first area. It is known to perform θ correction so that a straight line formed by the same pattern as the key pattern and the same pattern as the key pattern in the second area is parallel to the alignment reference line (hairline) ( For example, JP-A-60-54454.

[0003]

According to the above conventional alignment method, the chips in the first region and the chips in the second region must be in the same column, but belong to different columns. May be misaligned. That is, an oblique straight line is aligned with the cutting line, and dicing is performed along the oblique straight line to cut the chip itself. SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and it is an object of the present invention to provide an alignment method capable of preventing a chip cutting accident due to oblique alignment.

[0004]

As a means for technically solving the above-mentioned problems, the present invention provides a plurality of chips such as ICs which are divided by a cutting line and have the same pattern as a key pattern in the same row. An alignment method for dicing individually arranged semiconductor wafers, wherein a first region and a second region at predetermined positions in the semiconductor wafer are detected by pattern matching based on a key pattern, After performing θ correction so that a straight line formed by the detected pattern of the first region and the detected pattern of the second region is parallel to the alignment reference line, the cutting line of the semiconductor wafer and the alignment reference line To see if and are actually parallel
The gist of the present invention is an alignment method for checking, by pattern matching, whether a pattern identical to a key pattern exists on a straight line formed by the detected pattern of the first region and the pattern of the second region.

[0005]

[Operation] After aligning based on a straight line formed by the same pattern as the key pattern in the first area and the same pattern as the key pattern in the second area, the key is moved to the third area on the straight line. This is a method to check whether the same pattern as the pattern already exists. Therefore, it is possible to detect the misalignment of the inclined straight line due to the imaging of chips in different rows, and to prevent chip cutting accidents. Can be done.

[0006]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In FIG. 1, W is a wafer which is a workpiece, is held by a frame F via a tape T, is housed in a cassette 1 as shown in FIG. 7, and is mounted on a cassette mounting table 2 of a dicing device D. Placed.

The wafer W is carried out from the cassette 1 to the wafer carry-in / carry-out area 4 while the frame F is sandwiched by the wafer carry-in / carry-out means 3 of the dicing apparatus D.
At the time of carrying out the wafer, the notch N formed in the frame F shown in FIG. 1 abuts on a positioning pin (not shown) of the wafer carrying-in / out means 3 to perform mechanical alignment.

Thereafter, the wafer W is transported to the chuck table 6 while the frame F is suction-held by the revolving arm 5. The wafer W held on the chuck table 6 is positioned immediately below the imaging unit 7a of the alignment unit 7 by the movement of the chuck table 6 shown in FIG.

In this alignment, the image pickup means 7a constituting the alignment unit 7 has a first area A and a second area A of the wafer W which are spaced by a predetermined distance as shown in FIG.
The region B of is imaged. The alignment unit 7 that has imaged the first area A determines whether or not the same pattern as the predetermined key pattern exists in the first area A by pattern matching as shown in FIG. When a pattern identical to the predetermined key pattern is found, the coordinates of the reference point P of the pattern are stored as, for example, (x ₁ , y ₁ ).

Next, the image pickup means 7a moves from the first area A to x
An image of the second area B having a predetermined interval in the axial direction is imaged, a pattern identical to the predetermined key pattern is found in the same manner as described above, and the coordinates of the reference point Q thereof are set to (x ₂ , y ₂ ), for example. Remember.

Here, if y ₁ = y ₂ , the reference points P and Q
Is parallel to the x-axis (an axis which is the same direction as the cutting direction by the blade and serves as a reference for alignment),
Since it coincides with the cutting line by the blade 8 shown in FIG. 7, no angle correction is required. However, when y ₁ ≠ y ₂ , a straight line L connecting the reference points P and Q is x as shown in FIG.
It is not parallel to the axis and does not coincide with the cutting line S by the blade 8, so that angle correction is required.

In this case, the deviation angle dθ between the straight line L and the cutting line S by the blade 8 can be obtained by the following equation dθ = tan ⁻¹ (y ₂ −y ₁ ) / (x ₂ −x ₁ ). By calculating this deviation angle dθ,
The chuck table 6 is corrected by θ so that the straight line L is parallel to the x-axis (cutting line S by the blade).

Next, after the angle correction is completed, the position of the blade 8 is matched with the position of the street R. This is because the positional relationship between the position of the key pattern and the street R is registered in the CPU of the dicing apparatus in advance, and as shown in FIG.
The coordinates of the corrected reference points P ₁ and Q ₁ , for example (x ₃ , y
₃ ), (x ₄ , y ₃ ).

After all the alignments are completed, the chuck table 6 holding the wafer W further advances in the x-axis direction to perform dicing. Although the description of the y-axis direction alignment of the wafer W is omitted in the above alignment, the chuck table 6 is rotated by 90 ° and x
Alignment in the y-axis direction as well as the axial direction is performed.

As described above, proper dicing is performed under proper alignment. However, even if alignment is performed properly, dicing may not be performed properly. This is because the dicing is performed without knowing the error, although the misalignment is originally caused. Conventionally, it could not be found because there was no function to detect misalignment, but the present invention is configured to detect such misalignment.

Here, the case where misalignment occurs will be described. The area imaged by the imaging means 7a of the alignment unit 7 is relatively narrow, and the wafer W imaged in the first area A and the second area B
The upper chip must be the same row of chips divided by the street R. Therefore, the wafer W carried out from the cassette 1 is mechanically aligned by the notch N of the frame F and adjusted so that the angular deviation between the x axis and the street R is within ± 1.5 °.

As shown in FIG. 1, since the orientation flat U formed on the wafer W is formed substantially parallel to the street R, when the wafer W is attached to the frame F via the tape T, the notch N Are arranged so that the flat portion V of the frame F and the orientation flat U of the wafer W are parallel to each other, so that the angle deviation between the x-axis and the street R is within, for example, ± 1.5 °. ing.

However, when the orientation flat U of the wafer W and the flat portion V of the frame F are out of tolerance as shown in FIG. Even if proper alignment is performed properly, it becomes impossible to keep the angular deviation within the allowable range. Further, even when the wafer W is disposed within the allowable range on the frame F, a similar problem occurs if mechanical alignment based on the notch N is performed improperly.

In such a case, as shown in FIG.
In the area A'and the second area B ', different rows of chips are imaged, and the alignment is performed by erroneously recognizing this state as a proper state. As a result, at the time of dicing after the completion of alignment, the straight line L'connecting the reference points P'and Q'is properly aligned as shown in FIG.
Even if the straight line L 'is set to be parallel to the x-axis, if the line S' where the chips are actually arranged is not parallel to the x-axis and cutting is performed along a straight line parallel to L ' Each chip is cut, resulting in a great loss.

Therefore, according to the present invention, if the chips in the same row are imaged and the alignment is properly performed, the first region A
The reference point of the same pattern as the key pattern of any chip existing between the A and B areas always exists on the straight line L connecting the reference points P and Q of the second area B, and conversely, the A 'area When the chips of different rows are aligned by image pickup such as the B and B'regions, an arbitrary chip existing between the A'B 'regions is located on the straight line L'connecting the reference points P'and Q'. This is based on the idea that there is no reference point of the same pattern as the key pattern.

More specifically, the present invention will be described with reference to FIGS. 1 and 5. If, for example, about 10 chips exist between the first area A and the second area B, the first A region (though not limited to this) of the third chip from the region A chip is imaged by the image pickup means 7a as the third region C, and the reference point O of the same pattern as the key pattern is the y coordinate. Check whether the same value exists. If the coordinate of the reference point O of the third area C is (x ₅ , y ₃ ), the coordinate value of the y coordinate is y of the reference points P and Q of the first area A and the second area B. Since it is the same as the coordinate value y ₃ , it is determined that proper alignment has been performed.

On the other hand, as shown in FIG. 6, when the alignment is performed by imaging the chips in the different rows in the first area A'and the second area B ', the first area A'to the chip 3 is read.
When an image of an area that is separated by about an individual number is taken as the third area C ′, there is no reference point having the same y coordinate. Coordinates of 'reference point O' of the region C is recognized, for example, (x _12, y _11), which is the y-coordinate value y of the 'reference point P' of the first region A
_Since it is different from _10, it is judged that the alignment was incorrect.

If the alignment is determined to be inappropriate, the wafer W is removed from the dicing apparatus as an alignment error without proceeding to the next dicing step, and the cause of the alignment error is examined. For example, it is checked whether the wafer W is disposed within an allowable range with respect to the frame F. If the wafer W is out of the allowable range, the wafer W is removed from the frame F, and the frame F
And the orientation flat U of the wafer W is parallel to the frame F again.

As described above, since it is confirmed whether or not the alignment is properly performed, it is possible to avoid the situation where the wafer is diced in the misaligned state, and the loss of expensive chips is eliminated. As the chip size decreases, the probability of imaging chips in different rows increases and the frequency of misalignment increases. However, by employing the present invention, such a problem is solved.

In the embodiment, the third region is located at the third position from the chip in the first region. However, the present invention is not limited to this. For example, if the chip is small, the fifth region to the tenth region is arbitrarily selected. I can decide. Further, the third area does not need to be one place, and the check function can be enhanced as a plurality of places. Further, although the third region is a portion between A and B in the above embodiment, the third region is not limited to this and may be the outside between A and B.

[0026]

As described above, according to the present invention,
In a semiconductor wafer alignment method for dicing, after alignment based on a straight line connecting the reference points of the key patterns of the first region and the second region, the reference point of the key pattern in the third region is aligned on the straight line. Is checked to see if there is a misalignment, it is possible to find a misalignment in the case where the first region and the second region are in different rows, thereby preventing an expensive chip from being cut. The effect of preventing is obtained.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor wafer normally held on a frame.

FIG. 2 is a plan view of a semiconductor wafer held in an abnormal state by a frame.

FIG. 3 is an enlarged view of a portion A and a portion B of FIG.

FIG. 4 is a diagram showing coordinates of a reference point before angle correction in alignment.

FIG. 5 is a diagram showing coordinates of reference points in the alignment of FIG. 1;

FIG. 6 is a diagram showing coordinates of a reference point in the alignment of FIG. 2;

FIG. 7 is an external view of a dicing device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Cassette 2 ... Cassette mounting table 3 ... Wafer carrying-in / out means 4 ... Wafer carrying-in / out area 5 ... Rotating arm 6 ... Chuck table 7 ... Alignment unit 7a ... Imaging means 8 ... Blade A ... 1st area B ... 2nd Area C: Third area D: Dicing device F: Frame T: Tape W: Wafer

Claims (1)

(57) [Claims] 1. In the same row, divided by a cutting line
To a chip such as an IC having the same pattern as the key pattern.
Dicing semiconductor wafers with multiple
Method for aligning semiconductor wafers
The first area and the second area, which are set at the predetermined positions of
ー Detected by pattern matching based on patterns
Then, the detected pattern of the first area and the pattern of the second area are detected.
The straight line formed by the turn and the alignment reference
After performing θ correction so that it is parallel to the line,
C cutting line and alignment reference line are parallel to reality
In order to confirm that the first detected
And the pattern of the second area
An alignment method for checking whether a pattern identical to a key pattern exists on a straight line formed by pattern matching.