WO2020188392A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020188392A1
WO2020188392A1 PCT/IB2020/051933 IB2020051933W WO2020188392A1 WO 2020188392 A1 WO2020188392 A1 WO 2020188392A1 IB 2020051933 W IB2020051933 W IB 2020051933W WO 2020188392 A1 WO2020188392 A1 WO 2020188392A1
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Prior art keywords
insulator
oxide
transistor
conductor
semiconductor
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Ceased
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PCT/IB2020/051933
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English (en)
French (fr)
Japanese (ja)
Inventor
柳澤悠一
山根靖正
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to US17/437,439 priority Critical patent/US12396214B2/en
Priority to JP2021506779A priority patent/JP7472100B2/ja
Publication of WO2020188392A1 publication Critical patent/WO2020188392A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024063342A priority patent/JP2024102079A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • one aspect of the invention relates to semiconductor wafers, modules, and electronic devices.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • a semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of the semiconductor device.
  • Display devices liquid crystal display devices, light emission display devices, etc.
  • projection devices lighting devices
  • electro-optical devices power storage devices
  • storage devices semiconductor circuits
  • imaging devices electronic devices, etc.
  • One aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).
  • a CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes as connection terminals formed therein.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.
  • a technique for constructing a transistor by using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention.
  • the transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state.
  • a low power consumption CPU that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is low is disclosed (see Patent Document 1).
  • a storage device capable of holding a storage content for a long period of time by applying the characteristic that a transistor using an oxide semiconductor has a low leakage current is disclosed (see Patent Document 2).
  • One aspect of the present invention is to provide a semiconductor device having good electrical characteristics.
  • one aspect of the present invention is to provide a semiconductor device having good reliability.
  • One aspect of the present invention is to provide a semiconductor device having normally-off electrical characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device having a large on-current. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption.
  • One aspect of the present invention is to provide a semiconductor device having a high degree of freedom in design.
  • one aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration.
  • one aspect of the present invention is to provide a highly productive semiconductor device.
  • one aspect of the present invention is to provide a novel semiconductor device.
  • One aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time.
  • One aspect of the present invention is to provide a semiconductor device having a high information writing speed.
  • one aspect of the present invention is to provide a semiconductor device having high frequency characteristics.
  • One aspect of the present invention is an insulator having an excess oxygen region, a metal oxide on the insulator, a first oxide semiconductor on the metal oxide, and a first conductivity in contact with the first oxide semiconductor. It has a body, a second conductor in contact with a first oxide semiconductor, a first oxide semiconductor, and a second oxide semiconductor in contact with an insulator, and the metal oxide is a first.
  • the region in which the first oxide semiconductor and the second oxide semiconductor are in contact with each other includes an element having a smaller giving energy of the Elingham diagram than the metal element of the oxide semiconductor, and the first conductor and the second It is arranged between the conductor and the conductor.
  • a second insulator in contact with the lower part of the insulator and a third conductor below the second insulator are provided, and the second insulator is a third conductor from the insulator. Suppresses the diffusion of excess oxygen into.
  • the first conductor and the second conductor include an element having a larger Gibbs energy generated in the Ellingham diagram than the metal element possessed by the first oxide semiconductor.
  • the first oxide semiconductor is an In-Ga-Zn oxide.
  • the second insulator contains an element having a smaller Gibbs energy of the Eringham diagram than the element possessed by the first oxide semiconductor
  • the metal oxide contains an element having a smaller Gibbs energy than the element possessed by the second insulator.
  • the region where the first oxide semiconductor and the second oxide semiconductor are in contact with each other is arranged between the first conductor and the second conductor. Has been done.
  • a third insulator in contact with the lower part of the first insulator and a third conductor below the third insulator are provided, and the third insulator is the first insulator. Suppresses the diffusion of excess oxygen from the third conductor to the third conductor.
  • the first conductor and the second conductor include an element having a larger Gibbs energy generated in the Ellingham diagram than the metal element possessed by the first oxide semiconductor.
  • the first oxide semiconductor is an In-Ga-Zn oxide.
  • one aspect of the present invention it is possible to provide a semiconductor device having good electrical characteristics.
  • one aspect of the present invention can provide a semiconductor device with good reliability.
  • one aspect of the present invention it is possible to provide a semiconductor device having normally-off electrical characteristics.
  • one aspect of the present invention can provide a semiconductor device having a large on-current.
  • one aspect of the present invention can provide a semiconductor device capable of miniaturization or high integration.
  • one aspect of the present invention can provide a highly productive semiconductor device.
  • a new semiconductor device can be provided.
  • one aspect of the present invention can provide a semiconductor device having high frequency characteristics.
  • FIG. 1A is a top view of the semiconductor device, and FIGS. 1B and 1C are cross-sectional views of the semiconductor device.
  • FIG. 2A is a top view of the semiconductor device, and FIGS. 2B and 2C are sectional views of the semiconductor device.
  • FIG. 3A is a top view of the semiconductor device, and FIGS. 3B and 3C are sectional views of the semiconductor device.
  • FIG. 4A is a top view showing a method for manufacturing a semiconductor device, and FIGS. 4B and 4C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIG. 5A is a top view showing a method for manufacturing a semiconductor device, and FIGS. 5B and 5C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIG. 5A is a top view showing a method for manufacturing a semiconductor device, and FIGS. 5B and 5C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIG. 5A is a top view
  • FIG. 6A is a top view showing a method for manufacturing a semiconductor device
  • FIGS. 6B and 6C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIG. 7A is a top view showing a method for manufacturing a semiconductor device
  • FIGS. 7B and 7C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIG. 8A is a top view showing a method for manufacturing a semiconductor device
  • FIGS. 8B and 8C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • 9A is a top view showing a method for manufacturing a semiconductor device
  • FIGS. 9B and 9C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIG. 9A is a top view showing a method for manufacturing a semiconductor device
  • FIGS. 9B and 9C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIGS. 10A is a top view showing a method for manufacturing a semiconductor device
  • FIGS. 10B and 10C are cross-sectional views showing a method for manufacturing the semiconductor device.
  • FIG. 11 is a cross-sectional view showing the configuration of the storage device.
  • FIG. 12 is a cross-sectional view showing the configuration of the storage device.
  • FIG. 13 is a cross-sectional view showing the configuration of the storage device.
  • FIG. 14A is a block diagram showing a configuration example of the storage device, and FIG. 14B is a perspective view of the storage device.
  • 15A to 15H are circuit diagrams showing a configuration example of a storage device.
  • 16A is a block diagram showing a configuration example of the storage device
  • FIG. 16B is a perspective view of the storage device.
  • FIGS. 18B and 18C are diagrams for explaining a circuit configuration example of pixels.
  • 19A and 19B are diagrams for explaining a circuit configuration example of pixels.
  • 20A and 20B are diagrams for explaining a configuration example of the drive circuit.
  • 21A to 21C are diagrams illustrating an example of a display device.
  • 22A and 22B are diagrams illustrating an example of a display device.
  • FIG. 23 is a diagram illustrating an example of a display module.
  • 24A to 24H are diagrams showing electronic devices.
  • 25A and 25B are schematic views of a sample according to this embodiment.
  • FIG. 26A and 26B are diagrams showing the results of TDS analysis of the sample according to this example.
  • FIG. 27 is a diagram illustrating the electrical characteristics of the transistor produced in this embodiment.
  • FIG. 28 is a diagram illustrating a cross section of the transistor produced in this embodiment.
  • 29A and 29B are diagrams for explaining the electrical characteristics of the transistor created in this embodiment.
  • 30A and 30B are diagrams for explaining the electrical characteristics of the transistor created in this embodiment.
  • the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may not be reflected in the figure for ease of understanding.
  • the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted.
  • the hatch pattern may be the same and no particular reference numeral may be added.
  • a top view also referred to as a "plan view”
  • a perspective view the description of some components may be omitted.
  • some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first” can be appropriately replaced with the “second” or “third” for explanation.
  • the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • source and drain functions may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.
  • the channel width (hereinafter, also referred to as “effective channel width”) in the region where the channel is actually formed (channel formation region) and the top view of the transistor are shown.
  • the indicated channel width (hereinafter, also referred to as “apparent channel width”) may be different.
  • the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible.
  • the proportion of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to the apparent channel width.
  • channel width may refer to an effective channel width.
  • the values of the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the semiconductor impurities refer to, for example, other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors.
  • transition metals other than the main components of the above such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements other than oxygen and hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
  • silicon oxide nitride has a higher oxygen content than nitrogen as its composition. Further, silicon nitride oxide has a higher nitrogen content than oxygen in its composition.
  • the term “insulator” can be paraphrased as an insulating film or an insulating layer.
  • the term “conductor” can be rephrased as a conductive film or a conductive layer.
  • semiconductor can be paraphrased as a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • the barrier film is a film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, and when the barrier film has conductivity, it is referred to as a conductive barrier film. I may call it.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS FET or an OS transistor, it can be rephrased as a transistor having an oxide or an oxide semiconductor.
  • normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the current per 1 ⁇ m of the channel width flowing through the transistor is 1 ⁇ 10 -20 at room temperature. It means that it is A or less, 1 ⁇ 10 -18 A or less at 85 ° C, or 1 ⁇ 10 -16 A or less at 125 ° C.
  • FIG. 1A is a top view of a semiconductor device having the transistor 200 according to the positional aspect of the present invention.
  • 1B and 1C are cross-sectional views of the semiconductor device. In the top view of FIG. 1A, some elements are omitted for the purpose of clarifying the figure.
  • FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and shows a cross section of the transistor 200 in the channel length direction.
  • FIG. 1C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 1A, and shows a cross section of the transistor 200 in the channel width direction.
  • the semiconductor device having the transistor 200 has a substrate 211, a transistor 200 arranged on the substrate 211, and an insulator 280 arranged on the transistor 200 and functioning as an interlayer film.
  • the insulator 280 may be provided with a plug that electrically connects to the transistor 200 or a conductor that functions as wiring.
  • the transistor 200 includes an insulator 216, a conductor 205 (which has a two-layer structure in the figure, but is not limited thereto), an insulator 222, an insulator 224, and a metal oxide 226. , Oxide 230 (oxide 230b, and oxide 230c), conductor 240 (conductor 240a, and conductor 240b), insulator 274, insulator 250, and conductor 260 (conductor 260a, And the conductor 260b).
  • the oxide 230 has a region that functions as a semiconductor having at least a channel forming region.
  • the conductor 260 functions as the first gate of the transistor, and the conductor 205 functions as the second gate of the transistor. Further, the conductor 240a and the conductor 240b function as a source electrode or a drain electrode.
  • the insulator 250 functions as a first gate insulator, and the insulator 222 and the insulator 224 function as a second gate insulator.
  • the metal oxide 226 is arranged between the oxide 230 and the insulator 224.
  • a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as a semiconductor is used for the oxide 230 that includes a region in which a channel is formed (hereinafter, also referred to as a channel forming region). Is preferable.
  • oxide semiconductors for example, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium). , Hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used. Moreover, you may use In-Ga oxide and In-Zn oxide as the oxide semiconductor.
  • a transistor using an oxide semiconductor in the channel formation region can provide a semiconductor device with low power consumption because the leakage current is extremely small in a non-conducting state. Further, by using an oxide semiconductor, various elements can be laminated and integrated three-dimensionally. That is, since the oxide semiconductor can be deposited by using a sputtering method or the like, it constitutes a three-dimensional integrated circuit (three-dimensional integrated circuit) in which the circuit is developed not only on the plane of the substrate but also in the vertical direction. be able to.
  • a transistor using an oxide semiconductor has its electrical characteristics fluctuated due to impurities and oxygen deficiency in the oxide semiconductor, and has normal-on characteristics (channels exist even if no voltage is applied to the gate electrode, and the transistor has a transistor. (Characteristics in which current flows).
  • Impurities in oxide semiconductors that affect the electrical properties of transistors include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • a high-purity intrinsic oxide semiconductor in which impurities and oxygen deficiency are reduced as the oxide semiconductor used in the channel formation region of the transistor.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • Oxygen deficiency may occur as one of the changes over time.
  • indium (In) and zinc (Zn) have relatively large Gibbs energy generated in the Ellingham diagram. That is, since indium (In) and zinc (Zn) have a strong tendency to be reduced, oxygen bonded to indium (In) and zinc (Zn) is attracted to metals arranged in close proximity to each other. It is highly probable that oxygen deficiency will occur as a result of being pulled out.
  • the oxygen deficiency can be compensated for by diffusing the excess oxygen of the structure having the excess oxygen region into the oxygen deficiency generated in the oxide semiconductor.
  • excess oxygen oxygen released by heating
  • excess oxygen more oxygen than oxygen that satisfies the stoichiometric composition
  • excess oxygen region a region in which oxygen is present in excess of the stoichiometric composition
  • the insulator having an excess oxygen region it is preferable to use an oxide material in which a part of oxygen is desorbed by heating.
  • Oxygen that desorbs oxygen by heating (hereinafter, also referred to as an insulator material having an excess oxygen region) has a desorption amount of oxygen molecules of 1.0 ⁇ 10 18 molecules in TDS (Thermal Desortion Spectroscopy) analysis. / Cm 3 or more, preferably 1.0 ⁇ 10 19 molecules / cm 3 or more, more preferably 2.0 ⁇ 10 19 molecules / cm 3 or more, or 3.0 ⁇ 10 20 molecules / cm 3 or more.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • an insulator capable of forming an excess oxygen region specifically, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon and the like. Silicon oxide to which nitrogen is added and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxide nitride are preferable because they are stable against heat.
  • the metal layer when the metal layer is in contact with the oxide semiconductor, even if an insulator having an excess oxygen region is arranged in the vicinity of the oxide semiconductor, excess oxygen is supplied to the oxygen deficiency generated in the oxide semiconductor. , The metal layer absorbs oxygen from the oxide semiconductor. That is, the metal layer in contact with the oxide semiconductor absorbs excess oxygen in the excess oxygen region via the oxide semiconductor.
  • the amount of oxygen extracted from the oxide semiconductor by the conductor due to the absorption of excess oxygen in the excess oxygen region by the metal arranged in the vicinity of the insulator having the excess oxygen region is the oxygen generated in the oxide semiconductor. It may exceed the amount of excess oxygen that diffuses into the defect. When the excess oxygen is insufficient, the oxygen deficiency generated in the oxide semiconductor is not sufficiently compensated, and the electrical characteristics of the transistor fluctuate.
  • the movement or diffusion of oxygen is suppressed between the insulator having an excess oxygen region and the metal layer arranged close to the insulator (hereinafter, also referred to as having a barrier property against oxygen). It is good to arrange the structure.
  • the excess oxygen contained in the insulator having an excess oxygen region is absorbed by the metal layer in contact with the oxide semiconductor via the oxide semiconductor.
  • the contact resistance between the conductor and the oxide semiconductor can be reduced by causing oxygen deficiency in the region where the metal layer is in contact.
  • the oxide semiconductor it is preferable that excess oxygen is not supplied to the region in contact with or superposed on the metal layer (specifically, the region that functions as the source region and the drain region). Therefore, at least, it is preferable to arrange a structure having a barrier property against oxygen between a region that functions as a source region or a drain region of the oxide semiconductor and an insulator having an excess oxygen region.
  • a region that overlaps with a conductor via an insulator is a high-purity intrinsic oxide semiconductor in which impurities and oxygen deficiency are reduced. It is preferable to have. Therefore, it is advisable to provide a region in contact with the insulator having an excess oxygen region in the channel formation region of the oxide semiconductor or in the vicinity of the channel formation region.
  • the generated Gibbs energy of the Ellingham diagram is higher than that of the metal element possessed by the conductor. It is preferable to use a metal oxide containing a small element.
  • the Ellingham diagram generation Gibbs is more than the metal element of the oxide semiconductor. Metal oxides containing elements with low energy can be used.
  • the structure of the transistor 200 shown in FIG. 1 will be used for explanation.
  • the oxide 230 including the channel forming region is arranged on at least the oxide 230b on the metal oxide 226 and the oxide 230b, and at least a part of the oxide 230 is in contact with the upper surface of the oxide 230b. It has an oxide of 230c and.
  • the oxide 230c is arranged so as to be superimposed on the conductor 260 that functions as a gate electrode via the insulator 250. That is, the region where the oxide 230c and the oxide 230b overlap functions as a channel forming region.
  • the oxide 230c is arranged in contact with the insulator 224, the metal oxide 226, the oxide 230b, the conductor 240, the insulator 274, and the insulator 280. Further, the oxide 230b is arranged in contact with the conductor 240, the insulator 274, and the metal oxide 226.
  • an excess oxygen region is provided in the insulator 224 in contact with the oxide 230c.
  • the design of the insulator 224 can be easily changed such as the film thickness. That is, since the volume reduction due to the processing performed after the excess oxygen region is provided is small, the excess oxygen amount can be easily controlled by adjusting the film thickness of the insulator 224.
  • the oxide 230c has a structure in contact with the insulator 250 and the insulator 280. Therefore, excess oxygen regions may be provided in one or both of the insulator 250 and the insulator 280.
  • the insulator 222 is arranged between the insulator 224 having the excess oxygen region and the conductor 205.
  • a material that suppresses the movement or diffusion of excess oxygen from the insulator 224 to the conductor 205 is used. That is, the insulator 222 uses an insulating metal oxide containing an element having a smaller Gibbs energy of the Ellingham diagram than the metal element of the conductor 205.
  • the insulator 222 having a barrier property against oxygen between the conductor 205 and the insulator 224 having the excess oxygen region By arranging the insulator 222 having a barrier property against oxygen between the conductor 205 and the insulator 224 having the excess oxygen region, the excess oxygen possessed by the insulator 224 is extracted by the conductor 205. It can be suppressed. Further, it is possible to suppress that the conductor 205 is oxidized by excess oxygen and the resistance is increased.
  • a metal oxide 226 is provided between the oxide 230b and the insulator 224 having an excess oxygen region.
  • the metal oxide 226 shown in FIG. 1 is preferably insulating.
  • the metal oxide 226 is arranged between the oxide 230b and the insulator 224. Further, the oxide 230b and the conductor 240 (conductor 240a and conductor 240b) that function as a source electrode or a drain electrode are superimposed. Therefore, the metal oxide 226 suppresses the movement or diffusion of excess oxygen contained in the insulator 224 to the oxide 230b.
  • oxygen of the oxide 230b is absorbed by the conductor 240, and oxygen deficiency occurs in the oxide 230b.
  • the resistance of the oxide 230b can be reduced due to the occurrence of oxygen deficiency, and the contact resistance between the region of the oxide 230b overlapping with the conductor 240 and the conductor 240 can be reduced.
  • the metal oxide 226 is removed in the region where the oxide 230c and the insulator 224 are superimposed and not overlapped with the oxide 230b.
  • the oxide 230c and the metal oxide 226 have a region in which they overlap only in the region via the oxide 230b. That is, the oxide 230c has a region in contact with the insulator 224 in a region that does not overlap with the oxide 230b.
  • the oxide 230c has a region in contact with the insulator 224 in the vicinity of the channel forming region (see FIG. 1C). That is, the excess oxygen contained in the insulator 224 passes through the oxide 230c and moves and diffuses to the region where the oxide 230b overlaps with the conductor 260 via the insulator 250. That is, in the transistor 200, the excess oxygen contained in the insulator 224 is supplied to the channel forming region of the transistor 200, and the oxygen deficiency generated in the region can be compensated.
  • the metal oxide 226 or the insulator 222 it is preferable to use an oxide containing aluminum (Al), hafnium (Hf), or the like, which is an element having a small Gibbs energy generated in the Ellingham diagram.
  • Al aluminum
  • hafnium oxide, or the like may be arranged between the conductor and the insulator containing an excess oxygen region.
  • the present invention is not limited to this. Absent.
  • one or both of the oxide 230b and the oxide 230c may have a laminated structure of two or more layers, and the oxide 230 may have a multilayer structure of three or more layers.
  • the oxide 230b may have crystallinity.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, the transistor 200 is stable against high temperatures in the manufacturing process.
  • the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Further, it is preferable that the conductor 205 is embedded in the insulator 216.
  • the conductor 260 may function as a first gate (also referred to as a top gate). Further, the conductor 205 may function as a second gate (also referred to as a bottom gate).
  • the threshold voltage (Vth) of the transistor 200 is controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. be able to.
  • Vth threshold voltage
  • the conductor 205 may be provided so as to overlap the end of the conductor 240a on the channel formation region side and the end of the conductor 240b on the channel formation region side. Further, as shown in FIG. 1C, it is preferable that the conductor 205 is also stretched in a region outside the end portion intersecting the channel width direction of the oxide 230b. That is, it is preferable that the conductor 205 and the conductor 260 are superposed on each other via an insulator on the outside of the side surface of the oxide 230b in the channel width direction.
  • the conductor 205 may be superimposed on at least the oxide 230b located between the conductor 240a and the conductor 240b.
  • the conductor 205 has a two-layer structure, but it is not limited to this structure. It may be a single layer or a laminated structure of three or more layers.
  • the first conductor of the conductor 205 in contact with the insulator 216 is a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen.
  • titanium, titanium nitride, tantalum, or tantalum nitride can be used.
  • the second conductor of the conductor 205 it is preferable to use a conductive material containing tungsten, copper or aluminum as a main component.
  • the oxide semiconductor, the insulator or conductor located in the lower layer of the oxide semiconductor, and the insulator or conductor located in the upper layer of the oxide semiconductor are made of different films without opening to the atmosphere.
  • By continuously forming the seeds it is possible to form an oxide semiconductor film having a substantially high purity and intrinsicity in which the concentration of impurities (particularly hydrogen and water) is reduced, which is preferable.
  • the insulator 274 it is preferable to use a material that suppresses impurities such as water or hydrogen from being mixed into the transistor 200 from the substrate side or from above (hereinafter, also referred to as a material having a barrier property against impurities). Further, in addition to the insulator 274, it is preferable to use a material having a barrier property against impurities for the insulator 222.
  • the insulator 274 and the insulator 222 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), the diffusion of impurities such as copper atoms It is preferable to use an insulating material having a function of suppressing (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
  • silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide and the like can be used for the insulator 274 and the insulator 222.
  • the insulator 274 and the insulator 222 are shown as a single layer in the figure, a laminated structure of two or more layers may be used.
  • a laminated structure of silicon nitride or silicon nitride oxide and aluminum oxide or hafnium oxide may be preferable.
  • the insulator 274 By arranging the insulator 274, it is possible to prevent impurities such as water or hydrogen from diffusing from the insulator 280 or the like to the transistor 200 side via the insulator 274.
  • the insulator 222 it is possible to suppress the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200 side via the insulator 222.
  • oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side via the insulator 222.
  • the transistor 200 is sealed with an insulator 222 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen, and an insulator 274.
  • the insulator 222 and the insulator 224 have a function as a gate insulator. Further, in the structure shown in FIG. 1, the metal oxide 226 has a function as a gate insulator.
  • the insulator 224 desorbs oxygen by heating.
  • the insulator 222 preferably has an element having a smaller Gibbs energy of the Ellingham diagram than the conductor 205 and the insulator 216.
  • the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are elements having a small Gibbs energy generated in the Ellingham diagram.
  • an insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like.
  • the nitride film suppresses the diffusion of the excess oxygen when the structure in contact with the nitride film has excess oxygen.
  • a nitride such as silicon nitride may be used.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be laminated on these insulators, for example.
  • these insulators may be nitrided. Silicon oxide, silicon oxide or silicon nitride may be laminated on the above insulator.
  • the insulator 222 It is preferable to use a material for the insulator 222 that prevents impurities such as water and hydrogen from being mixed into the transistor 200 from the substrate side.
  • the insulator 222 preferably has a smaller hydrogen diffusion coefficient than the insulator 224.
  • the insulator 222 serves as a layer for suppressing the release of oxygen from the oxide 230 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Function.
  • the insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST) or the like. Insulators containing so-called high-k materials may be used in single layers or in layers. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the conductor 240 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, and strontium. It is preferable to use a metal element selected from tantalum, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen.
  • the insulator 274 is provided in contact with the upper surface of the conductor 240, and it is preferable to use a material having a barrier property against oxygen. By providing the insulator 274, it is possible to suppress the oxidation of the conductor 240 and suppress the increase in the contact resistance between the transistor 200 and the wiring. Therefore, good electrical characteristics and reliability can be given to the transistor 200.
  • the insulator 280 is an insulator having an excess oxygen region, the absorption of excess oxygen possessed by the insulator 280 by the conductor 240 can be suppressed.
  • the insulator 274 has a higher ability to suppress the diffusion of oxygen than the insulator 280.
  • the insulator 274 for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Further, as the insulator 274, for example, an insulator containing aluminum nitride and silicon nitride may be used.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably arranged in contact with the upper surface of the oxide 230c.
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores are used. be able to.
  • silicon oxide and silicon oxide nitride are preferable because they are stable against heat.
  • the insulator 250 is preferably formed by using an insulator that releases oxygen by heating.
  • an insulator that releases oxygen by heating As the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the channel forming region of the oxide 230b.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is reduced.
  • the film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
  • the conductor 260 is shown as a two-layer structure in FIG. 1, it may have a single-layer structure or a laminated structure of three or more layers.
  • Conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), conductive having a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
  • the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • a conductive material containing tungsten, copper, or aluminum as a main component for the conductor 260b.
  • the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity.
  • a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
  • the insulator 280 and the insulator 274 function as an interlayer film.
  • an insulator that desorbs oxygen by heating may be used in the same manner as the insulator 224. Since the insulator 280 has a region in contact with the oxide 230c, when the insulator 280 is provided with an excess oxygen region, the excess oxygen moves or diffuses to the channel forming region of the transistor 200 via the oxide 230c. be able to. Therefore, when the insulator 280 is provided with an excess oxygen region, the description of the insulator 224 can be incorporated.
  • the insulator 280 includes silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and the like. It is preferable to have.
  • silicon oxide and silicon oxide nitride are preferable for use as an insulator 280 because they are thermally stable. Further, materials such as silicon oxide, silicon oxide nitride, and silicon oxide having pores are preferable because a region containing oxygen desorbed by heating can be easily formed. Further, the insulator 280 may have a structure in which the above materials are laminated, for example, a laminated structure of silicon oxide formed by a sputtering method and silicon oxide formed by a CVD method laminated on the insulator. do it. Further, silicon nitride may be further laminated on top of it.
  • FIG. 2A shows a top view.
  • FIG. 2B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 2A.
  • 2C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in A3-A4 in FIG. 2A.
  • some elements are omitted for the sake of clarity.
  • the shape of the metal oxide 226 of the semiconductor device shown in FIG. 2 is different from that of the semiconductor device shown in FIG. As shown in FIG. 2, the metal oxide 226 may be provided so that the projected area coincides with the oxide 230b. That is, the metal oxide 226 is provided only below the oxide 230b.
  • the metal oxide 226 is completely separated between adjacent transistors. Therefore, in the structure shown in FIG. 2, not only an insulating material but also a semiconductor material can be used as the metal oxide 226.
  • Examples of the semiconductor material that can be used for the metal oxide 226 include gallium oxide, zinc oxide, GZO (gallium zinc oxide), In-Ga-Zn oxide used for the oxide 230, and a small amount of silicon (Si). In-Ga-Zn oxide to which impurities have been added can be used.
  • In-Ga-Zn oxide is used for the metal oxide 226, it is applied to all the metal atoms in the In-Ga-Zn oxide rather than the In-Ga-Zn oxide used for the oxide 230b. It is preferable to use one having a high ratio of the number of Ga atoms.
  • a metal oxide having a composition in the vicinity may be used.
  • FIG. 3A shows a top view.
  • FIG. 3B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 3A.
  • FIG. 3C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A3-A4 in FIG. 3A.
  • some elements are omitted for the sake of clarity.
  • an insulator 228 may be provided on the film 227 that suppresses the diffusion of excess oxygen.
  • the degree of freedom in selecting the material of the film 227 can be increased.
  • the insulator 228 may be an oxide having an element having a smaller Gibbs energy of the Ellingham diagram than the oxide 230.
  • the In-Ga-Zn oxide used for the oxide 230 can also be used as the film 227 that suppresses the diffusion of excess oxygen.
  • the excess oxygen contained in the insulator 224 diffuses to the film 227 that suppresses the diffusion of excess oxygen.
  • the excess oxygen diffused in the membrane 227 that suppresses the diffusion of excess oxygen suppresses the movement and diffusion from the membrane 227 that suppresses the diffusion of excess oxygen to the insulator 228.
  • a metal oxide having an element having an element having a smaller Gibbs energy of the Ellingham diagram than the insulator 228 may be used for the film 227 that suppresses the diffusion of excess oxygen.
  • a nitride such as silicon nitride may be used for the film 227 that suppresses the diffusion of excess oxygen.
  • the nitride film can suppress the diffusion of the excess oxygen when the structure in contact with the nitride film in contact has excess oxygen.
  • the laminated structure composed of an insulator arranged between the conductor 205 and the oxide 230b and a film that suppresses the diffusion of excess oxygen functions as a gate insulator. Therefore, by appropriately selecting the material of the insulator 228 and the metal oxide 226, the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator can be thinned or thickened.
  • EOT equivalent oxide film thickness
  • the height of the bottom surface can be arranged at a position lower than the height of the bottom surface of the oxide 230b. Since the conductor 260 functioning as a gate has a structure in which the side surfaces and the upper surface of the oxide 230b in the channel forming region are covered with the oxide 230c and the insulator 250, an electric field generated from the conductor 260 is generated in the oxide 230b. It becomes easy to act on the entire channel formation region.
  • the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • the structure of the transistor that electrically surrounds the channel formation region by the electric fields of the first gate and the second gate is referred to as a surroundd channel (S-channel) structure.
  • the oxide 230b preferably has a laminated structure due to a plurality of oxide layers having different atomic number ratios of each metal atom (shown by broken lines in FIGS. 3B and 3C).
  • the oxide 230b is placed between the first layer in contact with the insulator 228, the second layer on the first layer, the second layer and the conductor 240. It has an arranged third layer.
  • the atomic number ratio of the element M in the constituent elements is the atom of the element M in the constituent elements in the metal oxide used in the second layer of the oxide 230b. It is preferably larger than the number ratio.
  • the atomic number ratio of the element M to In is the atomic number ratio of the element M to In in the metal oxide used for the second layer of the oxide 230b. It is preferably larger.
  • the atomic number ratio of In to the element M is the atomic number ratio of In to the element M in the metal oxide used for the first layer of the oxide 230b. It is preferably larger.
  • the first layer of the oxide 230b By having the first layer of the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed below the first layer to the second layer of the oxide 230b.
  • the third layer of the oxide 230b has a function of suppressing the permeation of oxygen. That is, by interposing the third layer of the oxide 230b between the conductor 240 and the second layer of the oxide 230b, the conductor 240 can release oxygen from the second layer of the oxide 230b. Can be suppressed from pulling out.
  • a metal oxide having the element M may be used as the third layer of the oxide 230b.
  • aluminum, gallium, yttrium, or tin may be used as the element M.
  • the third layer of oxide 230b preferably has a higher concentration of element M than the second layer of oxide 230b.
  • a metal oxide such as In-M-Zn oxide may be used as the third layer of the oxide 230b.
  • the atomic number ratio of the element M to In is the ratio of the element M to In in the metal oxide used for the second layer of the oxide 230b. It is preferably larger than the atomic number ratio.
  • the film thickness of the third layer of the oxide 230b is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. Further, it is preferable that the third layer of the oxide 230b has crystallinity.
  • the release of oxygen in the oxide 230b can be suitably suppressed.
  • the third layer of the oxide 230b has a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 230b may be suppressed.
  • Metal Oxide As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, gallium, yttrium, tin and the like are preferably contained. Further, one kind or a plurality of kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.
  • the metal oxide is an In-M-Zn oxide having indium, the element M, and zinc.
  • the element M is aluminum, gallium, yttrium, or tin.
  • elements applicable to the other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M a plurality of the above-mentioned elements may be combined in some cases.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
  • Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystal oxide semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide semiconductor (a-lique).
  • OS amorphous-like oxide semiconductor
  • amorphous oxide semiconductors are amorphous oxide semiconductors.
  • CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction.
  • the strain refers to a region in which a plurality of nanocrystals are connected, in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned.
  • Nanocrystals are basically hexagons, but they are not limited to regular hexagons and may be non-regular hexagons. In addition, it may have a lattice arrangement such as a pentagon and a heptagon in distortion.
  • a lattice arrangement such as a pentagon and a heptagon in distortion.
  • CAAC-OS it is difficult to confirm a clear grain boundary (also referred to as grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. Because.
  • CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as the (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can be expressed as the (In, M) layer.
  • CAAC-OS is a highly crystalline metal oxide.
  • CAAC-OS it is difficult to confirm a clear grain boundary, so it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur.
  • CAAC-OS since the crystallinity of the metal oxide may be lowered due to the mixing of impurities or the formation of defects, CAAC-OS can be said to be a metal oxide having few impurities and defects (oxygen deficiency, etc.). Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors depending on the analysis method.
  • In-Ga-Zn oxide which is a kind of metal oxide having indium, gallium, and zinc, may have a stable structure by forming the above-mentioned nanocrystals. is there.
  • IGZO tends to have difficulty in crystal growth in the atmosphere, it is preferable to use smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, a few mm crystal or a few cm crystal). However, it may be structurally stable.
  • the a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.
  • Impurities mixed in oxide semiconductors may cause defect levels or oxygen deficiencies. Therefore, when impurities are mixed in the channel forming region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be deteriorated. Further, when the channel formation region contains oxygen deficiency, the transistor tends to have a normally-on characteristic.
  • the above defect level may include a trap level.
  • the charge captured at the trap level of the metal oxide takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor having a metal oxide having a high trap level density in the channel forming region may have unstable electrical characteristics.
  • the crystallinity of the channel forming region may be lowered, or the crystallinity of the oxide provided in contact with the channel forming region may be lowered. Poor crystallinity in the channel formation region tends to reduce the stability or reliability of the transistor. Further, if the crystallinity of the oxide provided in contact with the channel forming region is low, an interface state may be formed and the stability or reliability of the transistor may be deteriorated.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of the above-mentioned impurities obtained by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the concentration of the impurities obtained by elemental analysis using EDX in the channel formation region of the oxide semiconductor and its vicinity is set to 1.0 atomic% or less.
  • the concentration ratio of the above-mentioned impurities to the element M in the channel forming region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably 0.05. To less than.
  • the concentration of the element M used in calculating the concentration ratio may be the concentration in the same region as the region in which the concentration of the impurities is calculated, or may be the concentration in the oxide semiconductor.
  • the metal oxide with reduced impurity concentration has a low defect level density, so the trap level density may also be low.
  • an oxide semiconductor having a low carrier concentration for the transistor it is preferable to use an oxide semiconductor having a low carrier concentration for the transistor.
  • the impurity concentration in the oxide semiconductor may be lowered and the defect level density may be lowered.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon and the like.
  • the carrier concentration of the oxide semiconductor in the channel forming region is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3 , and 1 ⁇ 10 16 cm -3. It is more preferably less than 1 ⁇ 10 13 cm -3 , even more preferably less than 1 ⁇ 10 12 cm -3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
  • a semiconductor device having good reliability it is possible to provide a semiconductor device having good electrical characteristics. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Further, according to one aspect of the present invention, a semiconductor device having low power consumption can be provided.
  • FIGS. 4 to 8 A in each figure shows a top view.
  • B in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in A, and is also a cross-sectional view in the channel length direction of the transistor 200.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line in A3-A4, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • D in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line in A5-A6.
  • some elements are omitted for the purpose of clarifying the figure.
  • the substrate 211 is prepared, and the insulator 216 is formed on the substrate 211.
  • the film of the insulator 216 can be formed by using a sputtering method, chemical vapor deposition, molecular beam epitaxy (MBE) method, pulsed laser deposition (PLD) method, ALD method, or the like. it can.
  • the CVD method can be classified into a plasma CVD (PECVD :) method using plasma, a thermal CVD method using heat, an optical CVD method using light, and the like. Further, it can be divided into a metal CVD method and an organometallic CVD method depending on the raw material gas used. Further, depending on the pressure at the time of film formation, it can be divided into a normal pressure CVD method in which film formation is performed under atmospheric pressure and a reduced pressure CVD method in which film formation is performed in a reduced pressure state lower than atmospheric pressure.
  • PECVD plasma CVD
  • the plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage does not occur during film formation, so that a film having few defects can be obtained.
  • a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor, or the like can be used.
  • the ALD method utilizes the self-regulating properties of atoms and allows atoms to be deposited layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, pinholes, etc. It has the effects of being able to form a film with few defects, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
  • it may be preferable to use plasma because it is possible to form a film at a lower temperature.
  • Some precursors used in the ALD method contain impurities such as carbon. Therefore, the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
  • the quantification of impurities can be performed by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage.
  • the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method having a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas.
  • a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film.
  • silicon nitride is formed as the insulator 216 by the CVD method.
  • the film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide or silicon oxide nitride is used as the insulator 216.
  • the insulator 216 is formed by a film forming method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 216 can be reduced.
  • an opening reaching the substrate 211 is formed in the insulator 216.
  • the opening also includes, for example, a groove or a slit.
  • the area where the opening is formed may be referred to as the opening.
  • Wet etching may be used to form the openings, but dry etching is preferable for microfabrication.
  • a conductive film to be the conductor 205 is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen.
  • a conductor having a function of suppressing the permeation of oxygen For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy.
  • the film formation of the conductive film to be the conductor 205 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205 has a multilayer structure.
  • tantalum nitride is formed into a film by a sputtering method, and titanium nitride is laminated on the tantalum nitride.
  • a low resistance conductive material such as copper is formed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 205 By forming the conductor 205 in a laminated structure, it is possible to prevent easily diffusing metals such as copper from diffusing out of the conductor 205 due to the metal nitride.
  • a part of the conductive film to be the conductor 205 is removed, and the insulator 216 is exposed.
  • the conductor 205 remains only in the opening. That is, the conductor 205 having a flat upper surface can be formed.
  • a part of the insulator 216 may be removed by the CMP treatment (see FIG. 4).
  • the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but the present embodiment is not limited to this.
  • a conductor 205 is formed on the substrate 211, an insulator 216 is formed on the conductor 205, and the insulator 216 is subjected to CMP treatment to remove a part of the insulator 216 and to remove a part of the insulator 205. The surface of the material may be exposed.
  • the insulator 222 is formed on the insulator 216 and the conductor 205.
  • the insulator 222 it is preferable to use a material having a relatively small Gibbs energy produced in the Ellingham diagram.
  • the insulator 222 it is preferable to form an insulator containing oxides of one or both of aluminum and hafnium.
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like.
  • Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. , The formation of oxygen deficiency in the oxide 230 can be suppressed.
  • the film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 224 is formed on the insulator 222.
  • the film formation of the insulator 224 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide or silicon oxide nitride is used as the insulator 224.
  • the insulator 224 comes into contact with the oxide 230c in a later step, it is preferable that the hydrogen concentration is reduced. Therefore, the insulator 224 may be formed by a film forming method using a gas in which hydrogen atoms have been reduced or removed. Thereby, the hydrogen concentration of the insulator 224 can be reduced.
  • the heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in a nitrogen or inert gas atmosphere. Good.
  • the treatment is continuously performed in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.
  • impurities such as water and hydrogen contained in the insulator 224 can be removed.
  • the heat treatment may be performed after the film of the insulator 222 is formed.
  • the above-mentioned heat treatment conditions can be used for the heat treatment.
  • oxygen including at least one of an oxygen radical, an oxygen atom, and an oxygen ion
  • oxygen is introduced into the insulator 224 to form a region containing an excess oxygen.
  • oxygen is supplied to the insulator 224 using one or more methods selected from ion implantation, ion doping, plasma treatment, and plasma imaging ion implantation to form excess oxygen regions. You may. At this time, it is preferable to use an ion implantation method in which the ionized raw material gas is mass-separated and added because oxygen can be supplied to the insulator 224 in a controlled manner.
  • plasma treatment containing oxygen may be performed in a reduced pressure state.
  • the plasma treatment containing oxygen for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves.
  • the substrate side may have a power supply that applies a high frequency such as RF.
  • high-density plasma high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can.
  • the plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, the heat treatment does not have to be performed.
  • oxygen introduction treatment there is a method of laminating an oxide on the insulator 224 using a sputtering device.
  • oxygen can be introduced into the insulator 224 while forming the oxide film by performing the film formation in an oxygen gas atmosphere using a sputtering device.
  • the metal oxide 226 formed on the insulator 224 may be formed on the metal oxide 226 by a sputtering method in an oxygen gas atmosphere. Oxygen can be added to the insulator 224 at the same time that the metal oxide 226 is formed on the insulator 224.
  • an oxide film 230B is formed on the insulator 226 (see FIG. 4).
  • the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230B is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas.
  • excess oxygen in the oxide film formed can be increased.
  • the above oxide film is formed by a sputtering method
  • the above In—M—Zn oxide target can be used.
  • heat treatment may be performed.
  • the above-mentioned heat treatment conditions can be used.
  • impurities such as water and hydrogen in the oxide film 230B can be removed.
  • the treatment is continuously performed in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.
  • a conductive film 240A is formed on the oxide film 230B (see FIG. 4).
  • the film formation of the conductive film 240A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230B and the conductive film 240A are processed into an island shape to form the oxide 230b and the conductive layer 240B (see FIG. 5).
  • the oxide 230b and the conductive layer 240B are formed so that at least a part thereof overlaps with the conductor 205.
  • a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication. In this step, the film thickness of the region that does not overlap with the oxide 230b of the metal oxide 226 may be reduced.
  • the resist is first exposed through a mask. Next, the exposed region is removed or left with a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film to be a hard mask material is formed on the conductive film 240A, a resist mask is formed on the insulating film or a conductive film, and the hard mask material is etched to form a hard mask having a desired shape. can do.
  • Etching of the conductive film 240A or the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the conductive film 240A or the like.
  • the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate type electrodes can be used.
  • the capacitively coupled plasma etching apparatus having the parallel plate type electrodes may be configured to apply a high frequency power source to one of the parallel plate type electrodes.
  • a plurality of different high-frequency power supplies may be applied to one of the parallel plate type electrodes.
  • a high frequency power supply having the same frequency may be applied to each of the parallel plate type electrodes.
  • a high frequency power supply having a different frequency may be applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like can be used.
  • the side surfaces of the oxide 230b and the conductive layer 240B are substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230b and the conductive layer 240B are substantially perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when a plurality of transistors 200 are provided. However, the present invention is not limited to this, and the angle formed by the side surface of the oxide 230b and the conductive layer 240B and the upper surface of the insulator 222 may be small.
  • the insulator 274 and the insulator 280 are formed on the metal oxide 226, the oxide 230b, and the conductive layer 240B (see FIG. 6).
  • the film formation of the insulator 274 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is formed as the insulator 274 by a sputtering method.
  • Oxygen can be injected into the insulator 224 by forming an aluminum oxide film by a sputtering method.
  • silicon nitride may be formed into a film by a sputtering method.
  • the film formation of the insulator 280 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film may be formed by using a sputtering method, and a silicon oxide film may be formed on the silicon oxide film by using a PEALD method or a thermal ALD method. Further, it is preferable that the insulator 280 is formed by the above-mentioned film forming method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 280 can be reduced.
  • the insulator 280 is subjected to CMP treatment to form an insulator 280 having a flat upper surface (see FIG. 6).
  • aluminum oxide may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.
  • a part of the insulator 280, a part of the insulator 274, a conductive layer 240B, and a part of the metal oxide 226 are processed to form an opening reaching the oxide 230b and the insulator 224 (FIG. 7).
  • the opening is formed so as to overlap the conductor 205.
  • the conductor 240a and the conductor 240b are formed.
  • a dry etching method or a wet etching method can be used for processing a part of the insulator 280, a part of the insulator 274, a part of the conductive layer 240B, and a part of the metal oxide 226.
  • Processing by the dry etching method is suitable for microfabrication. Further, the processing may be performed under different conditions. For example, a part of the insulator 280 is processed by a dry etching method, a part of the insulator 274 is processed by a wet etching method, a part of the conductive layer 240B is processed by a dry etching method, and the metal oxide 226 is wet. It may be processed by an etching method.
  • Impurities caused by etching gas and the like may adhere to or diffuse on the surface or inside of the oxide 230b and the like.
  • Impurities include, for example, fluorine or chlorine.
  • cleaning method examples include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.
  • cleaning can be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, aqueous ammonia, hydrofluoric acid, etc. with carbonated water or pure water.
  • aqueous solution obtained by diluting oxalic acid, phosphoric acid, aqueous ammonia, hydrofluoric acid, etc. with carbonated water or pure water.
  • ultrasonic cleaning using pure water or carbonated water can be performed.
  • the heat treatment may be performed after the etching or the cleaning.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere.
  • the heat treatment may be performed before the oxide film 230C is formed, and it is preferable that the heat treatment is performed under reduced pressure to continuously form the oxide film 230C without exposing it to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By the heat treatment, the water and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the water concentration and the hydrogen concentration in the oxide 230b can be further reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower, and more preferably 150 ° C. or higher and 350 ° C. or lower. In the present embodiment, the heat treatment temperature is set to 200 ° C. and the heat treatment is performed under reduced pressure.
  • the oxide film 230C is at least a part of the upper surface of the insulator 224, a part of the upper surface of the oxide 230b, a part of the side surface of the conductor 240, a part of the side surface of the insulator 274, and the insulator 280. It is preferably provided so as to be in contact with a part of the side surface.
  • the oxide film 230C comes into contact with the insulator 224, the excess oxygen contained in the insulator 224 can move or diffuse to the oxide 230b via the oxide film 230C.
  • the film formation of the oxide film 230C can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a sputtering method it is preferable that the atomic number ratio of Ga to In is larger than the atomic number ratio of Ga to In of the oxide film 230B.
  • the oxide film 230C may be laminated.
  • a film may be formed using a target of [number ratio].
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.
  • heat treatment may be performed. Further, the heat treatment may be performed under reduced pressure to continuously form the insulating film 250A without exposing it to the atmosphere.
  • the heat treatment By performing the heat treatment, the water and hydrogen adsorbed on the surface of the oxide film 230C and the like can be removed, and the water and hydrogen concentrations in the oxide 230b and the oxide film 230C can be further reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In the present embodiment, the temperature of the heat treatment is set to 200 ° C.
  • an insulating film 250A is formed on the oxide film 230C (see FIG. 8).
  • the insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by the above-mentioned film forming method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes an insulator 250 in contact with the oxide 230c in a later step, it is preferable that the hydrogen concentration is reduced.
  • oxygen gas may be turned into plasma by a high frequency such as microwave or RF to form oxygen radicals. That is, the plasma treatment may be performed in an atmosphere in which the insulator 280, the insulating film 250A, and the oxide 230b have oxygen. Such processing may be referred to as oxygen plasma treatment in the following.
  • oxygen plasma treatment oxygen can be supplied into the insulator 280 and the oxide 230b by the formed oxygen radicals.
  • the oxide 230 may be configured so as to be difficult to be irradiated with a high frequency such as microwaves or RF.
  • the microwave processing apparatus having a power source for generating high-density plasma using microwaves.
  • the microwave processing apparatus may have a power source for applying RF to the substrate side.
  • high-density plasma high-density oxygen radicals can be generated.
  • RF radio frequency
  • oxygen ions generated by the high-density plasma can be efficiently guided into the insulator 280 and the oxide 230.
  • the oxygen plasma treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and further preferably 400 Pa or more.
  • the oxygen flow rate ratio (O 2 / O 2 + Ar) is 50% or less, preferably 10% or more and 30% or less.
  • the processing temperature may be, for example, about 400 ° C. Further, after the oxygen plasma treatment, the heat treatment may be continuously performed without exposing to the outside air.
  • the conductive film 260A and the conductive film 260B are formed (see FIG. 8).
  • the film formation of the conductive film 260A and the conductive film 260B can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a sputtering method e.g., a CVD method
  • MBE method e.g., MBE method
  • PLD method e.g., a PLD method
  • ALD method atomic layer deposition
  • the conductive film 260A is formed by using the ALD method
  • the conductive film 260B is formed by using the CVD method.
  • the oxide film 230C, the insulating film 250A, the conductive film 260A and the conductive film 260B are polished until the insulator 280 is exposed, so that the oxide 230c, the insulating film 250 and the conductor 260 (conductor 260a) are polished. And the conductor 260b) (see FIG. 1).
  • the semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured.
  • the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device shown in the present embodiment.
  • FIG. 9A shows a top view.
  • FIG. 9B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 9A.
  • FIG. 9C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A3-A4 in FIG. 9A.
  • some elements are omitted for the sake of clarity.
  • the semiconductor device shown in FIG. 9 has a different transistor shape from the semiconductor device shown in FIG.
  • an oxide film to be the oxide 230c, an insulating film to be the insulator 250, and a conductive film to be the conductor 260 are formed.
  • the conductor 260 that functions as the gate electrode, the insulator 250 that functions as the gate insulator, and the oxide 230c can be processed with a mask to create the structure shown in FIG.
  • the conductor 240 that functions as a source electrode or a drain electrode does not necessarily have to be provided.
  • the carrier density of the oxide semiconductor increases when hydrogen or nitrogen is added. Further, when hydrogen is added to an oxide semiconductor, it may react with oxygen bonded to a metal atom to become water and form an oxygen deficiency. When hydrogen enters the oxygen deficiency, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. That is, the oxide semiconductor to which nitrogen or hydrogen is added becomes n-type and has a low resistance.
  • the transistor 200 shown in FIG. 9 can reduce the resistance of the oxide 230b in a self-aligned manner by using the conductor 260 that functions as a gate electrode as a mask. That is, when a plurality of transistors 200 are formed at the same time, the variation in electrical characteristics between the transistors can be reduced. Further, the channel length of the transistor 200 is determined by the width of the conductor 260, and by setting the width of the conductor 260 to the minimum processing dimension, the transistor 200 can be miniaturized.
  • one or more methods selected from the ion implantation method, the ion doping method, the plasma treatment, and the plasma immersion ion implantation method are used to add nitrogen or the like to the oxide 230b. It is advisable to supply impurities.
  • the resistance of the oxide 230 can be selectively reduced. That is, by using an insulator containing nitrogen or hydrogen for the insulator 274, the region of the oxide 230b in contact with the insulator 274 can be reduced in resistance.
  • FIG. 9 shows a conductor 246 (conductor 246a and conductor 246b) that functions as a plug that electrically connects a transistor and another structure.
  • the conductor 246 may extract oxygen in the oxide 230b by coming into contact with the oxide 230b. Therefore, there is a high possibility that oxygen deficiency will occur in the region of the oxide 230b in contact with the conductor 246.
  • the region in contact with the conductor 246 of the oxide 230b has a low resistance due to oxygen deficiency, a low ohmic contact can be made between the oxide 230b and the conductor 246.
  • the metal oxide 226 or the like between the oxide 230b and the insulator 224 as described above the channel formation region of the oxide 230b can maintain a high resistance region, so that an off-current can be generated. It can be made smaller.
  • FIG. 10A shows a top view.
  • FIG. 10B is a cross-sectional view corresponding to the portion indicated by the one-point chain line of A1-A2 shown in FIG. 10A.
  • FIG. 10C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A3-A4 in FIG. 10A.
  • some elements are omitted for the sake of clarity.
  • the semiconductor device shown in FIG. 10 has a different transistor shape from the semiconductor device shown in FIG.
  • the conductive layer 240B is separated into the conductor 240a and the conductor 240b.
  • an oxide film to be an oxide 230c, an insulating film to be an insulator 250, and a conductive film to be a conductor 260 are formed. Subsequently, by processing with a mask, the conductor 260 that functions as the gate electrode, the insulator 250 that functions as the gate insulator, and the oxide 230c can be produced as shown in FIG.
  • This embodiment can be implemented in combination with at least a part thereof and other embodiments and examples described in the present specification as appropriate.
  • FIG. 11 shows an example of a semiconductor device (storage device) using a capacitive element which is one aspect of the present invention.
  • the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 200. It is preferable that at least a part of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. As a result, the occupied area of the capacitive element 100, the transistor 200, and the transistor 300 in the top view can be reduced, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated.
  • the semiconductor device is, for example, a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a DRAM (Dynamic Random Access Memory) or an NVM (Non-Volatile Memory). It can be applied to a memory circuit represented by.
  • a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a DRAM (Dynamic Random Access Memory) or an NVM (Non-Volatile Memory). It can be applied to a memory circuit represented by.
  • the transistor 200 As the transistor 200, the transistor 200 described in the previous embodiment can be used. Therefore, for the transistor 200 and the layer including the transistor 200, the description of the previous embodiment can be taken into consideration.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced. Further, the transistor 200 has better electrical characteristics at high temperatures than a transistor using silicon for the semiconductor layer. For example, the transistor 200 exhibits good electrical characteristics even in the temperature range of 125 ° C to 150 ° C. Further, in the temperature range of 125 ° C. to 150 ° C., the transistor 200 has a transistor on / off ratio of 10 digits or more. In other words, the transistor 200 has better characteristics as the on-current, frequency characteristics, and the like, which are examples of transistor characteristics, become higher than those of a transistor using silicon for the semiconductor layer.
  • the wiring 1001 is electrically connected to the source of the transistor 300
  • the wiring 1002 is electrically connected to the drain of the transistor 300
  • the wiring 1007 is electrically connected to the gate of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and drain of the transistor 200
  • the wiring 1004 is electrically connected to the first gate of the transistor 200
  • the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the other of the source and drain of the transistor 200 is electrically connected to one of the electrodes of the capacitive element 100
  • the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100.
  • the semiconductor device shown in FIG. 11 has a characteristic that the charged charge can be held in one of the electrodes of the capacitive element 100 by switching the transistor 200, so that information can be written, held, and read out.
  • the transistor 200 is an element provided with a back gate in addition to a source, a gate (top gate), and a drain. That is, since it is a 4-terminal element, MRAM (Magnetoresistive Random Access Memory) utilizing MTJ (Magnetic Tunnel Junction) characteristics, ReRAM (Resistive Random Access Memory), ReRAM (Resistive Random Access Memory), etc.
  • MRAM Magneticoresistive Random Access Memory
  • MTJ Magnetic Tunnel Junction
  • ReRAM Resistive Random Access Memory
  • ReRAM Resistive Random Access Memory
  • the MRAM, the ReRAM, and the phase change memory may undergo a structural change at the atomic level when the information is rewritten.
  • the semiconductor device shown in FIG. 11 operates by charging or discharging electrons using a transistor and a capacitive element when rewriting information, so that it has excellent resistance to repeated rewriting and has few structural changes.
  • the semiconductor devices shown in FIG. 11 can form a memory cell array by arranging them in a matrix.
  • the transistor 300 can be used as a read circuit, a drive circuit, or the like connected to the memory cell array.
  • the semiconductor device shown in FIG. 11 constitutes a memory cell array as described above.
  • an operating frequency of 200 MHz or more can be realized in a range of a drive voltage of 2.5 V and an evaluation environment temperature of ⁇ 40 ° C. to 85 ° C.
  • the transistor 300 is provided on the substrate 311 and functions as a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b.
  • the insulator 315 is arranged on the semiconductor region 313, and the conductor 316 is arranged on the insulator 315. Further, the transistors 300 formed in the same layer are electrically separated by an insulator 312 that functions as an element separation insulating layer. As the insulator 312, the same insulator as the insulator 326 described later can be used.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the substrate 311 includes a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 300 may be a HEMT (High Electro
  • the low resistance region 314a and the low resistance region 314b impart n-type conductivity-imparting elements such as arsenic and phosphorus, or p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor region 313. Contains elements that
  • the conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a material or a conductive material such as a metal oxide material can be used.
  • the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • transistor 300 shown in FIG. 11 is an example, and the transistor 300 is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.
  • the semiconductor device is provided by stacking the transistor 300 and the transistor 200.
  • the transistor 300 can be made of a silicon-based semiconductor material
  • the transistor 200 can be made of an oxide semiconductor.
  • the silicon-based semiconductor material and the oxide semiconductor can be mixedly mounted on different layers to form the semiconductor device.
  • the semiconductor device shown in FIG. 11 can be manufactured by the same process as the manufacturing device used for the silicon-based semiconductor material, and can be highly integrated.
  • the capacitive element 100 includes an insulator 114 on the insulator 160, an insulator 140 on the insulator 114, a conductor 110 arranged in the insulator 114 and an opening formed in the insulator 140, and a conductor. It has an insulator 130 on the 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130.
  • at least a part of the conductor 110, the insulator 130, and the conductor 120 is arranged in the openings formed in the insulator 114 and the insulator 140.
  • the conductor 110 functions as a lower electrode of the capacitance element 100
  • the conductor 120 functions as an upper electrode of the capacitance element 100
  • the insulator 130 functions as a dielectric of the capacitance element 100.
  • the capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched not only on the bottom surface but also on the side surface at the openings of the insulator 114 and the insulator 140, and the capacitance per unit area.
  • the capacity can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitive element 100 can be.
  • an insulator that can be used for the insulator 280 may be used.
  • the insulator 140 preferably functions as an etching stopper when forming an opening of the insulator 114, and an insulator that can be used for the insulator 214 may be used.
  • the shape of the openings formed in the insulator 114 and the insulator 140 when viewed from above may be a quadrangle, a polygonal shape other than the quadrangle, or a polygonal shape with curved corners. , It may be a circular shape including an ellipse.
  • it is preferable that the area where the opening and the transistor 200 overlap is large. With such a configuration, the occupied area of the semiconductor device having the capacitance element 100 and the transistor 200 can be reduced.
  • the conductor 110 is arranged in contact with the insulator 140 and the opening formed in the insulator 114. It is preferable that the upper surface of the conductor 110 substantially coincides with the upper surface of the insulator 140. Further, the conductor 152 provided on the insulator 160 is in contact with the lower surface of the conductor 110.
  • the conductor 110 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the insulator 130 is arranged so as to cover the conductor 110 and the insulator 140.
  • the insulator 130 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium oxide, and nitride.
  • Hafnium or the like may be used, and it can be provided in a laminated or single layer.
  • an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • a material having a large dielectric strength such as silicon oxide nitride or a material having a high dielectric constant (high-k) for the insulator 130.
  • a laminated structure of a material having a large dielectric strength and a high dielectric constant (high-k) material may be used.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and pores are used as materials having a large dielectric strength.
  • silicon oxide, resin, etc. laminated in the order of silicon nitride was deposited using ALD (SiN x), silicon oxide was deposited using PEALD method (SiO x), silicon nitride was deposited using ALD (SiN x)
  • An insulating film can be used.
  • the conductor 120 is arranged so as to fill the openings formed in the insulator 140 and the insulator 114. Further, the conductor 120 is electrically connected to the wiring 1005 via the conductor 112 and the conductor 153.
  • the conductor 120 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the transistor 200 is configured to use an oxide semiconductor, the compatibility with the capacitive element 100 is excellent. Specifically, since the transistor 200 using an oxide semiconductor has a small off-current, it is possible to retain the stored contents for a long period of time by using it in combination with the capacitive element 100.
  • a wiring layer provided with an interlayer film, wiring, a plug, or the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design.
  • the conductor that functions as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order on the transistor 300 as an interlayer film. Further, in the insulator 320, the insulator 322, the insulator 324, and the insulator 326, a conductor 328 and a conductor 330 that are electrically connected to the conductor 153 that functions as a terminal are embedded. The conductor 328 and the conductor 330 function as plugs or wirings.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or wiring.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are laminated in this order. Further, a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
  • the conductor 218 functions as a plug or wiring that electrically connects to the transistor 300.
  • the conductor 112 and the conductors (conductor 120, conductor 110) constituting the capacitive element 100 are embedded in the insulator 114, the insulator 140, the insulator 130, the insulator 150, and the insulator 154. Is.
  • the conductor 112 functions as a plug or wiring that electrically connects the capacitive element 100, the transistor 200, or the transistor 300 and the conductor 153 that functions as a terminal.
  • the conductor 153 is provided on the insulator 154, and the conductor 153 is covered with the insulator 156.
  • the conductor 153 is in contact with the upper surface of the conductor 112, and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.
  • the insulator that can be used as the interlayer film includes oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides, and the like having insulating properties.
  • the insulator that functions as an interlayer film can reduce the parasitic capacitance generated between the wirings by using a material having a low relative permittivity. Therefore, the material may be selected according to the function of the insulator.
  • the insulator 320, the insulator 322, the insulator 326, the insulator 352, the insulator 354, the insulator 212, the insulator 114, the insulator 150, the insulator 156, and the like have an insulator having a low relative dielectric constant.
  • the insulator includes silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores. , Resin and the like are preferable.
  • the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores.
  • resin it is preferable to have a laminated structure. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like.
  • the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 is 1.0 ⁇ 10 12 ⁇ cm or more and 1.0 ⁇ 10 15 ⁇ cm or less, preferably 5.0 ⁇ 10 12 ⁇ cm or more 1 It is preferably 0.0 ⁇ 10 14 ⁇ cm or less, more preferably 1.0 ⁇ 10 13 ⁇ cm or more and 5.0 ⁇ 10 13 ⁇ cm or less.
  • Silicon nitride or silicon nitride oxide can be used as such an insulator.
  • the resistivity of the insulator 160 or the insulator 154 may be set within the above range.
  • a transistor using an oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 324, the insulator 350, the insulator 210, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
  • Examples of insulators having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
  • a material containing at least one metal element selected from ruthenium and the like can be used.
  • a semiconductor having high electric conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.
  • the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, the conductor 152, the conductor 153, and the like include a metal material, an alloy material, and a metal nitride material formed of the above materials.
  • a conductive material such as a metal oxide material can be used as a single layer or laminated. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • an insulator 247 between the insulator 224 and the insulator 280 having excess oxygen and the conductor 246 and the conductor 248 it is preferable to use a material having a barrier property against oxygen and impurities for the insulator 282.
  • the conductor 248 and the transistor 200 can be sealed by the insulator having a barrier property.
  • the insulator 247 it is possible to prevent the excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 246 and the conductor 248. Further, by having the insulator 247, it is possible to prevent hydrogen, which is an impurity, from diffusing into the transistor 200 via the conductor 246 and the conductor 248.
  • the conductor 246 and the conductor 248 have a function as a plug or wiring for electrically connecting to the transistor 200 or the transistor 300.
  • the insulator 247 is provided in contact with the side wall of the opening of the insulator 284, the insulator 282, and the insulator 280, and the conductor 246 or the conductor 248 is formed in contact with the side surface thereof. ..
  • the conductor 240 is located at least a part of the bottom of the opening, and the conductor 248 is in contact with the conductor 240.
  • the conductor 246 and the conductor 248 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 246 and the conductor 248 may have a laminated structure.
  • the transistor 200 shows a configuration in which the conductor 246 and the conductor 248 are provided as a two-layer laminated structure, the present invention is not limited to this.
  • the conductor 246 and the conductor 248 may be provided as a single layer or a laminated structure having three or more layers.
  • the conductor 246 and the conductor 248 have a laminated structure, and the conductor in contact with the insulator 224, the insulator 280, the insulator 282, and the insulator 284 via the insulator 247 is provided with water.
  • a conductive material having a function of suppressing the permeation of impurities such as hydrogen it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen as the conductor in contact with the conductor 240.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated state.
  • the conductive material it is possible to prevent oxygen added to the insulator 224 and the insulator 280 from being absorbed by the conductor 246 and the conductor 248.
  • impurities such as water and hydrogen contained in the layer above the insulator 284 can be suppressed from diffusing into the oxide 230 through the conductor 246 and the conductor 248.
  • the insulator 247 for example, an insulator that can be used for the insulator 214 or the like may be used.
  • the insulator 247 can suppress impurities such as water and hydrogen contained in the insulator 224 and the insulator 280 from diffusing into the oxide 230 through the conductor 248. Further, it is possible to prevent oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 246 and the conductor 248.
  • the conductor 152 which functions as a wiring may be arranged in contact with the upper surface of the conductor 246 and the upper surface of the conductor 248.
  • the conductor that functions as wiring it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • a semiconductor device using a transistor having an oxide semiconductor can be miniaturized or highly integrated. Further, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Further, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Further, it is possible to provide a transistor having an oxide semiconductor having a small off-current. Further, it is possible to provide a semiconductor device having reduced power consumption.
  • FIG. 12 shows an example of a semiconductor device (storage device) using the semiconductor device according to one aspect of the present invention.
  • the semiconductor device shown in FIG. 12 has a transistor 200, a transistor 300, and a capacitive element 100, similarly to the semiconductor device shown in FIG.
  • the semiconductor device shown in FIG. 12 is different from the semiconductor device shown in FIG. 11 in that the capacitive element 100 is a planar type and the transistor 200 and the transistor 300 are electrically connected.
  • the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. It is preferable that at least a part of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. As a result, the occupied area of the capacitive element 100, the transistor 200, and the transistor 300 in the top view can be reduced, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated.
  • the above-mentioned transistor 200 and transistor 300 can be used as the transistor 200 and the transistor 300. Therefore, the above description can be taken into consideration for the transistor 200, the transistor 300, and the layer including these.
  • the wiring 2001 is electrically connected to the source of the transistor 300, and the wiring 2002 is electrically connected to the drain of the transistor 300.
  • the wiring 2003 is electrically connected to one of the source and drain of the transistor 200
  • the wiring 2004 is electrically connected to the first gate of the transistor 200
  • the wiring 2006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitance element 100
  • the wiring 2005 is electrically connected to the other of the electrodes of the capacitance element 100. ..
  • a node in which the gate of the transistor 300, the other of the source and drain of the transistor 200, and one of the electrodes of the capacitive element 100 are connected may be referred to as a node FG.
  • the semiconductor device shown in FIG. 12 has a characteristic that the potential of the gate (node FG) of the transistor 300 can be held by switching the transistor 200, so that information can be written, held, and read out.
  • the semiconductor devices shown in FIG. 12 can form a memory cell array by arranging them in a matrix.
  • the structure below the insulator 354 can take the above description into consideration.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are arranged on the insulator 354.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used, similarly to the insulator 350 and the like.
  • a conductor 218 is embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
  • the conductor 218 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300.
  • the conductor 218 is electrically connected to the conductor 316 which functions as a gate electrode of the transistor 300.
  • the conductor 248 functions as a plug or wiring that electrically connects to the transistor 200 or the transistor 300.
  • the conductor 248 electrically connects the conductor 240b, which functions as the other of the source and drain of the transistor 200, and the conductor 110, which functions as one of the electrodes of the capacitive element 100, via the conductor 248. There is.
  • the capacitive element 100 is provided above the transistor 200.
  • the capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
  • As the conductor 110, the conductor 120, and the insulator 130 those described in the above-mentioned storage device 1 can be used.
  • the conductor 153 and the conductor 110 are provided in contact with the upper surface of the conductor 248.
  • the conductor 153 is in contact with the upper surface of the conductor 248 and functions as a terminal of the transistor 200 or the transistor 300.
  • the conductor 153 and the conductor 110 are covered with an insulator 130, and the conductor 120 is arranged so as to overlap the conductor 110 via the insulator 130. Further, an insulator 114 is arranged on the conductor 120 and the insulator 130.
  • FIG. 12 an example in which a planar type capacitive element is used as the capacitive element 100 is shown, but the semiconductor device shown in the present embodiment is not limited to this.
  • a cylinder-type capacitance element 100 as shown in FIG. 11 may be used as the capacitance element 100.
  • FIG. 13 shows an example of a storage device using the semiconductor device which is one aspect of the present invention.
  • the storage device shown in FIG. 13 includes a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitive element 100 shown in FIG.
  • the transistor 400 can control the second gate voltage of the transistor 200.
  • the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the second gate of the transistor 200 are connected.
  • the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source become 0V.
  • the second gate of the transistor 200 since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the second gate of the transistor 200 does not need to be supplied with power to the transistor 200 and the transistor 400.
  • the negative potential can be maintained for a long time. Thereby, the storage device having the transistor 200 and the transistor 400 can hold the stored contents for a long period of time.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200. ..
  • the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100. ..
  • the wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is the drain of the transistor 400. Is electrically connected to.
  • the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
  • the storage devices shown in FIG. 13 can form a memory cell array by arranging them in a matrix like the storage devices shown in FIGS. 11 and 12. It should be noted that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, it is preferable to provide a smaller number of transistors 400 than the transistors 200.
  • the transistor 400 is a transistor formed in the same layer as the transistor 200 and can be manufactured in parallel with the transistor 200.
  • the transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) that functions as a first gate electrode, a conductor 405 (conductor 405a, and a conductor 405b) that functions as a second gate electrode, and the conductor 405b.
  • An insulator 222, an insulator 224, and an insulator 450 that function as a gate insulating layer, an oxide 430c having a region where a channel is formed, a conductor 440a that functions as one of a source or a drain, and an oxide 431b.
  • a conductor 440b which acts as the other of the source or drain, and an oxide 432b.
  • the conductor 405 is the same layer as the conductor 205.
  • Oxide 431b, oxide 432b, and oxide 230b are in the same layer.
  • the conductor 440 is the same layer as the conductor 240.
  • the oxide 430c is the same layer as the oxide 230c.
  • the insulator 450 is the same layer as the insulator 250.
  • the conductor 460 is the same layer as the conductor 260.
  • the structures formed in the same layer can be formed at the same time.
  • the oxide 430c can be formed by processing an oxide film that becomes the oxide 230c.
  • Oxide 430c which functions as an active layer of the transistor 400, has reduced oxygen deficiency and impurities such as hydrogen and water, similarly to oxide 230 and the like.
  • the threshold voltage of the transistor 400 can be made larger than 0V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small.
  • an OS transistor a transistor using an oxide as a semiconductor
  • a capacitive element according to one aspect of the present invention
  • a storage device hereinafter, may be referred to as an OS memory device
  • the OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.
  • FIG. 14A shows an example of the configuration of the OS memory device.
  • the storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470.
  • Peripheral circuit 1411 includes row circuit 1420, column circuit 1430, output circuit 1440, and control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a writing circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell.
  • the wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • the storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and column decoder, and WDATA is input to the write circuit.
  • the control logic circuit 1460 processes input signals (CE, WE, RE) from the outside to generate control signals for the row decoder and the column decoder.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
  • the memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in a row, and the like. Further, the number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
  • FIG. 14A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap under the memory cell array 1470.
  • FIG. 15 describes an example of a memory cell configuration applicable to the above-mentioned memory cell MC.
  • DOSRAM ⁇ DOSRAM
  • 15A to 15C show an example of a circuit configuration of a DRAM memory cell.
  • a DRAM using a memory cell of a 1OS transistor 1 capacitance element type may be referred to as a DOSRAM.
  • the memory cell 1471 shown in FIG. 15A has a transistor M1 and a capacitive element CA.
  • the transistor M1 has a gate (sometimes called a top gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1. Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL during data writing and reading.
  • the wiring BGL functions as wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 15B.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 having no back gate, as in the memory cell 1473 shown in FIG. 15C.
  • the transistor shown in the previous embodiment can be used as the transistor M1.
  • the leakage current of the transistor M1 can be made very low. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cells can be reduced. Moreover, the refresh operation of the memory cell can be eliminated. Further, since the leak current is very low, multi-valued data or analog data can be held for the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.
  • ⁇ NO SRAM 15D to 15G show a circuit configuration example of a gain cell type memory cell having two transistors and one capacitance element.
  • the memory cell 1474 shown in FIG. 15D includes a transistor M2, a transistor M3, and a capacitance element CB.
  • the transistor M2 has a top gate (sometimes referred to simply as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2. Is connected to the wiring BGL.
  • the second terminal of the capacitance element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitance element CB. It is preferable to apply a low level potential to the wiring CAL during data writing, data retention, and data reading.
  • the wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M2.
  • the threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 15E.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 15F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL, as in the memory cell 1477 shown in FIG. 15G.
  • the transistor shown in the previous embodiment can be used as the transistor M2.
  • the leakage current of the transistor M2 can be made very low.
  • the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cells can be reduced.
  • the refresh operation of the memory cell can be eliminated.
  • the leakage current is very low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in the channel forming region (hereinafter, may be referred to as a Si transistor).
  • the conductive type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a readout transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by stacking the transistor M3 on the transistor M3, so that the occupied area of the memory cell can be reduced and the storage device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • an OS transistor is used for the transistor M2 and the transistor M3, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.
  • FIG. 15H shows an example of a gain cell type memory cell having a 3-transistor and 1-capacity element.
  • the memory cell 1478 shown in FIG. 15H includes transistors M4 to M6 and a capacitive element CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL.
  • Wiring GNDL is a wiring that gives a low level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL.
  • the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not have to have a back gate.
  • the transistor M5 and the transistor M6 may be an n-channel Si transistor or a p-channel Si transistor, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured by using only n-type transistors.
  • the transistor shown in the previous embodiment can be used as the transistor M4.
  • the leakage current of the transistor M4 can be made very low.
  • the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above.
  • the arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
  • FIG. 16 shows an example of a chip 1200 on which the semiconductor device of the present invention is mounted.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, and one or more interfaces 1215. , One or more network circuits 1216 and the like.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • a bump (not shown) is provided on the chip 1200, and as shown in FIG. 16B, the chip 1200 is connected to the first surface of a printed circuit board (Printed Circuit Board: PCB) 1201. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • PCB printed Circuit Board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM shown in the previous embodiment can be used for the DRAM 1221.
  • the NO SRAM shown in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200.
  • the above-mentioned NOSRAM or DOSRAM can be used.
  • GPU1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, it becomes possible to execute image processing and product-sum calculation with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memory of the CPU 1211 and the GPU 1212, And after the calculation on the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.
  • the memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface High-Definition Multimedia Interface
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201, the DRAM 1221 provided with the chip 1200 having the GPU 1212, and the motherboard 1203 provided with the flash memory 1222 can be referred to as the GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines. Further, by the product-sum calculation circuit used for GPU1212, deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), self-encoder, deep Boltzmann machine (DBM), deep belief network ( Since a method such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recurrent neural network
  • DBM deep Boltzmann machine
  • DBN deep belief network
  • the semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, information terminal, computer, smartphone, electronic book terminal, digital camera (including video camera), recording / playback device, navigation system, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 17 schematically shows some configuration examples of the removable storage device.
  • the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 17A is a schematic diagram of the USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like of the substrate 1104.
  • FIG. 17B is a schematic view of the appearance of the SD card
  • FIG. 17C is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111 and a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 1113.
  • data on the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like of the substrate 1113.
  • FIG. 17D is a schematic view of the appearance of the SSD
  • FIG. 17E is a schematic view of the internal structure of the SSD.
  • the SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like of the substrate 1153.
  • a transistor using an oxide semiconductor described using a transistor 200 or the like may be referred to as an OS transistor below.
  • FIG. 18A is a block diagram illustrating a configuration example of the display device 500.
  • the display device 500 shown in FIG. 18A has a drive circuit 511, a drive circuit 521a, a drive circuit 521b, and a display area 531.
  • the drive circuit 511, the drive circuit 521a, and the drive circuit 521b may be collectively referred to as a "drive circuit” or a "peripheral drive circuit”.
  • the drive circuit 521a and the drive circuit 521b can function as, for example, a scanning line drive circuit. Further, the drive circuit 511 can function as, for example, a signal line drive circuit. The drive circuit 521a and the drive circuit 521b may be only one of them. Further, some kind of circuit may be provided at a position facing the drive circuit 511 with the display area 531 in between.
  • the display devices 500 illustrated in FIG. 18A are arranged substantially in parallel with each other and are substantially parallel to p wirings 535 whose potentials are controlled by the drive circuit 521a and / or the drive circuit 521b. It has q wirings 536 whose potential is controlled by the drive circuit 511 (p and q are both natural numbers of 1 or more).
  • the display area 531 has a plurality of pixels 532 arranged in a matrix. Pixel 532 includes a pixel circuit 534 and a display element.
  • each of the three pixels 532 controls the transmittance, reflectance, or amount of emitted light of red light, green light, or blue light.
  • the color of the light controlled by the three pixels 532 is not limited to the combination of red, green, and blue, and may be yellow, cyan, or magenta.
  • the pixel 532 that controls white light may be added to the pixel that controls red light, green light, and blue light, and the four pixels 532 may be collectively functioned as one pixel.
  • the brightness of the display area can be increased.
  • the reproducible color gamut can be expanded.
  • a display device 500 capable of displaying at so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) resolution.
  • a display device 500 capable of displaying at a so-called ultra-high definition also referred to as “4K resolution”, “4K2K”, “4K”, etc.
  • ultra-high definition also referred to as “4K resolution”, “4K2K”, “4K”, etc.
  • a display device 500 capable of displaying at a resolution of so-called super high definition (also referred to as “8K resolution”, “8K4K”, “8K”, etc.) is realized. be able to.
  • 8K resolution also referred to as “8K resolution”, “8K4K”, “8K”, etc.
  • the wiring 535_g in the g-th row (g is a natural number of 1 or more and p or less) is the q pixels arranged in the g-row among the plurality of pixels 532 arranged in the p-row and q-column in the display area 531. It is electrically connected to 532.
  • the wiring 536_h in the hth column (h is a natural number of 1 or more and q or less) is electrically connected to the p pixels 532 arranged in the h column among the pixels 532 arranged in the p row and q column. Connected to.
  • the display device 500 can use various forms or have various display elements.
  • display elements include EL (electroluminescence) elements (organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic substances), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors.
  • CMOS complementary metal-oxide-semiconductor
  • MEMS micro electro mechanical system
  • DMD digital micro mirror Devices
  • DMS Digital Micro Shutter
  • MIRASOL® MIRASOL®
  • IMOD Interferrometric Modulation
  • Shutter MEMS Display Elements Optical Interference MEMS Display Elements
  • Electrowetting Elements Some have a display medium such as a piezoelectric ceramic display or a display element using carbon nanotubes whose contrast, brightness, reflectance, transmittance, etc. are changed by an electric or magnetic action. Further, quantum dots may be used as the display element.
  • An example of a display device using an EL element is an EL display.
  • An example of a display device using an electron emitting element is a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-emitter Display).
  • An example of a display device using quantum dots is a quantum dot display.
  • An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display).
  • An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper.
  • the display device may be a plasma display panel (PDP).
  • the display device may be a retinal scanning type projection device.
  • a part or all of the pixel electrodes may have a function as a reflective electrode.
  • a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.
  • graphene or graphite may be arranged under the LED electrode or the nitride semiconductor.
  • Graphene and graphite may be formed into a multilayer film by stacking a plurality of layers.
  • a nitride semiconductor for example, an n-type GaN semiconductor layer having crystals can be easily formed on the graphene or graphite.
  • a p-type GaN semiconductor layer having crystals or the like can be provided on the p-type GaN semiconductor layer to form the LED.
  • An AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having crystals.
  • the GaN semiconductor layer of the LED may be formed by MOCVD.
  • the GaN semiconductor layer of the LED can be formed by a sputtering method.
  • 18B, 18C, 19A, and 19B show examples of circuit configurations that can be used for pixel 532.
  • the pixel circuit 534 shown in FIG. 18B includes a transistor 461, a capacitive element 463, a transistor 468, and a transistor 464. Further, the pixel circuit 534 shown in FIG. 18B is electrically connected to a light emitting element 469 that can function as a display element.
  • An OS transistor can be used for the transistor 461, the transistor 468, and the transistor 464. In particular, it is preferable to use an OS transistor for the transistor 461.
  • One of the source and drain of the transistor 461 is electrically connected to the wiring 536_h. Further, the gate of the transistor 461 is electrically connected to the wiring 535_g. A video signal is supplied from the wiring 536_h.
  • the transistor 461 has a function of controlling writing of a video signal to the node 465.
  • One of the pair of electrodes of the capacitive element 463 is electrically connected to the node 465 and the other is electrically connected to the node 467. Also, the other of the source and drain of the transistor 461 is electrically connected to the node 465.
  • the capacitance element 463 has a function as a holding capacitance for holding the data written in the node 465.
  • One of the source and drain of the transistor 468 is electrically connected to the potential supply line VL_a, and the other is electrically connected to the node 467. Further, the gate of transistor 468 is electrically connected to node 465.
  • One of the source and drain of the transistor 464 is electrically connected to the potential supply line V0, and the other is electrically connected to the node 467. Further, the gate of the transistor 464 is electrically connected to the wiring 535_g.
  • One of the anode or cathode of the light emitting element 469 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the node 467.
  • the light emitting element 469 for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used.
  • the light emitting element 469 is not limited to this, and for example, an inorganic EL element made of an inorganic material may be used.
  • one of the potential supply line VL_a or the potential supply line VL_b is given a high power supply potential VDD, and the other is given a low power supply potential VSS.
  • the drive circuit 521a and / or the drive circuit 521b sequentially selects the pixels 532 of each row, turns on the transistors 461 and 464, and sends the video signal to the node 465. Write.
  • Pixel 532 in which data is written to the node 465 is put into a holding state when the transistor 461 and the transistor 464 are turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 468 is controlled according to the potential of the data written in the node 465, and the light emitting element 469 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.
  • a transistor having a back gate may be used as the transistor 461, the transistor 464, and the transistor 468.
  • the gate is electrically connected to the back gate. Therefore, the gate and the back gate always have the same potential.
  • the back gate of the transistor 468 is electrically connected to the node 467. Therefore, the back gate always has the same potential as the node 467.
  • the OS transistor described above can be used for at least one of the transistor 461, the transistor 468, and the transistor 464.
  • the pixel circuit 534 shown in FIG. 18C includes a transistor 461 and a capacitive element 463. Further, the pixel circuit 534 shown in FIG. 18C is electrically connected to a liquid crystal element 462 that can function as a display element. It is preferable to use an OS transistor for the transistor 461.
  • the potential of one of the pair of electrodes of the liquid crystal element 462 is appropriately set according to the specifications of the pixel circuit 534.
  • a common potential may be applied to one of the pair of electrodes of the liquid crystal element 462, or the same potential as the capacitance line CL described later may be used.
  • a different potential may be applied to one of the pair of electrodes of the liquid crystal element 462 for each pixel 532.
  • the other of the pair of electrodes of the liquid crystal element 462 is electrically connected to the node 466.
  • the orientation state of the liquid crystal element 462 is set by the data written to the node 466.
  • Examples of the driving method of the display device including the liquid crystal element 462 include a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, a VA mode, an ASM (Axially Synmetrical Aligned Micro-cell) mode, and an Occupation Mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric Liquid Crystal) mode, MVA mode, PVA (Partnered Vertical Alignment) mode, IPS mode, FFS mode, or TBA (Transfer) Mode may be used.
  • the display device can be driven by an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Disperseed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, or a PNLC (Polymer Network Liquid Crystal) mode.
  • ECB Electrically Controlled Birefringence
  • PDLC Polymer Disperseed Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • thermotropic liquid crystal When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a strong dielectric liquid crystal, an anti-strong dielectric liquid crystal, or the like can be used. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like.
  • a liquid crystal showing a blue phase that does not use an alignment film may be used.
  • the blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require orientation treatment, and has a small viewing angle dependence.
  • the alignment film does not need to be provided, the rubbing process is not required, so that the electrostatic breakdown caused by the rubbing process can be prevented, and the defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. .. Therefore, it is possible to improve the productivity of the liquid crystal display device.
  • multi-domain rendering or multi-domain design in which pixels are divided into several regions (sub-pixels) and molecules are tilted in different directions.
  • the intrinsic resistance of the liquid crystal material is 1 ⁇ 10 9 ⁇ ⁇ cm or more, preferably 1 ⁇ 10 11 ⁇ ⁇ cm or more, and more preferably 1 ⁇ 10 12 ⁇ ⁇ cm or more.
  • the value of the intrinsic resistance in the present specification is a value measured at 20 ° C.
  • one of the source and drain of the transistor 461 is electrically connected to the wiring 536_h, and the other is electrically connected to the node 466.
  • the gate of transistor 461 is electrically connected to wiring 535_g.
  • a video signal is supplied from the wiring 536_h.
  • the transistor 461 has a function of controlling the writing of the video signal to the node 466.
  • One of the pair of electrodes of the capacitance element 463 is electrically connected to the wiring (hereinafter, capacitance line CL) to which a specific potential is supplied, and the other is electrically connected to the node 466.
  • the potential value of the capacitance line CL is appropriately set according to the specifications of the pixel circuit 534.
  • the capacitance element 463 has a function as a holding capacitance for holding the data written in the node 466.
  • the pixel circuit 534 of each row is sequentially selected by the drive circuit 521a and / or the drive circuit 521b, the transistor 461 is turned on, and the video signal is written to the node 466. ..
  • the pixel circuit 534 in which the video signal is written to the node 466 is in the holding state when the transistor 461 is turned off. By sequentially performing this line by line, an image can be displayed in the display area 531.
  • a transistor having a back gate in the transistor 461 may be used.
  • the gate is electrically connected to the back gate. Therefore, the gate and the back gate always have the same potential.
  • FIG. 20A shows a configuration example of the drive circuit 511.
  • the drive circuit 511 has a shift register 512, a latch circuit 513, and a buffer 514.
  • FIG. 20B shows a configuration example of the drive circuit 521a.
  • the drive circuit 521a has a shift register 522 and a buffer 523.
  • the drive circuit 521b can also have the same configuration as the drive circuit 521a.
  • the start pulse SP, clock signal CLK, etc. are input to the shift register 512 and the shift register 522.
  • Display device configuration example Using the OS transistor shown in the above embodiment, a part or the whole of the drive circuit including the shift register can be integrally formed on the same substrate as the pixel portion to form a system on panel.
  • a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and the pixel portion 4002 is sealed by the sealing material 4005 and the second substrate 4006.
  • a signal line drive circuit 4003 formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.
  • the scanning line drive circuit 4004 is mounted. Further, various signals and potentials given to the signal line drive circuit 4003, the scanning line drive circuit 4004, or the pixel unit 4002 are supplied from FPC4018a (FPC: Flexible Printed Circuit), FPC4018b.
  • a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. Further, a second substrate 4006 is provided on the pixel unit 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005, and the second substrate 4006.
  • a signal line formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate is formed in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.
  • the drive circuit 4003 is mounted.
  • various signals and potentials given to the signal line drive circuit 4003, the scan line drive circuit 4004, or the pixel unit 4002 are supplied from the FPC 4018.
  • FIGS. 21B and 21C an example in which the signal line drive circuit 4003 is separately formed and mounted on the first substrate 4001 is shown, but the present invention is not limited to this configuration.
  • the scanning line drive circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.
  • the method of connecting the separately formed drive circuit is not particularly limited, and wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), COF (Chip On Film), and the like can be used.
  • 21A is an example of mounting the signal line drive circuit 4003 and the scanning line drive circuit 4004 by COG
  • FIG. 21B is an example of mounting the signal line drive circuit 4003 by COG
  • FIG. 21C is an example of mounting the signal line drive circuit 4003 by TCP. This is an example of mounting the drive circuit 4003.
  • the display device may include a panel in which the display element is sealed and a module in which an IC or the like including a controller is mounted on the panel.
  • the pixel unit and the scanning line drive circuit provided on the first substrate have a plurality of transistors, and the OS transistor shown in the above embodiment can be applied.
  • FIG. 22A and 22B are cross-sectional views showing a cross-sectional configuration of a portion shown by a chain line of N1-N2 in FIG. 21B.
  • FIG. 22A is an example of a liquid crystal display device using a liquid crystal element as the display element.
  • FIG. 22B is an example of a light emitting display device (also referred to as “EL display device”) using a light emitting element as a display element.
  • EL display device also referred to as “EL display device”
  • the display devices shown in FIGS. 22A and 22B have an electrode 4015, and the electrode 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductor 4019. Further, the electrode 4015 is electrically connected to the wiring 4014 at the openings formed in the insulator 4112, the insulator 4111, and the insulator 4110.
  • the electrode 4015 is formed of the same conductor as the first electrode layer 4030, and the wiring 4014 is formed of the same conductor as the transistor 4010 and the source electrode and drain electrode of the transistor 4011.
  • the pixel unit 4002 and the scanning line drive circuit 4004 provided on the first substrate 4001 have a plurality of transistors, and in FIGS. 22A and 22B, the transistor 4010 included in the pixel unit 4002 and the scanning line The transistor 4011 included in the drive circuit 4004 is illustrated.
  • an insulator 4112 is provided on the transistor 4010 and the transistor 4011
  • a partition wall 4510 is formed on the insulator 4112.
  • the transistor 4010 and the transistor 4011 are provided on the insulator 4102. Further, the transistor 4010 and the transistor 4011 have an electrode 4017 formed on the insulator 4103, and the insulator 4112 is formed on the electrode 4017.
  • the electrode 4017 can function as a back gate electrode.
  • the transistor 4010 and the transistor 4011 the transistor shown in the above embodiment can be used. It is preferable to use an OS transistor as the transistor 4010 and the transistor 4011.
  • the OS transistor has suppressed fluctuations in electrical characteristics and is electrically stable. Therefore, the display device of the present embodiment shown in FIGS. 22A and 22B can be a highly reliable display device.
  • the OS transistor can lower the current value (off current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.
  • the OS transistor can obtain a relatively high field effect mobility, it can be driven at high speed. Therefore, by using the OS transistor in the drive circuit section and the pixel section of the display device, it is possible to provide a high-quality image. Further, since the drive circuit unit or the pixel unit can be separately manufactured on the same substrate, the number of parts of the display device can be reduced.
  • the display device shown in FIGS. 22A and 22B has a capacitance element 4020.
  • the capacitive element 4020 has an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and an electrode formed in the same process as the source electrode and the drain electrode. Each electrode overlaps via an insulator 4103.
  • the capacitance of the capacitance element provided in the pixel portion of the display device is set so as to hold the electric charge for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion.
  • the capacitance of the capacitive element may be set in consideration of the off-current of the transistor and the like.
  • the capacity of the capacitive element can be reduced to 1/3 or less, or even 1/5 or less of the liquid crystal capacity.
  • the OS transistor By using the OS transistor, the formation of the capacitive element can be omitted.
  • the transistor 4010 provided in the pixel unit 4002 is electrically connected to the display element.
  • the liquid crystal element 4013 which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Insulators 4032 and insulators 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008.
  • the second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 are superimposed via the liquid crystal layer 4008.
  • the spacer 4035 is a columnar spacer obtained by selectively etching an insulator, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. There is. A spherical spacer may be used.
  • an optical member such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an antireflection member may be appropriately provided.
  • a black matrix light-shielding layer
  • a polarizing member such as a polarizing member
  • a retardation member such as a retardation member
  • an antireflection member such as a polarization using a polarizing substrate and a retardation substrate.
  • a backlight, a side light or the like may be used as the light source.
  • the display device shown in FIGS. 22A and 22B has an insulator 4111 and an insulator 4104.
  • insulator 4111 and the insulator 4104 insulators that do not easily transmit impurity elements are used. By sandwiching the semiconductor layer of the transistor between the insulator 4111 and the insulator 4104, it is possible to prevent the infiltration of impurities from the outside. Further, when the insulator 4111 and the insulator 4104 are in contact with each other on the outside of the pixel portion 4002, the effect of preventing the infiltration of impurities from the outside can be enhanced.
  • the insulator 4104 may be formed by, for example, the same material and method as the insulator 222.
  • the insulator 4111 may be formed, for example, by the same material and method as the insulator 274.
  • a light emitting element also referred to as "EL element” utilizing electroluminescence can be applied.
  • the EL element has a layer (also referred to as an "EL layer") containing a luminescent compound between a pair of electrodes.
  • EL layer a layer containing a luminescent compound between a pair of electrodes.
  • the EL element is distinguished by whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.
  • the organic EL element by applying a voltage, electrons are injected into the EL layer from one electrode and holes are injected into the EL layer from the other electrode. Then, when those carriers (electrons and holes) are recombined, the luminescent organic compound forms an excited state, and when the excited state returns to the ground state, it emits light. From such a mechanism, such a light emitting element is called a current excitation type light emitting element.
  • the EL layer is a substance having a high hole injecting property, a substance having a high hole transporting property, a hole blocking material, a substance having a high electron transporting property, a substance having a high electron injecting property, or a bipolar. It may have a sex substance (a substance having high electron transport property and hole transport property) and the like.
  • the EL layer can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • Inorganic EL elements are classified into dispersed inorganic EL elements and thin film type inorganic EL elements according to their element configurations.
  • the dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emitting mechanism is donor-acceptor recombination type light emission utilizing a donor level and an acceptor level.
  • the thin-film inorganic EL device has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emitting mechanism is localized light emission utilizing the inner-shell electronic transition of metal ions.
  • an organic EL element will be used as the light emitting element.
  • the light emitting element may have at least one of a pair of electrodes transparent in order to extract light emission. Then, a top emission (top emission) structure in which a transistor and a light emitting element are formed on the substrate and light emission is taken out from the surface on the opposite side of the substrate, and a bottom emission (bottom emission) structure in which light emission is taken out from the surface on the substrate side.
  • a light emitting element having a double-sided emission (dual emission) structure that extracts light emission from both sides, and any light emitting element having an injection structure can be applied.
  • the light emitting element 4513 which is a display element, is electrically connected to the transistor 4010 provided in the pixel unit 4002.
  • the configuration of the light emitting element 4513 is a laminated structure of the first electrode layer 4030, the light emitting layer 4511, and the second electrode layer 4031, but is not limited to this configuration.
  • the configuration of the light emitting element 4513 can be appropriately changed according to the direction of the light extracted from the light emitting element 4513 and the like.
  • the partition wall 4510 is formed by using an organic insulating material or an inorganic insulating material.
  • a photosensitive resin material it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the side surface of the opening becomes an inclined surface formed with a continuous curvature.
  • the light emitting layer 4511 may be composed of a single layer or may be configured such that a plurality of layers are laminated.
  • a protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, water, carbon dioxide, etc. do not enter the light emitting element 4513.
  • the protective layer silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum nitride nitride, aluminum nitride oxide, DLC (Diamond Like Carbon) and the like can be formed.
  • a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. As described above, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material having high airtightness and little degassing so as not to be exposed to the outside air.
  • an ultraviolet curable resin or a thermosetting resin in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin can be used. , PVB (polyvinyl butyral), EVA (ethylene vinyl acetate) and the like can be used. Further, the filler 4514 may contain a desiccant.
  • the sealing material 4005 a glass material such as glass frit, a curable resin such as a two-component mixed resin that cures at room temperature, a photocurable resin, and a resin material such as a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.
  • an optical film such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate ( ⁇ / 4 plate, ⁇ / 2 plate), and a color filter is attached to the ejection surface of the light emitting element. It may be provided as appropriate. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment that can diffuse reflected light due to the unevenness of the surface and reduce reflection can be applied.
  • the light emitting element a microcavity structure
  • the reflection can be reduced and the visibility of the displayed image can be improved.
  • the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) for applying a voltage to the display element, the direction of the light to be taken out, the place where the electrode layer is provided, and Translucency and reflectivity may be selected according to the pattern structure of the electrode layer.
  • the first electrode layer 4030 and the second electrode layer 4031 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide.
  • a translucent conductive material such as tin oxide, indium zinc oxide, and indium tin oxide to which silicon oxide is added can be used.
  • first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium (Ti), Platinum (Pt), Aluminum (Al), Copper (Cu), Silver (Ag) and other metals, or alloys thereof, or their alloys. It can be formed from metal nitride using one or more.
  • the first electrode layer 4030 and the second electrode layer 4031 can be formed by using a conductive composition containing a conductive polymer (also referred to as a conductive polymer).
  • a conductive polymer also referred to as a conductive polymer.
  • a so-called ⁇ -electron conjugated conductive polymer can be used. Examples thereof include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer consisting of two or more kinds of aniline, pyrrole and thiophene or a derivative thereof.
  • the protection circuit is preferably configured by using a non-linear element.
  • a reliable display device can be provided. Further, by using the transistor shown in the above embodiment, the reliability of the display device can be further improved. Further, by using the transistor shown in the above embodiment, it is possible to provide a display device capable of increasing the definition and the area and having good display quality. In addition, it is possible to provide a display device with reduced power consumption.
  • a display module will be described as an example of a semiconductor device using the OS transistor described above.
  • the display module 6000 shown in FIG. 23 has a touch sensor 6004 connected to the FPC 6003, a display panel 6006 connected to the FPC 6005, a backlight unit 6007, a frame 6009, and a printed circuit board 6010 between the upper cover 6001 and the lower cover 6002. , Battery 6011.
  • the backlight unit 6007, battery 6011, touch sensor 6004, and the like may not be provided.
  • the semiconductor device can be used, for example, in an integrated circuit mounted on a touch sensor 6004, a display panel 6006, or a printed circuit board 6010.
  • the display device described above can be used for the display panel 6006.
  • the shape and dimensions of the upper cover 6001 and the lower cover 6002 can be appropriately changed according to the size of the touch sensor 6004, the display panel 6006, and the like.
  • the touch sensor 6004 can be used by superimposing a resistive film type or capacitance type touch sensor on the display panel 6006. It is also possible to add a touch sensor function to the display panel 6006. For example, it is possible to provide a touch sensor electrode in each pixel of the display panel 6006 and add a capacitance type touch panel function. Alternatively, it is also possible to provide an optical sensor in each pixel of the display panel 6006 and add the function of an optical touch sensor. If it is not necessary to provide the touch sensor 6004, the touch sensor 6004 can be omitted.
  • the backlight unit 6007 has a light source 6008.
  • a light source 6008 may be provided at the end of the backlight unit 6007, and a light diffusing plate may be used. Further, when a light emitting display device or the like is used for the display panel 6006, the backlight unit 6007 can be omitted.
  • the frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010 side, in addition to the protective function of the display panel 6006. Further, the frame 6009 may have a function as a heat radiating plate.
  • the printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal, a clock signal, and the like.
  • the power source for supplying electric power to the power supply circuit may be a battery 6011 or a commercial power source. When a commercial power source is used as the power source, the battery 6011 can be omitted.
  • members such as a polarizing plate, a retardation plate, and a prism sheet may be additionally provided in the display module 6000.
  • the semiconductor device can be used for a processor such as a CPU or GPU, or a chip.
  • FIG. 24 shows a specific example of a processor such as a CPU or GPU, or an electronic device provided with a chip according to one aspect of the present invention.
  • the GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signage), and large game machines such as pachinko machines.
  • digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be mentioned.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one aspect of the present invention may have an antenna.
  • the display unit can display images, information, and the like.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
  • the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • FIG. 24 shows an example of an electronic device.
  • FIG. 24A illustrates a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5100 has a housing 5101 and a display unit 5102, and as an input interface, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.
  • the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102.
  • Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
  • FIG. 24B illustrates a notebook type information terminal 5200.
  • the notebook-type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
  • the notebook-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
  • a smartphone and a notebook-type information terminal are taken as examples of electronic devices, respectively, as shown in FIGS. 24A and 24B, but information terminals other than the smartphone and the notebook-type information terminal can be applied.
  • information terminals other than smartphones and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop-type information terminals, workstations, and the like.
  • FIG. 24C shows a portable game machine 5300, which is an example of a game machine.
  • the portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like.
  • the housing 5302 and the housing 5303 can be removed from the housing 5301.
  • the connection unit 5305 provided in the housing 5301 to another housing (not shown)
  • the image output to the display unit 5304 can be output to another video device (not shown). it can.
  • the housing 5302 and the housing 5303 can each function as operation units. This allows a plurality of players to play the game at the same time.
  • the chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
  • FIG. 24D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
  • a low power consumption game machine can be realized by applying the GPU or chip of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5300.
  • Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
  • the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one player can play the game. You can play games.
  • FIGS. 24C and 24D a portable game machine and a stationary game machine are illustrated as examples of the game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like. Can be mentioned.
  • the GPU or chip of one aspect of the present invention can be applied to a large computer.
  • FIG. 24E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 24F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
  • the supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502.
  • the plurality of computers 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or chip described in the above embodiment can be mounted on the substrate.
  • the supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the heat generated by the chip is large.
  • the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • a supercomputer is illustrated as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the large-scale computer to which the GPU or chip of one aspect of the present invention is applied include a computer (server) that provides a service, a large-scale general-purpose computer (mainframe), and the like.
  • the GPU or chip of one aspect of the present invention can be applied to a moving vehicle and around the driver's seat of the vehicle.
  • FIG. 24G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body.
  • the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are shown.
  • the display panel 5701 to the display panel 5703 can provide various other information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like.
  • the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
  • the display panel 5701 to 5703 can also be used as a lighting device.
  • the field of view (blind spot) blocked by the pillars can be complemented. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
  • the chip can be used, for example, in an automatic driving system of an automobile.
  • the chip can be used in a system for road guidance, danger prediction, and the like.
  • the display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects may include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, a system using artificial intelligence can be provided.
  • FIG. 24H shows an electric freezer / refrigerator 5800 which is an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 having artificial intelligence can be realized.
  • the electric freezer / refrigerator 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800 and the expiration date of the foodstuffs, and is stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the food.
  • the electric refrigerator / freezer has been described as an example of electric appliances, but other electric appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic device described in the present embodiment the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
  • sample 1A, sample 1B, sample 1C, sample 1D, sample 1E, sample 1F, sample 1G, and sample 1H were prepared and TDS analysis was performed.
  • Samples 1A to 1D include a substrate 900, an insulator 902 on the substrate 900, an insulator 904 containing excess oxygen on the insulator 902, an oxide semiconductor 906 on the insulator 904 containing excess oxygen, and oxidation. It has a metal layer 908 on the material semiconductor 906.
  • Samples 1E to 1H include a substrate 900, an insulator 902 on the substrate 900, an insulator 904 containing excess oxygen on the insulator 902, an oxide semiconductor 906 on the insulator 904 containing excess oxygen, and oxidation. It has an oxide 907 on a physical semiconductor 906 and a metal layer 908 on the oxide 907. As the oxide 907, an oxide of an element having a smaller Gibbs energy of the Ellingham diagram than the oxide semiconductor 906 was used.
  • Samples 1B to 1D and Samples 1E to 1H have metal layers 908 having different materials and film forming methods.
  • the table below shows the presence or absence of oxide 907 in each sample, the material of the metal layer 908, and the film forming method.
  • sample 1A has a structure shown in FIG. 25A without a metal layer 908. Further, the sample 1E has a structure shown in FIG. 25B without a metal layer 908.
  • a silicon substrate was prepared as the substrate 900. Subsequently, a thermal oxide film of 100 nm was formed on the substrate 900 as an insulator 902.
  • a silicon nitride film having a diameter of 300 nm was formed by using a plasma CVD method.
  • silane (SiH 4 ) having a flow rate of 2.3 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the pressure in the reaction chamber was 40 Pa
  • the film formation temperature was 400 ° C.
  • a high frequency (RF) power of 50 W (27.12 MHz) was applied to form a film.
  • oxygen ions 16 O
  • the oxygen ion injection conditions were an accelerating voltage of 60 kV and a dose amount of 2.0 ⁇ 10 16 ions / cm 2 .
  • an In-Ga-Zn oxide was formed by a sputtering method.
  • the oxide semiconductor 906 has a two-layer structure.
  • As the second layer oxide semiconductor 906, an In-Ga-Zn oxide having a film thickness of 15 nm was formed using a target of In: Ga: Zn 4: 2: 4.1 [atomic number ratio].
  • a silicon oxide film having a film thickness of 10 nm was formed as an oxide 907 on the oxide semiconductor 906.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 200 Pa, setting the film forming temperature to 350 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • the metal layer 908 shown in the above table was formed as the metal layer 908 on the oxide semiconductor 906, respectively. Further, in Samples 1F to 1H, the metal layer 908 shown in the above table was formed as the metal layer 908 on the oxide 907, respectively.
  • the substrate not subjected to the heat treatment (before heating).
  • a substrate showing the state) and a substrate subjected to heat treatment assuming a treatment involving heating (a substrate showing the state after heating) were prepared.
  • As the heat treatment a heat treatment at 400 ° C. for 4 hours was performed in a nitrogen atmosphere.
  • the sample of this example was prepared by the above steps.
  • FIG. 26A shows the amount of oxygen (O 2 ) released [pieces / cm 2 ] when Samples 1A to 1D are heated to 500 ° C. Therefore, in FIG. 26A, the vertical axis is the amount of oxygen (O 2 ) released [pieces / cm 2 ]. Samples 1B to 1D indicate the amount of oxygen (O 2 ) released before and after the heat treatment [pieces / cm 2 ].
  • FIG. 26B shows the amount of oxygen (O 2 ) released [pieces / cm 2 ] when Samples 1E to 1H are heated to 500 ° C. Therefore, in FIG. 26B, the vertical axis is the amount of oxygen (O 2 ) released [pieces / cm 2 ]. Samples 1F to 1H indicate the amount of oxygen (O 2 ) released before and after the heat treatment [pieces / cm 2 ].
  • the lower limit of the temperature range was the temperature at which degassing could be confirmed (about 40 ° C or higher). Therefore, the amount released below the lower limit of measurement is not included.
  • an oxide of an element having a relatively large generated Gibbs energy corresponding to an oxide semiconductor 906
  • an oxide of an element having a relatively small produced Gibbs energy corresponding to an oxide 907
  • the transfer of oxygen from the oxide of the element having a small generated Gibbs energy to the oxide of the element having a large produced Gibbs energy is suppressed.
  • the metal layer 908 absorbs excess oxygen of the insulator 904 via the oxide semiconductor 906 by heat treatment.
  • the oxide 907 between the oxide semiconductor 906 and the metal layer 908 the excess oxygen of the insulator 904 can be suppressed from moving to the metal layer 908.
  • a film with excess oxygen a film that suppresses the diffusion of oxygen, an oxide film of an element that produces an Eringham diagram with a smaller Gibbs energy than an oxide semiconductor, a film containing an oxide semiconductor, and a film that absorbs oxygen. It was found that the structure in which the layers are laminated in order can suppress the absorption of excess oxygen in the film having excess oxygen with respect to the film absorbing oxygen.
  • a semiconductor device having a plurality of regions having a plurality of transistors 200 shown in FIG. 1 (hereinafter referred to as a transistor formation region) was manufactured, and the electrical characteristics of an arbitrary transistor 200 were measured.
  • the density of the transistors 200 in the transistor forming region was set to 2.9 / ⁇ m 2 .
  • the channel length of the transistor 200 was designed to be 60 nm, and the channel width was designed to be 60 nm.
  • the transistor 200 shown in FIG. 1 produced in this example was used as sample 2A. Further, as a comparative example, in the transistor 200 shown in FIG. 1, a semiconductor device in which transistors having a structure not provided with a metal oxide 226 were arranged in the same layout as sample 2A was produced and used as sample 2B.
  • the conductor 205 was formed by forming a tungsten film by a sputtering method and processing it.
  • a hafnium oxide film having a film thickness of 20 nm was formed by the ALD method.
  • a silicon oxynitride film having a film thickness of 30 nm was formed as the insulator 224.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 40 Pa, setting the film forming temperature to 400 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • An aluminum oxide film having a film thickness of 3 nm was formed as the metal oxide 226.
  • excess oxygen was injected into the insulator 224 by forming an oxide film in an atmosphere containing oxygen using a sputtering method.
  • the aluminum oxide film was formed by a sputtering method in a mixed atmosphere of oxygen (O 2 ) and argon (Ar) using a target of Al 2 O 3 . Further, the pressure in the reaction chamber was 0.4 Pa, the film formation temperature was 250 ° C., and the film formation power was 2.5 kW (RF).
  • the oxide 230b has a laminated structure consisting of two layers.
  • the first oxide 230b and the second oxide 230b were continuously formed into a film.
  • the oxide 230c has a laminated structure consisting of two layers.
  • the first oxide 230c and the second oxide 230c were continuously formed into a film.
  • a silicon oxide film having a film thickness of 10 nm was formed as the insulator 250.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 200 Pa, setting the film forming temperature to 350 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • the conductor 260 was formed by continuously forming a titanium nitride film and a tungsten film by a CVD method and processing them.
  • Transistor 200 was manufactured from the above steps.
  • FIG. 28 shows the cross-sectional STEM observation results of sample 2A. As shown in FIG. 28, it was found that a structure in which the insulator 224 and the oxide 230b are not in contact with each other and the oxide 230c and the insulator 224 are in direct contact with each other can be produced.
  • the electrical characteristics of the transistor arranged in the center of the region and the transistor arranged at the end of the region include the Id-Vg characteristic and the field effect mobility (hereinafter collectively referred to as electricity). (Also called characteristic) was measured.
  • FIG. 27 shows the initial characteristics of the Id-Vg characteristics of the transistors arranged in each region in each sample and the field effect mobility.
  • the conductivity when the potential applied to the conductor 260 of the transistor 200 (hereinafter, also referred to as the gate potential (Vg)) is changed from the first value to the second value.
  • the change in the current (hereinafter, also referred to as drain current (Id)) between the body 240a and the conductor 240b is measured.
  • a voltage which is the difference between the potential applied to the conductor 240a (hereinafter, also referred to as source potential Vs) and the potential applied to the conductor 240b (hereinafter, also referred to as drain potential Vd).
  • Vs potential applied to the conductor 240a
  • Vd potential applied to the conductor 240b
  • the potential of the conductor 205 (hereinafter, also referred to as back gate potential (Vbg)) that functions as the second gate electrode (back gate electrode) was set to 0.0 V.
  • the graph of electrical characteristics shows the Id when Vd is 1.2V and the Id when Vd is 0.1V.
  • the broken line indicates the electric field effect mobility.
  • the first vertical axis represents Id [A]
  • the second vertical axis represents field effect mobility ( ⁇ FE [cm 2 / Vs])
  • the horizontal axis represents Vg [V]. ..
  • the field effect mobility was calculated from the value measured with Vd set to 1.2V.
  • sample 2A good transistor characteristics could be obtained at both the central portion and the end portion of the transistor formation region.
  • sample 2B which is a comparative example, transistor characteristics could not be obtained in the central portion of the transistor formation region.
  • sample 2B it can be inferred that the excess oxygen of the insulator 224 was absorbed by the conductor 240 via the oxide 230b. That is, it is considered that in the sample 2B, the excess oxygen of the insulator 224 diffuses into the oxygen deficiency generated in the oxide 230, while the conductor 240 absorbs oxygen from the oxide 230.
  • sample 2B it is considered that the amount of oxygen extracted from the oxide 230 by the conductor 240 exceeds the amount of excess oxygen diffused from the insulator 224 to the oxide 230 in the central portion of the transistor forming region where the transistors are dense. .. Therefore, since the excess oxygen in the insulator 224 was insufficient, carriers were generated due to the oxygen deficiency generated in the oxide 230, and the transistor characteristics could not be obtained.
  • the excess oxygen amount of the insulator 224 per transistor is larger than that at the center of the transistor forming region. That is, the amount of oxygen extracted from the oxide 230 by the conductor 240 is equal to or less than the amount of excess oxygen diffused from the insulator 224 to the oxide 230, and the excess oxygen compensates for the oxygen deficiency generated in the oxide 230. The generation of carriers could be suppressed.
  • sample 2A has a structure in which the oxide 230b and the insulator 224 do not come into direct contact with each other. That is, the excess oxygen of the insulator 224 does not diffuse into the oxide 230b because the metal oxide 226 intervenes. Therefore, it was possible to suppress the oxidation of the conductor 240 due to the excess oxygen diffused through the oxide 230b.
  • the channel forming region of the transistor 200 (corresponding to the region where the oxide 230c and the oxide 230b overlap) has an excess contained in the insulator 224 via the oxide 230c in contact with the insulator 224.
  • transistor characteristics could be obtained even in the central part of the transistor formation region where the transistors are dense. That is, in the oxide 230b, the diffusion of excess oxygen contained in the insulator 224 to the region overlapping with the conductor 240 is suppressed, so that the excess oxygen contained in the insulator 224 is insufficient even in the region where the transistors are dense. There wasn't. Further, it is considered that the oxygen deficiency could be compensated by efficiently supplying excess oxygen to the channel formation region of the transistor 200.
  • the semiconductor device having this structure can have a high degree of freedom in design.
  • the metal oxide 226 it is possible to suppress variations in the electrical characteristics of the transistor 200 having the oxide 230 functioning as an oxide semiconductor. Further, it can be inferred that the electrical characteristics of the transistor 200 having the oxide 230 functioning as an oxide semiconductor can be controlled by arranging the metal oxide 226.
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
  • transistor forming regions a semiconductor device having a plurality of regions having a plurality of transistors 200 shown in FIGS. 2 and 3 (hereinafter referred to as transistor forming regions) was manufactured, and the electrical characteristics of an arbitrary transistor 200 were measured.
  • the density of the transistors 200 in the transistor forming region was set to 2.0 / ⁇ m 2 .
  • the channel length of the transistor 200 was designed to be 60 nm, and the channel width was designed to be 60 nm.
  • the transistor 200 shown in FIG. 2 produced in this example was used as sample 3A. Further, the transistor 200 shown in FIG. 3 produced in this example was used as sample 3B.
  • sample preparation method The preparation method of the sample 3A and the sample 3B prepared in this example will be described below.
  • the conductor 205 was formed by forming a tungsten film by a sputtering method and processing it.
  • the insulator 222 formed a hafnium oxide film having a film thickness of 20 nm by the ALD method.
  • a silicon oxynitride film having a film thickness of 30 nm was formed as an insulator 224.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 40 Pa, setting the film forming temperature to 400 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • an aluminum oxide film having a film thickness of 3 nm was formed as a metal oxide 226.
  • excess oxygen was injected into the insulator 224 by forming an oxide film in an atmosphere containing oxygen using a sputtering method.
  • the aluminum oxide film was formed by a sputtering method in a mixed atmosphere of oxygen (O 2 ) and argon (Ar) using a target of Al 2 O 3 . Further, the pressure in the reaction chamber was 0.4 Pa, the film formation temperature was 250 ° C., and the film formation power was 2.5 kW (RF).
  • an aluminum oxide film having a film thickness of 3 nm was formed as a film 227 that suppresses the diffusion of excess oxygen.
  • excess oxygen was injected into the insulator 224 by forming an oxide film in an atmosphere containing oxygen using a sputtering method.
  • the aluminum oxide film was formed by a sputtering method in a mixed atmosphere of oxygen (O 2 ) and argon (Ar) using a target of Al 2 O 3 . Further, the pressure in the reaction chamber was 0.4 Pa, the film formation temperature was 250 ° C., and the film formation power was 2.5 kW (RF).
  • a silicon oxynitride film having a thickness of 5 nm was formed as an insulator 228 on the film 227 that suppresses the diffusion of excess oxygen.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 40 Pa, setting the film forming temperature to 400 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • the oxide 230b had a laminated structure consisting of two layers.
  • the first oxide 230b and the second oxide 230b were continuously formed into a film.
  • the oxide 230c had a laminated structure consisting of two layers.
  • the first oxide 230c and the second oxide 230c were continuously formed into a film.
  • a silicon oxide film having a film thickness of 10 nm was formed as an insulator 250.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 200 Pa, setting the film forming temperature to 350 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • the conductor 260 was formed by continuously forming a titanium nitride film and a tungsten film by a CVD method and processing them.
  • Sample 3A and Sample 3B were heat-treated at 400 ° C. for 4 hours in an atmosphere containing nitrogen.
  • Sample 3A and Sample 3B having the transistor 200 were prepared.
  • FIG. 29 shows the initial characteristics of the Id-Vg characteristics of the transistors arranged in each region in each sample and the field effect mobility.
  • the conductivity when the potential applied to the conductor 260 of the transistor 200 (hereinafter, also referred to as the gate potential (Vg)) is changed from the first value to the second value.
  • the change in the current (hereinafter, also referred to as drain current (Id)) between the body 240a and the conductor 240b is measured.
  • a voltage which is the difference between the potential applied to the conductor 240a (hereinafter, also referred to as source potential Vs) and the potential applied to the conductor 240b (hereinafter, also referred to as drain potential Vd).
  • Vs potential applied to the conductor 240a
  • Vd potential applied to the conductor 240b
  • the potential of the conductor 205 (hereinafter, also referred to as back gate potential (Vbg)) that functions as the second gate electrode (back gate electrode) was set to 0.0 V.
  • Id when Vd is 1.2V and Id when Vd is 0.1V are shown.
  • the vertical axis represents Id [A] and the horizontal axis represents Vg [V].
  • FIG. 29A shows the measurement result of sample 3A
  • FIG. 29B shows the measurement result of sample 3B. From the results shown in FIG. 29, it can be seen that good transistor characteristics were obtained for both Sample 3A and Sample 3B.
  • the semiconductor device having this structure can have a high degree of freedom in design.
  • the metal oxide 226 it is possible to suppress variations in the electrical characteristics of the transistor 200 having the oxide 230 functioning as an oxide semiconductor. Further, it can be inferred that the electrical characteristics of the transistor 200 having the oxide 230 functioning as an oxide semiconductor can be controlled by arranging the metal oxide 226.
  • the electrical characteristics of the transistor 200 having the oxide 230 that functions as an oxide semiconductor can be obtained. It is possible to suppress variation. Further, by arranging the insulator 228 on the film 227 that suppresses the diffusion of excess oxygen and the film 227 that suppresses the diffusion of excess oxygen, the electrical characteristics of the transistor 200 having the oxide 230 that functions as an oxide semiconductor can be improved. It could be inferred that it was possible to control it.
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
  • a semiconductor device having a plurality of regions having a plurality of transistors 200 shown in FIG. 2 (hereinafter referred to as a transistor forming region) was manufactured, and the electrical characteristics of an arbitrary transistor 200 were measured.
  • the density of the transistors 200 in the transistor forming region was set to 2.0 / ⁇ m 2 .
  • the channel length of the transistor 200 was designed to be 60 nm, and the channel width was designed to be 60 nm.
  • the transistor 200 shown in FIG. 2 produced in this example was used as sample 4A and sample 4B.
  • Sample 4A and Sample 4B have different structures of plugs (conductor 246 shown in FIG. 11) that are electrically connected to the transistor 200. Specifically, in sample 4B, an insulator 247 was provided between the insulator 224 and the insulator 280 having excess oxygen and the conductor 246 and the conductor 248. On the other hand, in sample 4A, the insulator 247 was not provided.
  • sample preparation method The preparation method of the sample 4A and the sample 4B prepared in this example will be described below.
  • the conductor 205 was formed by forming a tungsten film by a sputtering method and processing it.
  • a hafnium oxide film having a film thickness of 20 nm was formed as an insulator 222 by the ALD method.
  • a silicon oxynitride film having a film thickness of 30 nm was formed as an insulator 224.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 40 Pa, setting the film forming temperature to 400 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • an aluminum oxide film having a film thickness of 3 nm was formed as a metal oxide 226.
  • excess oxygen was injected into the insulator 224 by forming an oxide film in an atmosphere containing oxygen using a sputtering method.
  • the aluminum oxide film was formed by a sputtering method in a mixed atmosphere of oxygen (O 2 ) and argon (Ar) using a target of Al 2 O 3 . Further, the pressure in the reaction chamber was 0.4 Pa, the film formation temperature was 250 ° C., and the film formation power was 2.5 kW (RF).
  • the oxide 230b had a laminated structure composed of two layers.
  • the first oxide 230b and the second oxide 230b were continuously formed into a film.
  • the oxide 230c had a laminated structure consisting of two layers.
  • the first oxide 230c and the second oxide 230c were continuously formed into a film.
  • a silicon oxide film having a film thickness of 10 nm was formed as an insulator 250.
  • silane (SiH 4 ) having a flow rate of 1 sccm and nitrous oxide (N 2 O) having a flow rate of 800 sccm were used.
  • the film was formed by setting the pressure in the reaction chamber to 200 Pa, setting the film forming temperature to 350 ° C., and applying high frequency (RF) power of 150 W (60 MHz).
  • the conductor 260 was formed by continuously forming a titanium nitride film and a tungsten film by a CVD method and processing them.
  • sample 4B an aluminum oxide film having a film thickness of 13 nm was formed as an insulator 247 by the ALD method. Subsequently, a part of the aluminum oxide film was removed to expose the conductor 240a and the conductor 240b.
  • the conductor 246 was formed by continuously forming a titanium nitride and a tungsten film by a CVD method and processing them.
  • Sample 4A and Sample 4B were heat-treated at 400 ° C. for 4 hours in an atmosphere containing nitrogen.
  • Sample 4A and Sample 4B having the transistor 200 were prepared.
  • FIG. 30 shows the initial characteristics of the Id-Vg characteristics of the transistors arranged in each region in each sample and the field effect mobility.
  • the conductivity when the potential applied to the conductor 260 of the transistor 200 (hereinafter, also referred to as the gate potential (Vg)) is changed from the first value to the second value.
  • the change in the current (hereinafter, also referred to as drain current (Id)) between the body 240a and the conductor 240b is measured.
  • a voltage which is the difference between the potential applied to the conductor 240a (hereinafter, also referred to as source potential Vs) and the potential applied to the conductor 240b (hereinafter, also referred to as drain potential Vd).
  • Vs potential applied to the conductor 240a
  • Vd potential applied to the conductor 240b
  • the potential of the conductor 205 (hereinafter, also referred to as back gate potential (Vbg)) that functions as the second gate electrode (back gate electrode) was set to 0.0 V.
  • Id when Vd is 1.2V and Id when Vd is 0.1V are shown.
  • the vertical axis represents Id [A] and the horizontal axis represents Vg [V].
  • FIG. 30A shows the measurement result of sample 4A
  • FIG. 30B shows the measurement result of sample 4B. From the results shown in FIG. 30, it can be seen that good transistor characteristics were obtained for both Sample 4A and Sample 4B.
  • excess oxygen can be efficiently supplied to the channel formation region of the transistor 200. Further, in the structure, the amount of excess oxygen to be supplied to the channel forming region can be controlled by the film thickness of the insulator 224 and the film forming conditions. Therefore, the electrical characteristics of the transistor 200 are not affected by the process of the transistor 200, and the semiconductor device having this structure can have a high degree of freedom in design.
  • the metal oxide 226 it is possible to suppress variations in the electrical characteristics of the transistor 200 having the oxide 230 functioning as an oxide semiconductor. Further, it can be inferred that the electrical characteristics of the transistor 200 having the oxide 230 functioning as an oxide semiconductor can be controlled by arranging the metal oxide 226.
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
  • 200 Transistor, 205: Conductor, 210: Insulator, 211: Substrate, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 226: Metal oxide, 227: A film that suppresses the diffusion of excess oxygen, 228: Insulator, 230: Oxide, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 240: Conductor, 240a: Conductor, 240A: Conductive, 240b: Conductor, 240B: Conductive layer, 246: Conductor, 246a: Conductor, 246b: Conductor, 247: Insulator, 248: Conductor, 250: Insulator, 250A: Insulation film, 260: Conductor, 260a: Conductor, 260A: Conductor, 260b: Conductor, 260B: Conductor, 274: Insulator, 280: Insulator, 282: Insulator

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  • Liquid Crystal (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electroluminescent Light Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)
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