WO2020186414A1 - 时间数字转换电路及相关方法 - Google Patents

时间数字转换电路及相关方法 Download PDF

Info

Publication number
WO2020186414A1
WO2020186414A1 PCT/CN2019/078448 CN2019078448W WO2020186414A1 WO 2020186414 A1 WO2020186414 A1 WO 2020186414A1 CN 2019078448 W CN2019078448 W CN 2019078448W WO 2020186414 A1 WO2020186414 A1 WO 2020186414A1
Authority
WO
WIPO (PCT)
Prior art keywords
oscillator
signal
counting
time
circuit
Prior art date
Application number
PCT/CN2019/078448
Other languages
English (en)
French (fr)
Inventor
黄彦颖
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201980000430.4A priority Critical patent/CN110088696B/zh
Priority to EP19920363.9A priority patent/EP3828647B1/en
Priority to PCT/CN2019/078448 priority patent/WO2020186414A1/zh
Priority to JP2020561796A priority patent/JP7137636B2/ja
Priority to US17/009,484 priority patent/US11309899B2/en
Publication of WO2020186414A1 publication Critical patent/WO2020186414A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H03L7/145—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop the switched reference signal being derived from the controlled oscillator output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
    • H03L7/148—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal said digital means comprising a counter or a divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/504—Analogue/digital converters with intermediate conversion to time interval using pulse width modulation
    • H03M1/508—Analogue/digital converters with intermediate conversion to time interval using pulse width modulation the pulse width modulator being of the self-oscillating type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

Definitions

  • This application relates to a digital conversion circuit and related methods.
  • the commonly used methods are usually divided into optical and ultrasonic methods. Regardless of whether the final selection is optical or ultrasonic, a circuit is needed to detect the time signal, and the resolution and cost of this circuit are more important in design. Factors to consider.
  • One of the objectives of this application is to disclose a time-to-digital conversion circuit and related methods to solve the above-mentioned problems.
  • An embodiment of the present application discloses a time-to-digital conversion circuit, including a first oscillator, a second oscillator, a first counting circuit, a second counting circuit, a first conversion circuit, and a processing circuit.
  • the first oscillator is activated by a first signal and includes a plurality of oscillation units with a first delay amount, wherein a first initial oscillation unit of the plurality of oscillation units in the first oscillator receives the The first signal and the first end output signal, and the first end oscillating unit of the plurality of oscillating units in the first oscillator is used to generate the first end output signal.
  • the first counting circuit is coupled to the first oscillator, and is used for counting the number of times the first end output signal changes, and storing the counting times as a first counting result.
  • the second counting circuit is coupled to the first oscillator, and is used to count the outputs of the remaining oscillation units except the first end oscillation unit each time the output of the first initial oscillation unit changes Change the number of oscillation units, and store the number of oscillation units as the second counting result.
  • the second oscillator is coupled to the first oscillator through the first counting circuit and the second counting circuit, and the second oscillator is activated by a second signal.
  • the first conversion circuit is coupled to the first oscillator and the second oscillator, and is configured to depend on the first delay amount and the first stored when the second oscillator is activated
  • a counting result and the second counting result are used to generate a first conversion signal, wherein the first conversion signal indicates a first estimated time difference.
  • the processing circuit is configured to generate an output signal according to at least a first conversion signal, wherein the output signal represents a measured time difference between the activation time of the first signal and the activation time of the second signal.
  • the time-to-digital conversion circuit disclosed in this application even if the first oscillator only includes a limited number of oscillating units, as long as the oscillating unit continues to oscillate, the first counting circuit and the second counting circuit will continue to calculate The number of times the oscillating unit in the first oscillator oscillates. In this way, the time-to-digital conversion circuit proposed in the present application will not need to consume a large amount of area to implement the oscillator, and will be able to achieve the same purpose. Reduce production costs and power consumption.
  • An embodiment of the present application discloses a time-to-digital conversion method, which includes transmitting a first signal to activate a first oscillator.
  • the first oscillator includes a plurality of oscillation units with a first delay.
  • the first oscillator The first initial oscillation unit of the plurality of oscillation units in the first oscillator receives the first signal and the first end output signal, and the first end oscillation unit of the plurality of oscillation units in the first oscillator is used for To generate the first end output signal; transmit a second signal to activate the second oscillator; count the number of times the first end output signal changes, and store the number of counts as the first count result; count when the first end When the output of an initial oscillation unit changes, the output of the remaining oscillation units except the first end oscillation unit changes the number of oscillation units, and the number of oscillation units is stored as the second count result; according to the first end oscillation unit A delay amount and the first counting result and the second counting result stored when the second oscillator is activated to generate
  • FIG. 1 is a schematic diagram of a time-to-digital conversion circuit according to the first embodiment of the present application.
  • FIG. 2 is a schematic diagram of the output of the first oscillator and the oscillation unit according to an embodiment of the present application.
  • Fig. 3 is a schematic diagram of a time-to-digital conversion circuit according to a second embodiment of the present application.
  • FIG. 4 is a schematic diagram of output waveforms of the first oscillator and the second oscillator according to an embodiment of the present application.
  • Fig. 5 is a schematic diagram of a time-to-digital conversion circuit according to a third embodiment of the present application.
  • FIG. 6 is a schematic diagram of the operation of the detection circuit according to an embodiment of the present application.
  • FIG. 7 is a flowchart of a time-to-digital conversion method according to an embodiment of the present application.
  • first and second features are in direct contact with each other; and may also include
  • additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact.
  • present disclosure may reuse component symbols and/or labels in multiple embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not in itself represent the relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms here such as “below”, “below”, “below”, “above”, “above” and similar, may be used to facilitate the description of the drawing
  • the relationship between one component or feature relative to another component or feature is shown.
  • these spatially relative terms also cover a variety of different orientations in which the device is in use or operation.
  • the device may be placed in other orientations (for example, rotated by 90 degrees or in other orientations), and these spatially-relative description words should be explained accordingly.
  • FIG. 1 is a schematic diagram of a time-to-digital conversion circuit 100 according to the first embodiment of the present application.
  • the time-to-digital conversion circuit 100 includes a first oscillator 110, a second oscillator 120, a first counting circuit 130, a second counting circuit 140, a first conversion circuit 150 and a processing circuit 160.
  • the first oscillator 110 may be a ring oscillator.
  • the first oscillator 110 includes N oscillating units, where N is an integer greater than 1, and in this embodiment, N is an odd number.
  • the N oscillating units in the first oscillator 110 all have a first delay amount D1, and include a first initial oscillating unit 11, a first end oscillating unit 13, and coupled to the first initial oscillating unit 11 and the first end A plurality of (ie N-2) oscillating units 12 between the oscillating units 13.
  • the first ring oscillation unit 110 is activated by the first signal S1.
  • the initial oscillation unit is defined as an oscillation unit for receiving the first signal S1 (ie, the first initial oscillation unit 11), and the end oscillation unit is defined as its output The oscillation unit received by the initial oscillation unit (ie, the first end oscillation unit 13).
  • the first initial oscillation unit 11 receives the first signal S1 and the first end output signal SoN generated by the first end oscillation unit, and generates an output signal So1 to the oscillation unit 12.
  • the oscillating unit 12 receives the output signal So1 and generates the output signal So2 accordingly, and so on.
  • the second oscillator 120 may also be a ring oscillator, however, this is not in the limitation of this embodiment. Relative to the first oscillator 110, the second oscillator 120 is activated by the second signal S2.
  • the first counting circuit 130 is used to count the number of times the first end output signal SoN changes, and to store the number of counts as the first counting result CN1. In detail, when the first end output signal SoN transitions from the logic value “0” to the logic value “1”, the first counting result CN1 generated by the first counting circuit 130 is increased by 1. Similarly, when the first end When the output signal SoN transitions from the logic value “1” to the logic value “0”, the first counting result CN1 generated by the first counting circuit 130 is increased by 1.
  • the second counting circuit 140 is used to count the outputs of the remaining oscillation units except the first end oscillation unit 13 (ie, the first initial oscillation unit 11 and multiple oscillation units 12) each time the output of the first initial oscillation unit 11 changes Change the number of oscillation units, and store the number of oscillation units as the second counting result CN2.
  • the first oscillator 110 continues to oscillate, the outputs of the multiple oscillating units in the first oscillator 110 continue to change.
  • the first end output signal SoN changes, it means that the signal change has completed one circle.
  • the first counting result CN1 generated by the counting circuit 130 will be incremented by 1, and the second counting result CN2 will be reset.
  • the output signal So1 will continue to change accordingly.
  • the second counting result CN2 generated by the second counting circuit 140 will indicate 1; then, because the output signal So1 changes, Correspondingly, the output signal So2 will continue to change.
  • the second counting result CN2 generated by the second counting circuit 140 will be indicated as 2, and so on, until the first end output signal SoN changes again.
  • the first counting result CN1 generated by the counting circuit 130 will be incremented by 1, and the second counting result CN2 will be reset.
  • the output signal So1 continuously changes again.
  • the second counting result CN2 generated by the second counting circuit 140 will be indicated as 1 again.
  • first counting circuit 130 and the second counting circuit 140 may respectively include storage circuits for storing the first counting result CN1 and the second counting result CN2 respectively.
  • the storage circuit may also be designed outside of the first counting circuit 130 and the second counting circuit 140. In other words, the storage circuit and the first counting circuit 130 and the second counting circuit 140 may be Independent setting.
  • the first conversion circuit 150 When the second oscillator 120 is activated by the second signal S2, the first counting circuit 130 and the second counting circuit 140 will be triggered at the same time to transmit the first counting result CN1 and the second counting result CN2 stored at this time to the first Conversion circuit 150.
  • the first conversion circuit 150 generates a first conversion signal TS1 according to the first delay amount D1 and the received first counting result CN1 and second counting result CN2, wherein the first conversion signal TS1 is used to indicate the activation of the first signal S1
  • the processing circuit 160 is configured to generate an output signal OUT according to at least the first conversion signal TS1, where the output signal OUT represents the measured time difference between the activation time of the first signal S1 and the activation time of the second signal S2.
  • the integrator requires a higher level of circuit architecture, so the integrator occupies a relatively large area to realize the required circuit, but such a design method will make the entire hardware cost too high, and at the same time, it requires high resolution
  • the difference between the delay amounts of the two oscillators will also have a large deviation ratio. Since the time-to-digital conversion circuit 100 proposed in the present application properly designs the first oscillator 110, the first counting circuit 130, and the second counting circuit 140, the oscillation signal is continuously circulated in the first oscillator 110 and passed through the first oscillator 110.
  • a counting circuit 130 and a second counting circuit 140 obtain the number of times the output of the oscillating unit in the first oscillator 110 has changed, so the time difference between the activation time of the first signal S1 and the activation time of the second signal S2 does not need to be too large.
  • the circuit architecture saves design cost and power consumption.
  • FIG. 2 is a schematic diagram of a first oscillator 200 according to an embodiment of the present application, where the first oscillator 200 of this embodiment can be used to implement the first oscillator 110.
  • the first oscillator 200 may be a ring oscillator.
  • the first oscillator 200 includes a NAND gate 21 and a plurality of inverters 22, 23, 24, 25, wherein the NAND gate 21 may be used to implement the first oscillator 110
  • the first initial oscillating unit 11, inverters 22, 23, 24 in the first oscillator 110 can be used to implement multiple oscillating units 12 in the first oscillator 110, and the inverter 25 can be used to implement the first end of the first oscillator 110.
  • Oscillation unit 13 is a schematic diagram of a first oscillator 200 according to an embodiment of the present application, where the first oscillator 200 of this embodiment can be used to implement the first oscillator 110.
  • the first oscillator 200 may be a ring oscillator.
  • the first oscillator 200
  • the NOT AND gate 21 receives the first signal S1 and the first terminal output signal So5 generated by the inverter 25, and generates the output signal So1 accordingly; the inverter 22 receives the output signal So1, and generates the output signal So2 accordingly; The phaser 23 receives the output signal So2 and generates the output signal So3 accordingly; the inverter 24 receives the output signal So3 and generates the output signal So4 accordingly; the inverter 25 receives the output signal So4 and generates the first end output accordingly Signal So5.
  • the first counting result CN1 generated by the first counting circuit 130 in FIG. 1 indicates When the first end output signal So5 transitions for the first time, the output signal So1, the output signal So2, the output signal So3, and the output signal So4 all change (transition), so the second counting circuit 140 generates The second counting result CN2 indicates 4.
  • the first conversion circuit 150 in FIG. 1 Since the first oscillator 200 includes 5 oscillating units, the first conversion circuit 150 in FIG. 1 generates the first conversion signal TS1 according to the first delay amount D1, the first counting result CN1, and the second counting result CN2.
  • the first estimated time difference indicated by the first conversion signal TS1 can be expressed as (1*5+4)*D1.
  • FIG. 3 is a schematic diagram of a time-to-digital conversion circuit 300 according to the second embodiment of the present invention.
  • the time-to-digital conversion circuit 300 is similar to the time-to-digital conversion circuit 100, and also includes a first oscillator 110, a first counting circuit 130, a second counting circuit 140, and a first conversion circuit 150.
  • the operation of the above circuit has been described in FIG. 1 and FIG. 2 embodiments, so the similarities will be omitted here to save space.
  • the time-to-digital conversion circuit 300 also includes a second oscillator 320, a third counting circuit 350, a fourth counting circuit 360, a second conversion circuit 380, and a processing circuit 390.
  • the second oscillator may be a ring oscillator, including N oscillating units, where N is a whole statement greater than 1.
  • the N oscillation units all have a second delay amount D2, and include a second initial oscillation unit 31, a second end oscillation unit 33, and are coupled between the second initial oscillation unit 31 and the second end oscillation unit 33 The number of oscillation units 32.
  • the second ring oscillating unit 320 is activated by the second signal S2.
  • the second initial oscillating unit 31 receives the second signal S2 and the second end output signal SoN' generated by the second end oscillating unit 33, and generates an output The signal So1' to the oscillating unit 32.
  • the oscillating unit 32 receives the output signal So1' and generates the output signal So2' accordingly, and so on.
  • the number of oscillating units in the second oscillator 320 should be an odd number to generate an oscillating signal.
  • the third counting circuit 350 is used to count the number of times the second end output signal SoN' changes, and to store the counted times as the third counting result CN3.
  • the third counting result CN3 generated by the third counting circuit 350 is increased by 1; similarly, when the second When the terminal output signal SoN' transitions from the logic value '1' to the logic value '0', the third counting result CN3 generated by the third counting circuit 350 is increased by 1.
  • the fourth counting circuit 360 is used to count the remaining oscillation units except the second end oscillation unit 33 (that is, the second initial oscillation unit 31 and the plurality of oscillation units 32 each time the output of the second initial oscillation unit 31 changes). ) Output the number of oscillation units changed, and store the number of oscillation units as the fourth counting result CN4.
  • the outputs of the multiple oscillating units in the second oscillator 320 continue to change.
  • the third counting result CN3 generated by the three counting circuit 350 will increase by one. Later, as the second end output signal SoN' changes, the output signal So1' will continue to change accordingly.
  • the fourth counting result CN4 generated by the fourth counting circuit 360 will indicate 1; then, due to the output signal So1' Correspondingly, the output signal So2' will continue to change. At this time, the fourth counting result CN4 produced by the fourth counting circuit 360 will be indicated as 2, and so on, until the second end output signal SoN' changes again.
  • the third counting result CN3 generated by the third counting circuit 350 will increase by one.
  • the output signal So1' continues to change again.
  • the fourth counting result CN4 generated by the fourth counting circuit 360 will be indicated as 1 again.
  • the third counting circuit 350 and the fourth counting circuit 360 may respectively include storage circuits for storing the third counting result CN3 and the fourth counting result CN4 respectively.
  • the storage circuit may also be designed in addition to the third counting circuit 350 and the fourth counting circuit 360.
  • the storage circuit, the third counting circuit 350 and the fourth counting circuit 360 may be Independent setting.
  • the third counting circuit 350 may be realized by the first counting circuit 130
  • the fourth counting circuit 360 may be realized by the second counting circuit 140.
  • the first counting circuit 130 is used to count the number of times the second end output signal SoN' changes, and store the counted times as the third counting result CN3.
  • the second counting circuit 140 is used to count the remaining oscillation units except the second end oscillation unit 33 (that is, the second initial oscillation unit 31 and the multiple oscillation units 32 each time the output of the second initial oscillation unit 31 changes). ) Output the number of oscillation units changed, and store the number of oscillation units as the fourth counting result CN4.
  • the second conversion circuit 380 is used to generate the second conversion signal TS2 according to the first delay amount D1, the second delay amount D2, the third counting result CN3, and the fourth counting result CN4 after the second ring oscillator 320 is activated,
  • the second conversion signal TS2 indicates a second estimated time difference, and the second estimated time difference is less than the first delay amount D1.
  • the second conversion circuit 380 includes a logic circuit 381, wherein the logic circuit 381 is used to activate any of the oscillation units in the second oscillator 320, that is, the second initial oscillation
  • the logic circuit 381 is used to activate any of the oscillation units in the second oscillator 320, that is, the second initial oscillation
  • the output of an end oscillating unit 13 is logically operated according to the output of the multiple oscillating units in the first oscillator 110 and the output of the oscillating unit whose output changes in the second oscillator 320 to generate a logical result.
  • the detailed operations of the second conversion circuit 380 and the logic circuit 381 will be described in the following paragraphs. It should be noted that, in order
  • the processing circuit 390 is configured to generate an output signal OUT according to the first conversion signal TS1 and the second conversion signal TS2, where the output signal represents the measured time difference between the activation time of the first signal S1 and the activation time of the second signal S2. It should be noted that the first oscillator 200 shown in FIG. 2 can also be used to implement the second oscillator 320.
  • FIG. 4 is a schematic diagram of output waveforms of the first oscillator 110 and the second oscillator 320 according to an embodiment of the present application.
  • the second delay amount D2 is slightly larger than the first delay amount D1.
  • the first signal S1 is activated at time t1 and the second signal S2 is activated at time t2.
  • the second signal S2 is activated at time t2, after a second delay amount D2, the output signal So1 'Transition; and after a second delay amount D2, the output signal So2' transitions, and so on.
  • the falling edge dn1' is located after the rising edge up1 of the first end output signal So5 and before the falling edge dn1 of the output signal So1;
  • the first transition of the output signal So2' that is, when the rising edge up1' occurs, the rising edge up1' is located after the falling edge dn1 of the output signal So1 and is located at the rising edge up2 of the output signal So2 Previously, however, since the second delay amount D2 is slightly larger than the first delay amount D1, the distance between the rising edge up1' and the rising edge up2 is smaller than the distance between the falling edge dn1 and the falling edge dn1'.
  • the rising edge up3' of the output signal So1' is located after the rising edge up3 of the output signal So1.
  • the first delay amount D1 is the same as the second delay amount D2
  • the rising edge up3' of the output signal So1' should be located after the falling edge dn2 and before the rising edge up3.
  • the second delay amount D2 is slightly larger than the first delay amount D1 , Resulting in the rising edge up3' at the time point t4 retreating after the rising edge up3.
  • the third counting result CN3 and the fourth technical result CN4 will be transmitted to the second conversion circuit 380.
  • a total of 6*D2 has elapsed from points t2 to t4, and from time points t2 to t4, the first delay amount D1 passed by the first oscillator 110 is greater than the second delay amount D2 passed by the second oscillator 320 1.
  • the second conversion circuit 380 generates the second conversion signal TS2 according to the first delay amount D1, the second delay amount D2, the third counting result CN3, and the fourth counting result CN4, wherein the second conversion signal TS2 indicates the second conversion signal TS2.
  • the second estimated time difference can be expressed as (6+1)*D1-6*D2, and the second estimated time difference is the time difference from time t3 to t2.
  • the processing circuit 390 Since the first conversion signal TS1 is generated based on the first counting result CN1 and the second counting result CN2, the first estimated time difference indicated by the first conversion signal TS1 is calculated between the time points t1 and t3, and the second conversion signal The second estimated time difference indicated by TS2 is calculated between time points t2 and t3.
  • the processing circuit 390 generates the output signal OUT according to the first conversion signal TS1 and the second conversion signal TS2.
  • the second conversion circuit 380 determines that the rising edge up3' of the output signal So1' is located after the rising edge up3 of the output signal So1.
  • the corresponding logical values of the outputs of the multiple oscillation units of the first oscillator 110 that is, the output signals So1, So2, So3, So4 and the first end output signal So5
  • the logic circuit 381 receives the logic value '10101', it can be known by performing a logic operation on the logic value '10101' and the logic value '0' of the output signal So1'.
  • the first end output signal So5 The transition has just been performed and the output signal So1 has not yet completed the transition.
  • the number of 0s and 1s of the logical value '10101' integrated logical value '0' is the same, so it can be determined that the falling edge dn1' of the output signal So1' is located after the rising edge up1 of the first end output signal So5 and is located Before the falling edge dn1 of the output signal So1, a logic result is generated which indicates a certain logic value, such as a logic value of '0'.
  • the corresponding logical value of the output of the multiple oscillation units of the first oscillator 110 is '00101', and when the logic circuit 381 receives the logical value '00101', it transmits The logic value '00101' and the logic value '1' of the output signal So2' perform logical operations, and it can be known that at this time, the output signal So1 has just transitioned but the output signal So2 has not yet completed the transition.
  • the number of 0 and 1 of the logic value '00101' and the integrated logic value '1' is the same, so it can be determined that the rising edge up1' of the output signal So2' is located after the falling edge dn1 and before the rising edge up2, and generates The logical result indicates the logical value '0'.
  • the original rising edge up3' should be located between the falling edge dn2 and the rising edge up3 to obtain the corresponding logical value of the output of the multiple oscillation units of the first oscillator 110 as '01010', however Because the second delay amount D2 is slightly larger than the first delay amount D1, the rising edge up3' is located after the rising edge up3, and the logical value of the output of the multiple oscillation units of the corresponding first oscillator 110 is obtained as '11010', Therefore, the logic circuit 381 performs a logical operation on the logic value '11010' and the logic value '1' of the output signal So1', and it can be known that the rising edge up3' of the output signal So1' is located after the rising edge up3 of the output signal So1. For example, at this time, the number of 0s and 1s of the logical value '11010' integrated logical value '1' is different, and the logical result indicates different logical value '1'.
  • the second delay amount D2 is slightly larger than the first delay amount D1, however, this is not a limitation of the present application. In other embodiments, the second delay amount D2 is slightly smaller than the first delay amount D1, and the operations of the second conversion circuit 380 and the logic circuit 381 will be as described in the embodiment of FIG. 4, therefore, the detailed description is omitted here. space.
  • FIG. 5 is a schematic diagram of a time-to-digital conversion circuit 500 according to the third embodiment of the present invention.
  • the time-to-digital conversion circuit 500 is roughly the same as the time-to-digital conversion circuit. The only difference is that the time-to-digital conversion circuit 500 includes a detection circuit 510, which is coupled to the logic circuit 381 for when the logic result generated by the logic circuit 381 changes When adjusting the oscillation frequency of the second oscillator 320, the detailed function of the detection circuit 510 will be described in subsequent embodiments.
  • the detection circuit 510 may include an array of capacitors to couple the capacitors to the second oscillator 320 to adjust the oscillation frequency of the second oscillator 320.
  • FIG. 6 is a schematic diagram of the operation of the detection circuit 510 according to an embodiment of the present application.
  • the output signal So1' transitions, and the logic result determines that the rising edge up3' is located after the rising edge up3, and the detection circuit 510 therefore increases the oscillation frequency of the second oscillator 320, so that After a period of time, the rising edge up4' of the output signal So1' falls before the rising edge up4 of the output signal So1.
  • the detection circuit 510 can adjust the oscillation frequency of the second oscillator 320 so that the rising edge up4' is advanced by a fixed time difference tX, and since the second delay amount D2 and the first delay amount D1 remain unchanged, as described in the embodiment of FIG.
  • the logic circuit 381 determines when the output of the second oscillator 320 falls after the output of the first oscillator 110 again, and the second conversion circuit 380 is based on the A delay amount D1, a second delay amount D2, and the third counting result CN3 and the fourth counting result CN4 at this time can be used to determine the time difference tY between the time points t5 and t4. In this way, the generated second conversion signal TS2 will have a higher resolution.
  • the second conversion circuit 380 generates a second conversion signal TS2 according to the first delay amount D1, the second delay amount D2, the third counting result CN3, and the fourth counting result CN4, wherein the second The second estimated time difference indicated by the conversion signal TS2 can be expressed as (6+1)*D1-6*D2+tY, and the second estimated time difference is the time difference between time points t3 and t2.
  • FIG. 7 is a flowchart of a time-to-digital conversion method 700 according to an embodiment of the present application. If substantially the same result can be obtained, the present application does not limit the execution of the time-to-digital conversion method 700 completely in accordance with the process steps shown in FIG. 7.
  • the time-to-digital conversion method 700 is summarized as follows:
  • Step 702 Transmit a first signal to activate the first oscillator.
  • Step 704 Transmit a second signal to activate the second oscillator.
  • Step 706 Count the number of times the first end output signal changes, and store the count number as the first counting result.
  • Step 708 Count the number of oscillation units whose outputs of the remaining oscillation units except the first end oscillation unit change every time the output of the first initial oscillation unit changes, and store the number of oscillation units It is the second counting result.
  • Step 710 Generate a first conversion signal according to the first delay amount and the first counting result and the second counting result stored when the second oscillator is activated.
  • Step 712 Generate an output signal according to at least the first conversion signal.

Abstract

一种时间数字转换电路(100)包括第一振荡器(110)、第二振荡器(120)、第一计数电路(130)、第二计数电路(140)、第一转换电路(150)以及处理电路(160)。所述第一振荡器由第一信号激活，并包括具有第一延迟量的振荡单元，第一计数电路用于计数所述第一振荡器中第一末端输出信号改变的次数并储存为第一计数结果；第二计数电路计数除所述第一末端振荡单元外的其余振荡单元的输出改变的振荡单元个数并储存为第二计数结果；所述第一转换电路依据第一计数结果与第二计数结果产生第一转换信号；所述处理电路至少依据第一转换信号产生输出信号。

Description

时间数字转换电路及相关方法 技术领域
本申请涉及一种数字转换电路及相关方法。
背景技术
近来由于测距的发展，可应用在复杂如一整张画面的3-D测距；在量测系统中更是常见其踪影:包含测量液位，流速，流量，材质侦测，医疗超声波等等。
而在此背景下常见采用方法通常分为光学以及超声的方式，而不论最后选取的是光学式或超声式，都需要电路来侦测时间讯号，而此电路的分辨率以及成本更是设计上所需考虑的因素。
发明内容
本申请的目的之一在于公开一种时间数字转换电路以及相关方法，来解决上述问题。
本申请的一实施例公开了一种时间数字转换电路，包括第一振荡器、第二振荡器、第一计数电路、第二计数电路、第一转换电路及处理电路。所述第一振荡器由第一信号所激活，并包括多个具有第一延迟量的振荡单元，其中所述第一振荡器中的所述多个振荡单元中的第一起始振荡单元接收所述第一信号与第一末端输出信号，且所述第一振荡器中的所述多个振荡单元中的第一末端振荡单元用于产生所述第一末端输出信号。所述第一计数电路耦接至所述第一振荡器，且用于计数所述第一末端输出信号改变的次数，并且将计数次数储存为第一计数结果。所述第二计数电路耦接至所述第一振荡器，且用于当每次所述第一起始振荡单元的输出改变时，计数除所述第一末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述振荡单元个数储存为第二计数结果。所述第二振荡器透过所述第一计数电路及所述第二计数电路耦接至所述第一振荡器，且所述第二振荡器由第二信号所激活。所述第一转换电路耦接至所述第 一振荡器及所述第二振荡器，且用于依据所述第一延迟量以及当所述第二振荡器被激活时所储存的所述第一计数结果与所述第二计数结果来产生第一转换信号，其中所述第一转换信号指示第一预估时间差。所述处理电路用于至少依据第一转换信号产生输出信号，其中所述输出信号代表所述第一信号的激活时间与所述第二信号的激活时间的测量时间差。透过本申请所揭露的时间数字转换电路，即便所述第一振荡器仅仅包含有限数量的振荡单元，只要振荡单元持续振荡，所述第一计数电路及所述第二计数电路将持续计算所述第一振荡器中的振荡单元振荡的次数，如此一来，在能达到相同目的的情况下，本申请所提出的时间数字转换电路将不需要消耗大量的面积来实现振荡器，将可大幅降低生产成本及功率消耗。
本申请的一实施例公开了一种时间数字转换方法，包括传送第一信号激活第一振荡器，所述第一振荡器包括多个具有第一延迟量的振荡单元，所述第一振荡器中的所述多个振荡单元中的第一起始振荡单元接收所述第一信号与第一末端输出信号，所述第一振荡器中的所述多个振荡单元中的第一末端振荡单元用于产生所述第一末端输出信号；传送第二信号激活第二振荡器；计数所述第一末端输出信号改变的次数，并且将计数次数储存为第一计数结果；计数当每次所述第一起始振荡单元的输出改变时，除所述第一末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述振荡单元个数储存为第二计数结果；依据所述第一延迟量以及当所述第二振荡器被激活时所储存的所述第一计数结果与所述第二计数结果来产生第一转换信号，所述第一转换信号指示第一预估时间差；及至少依据第一转换信号产生输出信号，其中所述输出信号代表所述第一信号的激活时间与所述第二信号的激活时间的测量时间差。
附图说明
图1是依据本申请第一实施例的时间数字转换电路的示意图。
图2是依据本申请一实施例的第一振荡器及振荡单元输出的示意图。
图3是依据本申请第二实施例的时间数字转换电路的示意图。
图4是依据本申请一实施例的第一振荡器与第二振荡器的输出波形示意图。
图5是依据本申请第三实施例的时间数字转换电路的示意图。
图6是依据本申请一实施例的侦测电路的操作示意图。
图7是依据本申请一实施例的时间数字转换方法的流程图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有 通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
图1是依据本申请第一实施例的时间数字转换电路100的示意图。如图1所示，时间数字转换电路100包括第一振荡器110、第二振荡器120、第一计数电路130、第二计数电路140、第一转换电路150以及处理电路160。如图1所示，第一振荡器110可以是环形振荡器。第一振荡器110包括N个振荡单元，其中N为大于1的整数，在本实施例中，N为奇数。第一振荡器110中的所述N个振荡单元皆具有第一延迟量D1，并包括第一起始振荡单元11、第一末端振荡单元13以及耦接于第一起始振荡单元11与第一末端振荡单元13之间的多个(即N-2个)振荡单元12。第一环形振荡单元110由第一信号S1激活，详细来说，起始振荡单元定义为用以接收第一信号S1的振荡单元(即第一起始振荡单元11)，末端振荡单元定义为其输出由起始振荡单元所接收的振荡单元(即第一末端振荡单元13)。第一起始振荡单元11接收第一信号S1及第一末端振荡单元所产生的第一末端输出信号SoN，并产生输出信号So1至振荡单元12。振荡单元12接收输出信号So1并据此产生输出信号So2，依此类推。
在本实施例中，第二振荡器120可以同样是环形振荡器，然而，此不在本实施例的限制中。相对于第一振荡器110，第二振荡器120由第二信号S2激活。
第一计数电路130用于计数第一末端输出信号SoN改变的次数，并且将计 数次数储存为第一计数结果CN1。详细来说，当第一末端输出信号SoN自逻辑值’0’转态为逻辑值’1’时，第一计数电路130所产生的第一计数结果CN1加1；同样地，当第一末端输出信号SoN自逻辑值’1’转态为逻辑值’0’时，第一计数电路130所产生的第一计数结果CN1加1。第二计数电路140用于当每次第一起始振荡单元11的输出改变时，计数除第一末端振荡单元13外的其余振荡单元(即第一起始振荡单元11与多个振荡单元12)的输出改变的振荡单元个数，并将所述振荡单元个数储存为第二计数结果CN2。详细来说，若第一振荡器110持续振荡，第一振荡器110中的多个振荡单元的输出持续改变，当第一末端输出信号SoN改变，代表信号改变完成一圈，此时，第一计数电路130所产生的第一计数结果CN1将加1，并重置第二计数结果CN2。之后，由于第一末端输出信号SoN改变，相应地，输出信号So1将接续改变，此时，第二计数电路140所产生的第二计数结果CN2将指示为1；接着，由于输出信号So1改变，相应地，输出信号So2将接续改变，此时，第二计数电路140所产生的第二计数结果CN2将指示为2，依此类推，直到第一末端输出信号SoN再次改变，此时，第一计数电路130所产生的第一计数结果CN1将加1，并重置第二计数结果CN2。而相应地，输出信号So1再次接续改变，此时，第二计数电路140所产生的第二计数结果CN2将重新指示为1。需注意的是，第一计数电路130与第二计数电路140可分别包括储存电路，用于分别储存第一计数结果CN1与第二计数结果CN2。然而，在其他实施例中，所述储存电路也可以设计于第一计数电路130与第二计数电路140之外，换言之，所述储存电路与第一计数电路130、第二计数电路140可以为独立设置。
当第二振荡器120由第二信号S2激活时，将同时触发第一计数电路130与第二计数电路140来将此时所储存的第一计数结果CN1与第二计数结果CN2传送至第一转换电路150。第一转换电路150依据第一延迟量D1以及所接收到的第一计数结果CN1与第二计数结果CN2来产生第一转换信号TS1，其中第一转换信号TS1用于指示第一信号S1的激活时间与第二信号S2的激活时间之间的 第一预估时间差。处理电路160用于至少依据第一转换信号TS1产生输出信号OUT，其中输出信号OUT代表第一信号S1的激活时间与第二信号S2的激活时间的测量时间差。
目前常见的时间数字转换器中若想要检出两个讯号的时间差必须透过透过累计两个振荡器的延迟量的差值来逼近想要得到的时间差，一旦最终数值转态时的数值即是需要的结果，但传统的技术手段如果要求两个讯号的时间差的侦测范围需要够大并且同时希望有高的分辨率时，则设计上需要两个振荡器的延迟量的差异较小，且积分器需要较多级的电路架构，因此积分器所占的面积相对较大，才足以实现所需要的电路，但如此的设计方式会使得整个硬件代价过高，同时，在要求高分辨率时，两个振荡器的延迟量的差异也会有很大的偏差比率。由于本申请提出的时间数字转换电路100妥善设计了第一振荡器110、第一计数电路130、第二计数电路140，透过将振荡信号在第一振荡器110不停循环，并且透过第一计数电路130与第二计数电路140得到第一振荡器110中的振荡单元的输出改变的次数，因此计算第一信号S1的激活时间与第二信号S2的激活时间的时间差也不需要过多的电路架构，节省了设计成本与功耗。
图2是依据本申请一实施例的第一振荡器200的示意图，其中本实施例的第一振荡器200可用于实现第一振荡器110。第一振荡器200可以是一个环形振荡器，第一振荡器200包括一与非门21以及多个反相器22、23、24、25，其中非与门21可用以实现第一振荡器110中的第一起始振荡单元11，反相器22、23、24可用以实现第一振荡器110中的多个振荡单元12，反相器25可用以实现第一振荡器110中的第一末端振荡单元13。非与门21接收第一信号S1以及反相器25所产生的第一末端输出信号So5，并据此产生输出信号So1；反相器22接收输出信号So1，并据此产生输出信号So2；反相器23接收输出信号So2，并据此产生输出信号So3；反相器24接收输出信号So3，并据此产生输出信号So4；反相器25接收输出信号So4，并据此产生第一末端输出信号So5。
参考图2下半部的波形图，当第一信号S1在时间点t1激活时，经过一个第一延迟量D1后，输出信号So1转态；并且在经过一个第一延迟量D1后，输出信号So2转态，依此类推。如图2所示，当第二信号S2在时间点t2激活时，由于第一末端输出信号So5转态1次，因此，图1中的第一计数电路130所产生的第一计数结果CN1指示为1；而当第一末端输出信号So5在第一次转态后，输出信号So1、输出信号So2、输出信号So3与输出信号So4皆改变(转态)，因此，第二计数电路140所产生的第二计数结果CN2指示为4。由于，第一振荡器200包括5个振荡单元，因此，图1中的第一转换电路150依据第一延迟量D1、第一计数结果CN1与第二计数结果CN2来产生第一转换信号TS1，而第一转换信号TS1所指示的第一预估时间差可表示为(1*5+4)*D1。
图3是依据本发明第二实施例的时间数字转换电路300的示意图。时间数字转换电路300与时间数字转换电路100相似，同样包括第一振荡器110、第一计数电路130、第二计数电路140以及第一转换电路150，上述电路的操作已描述于图1与图2的实施例，因此相同之处将在此省略以省篇幅。除上述电路外，时间数字转换电路300还包括第二振荡器320、第三计数电路350、第四计数电路360、第二转换电路380以及处理电路390。第二振荡器可以是一个环形振荡器，包括N个振荡单元，其中N为大于1的整述。所述N个振荡单元皆具有第二延迟量D2，并包括第二起始振荡单元31、第二末端振荡单元33以及耦接于第二起始振荡单元31与第二末端振荡单元33之间的多个振荡单元32。第二环形振荡单元320由第二信号S2激活，详细来说，第二起始振荡单元31接收第二信号S2以及第二末端振荡单元33所产生的第二末端输出信号SoN’，并产生输出信号So1’至振荡单元32。振荡单元32接收输出信号So1’并据此产生输出信号So2’，依此类推。本技术领域具有通常知识者应能轻易理解第二振荡器320中的所述多个振荡单元应为奇数个来产生振荡信号。
类似于第一计数电路130，第三计数电路350用于计数第二末端输出信号 SoN’改变的次数，并且将计数次数储存为第三计数结果CN3。详细来说，当第二末端输出信号SoN’自逻辑值’0’转态为逻辑值’1’时，第三计数电路350所产生的第三计数结果CN3加1；同样地，当第二末端输出信号SoN’自逻辑值’1’转态为逻辑值’0’时，第三计数电路350所产生的第三计数结果CN3加1。第四计数电路360用于当每次第二起始振荡单元31的输出改变时，计数除第二末端振荡单元33外的其余振荡单元(即第二起始振荡单元31与多个振荡单元32)的输出改变的振荡单元个数，并将所述振荡单元个数储存为第四计数结果CN4。
详细来说，若第二振荡器320持续振荡，第二振荡器320中的多个振荡单元的输出持续改变，当第二末端输出信号SoN’改变，代表信号改变完成一圈，此时，第三计数电路350所产生的第三计数结果CN3将加1。之后由于第二末端输出信号SoN’改变，相应地，输出信号So1’将接续改变，此时，第四计数电路360所产生的第四计数结果CN4将指示为1；接着，由于输出信号So1’改变，相应地，输出信号So2’将接续改变，此时，第四计数电路360所产生的第四计数结果CN4将指示为2，依此类推，直到第二末端输出信号SoN’再次改变，此时，第三计数电路350所产生的第三计数结果CN3将加1。而相应地，输出信号So1’再次接续改变，此时，第四计数电路360所产生的第四计数结果CN4将重新指示为1。
需注意的是，第三计数电路350与第四计数电路360可分别包括储存电路，用于分别储存第三计数结果CN3与第四计数结果CN4。然而，在其他实施例中，所述储存电路也可以设计于第三计数电路350与第四计数电路360之外，换言之，所述储存电路与第三计数电路350、第四计数电路360可以为独立设置。
在其他实施例中，第三计数电路350可由第一计数电路130实现，而第四计数电路360可由第二计数电路140实现。如此一来，当第二振荡器320被第二信号S2激活后，第一计数电路130用于计数第二末端输出信号SoN’改变的次数，并且将计数次数储存为第三计数结果CN3。第二计数电路140用于当每次第二 起始振荡单元31的输出改变时，计数除第二末端振荡单元33外的其余振荡单元(即第二起始振荡单元31与多个振荡单元32)的输出改变的振荡单元个数，并将所述振荡单元个数储存为第四计数结果CN4。
第二转换电路380用于在激活第二环型振荡器320后，依据第一延迟量D1、第二延迟量D2、第三计数结果CN3及第四计数结果CN4来产生第二转换信号TS2，其中第二转换信号TS2指示第二预估时间差，且所述第二预估时间差小于第一延迟量D1。在本实施例中，第二转换电路380包括逻辑电路381，其中逻辑电路381用于在激活第二振荡器320后，当第二振荡器320中的任一振荡单元，即第二起始振荡单元31、多个振荡单元32与第二末端振荡单元33的任一的输出改变时，接收第一振荡器110中多个振荡单元，即第一起始振荡单元11、多个振荡单元12与第一末端振荡单元13的输出，并依据所述第一振荡器110中多个振荡单元的输出以及第二振荡器320中输出改变的振荡单元的输出来进行逻辑操作以产生一逻辑结果。关于第二转换电路380与逻辑电路381的详细操作将在下面段落说明。需注意的是，为维持图标画面的简洁，逻辑电路381与其他电路的连接关系并未完整绘示于图3。
处理电路390用于依据第一转换信号TS1与第二转换信号TS2来产生输出信号OUT，其中输出信号代表第一信号S1的激活时间与第二信号S2的激活时间的测量时间差。需注意的是，图2所示的第一振荡器200可同样用以实现第二振荡器320。
接续图2的实施例，图4是依据本申请一实施例的第一振荡器110与第二振荡器320的输出波形示意图。在本实施例中，第二延迟量D2略大于第一延迟量D1。如图4所示，第一信号S1在时间点t1激活而第二信号S2在时间点t2激活，当第二信号S2在时间点t2激活时，经过一个第二延迟量D2后，输出信号So1’转态；并且在经过一个第二延迟量D2后，输出信号So2’转态，依此类推。当输出信号So1’的第一次转态，即下降沿dn1’发生时，下降沿dn1’位于第一末端输 出信号So5的上升沿up1之后并且位于输出信号So1的下降沿dn1之前；接着，过了一个第二延迟量D2后，输出信号So2’的第一次转态，即上升沿up1’发生时，上升沿up1’位于输出信号So1的下降沿dn1之后并且位于输出信号So2的上升沿up2之前，然而，由于第二延迟量D2略大于第一延迟量D1，因此上升沿up1’与上升沿up2的距离较下降沿dn1与下降沿dn1’的距离小。此情形一直持续至时间点t4，输出信号So1’的上升沿up3’位于输出信号So1的上升沿up3之后。若第一延迟量D1与第二延迟量D2相同则输出信号So1’的上升沿up3’应位于下降沿dn2之后及上升沿up3之前，然而，由于第二延迟量D2略大于第一延迟量D1，导致在时间点t4上升沿up3’退到上升沿up3之后。当此情形发生时，第三计数结果CN3与第四技术结果CN4将传送至第二转换电路380。
在时间点t4时，由于信号转态完成一圈，因此，第三计数结果CN3将指示为1，并且输出信号So1’完成转态，第四计数结果CN4将指示为1。如上所述，第二转换电路380依据第三计数结果CN3以及第四计数结果CN4得知自时间点t2至t4经过了1*5+1＝6个延迟，因此依据第二延迟量D2可知时间点t2至t4总共经过6*D2的时间，并且自时间点t2至t4之间，第一振荡器110所经过的第一延迟量D1较第二振荡器320所经过的第二延迟量D2多1，因此，第二转换电路380依据第一延迟量D1、第二延迟量D2、第三计数结果CN3及第四计数结果CN4产生第二转换信号TS2，其中第二转换信号TS2所指示的第二预估时间差可表示为(6+1)*D1-6*D2，第二预估时间差及为时间点t3至t2的时间差。
由于第一转换信号TS1是依据第一计数结果CN1与第二计数结果CN2产生，因此第一转换信号TS1所指示的第一预估时间差计算到时间点t1至t3之间，而第二转换信号TS2所指示的第二预估时间差计算时间点t2至t3之间。处理电路390依据第一转换信号TS1与第二转换信号TS2来产生输出信号OUT。
接着将说明第二转换电路380如何判定输出信号So1’的上升沿up3’位于输出信号So1的上升沿up3之后。当输出信号So1’的下降沿dn1’发生时，所对应 的第一振荡器110的多个振荡单元的输出(即输出信号So1、So2、So3、So4与第一末端输出信号So5)的逻辑值为’10101’，当逻辑电路381接收逻辑值’10101’后透过对逻辑值’10101’与输出信号So1’的逻辑值’0’执行逻辑操作可得知，此时第一末端输出信号So5刚进行转态而输出信号So1尚未完成转态。举例来说，此时逻辑值’10101’综合逻辑值’0’的0与1数量相同，因此可判定输出信号So1’的下降沿dn1’位于第一末端输出信号So5的上升沿up1之后且位于输出信号So1的下降沿dn1之前，并产生逻辑结果其指示某一逻辑值，如逻辑値’0’。
当输出信号So2’的上升沿up1’发生时，所对应的第一振荡器110的多个振荡单元的输出的逻辑值为’00101’，当逻辑电路381接收逻辑值’00101’后透过对逻辑值’00101’与输出信号So2’的逻辑值’1’执行逻辑操作可得知，此时输出信号So1刚进行转态而输出信号So2尚未完成转态。举例来说，此时逻辑值’00101’综合逻辑值’1’的0与1数量相同，因此可判定输出信号So2’的上升沿up1’位于下降沿dn1之后且位于上升沿up2之前，并产生逻辑结果其指示逻辑值’0’。当上升沿up3’发生时，原先上升沿up3’应位于下降沿dn2与上升沿up3之间进而得到所对应的第一振荡器110的多个振荡单元的输出的逻辑值为’01010’，然而因为第二延迟量D2略大于第一延迟量D1的缘故，上升沿up3’位于上升沿up3之后，得到所对应的第一振荡器110的多个振荡单元的输出的逻辑值为’11010’，因此，逻辑电路381对逻辑值’11010’与与输出信号So1’的逻辑值’1’执行逻辑操作，可得知输出信号So1’的上升沿up3’位于输出信号So1的上升沿up3之后。举例来说，此时逻辑值’11010’综合逻辑值’1’的0与1数量不同，进而产生逻辑结果指示不同的逻辑值’1’。
需注意的是，在图4的实施例中，第二延迟量D2略大于第一延迟量D1，然而，此并非本申请的一限制。在其他实施例中，第二延迟量D2略小于第一延迟量D1，而第二转换电路380与逻辑电路381的操作将如同图4的实施例所描述，因此，详细说明在此省略已省篇幅。
图5是依据本发明第三实施例的时间数字转换电路500的示意图。时间数字转换电路500与时间数字转换电路大致相同，差别仅在于时间数字转换电路500包括侦测电路510，侦测电路510耦接至逻辑电路381，用于当逻辑电路381所产生的逻辑结果改变时，调整第二振荡器320的振荡频率，侦测电路510的详细功能将在后续实施例说明。在本实施例中，侦测电路510可包括电容数组，藉以耦接电容至第二振荡器320来调整第二振荡器320的振荡频率。
图6是依据本申请一实施例的侦测电路510的操作示意图。接续图4的实施例，在时间点t4时，输出信号So1’转态，并且逻辑结果判定上升沿up3’位于上升沿up3之后，侦测电路510因此提高第二振荡器320的振荡频率，使得在一段时间后，输出信号So1’的上升沿up4’落于输出信号So1的上升沿up4之前。侦测电路510可调整第二振荡器320的振荡频率使得上升沿up4’推前固定时间差tX，而由于第二延迟量D2与第一延迟量D1不变，透过图4的实施例所描述的逻辑电路381，在调整第二振荡器320的振荡频率后，逻辑电路381判定何时第二振荡器320的输出再次落于第一振荡器110的输出之后，并且第二转换电路380依据第一延迟量D1、第二延迟量D2以及此时的第三计数结果CN3与第四计数结果CN4，即可藉以判定时间点t5与t4之间的时间差tY。如此一来，所产生的第二转换信号TS2将具有更高的分辨率。
详细来说，假设tX为45皮秒(picosecond)并且第二延迟量D2较第一延迟量D1大5皮秒，假设在时间点t6之后过了三个第二延迟量D2时间，输出信号So4’的下降沿与输出信号So4的下降沿刚好对齐，因此可知时间点t5与t4之间的时间差tY为45-3*5＝30皮秒。同时参考图4与图6的实施例，第二转换电路380依据第一延迟量D1、第二延迟量D2、第三计数结果CN3及第四计数结果CN4产生第二转换信号TS2，其中第二转换信号TS2所指示的第二预估时间差可表示为(6+1)*D1-6*D2+tY，第二预估时间差及为时间点t3至t2的时间差。
图7是依据本申请一实施例的时间数字转换方法700的流程图。倘若大体上能得到相同结果，本申请并不限定完全依照图7所示的的流程步骤运行时间数字转换方法700。时间数字转换方法700归纳如下:
步骤702:传送第一信号激活第一振荡器。
步骤704:传送第二信号激活第二振荡器。
步骤706:计数所述第一末端输出信号改变的次数，并且将计数次数储存为第一计数结果。
步骤708:计数当每次所述第一起始振荡单元的输出改变时，除所述第一末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述振荡单元个数储存为第二计数结果。
步骤710:依据所述第一延迟量以及当所述第二振荡器被激活时所储存的所述第一计数结果与所述第二计数结果来产生第一转换信号。
步骤712:至少依据第一转换信号产生输出信号。
本领域具有通常知识者在阅读完图1至图6的实施例后应能轻易理解时间数字转换方法700的细节，详细内容在此省略以省篇幅。

Claims (20)

  1. 一种时间数字转换电路，其特征在于，包括:
    第一振荡器，由第一信号所激活，所述第一振荡器包括多个具有第一延迟量的振荡单元，所述第一振荡器中的所述多个振荡单元中的第一起始振荡单元接收所述第一信号与第一末端输出信号，所述第一振荡器中的多个振荡单元中的第一末端振荡单元用于产生所述第一末端输出信号；
    第一计数电路，耦接至所述第一振荡器，用于计数所述第一末端输出信号改变的次数，并且将计数次数储存为第一计数结果；
    第二计数电路，耦接至所述第一振荡器，用于计数当每次所述第一起始振荡单元的输出改变时，除所述第一末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述振荡单元个数储存为第二计数结果；
    第二振荡器，透过所述第一计数电路及所述第二计数电路耦接至第一振荡器，其中所述第二振荡器由第二信号激活；
    第一转换电路，耦接至所述第一计数电路及所述第二计数电路，用于依据所述第一延迟量以及当所述第二振荡器被激活时所储存的所述第一计数结果与所述第二计数结果来产生第一转换信号，所述第一转换信号指示一第一预估时间差；及
    处理电路，耦接至所述第一转换电路，用于至少依据第一转换信号产生输出信号，其中所述输出信号代表所述第一信号的激活时间与所述第二信号的激活时间的测量时间差。
  2. 如权利要求1的时间数字转换电路，其特征在于，所述第二振荡器包括具有多个第二延迟量的多个振荡单元，所述第二振荡器中的所述多个振荡单元中的第二起始振荡单元接收所述第二信号与第二末端输出信号，所述多个振荡单元中的第二末端振荡单元产生所述第二末端输出信号。
  3. 如权利要求2的时间数字转换电路，其特征在于，还包括:
    第三计数电路，耦接至所述第二振荡器，用于计数所述第二末端输出信号 改变的次数，并且将计数次数储存为第三计数结果；
    第四计数电路，耦接至所述第二振荡器，用于计数所述第二振荡器中除所述第二末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述第二振荡器中的除所述第二末端振荡单元外的其余振荡单元的输出改变的所述振荡单元个数储存为第四计数结果。
  4. 如权利要求2的时间数字转换电路，其特征在于，所述第一计数电路另用于在所述第二振荡器被激活后，计数所述第二末端输出信号改变的次数，并且将计数次数储存为第三计数结果；所述第二计数电路另用于在所述第二振荡器被激活后，计数除所述第二末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述振荡单元个数储存为第四计数结果。
  5. 如权利要求3-4中任意一项的时间数字转换电路，其特征在于，还包括:
    第二转换电路，用于在激活所述第二振荡器后，依据所述第一延迟量、所述第二延迟量、所述第三计数结果及所述第四计数结果来产生第二转换信号，所述第二转换信号指示第二预估时间差，且所述第二预估时间差小于所述第一延迟量。
  6. 如权利要求5的时间数字转换电路，其特征在于，所述处理电路依据所述第一转换信号与所述第二转换信号来产生输出信号。
  7. 如权利要求5的时间数字转换电路，其特征在于，所述第二转换电路包括:
    逻辑电路，用于在激活所述第二振荡器后，当所述第二振荡器中的任一振荡单元的输出改变时，接收所述第一振荡器中所述多个振荡单元的输出，并至少依据所述第一振荡器中所述多个振荡单元的输出以及所述第二振荡器中输出改变的振荡单元的输出来进行逻辑操作以产生一逻辑结果。
  8. 如权利要求7的时间数字转换电路，其特征在于，所述第二转换电路依据所述第一延迟量、所述第二延迟量以及当所述逻辑结果改变时的所述第三 计算结果与所述第四计算结果来产生所述第二转换信号。
  9. 如权利要求7的时间数字转换电路，其特征在于，另包括:
    侦测电路，用于依据所述逻辑结果选择性地调整所述第二振荡器的振荡频率。
  10. 如权利要求9的时间数字转换电路，其特征在于，所述第二转换电路依据所述第一延迟量、所述第二延迟量以及当所述第二振荡器的振荡频率改变后且所述逻辑结果改变时的所述第三计算结果与所述第四计算结果来产生所述第二转换信号。
  11. 一种时间数字转换方法，其特征在于，包括:
    传送第一信号激活第一振荡器，所述第一振荡器包括多个具有第一延迟量的振荡单元，所述第一振荡器中的所述多个振荡单元中的第一起始振荡单元接收所述第一信号与第一末端输出信号，所述多个振荡单元中的第一末端振荡单元用于产生所述第一末端输出信号；
    传送第二信号激活第二振荡器；
    计数所述第一末端输出信号改变的次数，并且将计数次数储存为第一计数结果；
    计数当每次所述第一起始振荡单元的输出改变时，除所述第一末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述振荡单元个数储存为第二计数结果；
    依据所述第一延迟量以及当所述第二振荡器被激活时所储存的所述第一计数结果与所述第二计数结果来产生第一转换信号，所述第一转换信号指示第一预估时间差；及
    至少依据第一转换信号产生输出信号，其中所述输出信号代表所述第一信号的激活时间与所述第二信号的激活时间的测量时间差。
  12. 如权利要求11的时间数字转换方法，其特征在于，所述第二振荡器包括具有多个第二延迟量的多个振荡单元，所述第二振荡器中的所述多个振荡 单元中的第二起始振荡单元接收所述第二信号与第二末端输出信号，所述多个振荡单元中的第二末端振荡单元产生所述第二末端输出信号。
  13. 如权利要求12的时间数字转换方法，其特征在于，还包括:
    计数所述第二末端输出信号改变的次数，并且将计数次数储存为第三计数结果；及
    计数所述第二振荡器中除所述第二末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述第二振荡器中除所述第二末端振荡单元外的其余振荡单元的输出改变的所述振荡单元个数储存为第四计数结果。
  14. 如权利要求12的时间数字转换方法，其特征在于，还包括:
    在所述第二振荡器被激活后，计数所述第一末端输出信号改变的次数，并且将计数次数储存为第三计数结果；及
    在所述第二振荡器被激活后，计数除所述第一末端振荡单元外的其余振荡单元的输出改变的振荡单元个数，并将所述振荡单元个数储存为第四计数结果。
  15. 如权利要求13-14中任意一项的时间数字转换方法，其特征在于，还包括:
    在激活所述第二振荡器后，依据所述第一延迟量、所述第二延迟量、所述第三计数结果及所述第四计数结果来产生第二转换信号，所述第二转换信号指示第二预估时间差，且所述第二预估时间差小于所述第一延迟量。
  16. 如权利要求15的时间数字转换方法，其特征在于，至少依据第一转换信号产生输出信号包括:
    依据所述第一转换信号与所述第二转换信号来产生输出信号。
  17. 如权利要求15的时间数字转换方法，其特征在于，依据所述第一延迟量、所述第二延迟量、所述第三计数结果及所述第四计数结果来产生所述第二转换信号包括:
    在激活所述第二振荡器后，所述第二振荡器中的任一振荡单元的输出改变 时，接收所述第一振荡器中所述多个振荡单元的输出；及
    依据所述第一振荡器中所述多个振荡单元的输出以及所述第二振荡器中输出改变的振荡单元的输出来进行逻辑操作以产生逻辑结果。
  18. 如权利要求17的时间数字转换方法，其特征在于，依据所述第一延迟量、所述第二延迟量、所述第三计数结果及所述第四计数结果来产生所述第二转换信号包括:
    依据所述第一延迟量、所述第二延迟量以及当所述逻辑结果改变时的所述第三计算结果与所述第四计算结果来产生所述第二转换信号。
  19. 如权利要求17的时间数字转换方法，其特征在于，另包括:
    依据所述逻辑结果选择性地调整所述第二振荡器的振荡频率。
  20. 如权利要求19的时间数字转换方法，其特征在于，依据所述第一延迟量、所述第二延迟量、所述第三计数结果及所述第四计数结果来产生所述第二转换信号包括:
    依据所述第一延迟量、所述第二延迟量以及当所述第二振荡器的振荡频率改变后且所述逻辑结果改变时的所述第三计算结果与所述第四计算结果来产生所述第二转换信号。
PCT/CN2019/078448 2019-03-18 2019-03-18 时间数字转换电路及相关方法 WO2020186414A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201980000430.4A CN110088696B (zh) 2019-03-18 2019-03-18 时间数字转换电路及相关方法
EP19920363.9A EP3828647B1 (en) 2019-03-18 2019-03-18 Time-to-digital conversion circuit and related method
PCT/CN2019/078448 WO2020186414A1 (zh) 2019-03-18 2019-03-18 时间数字转换电路及相关方法
JP2020561796A JP7137636B2 (ja) 2019-03-18 2019-03-18 時間－デジタル変換回路および関連する方法
US17/009,484 US11309899B2 (en) 2019-03-18 2020-09-01 Time-to-digital conversion circuit and method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/078448 WO2020186414A1 (zh) 2019-03-18 2019-03-18 时间数字转换电路及相关方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/009,484 Continuation US11309899B2 (en) 2019-03-18 2020-09-01 Time-to-digital conversion circuit and method of the same

Publications (1)

Publication Number Publication Date
WO2020186414A1 true WO2020186414A1 (zh) 2020-09-24

Family

ID=67424430

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/078448 WO2020186414A1 (zh) 2019-03-18 2019-03-18 时间数字转换电路及相关方法

Country Status (5)

Country Link
US (1) US11309899B2 (zh)
EP (1) EP3828647B1 (zh)
JP (1) JP7137636B2 (zh)
CN (1) CN110088696B (zh)
WO (1) WO2020186414A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022085540A (ja) * 2020-11-27 2022-06-08 セイコーエプソン株式会社 遷移状態出力装置、時間デジタル変換器及びａ／ｄ変換回路
CN114625208A (zh) * 2020-12-10 2022-06-14 炬芯科技股份有限公司 时钟电路和蓝牙设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150077279A1 (en) * 2013-09-17 2015-03-19 Qualcomm Incorporated Time-to-digital converter
CN106066599A (zh) * 2016-07-15 2016-11-02 中国地震局地震研究所 用于三维激光扫描仪的精密时间测量系统
CN106168753A (zh) * 2016-06-28 2016-11-30 中国科学院微电子研究所 时间数字转换器
CN106444344A (zh) * 2016-10-13 2017-02-22 东南大学 一种基于自偏置频率锁定环的高稳定时钟产生电路
CN108170018A (zh) * 2017-12-28 2018-06-15 东北大学 一种门控环型时间数字转换器及时间数字转换方法
CN109104190A (zh) * 2018-09-28 2018-12-28 东北大学 一种基于多次采样的时间数字转换电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3572809B2 (ja) * 1996-06-17 2004-10-06 株式会社デンソー Ａ／ｄ変換器
US20030076181A1 (en) * 2000-03-17 2003-04-24 Sassan Tabatabaei Tunable oscillators and signal generation methods
JP4396063B2 (ja) * 2001-07-13 2010-01-13 株式会社デンソー Ａ／ｄ変換方法及び装置
CN2736821Y (zh) * 2004-05-18 2005-10-26 西安电子科技大学 基于可编程逻辑器件的短时间间隔测量器
JP2010273118A (ja) * 2009-05-21 2010-12-02 Toshiba Corp 時間デジタル変換器
JP2012070087A (ja) * 2010-09-21 2012-04-05 Toshiba Corp デジタル位相比較器及びデジタル位相同期回路
JP5617688B2 (ja) * 2011-02-24 2014-11-05 富士通株式会社 時間デジタル変換装置
KR101202742B1 (ko) * 2011-04-05 2012-11-19 연세대학교 산학협력단 시간-디지털 변환기 및 변환방법
CN103425043A (zh) * 2013-09-11 2013-12-04 安徽问天量子科技股份有限公司 基于usb的高精度时间数字转换器
US9213316B2 (en) * 2014-02-06 2015-12-15 Texas Instruments Incorporated Circuit for detecting and correcting timing errors
CN106354001B (zh) * 2016-08-31 2019-03-12 中国科学院上海高等研究院 时间数字转换电路
US10007235B2 (en) * 2016-09-23 2018-06-26 Microsemi Semiconductor Ulc Time-to-digital converter with phase-scaled course-fine resolution

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150077279A1 (en) * 2013-09-17 2015-03-19 Qualcomm Incorporated Time-to-digital converter
CN106168753A (zh) * 2016-06-28 2016-11-30 中国科学院微电子研究所 时间数字转换器
CN106066599A (zh) * 2016-07-15 2016-11-02 中国地震局地震研究所 用于三维激光扫描仪的精密时间测量系统
CN106444344A (zh) * 2016-10-13 2017-02-22 东南大学 一种基于自偏置频率锁定环的高稳定时钟产生电路
CN108170018A (zh) * 2017-12-28 2018-06-15 东北大学 一种门控环型时间数字转换器及时间数字转换方法
CN109104190A (zh) * 2018-09-28 2018-12-28 东北大学 一种基于多次采样的时间数字转换电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3828647A4 *

Also Published As

Publication number Publication date
CN110088696B (zh) 2021-02-23
EP3828647A4 (en) 2021-11-10
CN110088696A (zh) 2019-08-02
EP3828647B1 (en) 2023-01-25
JP2021520756A (ja) 2021-08-19
US20200403625A1 (en) 2020-12-24
US11309899B2 (en) 2022-04-19
JP7137636B2 (ja) 2022-09-14
EP3828647A1 (en) 2021-06-02

Similar Documents

Publication Publication Date Title
JP3993717B2 (ja) 半導体集積回路装置
US5428309A (en) Delay circuit
TWI390852B (zh) 延遲電路
US9564885B2 (en) Event-driven clock duty cycle control
US7688671B2 (en) Semiconductor memory chip with on-die termination function
JP5397471B2 (ja) Ｔｄｃ回路及びａｄｐｌｌ回路
JP5579979B2 (ja) 半導体装置、内部信号タイミング回路、及び遅延時間測定方法
JP5932237B2 (ja) 半導体装置
JPH0974339A (ja) クロック発生回路、ｐｌｌ回路及び半導体装置、並びにクロック発生回路の単位遅延素子接続段数算出方法
WO2020186414A1 (zh) 时间数字转换电路及相关方法
JP2009065533A (ja) ジッタ検出回路及び半導体装置
JP3388134B2 (ja) 位相比較回路、ｄｌｌ回路および半導体集積回路
US20110187419A1 (en) Semiconductor integrated circuit and voltage controller therewith
JPH11312962A (ja) 逓倍回路
CN112230130A (zh) 监测传感器及芯片
US20070170969A1 (en) Electronic system having a clock signal correcting device
JP2006039693A (ja) 半導体装置
US8169232B2 (en) Apparatus and method for generating resistance calibration code in semiconductor integrated circuit
JP2014096691A (ja) 半導体装置
KR100503682B1 (ko) 원숏 신호 발생회로
US8754685B1 (en) Delay locked loop
US20090309667A1 (en) Ring oscillator using analog parallelism
US8305129B2 (en) Internal clock generating circuit and method for generating internal clock signal with data signal
JP2004343291A (ja) 位相調整回路
JP2001216047A (ja) 遅延調整回路

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2020561796

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19920363

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2019920363

Country of ref document: EP

Effective date: 20201030

NENP Non-entry into the national phase

Ref country code: DE