WO2020177339A1 - 压力传感器及其制造方法 - Google Patents

压力传感器及其制造方法 Download PDF

Info

Publication number
WO2020177339A1
WO2020177339A1 PCT/CN2019/112938 CN2019112938W WO2020177339A1 WO 2020177339 A1 WO2020177339 A1 WO 2020177339A1 CN 2019112938 W CN2019112938 W CN 2019112938W WO 2020177339 A1 WO2020177339 A1 WO 2020177339A1
Authority
WO
WIPO (PCT)
Prior art keywords
vacuum chamber
groove
heat treatment
substrate
manufacturing
Prior art date
Application number
PCT/CN2019/112938
Other languages
English (en)
French (fr)
Inventor
李刚
刘迪
胡维
吕萍
Original Assignee
苏州敏芯微电子技术股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州敏芯微电子技术股份有限公司 filed Critical 苏州敏芯微电子技术股份有限公司
Publication of WO2020177339A1 publication Critical patent/WO2020177339A1/zh

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
    • G01L1/22—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges

Definitions

  • the invention relates to the field of microelectronic mechanical systems, in particular to a pressure sensor and a manufacturing method thereof.
  • the piezoresistive pressure sensor has a relatively simple process and is suitable for mass production. It is the mainstream direction of pressure sensor development.
  • the pressure-sensitive film of a piezoresistive pressure sensor is the most critical structure.
  • there are several methods commonly used to prepare a piezoresistive pressure-sensitive film One is to use alkaline solution to anisotropically etch the backside of the silicon wafer. This method obtains the back cavity through time control and also obtains a certain thickness of pressure-sensitive film, but this method cannot guarantee the uniform corrosion of the entire wafer It is difficult to obtain a pressure-sensitive film with high flatness.
  • the second is electrochemical corrosion. This method requires an expensive potentiostat and has a high production cost.
  • the third type is: using the C-SOI process, first etch a groove with the shape of the pressure chamber on the front side of a Si wafer (called wafer 1); then, on another Si wafer (called wafer 2) Depositing silicon oxide on both sides, bonding the front side of wafer 1 and any side of wafer 2 by Si-SiO 2 ; thinning wafer 2 to a certain thickness, thereby obtaining a suspended film and obtaining a closed pressure chamber;
  • the back of the wafer 1 is etched by deep reactive ion etching, so that the pressure chamber communicates with the outside.
  • the thickness of the film obtained by this method is relatively large, and the production cost for preparing a small-range pressure sensor is relatively high.
  • the technical problem to be solved by the present invention is to reduce the manufacturing cost of the pressure-sensitive film of the pressure sensor, improve the flatness of the pressure-sensitive film, and reduce the thickness of the pressure-sensitive film.
  • the present invention provides a method for manufacturing a pressure sensor, which includes: providing a substrate; forming a plurality of first holes arranged at intervals on the surface of the substrate; performing a first heat treatment to make a plurality of the first holes A hole is merged into a suspended first vacuum chamber; a groove communicating with the first vacuum chamber and an induction body surrounded by the groove are formed.
  • the first heat treatment is rapid thermal annealing.
  • the temperature of the first heat treatment is not less than 1100 degrees Celsius.
  • the method further includes: forming a device layer covering the substrate by an epitaxial process.
  • the method further includes: forming a plurality of second holes arranged at intervals on the surface of the device layer; performing a second heat treatment so that the plurality of second holes are merged into a suspended second vacuum chamber, the second vacuum chamber Located in the sensing body.
  • the second heat treatment is rapid thermal annealing.
  • the temperature of the second heat treatment is not less than 1100 degrees Celsius.
  • the diameter of the second hole is 0.5 ⁇ m to 1.5 ⁇ m
  • the diameter of the first hole is 0.5 ⁇ m to 1.5 ⁇ m.
  • the second vacuum chamber is located directly above the first vacuum chamber.
  • the groove is a ring with a gap; the number of the grooves is two, which are first and second grooves respectively, and the first groove surrounds the outside of the second groove , And the notch of the first groove and the notch of the second groove are arranged at an interval of 180 degrees.
  • the present invention also provides a pressure sensor, which includes: a semiconductor substrate; a suspended first vacuum chamber located in the semiconductor substrate, and the first vacuum chamber consists of a plurality of spaced first grooves passing through the first vacuum chamber. A heat treatment combined; a trench located in the semiconductor substrate, the trench passes through a part of the semiconductor substrate until it communicates with the first vacuum chamber, and the trench and the first vacuum chamber form an induction body .
  • the semiconductor substrate includes a substrate and a device layer on the substrate, and the device layer is an epitaxial layer.
  • the second vacuum chamber is located in the sensing body and is formed by combining a plurality of spaced second grooves through a second heat treatment.
  • the second vacuum chamber is located directly above the first vacuum chamber.
  • the second heat treatment is rapid thermal annealing.
  • the groove is a ring with a gap; the number of the grooves is two, which are first and second grooves respectively, and the first groove surrounds the outside of the second groove , And the notch of the first groove and the notch of the second groove are arranged at an interval of 180 degrees.
  • the first heat treatment is rapid thermal annealing.
  • a plurality of first holes arranged at intervals are formed on the surface of the substrate, and then the substrate is subjected to a first heat treatment, so that the plurality of first holes are combined into a suspended first vacuum chamber and the parts between the first holes are combined together.
  • a pressure-sensitive film also known as a suspended film
  • the pressure-sensitive film formed by this heat treatment process has high flatness and thin thickness, which can be as thin as 1 micron.
  • the side walls of the first vacuum chamber formed by the heat treatment process are relatively smooth, and the corners are rounded, so that the pressure-sensitive film is basically free of stress.
  • a device layer can be formed on the substrate by an epitaxial process.
  • the material of the device layer is the same as that of the pressure-sensitive film and can be used as a part of the pressure-sensitive film. Since the thickness of the device layer is easy to control, the overall thickness of the pressure sensitive film of the pressure sensor can be adjusted within a relatively large range.
  • 1 to 15 are cross-sectional views of the pressure sensor in different manufacturing stages in an embodiment of the present invention.
  • Fig. 16 is a plan view of a pressure sensor in an embodiment of the present invention.
  • a substrate 1 is provided, and the substrate 1 includes an upper surface 11 and a lower surface 12.
  • the substrate 1 is a single crystal silicon substrate.
  • the substrate 1 can also be selected from other suitable semiconductor materials.
  • a protective layer 13 having a plurality of patterns 14 is formed on the upper surface of the substrate 1.
  • the manufacturing method of the protective layer 13 includes: forming a protective material layer (not shown) on the upper surface of the substrate 1 using low pressure chemical vapor deposition, plasma chemical vapor deposition, or thermal oxidation, and then using photolithography and wet etching Process, or photolithography and dry etching processes, remove part of the protective material layer, and form the protective layer 13 with the pattern 14.
  • the material of the protective layer 13 is silicon oxide.
  • the material of the protective layer 13 can also be a dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, etc. Layer or multilayer composite structure.
  • the substrate 1 is etched with the protective layer 13 as a mask, and a number of first holes 15 are formed in the substrate 1. Since the first hole 15 is located on the surface of the substrate 1, it can also be called a first groove.
  • an anisotropic etching process such as a deep reactive ion silicon etching (DRIE) process, is used to etch the substrate 1 to obtain a number of first holes 15, defining the part between two adjacent first holes 15 It is figure 15a.
  • a number of first holes 15 are arranged in an array.
  • the first holes 15 are circular holes. The depth of the circular holes is a few micrometers and the diameter is about 0.5 micrometers to 1.5 micrometers.
  • the first hole 15 may also be set as a hole of other shape, the hole may be rectangular, circular, pentagonal, hexagonal or other polygonal shape, and the size and interval of the first hole may be according to The lithography capability of the lithography machine is adjusted accordingly.
  • the protective layer 13 is removed.
  • a dry etching or wet etching process such as buffered hydrofluoric acid (BOE) is used to remove the protective layer 13.
  • BOE buffered hydrofluoric acid
  • the substrate 1 is subjected to a first heat treatment, so that a number of first holes 15 (refer to FIG. 4) are combined into a suspended first vacuum chamber 16.
  • the so-called suspension means that the first vacuum chamber 16 is located on the substrate 1 Inside, there is a certain distance from the upper surface 11 of the substrate 1. The portion of the substrate 1 between the upper surface 11 and the first vacuum chamber 16 is defined as the first suspended film 17.
  • the first holes 15 will expand in the horizontal direction, so that the first holes 15 are connected to each other, thereby combining into a complete large hole, namely For the first vacuum chamber 16.
  • the energy of the upper surface of the substrate 1 is reduced, causing the upper surface of the substrate 1 to migrate, and the ends of each pattern 15a can be combined with each other as a whole, so that the A first suspended film 17 is formed above the vacuum chamber 16.
  • the first suspended film 17 formed by the first heat treatment process is very flat and has a relatively thin thickness, which can be as thin as 1 micron.
  • the first vacuum chamber 16 is located above the center of the substrate 1.
  • the side walls of the first vacuum chamber 16 formed by the first heat treatment process are relatively smooth, and as shown in FIG. 5, the corners of the first vacuum chamber 16 are rounded, so that the first suspended film 17 is basically free of stress. . Since the vacuum cavity and the suspended film are formed by a heat treatment process, a series of adverse effects caused by traditional bulk silicon etching, sacrificial layer etching, and wafer bonding are avoided.
  • the first heat treatment is performed in an oxygen-free, low-pressure (lower than atmospheric pressure) environment to prevent the substrate 1 from being oxidized.
  • the oxygen-free environment is a pure hydrogen environment.
  • the oxygen-free environment may also be an inert gas environment.
  • the environmental pressure of the first heat treatment may be less than 1 atmosphere, so that the pressure in the first vacuum chamber 16 formed is less than 1 atmosphere.
  • the temperature of the first heat treatment is 1100 degrees Celsius.
  • the temperature of the first heat treatment may also be higher than 1100 degrees Celsius.
  • the first heat treatment is rapid thermal annealing.
  • the device layer 18 covering the substrate 1 is formed by an epitaxial process. Due to the epitaxial process, the material of the device layer 18 is the same as the material of the substrate 1. In this embodiment, the material of the device layer 18 is monocrystalline silicon.
  • a protective layer 19 having a plurality of patterns 20 is formed on the device layer 18.
  • the manufacturing method of the protective layer 19 includes: forming a protective material layer (not shown) on the upper surface of the device layer 18 by using processes such as low pressure chemical vapor deposition, plasma chemical vapor deposition or thermal oxidation, and then using photolithography and wet etching Process, or photolithography and dry etching processes, remove part of the protective material layer, and form the protective layer 19 with the pattern 20.
  • the material of the protective layer 19 is silicon oxide.
  • the material of the protective layer 19 can also be a dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, etc. Layer or multilayer composite structure.
  • the substrate 1 with the device layer 18 is etched, and a number of second holes 21 are formed in the substrate 1. Since the second hole 21 is located on the surface of the device layer 18, the second hole 21 can also be referred to as a second groove.
  • an anisotropic etching process such as a deep reactive ion silicon etching (DRIE) process, is used to etch the substrate 1 to obtain a number of second holes 21, defining the portion between two adjacent second holes 21 It is figure 21a.
  • a number of second holes 21 are arranged in an array.
  • the second holes 21 are round holes.
  • the depth of the round holes is a few microns, and the diameter can be 0.5 to 1.5 microns, for example, 1 micron.
  • the spacing between the holes is about 0.5 microns.
  • the second hole 21 may also be a hole of other shapes, and the hole may be rectangular, circular, pentagonal, hexagonal or other polygonal shapes.
  • the plurality of second holes 21 are all located directly above the first vacuum chamber 16.
  • the protective layer 19 is removed.
  • a dry etching or wet etching process such as buffered hydrofluoric acid (BOE) is used to remove the protective layer 19.
  • BOE buffered hydrofluoric acid
  • the first heat treatment is performed on the substrate 1, so that a number of second holes 21 (refer to FIG. 9) are merged into a suspended second vacuum chamber 7.
  • the so-called suspension means that the second vacuum chamber 7 is located with a device layer 18. There is a certain distance between the inside of the substrate 1 and the upper surface of the device layer 18. The portion between the upper surface 11 of the device layer 18 and the second vacuum chamber 7 is defined as a second suspended film 8 (also called a pressure sensitive film).
  • the second vacuum chamber 7 is located directly above the first vacuum chamber 16, and the width (horizontal dimension) of the second vacuum chamber 7 is smaller than the width of the first vacuum chamber 16.
  • the second hole 21 will expand in the horizontal direction, so that the second holes 21 are connected to each other, thereby combining into a complete large hole, namely For the second vacuum chamber 7.
  • the energy of the upper surface of the device layer 18 is reduced, causing the upper surface of the device layer 18 to migrate, and the ends of the respective patterns 21a can be combined with each other as a whole, so that in the second A second suspended film 8 is formed above the vacuum chamber 7.
  • the second suspended film 8 formed by the second heat treatment process is very flat and has a relatively thin thickness, which can be as thin as 1 micron.
  • the sidewalls of the second vacuum chamber 7 formed by the first heat treatment process are relatively smooth, and as shown in FIG. 10, the corners of the second vacuum chamber 7 are rounded, and the second suspended film 8 is basically free of stress.
  • the second heat treatment is performed in an oxygen-free, low-pressure (lower than atmospheric pressure) environment to prevent the substrate 1 from being oxidized.
  • the oxygen-free environment is a pure hydrogen environment.
  • the oxygen-free environment may also be an inert gas environment.
  • the environmental pressure of the second heat treatment may be less than 1 atmosphere, so that the pressure in the second vacuum chamber 7 formed is less than 1 atmosphere.
  • the temperature of the second heat treatment is 1100 degrees Celsius.
  • the temperature of the second heat treatment may also be higher than 1100 degrees Celsius.
  • the second heat treatment is rapid thermal annealing.
  • a first dielectric layer 23 is formed on the device layer 18, which serves as a barrier layer.
  • the material can be silicon oxide, silicon nitride, silicon oxynitride, etc., and the formation process can be low pressure chemical vapor deposition, plasma chemistry, etc. Processes such as vapor deposition or thermal oxidation.
  • a number of piezoresistors 10 are formed, and the piezoresistors 10 are located directly above the second vacuum chamber 7.
  • the formation process of the piezoresistor 10 is ion implantation, that is, the piezoresistor 10 is obtained by ion implanting a specific area of the surface layer of the device layer 18.
  • a second dielectric layer 22 covering the first dielectric layer 23 is formed.
  • the material of the second dielectric layer 22 may be silicon oxide, silicon nitride, silicon oxynitride, etc., and the formation process may be low pressure chemical vapor deposition, plasma chemical vapor deposition, or thermal oxidation.
  • part of the second dielectric layer 22 and the first dielectric layer 23 are removed to form a plurality of windows 24, and each window 24 exposes a corresponding part of the piezoresistor 10.
  • the method of forming the window 24 is to perform photolithography and then reactive ion etching.
  • the method for forming the metal electrode 9 includes: forming a metal material layer covering the second dielectric layer 22, a part of the metal material layer is filled into the window 24, and an ohmic contact is formed with the piezoresistor 10 below;
  • the method for forming the metal material layer may be deposition or electroplating; a patterned mask layer is formed on the metal material layer, and the metal material layer is etched using the patterned mask layer as a mask to form a metal electrode 9.
  • the etching process may be dry etching or wet etching, and the patterned mask layer may be a photoresist layer.
  • a protective layer 26 with a pattern 27 is formed on the metal electrode 9, the protective layer 26 covers the second dielectric layer 22, and the pattern 27 is located on the periphery of the metal electrode 9.
  • the manufacturing method of the protective layer 26 includes: forming a protective material layer (not shown) on the upper surface of the second dielectric layer 22 and the metal electrode 9 by using low-pressure chemical vapor deposition, plasma chemical vapor deposition, or thermal oxidation, and then using The photolithography and wet etching processes, or the photolithography and dry etching processes remove part of the protective material layer, and form the protective layer 26 with the pattern 27.
  • the material of the protective layer 26 is silicon oxide.
  • the material of the protective layer 26 may also be a dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, etc. Layer or multilayer composite structure.
  • the second dielectric layer 22 and the first dielectric layer 23 are etched to the substrate 1 to form a trench 25 and the sensing body 6 surrounded by the trench 25. 25 communicates with the first vacuum chamber 16 to form a receiving chamber (not labeled).
  • the etching process is dry etching, specifically a deep reactive ion silicon etching (DRIE) process.
  • the second vacuum chamber 7 is located in the sensing body 6, and the piezoresistor 10 and the metal electrode 9 are both located in the sensing body 6.
  • the sensing body 6 is surrounded by the groove 25 and the first vacuum chamber 16 and can move along a direction perpendicular to the substrate 1 to deform when subjected to an external force to detect pressure according to the resistance change of the piezoresistor 10.
  • the groove 25 is in the shape of a ring with a notch (not marked), and the number of grooves 25 is two, which are an outer groove and an inner groove, respectively.
  • the notch of the outer groove and the notch of the inner groove are arranged at an interval of 180 degrees. More specifically, the groove 25 is rectangular, and one side is provided with a notch.
  • the part of the substrate 1 located between the outer groove and the inner groove constitutes a support beam 5, and the part of the substrate 1 located in the gap of the groove 25 also constitutes another support beam.
  • the two support beams are connected to the induction
  • the body 6 is connected so that the sensing body 6 can be suspended.
  • the number of grooves 25 should not be limited to two, and the number can be set arbitrarily, for example, the groove 25 can be only one.
  • the number of notches in each groove 25 can be set arbitrarily, for example, it can be two.
  • the shape of the groove 25 should not be limited to a rectangular shape, and can also be set to a polygonal shape such as a circle, a pentagon, and a hexagon.
  • the number of the first vacuum chamber 16 should not be limited to one, it can also be two.
  • the two first vacuum chambers 16 are spaced apart in the horizontal direction, and the second vacuum chamber 7 is located between the two first vacuum chambers 16.
  • each of the first vacuum chambers is in communication with vertically extending grooves. In this case, all the first vacuum chambers and all the grooves enclose the sensing body.
  • the steps of forming the device layer and the second vacuum chamber can be omitted, and the steps of forming piezoresistance, metal electrodes, and trenches can be directly performed.
  • the pressure sensor includes a substrate 1.
  • the substrate 1 is a single crystal silicon substrate.
  • the substrate 1 can also be selected from other suitable semiconductor materials.
  • a suspended first vacuum chamber 16 is formed in the substrate 1.
  • the term suspended means that the first vacuum chamber 16 is located inside the substrate 1 and has a certain distance from the upper surface (not labeled) of the substrate 1.
  • the first vacuum chamber 16 is formed by combining a plurality of spaced first grooves after a first heat treatment, and the first grooves are located on the surface of the substrate 1. In other words, by first forming a number of first grooves arranged at intervals on the surface of the substrate 1 and then performing the first heat treatment, the first grooves can be combined into a suspended first vacuum chamber 16.
  • the first groove Under the action of the first heat treatment, the first groove will expand in the horizontal direction, so that the first grooves are connected to each other, and thus merge into a complete large hole, that is, the first vacuum chamber 16. At the same time, under the action of the first heat treatment, the energy of the upper surface of the substrate 1 is reduced, causing the upper surface of the substrate 1 to migrate, and the ends of the parts between the first grooves can be combined into a whole. , Thereby forming a first suspended film (not labeled) above the first vacuum chamber 16.
  • the first suspended film formed by the first heat treatment process is very flat and has a relatively thin thickness, which can be as thin as 1 micron.
  • the first vacuum chamber 16 is located above the center of the substrate 1.
  • the first heat treatment is performed in an oxygen-free, low-pressure (lower than atmospheric pressure) environment to prevent the substrate 1 from being oxidized.
  • the oxygen-free environment is a pure hydrogen environment.
  • the oxygen-free environment may also be an inert gas environment.
  • the environmental pressure of the first heat treatment may be less than 1 atmosphere, so that the pressure in the first vacuum chamber 16 formed is less than 1 atmosphere.
  • the temperature of the first heat treatment is 1100 degrees Celsius.
  • the temperature of the first heat treatment may also be higher than 1100 degrees Celsius.
  • the first heat treatment is rapid thermal annealing.
  • the device layer 18 is formed on the substrate 1.
  • the device layer 18 is formed by epitaxial growth, that is, the epitaxial layer, which has the same material as the substrate 1.
  • the substrate 1 and the device layer 18 constitute a semiconductor substrate. Bottom (not marked).
  • a first dielectric layer 23 is formed on the device layer 18, which serves as a barrier layer.
  • the material can be silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the formation process can be low pressure chemical vapor deposition, plasma chemical vapor deposition, or thermal oxidation, etc. Craft.
  • a second dielectric layer 22 is formed on the first dielectric layer 23.
  • the material of the second dielectric layer 22 may be silicon oxide, silicon nitride, silicon oxynitride, etc., and the formation process may be low pressure chemical vapor deposition, plasma chemical vapor deposition, or thermal oxidation.
  • the trench 25 penetrates the semiconductor substrate above the first vacuum chamber 16, the first dielectric layer 23 and the second dielectric layer 22, and communicates with the first vacuum chamber 16.
  • the groove 25 and the first vacuum chamber 16 enclose the induction body 6.
  • the groove 25 is in the shape of a ring with a notch (not marked), and the number of grooves 25 is two, which are an outer groove and an inner groove, respectively.
  • the notch of the outer groove and the notch of the inner groove are arranged at an interval of 180 degrees. More specifically, the groove 25 is rectangular, and one side is provided with a notch.
  • the part of the substrate 1 located between the outer groove and the inner groove constitutes a support beam 5, and the part of the substrate 1 located in the gap of the groove 25 also constitutes another support beam.
  • the two support beams are connected to the induction
  • the body 6 is connected so that the sensing body 6 can be suspended.
  • the number of grooves 25 should not be limited to two, and the number can be set arbitrarily, for example, the groove 25 can be only one.
  • the number of notches in each groove 25 can be set arbitrarily, for example, it can be two.
  • the shape of the groove 25 should not be limited to a rectangular shape, and can also be set to a polygonal shape such as a circle, a pentagon, and a hexagon.
  • a suspended second vacuum chamber 7 is formed in the device layer 18.
  • the so-called suspended means that the second vacuum chamber 7 is located inside the device layer 18, and has a certain distance from the upper surface (unmarked) of the device layer 18. interval.
  • the second vacuum chamber 7 is located in the sensing body 6 and directly above the first vacuum chamber 16.
  • the second vacuum chamber 7 is formed by combining a plurality of spaced second grooves after a second heat treatment, and the second grooves are located on the surface of the device layer 18. In other words, by first forming a number of second grooves arranged at intervals on the surface of the device layer 18 and then performing the second heat treatment, the second grooves can be merged into the suspended second vacuum chamber 7.
  • the second groove Under the action of the second heat treatment, the second groove will expand in the horizontal direction, so that the second grooves communicate with each other, and thus merge into a complete large hole, that is, the second vacuum chamber 7.
  • the energy of the upper surface of the device layer 18 is reduced, so that the upper surface of the device layer 18 migrates, and the ends of the portions between the second grooves can be combined into a whole.
  • the second suspended film formed by the second heat treatment process is very flat and has a relatively thin thickness, which can be as thin as 1 micron.
  • the second vacuum chamber 7 is located above the center of the device layer 18.
  • the second heat treatment is performed in an oxygen-free, low-pressure (lower than atmospheric pressure) environment to prevent the device layer 18 and the substrate 1 from being oxidized.
  • the oxygen-free environment is a pure hydrogen environment.
  • the oxygen-free environment may also be an inert gas environment.
  • the environmental pressure of the second heat treatment may be less than 1 atmosphere, so that the pressure in the second vacuum chamber 7 formed is less than 1 atmosphere.
  • the temperature of the second heat treatment is 1100 degrees Celsius.
  • the temperature of the second heat treatment may also be higher than 1100 degrees Celsius.
  • the second heat treatment is rapid thermal annealing.
  • the number of the first vacuum chamber 16 should not be limited to one, it can also be two.
  • the two first vacuum chambers 16 are spaced apart in the horizontal direction, and the second vacuum chambers 7 are located in the two first vacuum chambers. Between the cavities 16, each of the first vacuum cavities communicates with vertically extending grooves. In this case, all the first vacuum cavities and all the grooves enclose the sensing body.
  • the semiconductor substrate is only composed of a simple substrate.
  • the first dielectric layer 23 directly covers the surface of the substrate 1.
  • the piezoresistor 10 is directly formed on the surface of the substrate 1.
  • a number of piezoresistors 10 are formed on the surface of the device layer 18, and the piezoresistors 10 are located directly above the second vacuum chamber 7.
  • the formation process of the piezoresistor 10 is ion implantation, that is, the piezoresistor 10 is obtained by ion implanting a specific area of the surface layer of the device layer 18.
  • the metal electrode 9 is located above the second dielectric layer 22, and one end thereof passes through the second dielectric layer 22 and the first dielectric layer 23 to form an ohmic contact with the piezoresistor 10 below.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Measuring Fluid Pressure (AREA)
  • Pressure Sensors (AREA)

Abstract

一种压力传感器及其制造方法，该方法包括：提供衬底(1)；在衬底(1)的表面形成若干间隔排列的第一孔(15)；进行第一热处理，使得若干第一孔(15)合并成悬空的第一真空腔(16)；形成与第一真空腔(16)连通的沟槽(25)以及由沟槽(25)环绕的感应本体(6)。该方法简化了感压薄膜的制造工艺。同时，通过这种热处理工艺形成的感压薄膜平整度高、厚度较薄，可以薄至1微米。

Description

压力传感器及其制造方法 技术领域
本发明涉及微电子机械系统领域，尤其涉及一种压力传感器及其制造方法。
背景技术
随着微机电系统技术的不断发展，压力传感器的成本在逐渐减小，压力传感器的应用也已经进入医疗、汽车、气象检测、高度测量、消费电子等众多领域。常用的压力传感器有电容式、压电式、压阻式三种，其中压阻式压力传感器的工艺较为简单，适合批量生产，是压力传感器发展的主流方向。
压阻式压力传感器的感压薄膜是最关键的结构，目前常用于制备压阻式感压薄膜的方法有以下几种。一种是采用碱性溶液各向异性腐蚀的硅片背面的方法，该方法通过时间控制得到背腔的同时也得到一定厚度的感压薄膜，但采用该方法不能保证整片晶圆腐蚀的均匀性，因而很难获得平整度较高的感压薄膜。第二种是电化学腐蚀，该方法需要昂贵的恒电位仪，生产成本较高。第三种是：采用C-SOI工艺，先在一片Si晶圆(称晶圆1)的正面刻蚀出压力腔外形的凹槽；然后，在另一片Si晶圆(称晶圆2)上双面沉积氧化硅，将晶圆1的正面与晶圆2任意一面进行Si-SiO 2键合；减薄晶圆2使其达到一定厚度，进而得到悬空薄膜，同时得到封闭的压力腔；若用于制备表压传感器，则通过深反应离子刻蚀的方式刻蚀晶圆1的背部，使得压力腔与外界连通。这种方法得到的薄膜厚度较大，用于制备小量程压力传感器生产成本较高。
因此，如何获得制造成本低、厚度更薄、平整度更高的感压薄膜成为亟待本领域解决的技术问题。
发明内容
本发明所要解决的技术问题是降低压力传感器的感压薄膜的制造成本，提高感压薄膜的平整度，降低感压薄膜的厚度。
为了解决上述问题，本发明提供了一种压力传感器的制造方法，其包括：提供衬底；在所述衬底的表面形成若干间隔排列的第一孔；进行第一热处理，使得若干所述第一孔合并成悬空的第一真空腔；形成与所述第一真空腔连通的 沟槽以及由所述沟槽环绕的感应本体。
可选地，所述第一热处理为快速热退火。
可选地，所述第一热处理的温度不小于1100摄氏度。
可选地，还包括：通过外延工艺形成覆盖所述衬底的器件层。
可选地，还包括：在所述器件层的表面形成若干间隔排列的第二孔；进行第二热处理，使得若干所述第二孔合并成悬空的第二真空腔，所述第二真空腔位于所述感应本体内。
可选地，所述第二热处理为快速热退火。
可选地，所述第二热处理的温度不小于1100摄氏度。
可选的，所述第二孔的直径为0.5微米～1.5微米，所述第一孔的直径为0.5微米～1.5微米。
可选地，所述第二真空腔位于所述第一真空腔的正上方。
可选地，所述沟槽为具有缺口的环状；所述沟槽的数量为两个，分别为第一、二沟槽，所述第一沟槽环绕在所述第二沟槽的外侧，且所述第一沟槽的缺口与第二沟槽的缺口呈180度间隔设置。
另外，本发明还提供了一种压力传感器，其包括：半导体衬底；位于所述半导体衬底内的悬空的第一真空腔，所述第一真空腔由若干间隔排列的第一槽经第一热处理合并而成；位于所述半导体衬底内的沟槽，所述沟槽穿过部分半导体衬底直至与所述第一真空腔连通，所述沟槽与第一真空腔围成感应本体。
可选地，所述半导体衬底包括衬底和位于所述衬底上的器件层，所述器件层为外延层。
可选地，所述器件层内具有悬空的第二真空腔，所述第二真空腔位于所述感应本体内，并由若干间隔排列的第二槽经第二热处理合并而成。
可选地，所述第二真空腔位于所述第一真空腔的正上方。
可选地，所述第二热处理为快速热退火。
可选地，所述沟槽为具有缺口的环状；所述沟槽的数量为两个，分别为第一、二沟槽，所述第一沟槽环绕在所述第二沟槽的外侧，且所述第一沟槽的缺口与第二沟槽的缺口呈180度间隔设置。
可选地，所述第一热处理为快速热退火。
本发明先在衬底的表面形成若干间隔排列的第一孔，再对衬底进行第一热处理，使得若干第一孔合并成悬空的第一真空腔且第一孔之间的部分结合在一起形成感压薄膜(也成为悬空薄膜)，简化了感压薄膜的制造工艺。与此同时，通过这种热处理工艺形成的感压薄膜平整度高、厚度较薄，可以薄至1微米。再者，经热处理工艺形成的第一真空腔的侧壁比较平滑，边角均为圆角，使得感压薄膜基本无应力存在。
进一步地，在进行第一热处理之后，可以通过外延工艺在衬底上形成器件层，该器件层的材料与感压薄膜的材料相同，可以作为感压薄膜的一部分。由于该器件层的厚度很容易控制，故压力传感器的感压薄膜的整体厚度可以在较大范围内调整。
附图说明
图1至图15是本发明的一实施例中压力传感器在不同制造阶段的截面图；
图16是本发明的一实施例中压力传感器的平面图。
具体实施方式
下面结合附图先对本发明提供的压力传感器制造方法的具体实施方式做详细说明。
如图1所示，提供衬底1，衬底1包括上表面11和下表面12。在本实施例中，衬底1为单晶硅衬底。当然，在其他实施例中，衬底1也可以选用其他合适的半导体材料。
如图2所示，在衬底1的上表面上形成具有若干图形14(即为窗口)的保护层13。保护层13的制造方法包括：采用低压化学气相沉积、等离子体化学气相沉积或热氧化等工艺在衬底1的上表面形成保护材料层(未图示)之后，然后采用光刻和湿法腐蚀工艺，或者光刻和干法刻蚀工艺去除部分保护材料层，形成具有图形14的保护层13。该具体实施方式中，保护层13的材料为氧化硅，在本发明的其他具体实施方式中，保护层13的材料还可以为氮化硅、碳化硅、氮氧化硅等介质材料，可以为单层或多层复合结构。
如图3所示，以保护层13为掩膜，刻蚀衬底1，在衬底1内形成若干第一 孔15。由于第一孔15位于衬底1的表面，故也可以将其称之为第一槽。该具体实施方式中，采用各向异性刻蚀工艺，例如深反应离子硅刻蚀(DRIE)工艺，刻蚀衬底1得到若干第一孔15，定义相邻两第一孔15之间的部分为图形15a。在本实施例中，若干第一孔15呈阵列排布，第一孔15为圆孔，该圆孔的深度为几微米，直径约为0.5微米～1.5微米，例如可以为1微米，各个圆孔之间的间隔约为0.5微米。当然，在其他实施例中，第一孔15也可以设置为其他形状的孔，该孔可以是矩形、圆形、五边形、六边形或其他多边形，第一孔的尺寸以及间隔可以根据光刻机的光刻能力做出相适应调整。
如图4所示，去除保护层13。在具体实施例中，采用干法刻蚀或湿法腐蚀工艺，如用缓冲氢氟酸(BOE)去除保护层13。
如图5所示，对衬底1进行第一热处理，使得若干第一孔15(参考图4)合并成悬空的第一真空腔16，所谓悬空是指第一真空腔16位于衬底1的内部，与衬底1的上表面11存在一定的间隔。衬底1中位于上表面11与第一真空腔16之间的部分定义为第一悬空薄膜17。
结合图4至图5所示，在所述第一热处理的作用下，第一孔15会沿水平方向扩大，使得各个第一孔15之间相互连通，从而合并为一个完整的大孔，即为第一真空腔16。与此同时，在所述第一热处理的作用下，衬底1的上表面能量降低，使得衬底1的上表面发生迁移，各个图形15a的端部得以相互结合为一个整体，从而在第一真空腔16的上方形成第一悬空薄膜17。通过该第一热处理工艺形成的第一悬空薄膜17很平整，且厚度较薄，可以薄至1微米。在具体实施例中，第一真空腔16位于衬底1内部的中心偏上位置。而且，利用第一热处理工艺形成的第一真空腔16的侧壁比较平滑，且如图5所示，第一真空腔16的边角均为圆角，使得第一悬空薄膜17基本无应力存在。由于真空腔与悬空薄膜利用热处理工艺形成，避免了传统的体硅刻蚀、牺牲层刻蚀、晶圆键合所带来的一系列不良影响。
具体的，所述第一热处理在不含氧、低压(低于大气压)的环境下进行，以防止衬底1被氧化。在一实施例中，该不含氧的环境为纯氢气环境。当然，在其他实施例中，该不含氧的环境也可以为惰性气体环境。所述第一热处理的环境压强可以小于1个大气压，使得形成的第一真空腔16内气压小于1个大 气压。
在本实施例中，所述第一热处理的温度1100摄氏度。当然，在其他实施例中，所述第一热处理的温度也可以高于1100摄氏度。进一步的，在本实施例中，所述第一热处理为快速热退火。
如图6所示，通过外延工艺形成覆盖衬底1的器件层18。由于采用外延工艺，故器件层18的材料与衬底1的材料相同，在本实施例中，器件层18的材料为单晶硅。
如图7所示，在器件层18上形成具有若干图形20(即为窗口)的保护层19。保护层19的制造方法包括：采用低压化学气相沉积、等离子体化学气相沉积或热氧化等工艺在器件层18的上表面形成保护材料层(未图示)之后，然后采用光刻和湿法腐蚀工艺，或者光刻和干法刻蚀工艺去除部分保护材料层，形成具有图形20的保护层19。该具体实施方式中，保护层19的材料为氧化硅，在本发明的其他具体实施方式中，保护层19的材料还可以为氮化硅、碳化硅、氮氧化硅等介质材料，可以为单层或多层复合结构。
如图8所示，以保护层19为掩膜，刻蚀具有器件层18的衬底1，在衬底1内形成若干第二孔21。由于第二孔21位于器件层18的表面，故也可以将第二孔21称之为第二槽。该具体实施方式中，采用各向异性刻蚀工艺，例如深反应离子硅刻蚀(DRIE)工艺，刻蚀衬底1得到若干第二孔21，定义相邻两第二孔21之间的部分为图形21a。在本实施例中，若干第二孔21呈阵列排布，第二孔21为圆孔，该圆孔的深度为几微米，直径可以为0.5微米～1.5微米，例如可以为1微米，各个圆孔之间的间隔约为0.5微米。当然，在其他实施例中，第二孔21也可以设置为其他形状的孔，该孔可以是矩形、圆形、五边形、六边形或其他多边形。进一步的，在本实施例中，若干第二孔21均位于第一真空腔16的正上方。
如图9所示，去除保护层19。在具体实施例中，采用干法刻蚀或湿法腐蚀工艺，如用缓冲氢氟酸(BOE)去除保护层19。
如图10所示，对衬底1进行第一热处理，使得若干第二孔21(参考图9)合并成悬空的第二真空腔7，所谓悬空是指第二真空腔7位于具有器件层18的衬底1的内部，与器件层18的上表面存在一定的间隔。器件层18的上表面 11与第二真空腔7之间的部分定义为第二悬空薄膜8(也称之为感压薄膜)。在本实施例中，第二真空腔7位于第一真空腔16的正上方，且第二真空腔7的宽度(水平方向尺寸)小于第一真空腔16的宽度。
结合图9至图10所示，在所述第二热处理的作用下，第二孔21会沿水平方向扩大，使得各个第二孔21之间相互连通，从而合并为一个完整的大孔，即为第二真空腔7。与此同时，在所述第二热处理的作用下，器件层18的上表面能量降低，使得器件层18的上表面发生迁移，各个图形21a的端部得以相互结合为一个整体，从而在第二真空腔7的上方形成第二悬空薄膜8。通过该第二热处理工艺形成的第二悬空薄膜8很平整，且厚度较薄，可以薄至1微米。而且，利用第一热处理工艺形成的第二真空腔7的侧壁比较平滑，且如图10所示，第二真空腔7的边角均为圆角，第二悬空薄膜8基本无应力存在。
具体的，所述第二热处理在不含氧、低压(低于大气压)的环境下进行，以防止衬底1被氧化。在一实施例中，该不含氧的环境为纯氢气环境。当然，在其他实施例中，该不含氧的环境也可以为惰性气体环境。所述第二热处理的环境压强可以小于1个大气压，使得形成的第二真空腔7内气压小于1个大气压。
在本实施例中，所述第二热处理的温度1100摄氏度。当然，在其他实施例中，所述第二热处理的温度也可以高于1100摄氏度。进一步的，在本实施例中，所述第二热处理为快速热退火。
如图11所示，在器件层18上形成第一介质层23，其作为阻挡层，材料可以为氧化硅、氮化硅、氮氧化硅等，形成工艺可以为低压化学气相沉积、等离子体化学气相沉积或热氧化等工艺。
继续参考图11所示，形成若干压阻10，压阻10位于第二真空腔7的正上方。在本实施例中，压阻10的形成工艺为离子注入，即通过对器件层18表层的特定区域进行离子注入以获得压阻10。
继续参考图11所示，形成覆盖于第一介质层23的第二介质层22。第二介质层22的材料可以为氧化硅、氮化硅、氮氧化硅等，形成工艺可以为低压化学气相沉积、等离子体化学气相沉积或热氧化等工艺。
如图12所示，去除部分第二介质层22和第一介质层23，以形成若干窗口 24，各个窗口24露出对应的部分压阻10。窗口24的形成方法为先光刻再进行反应离子刻蚀。
如图13所示，在第二介质层22上形成若干金属电极9，金属电极9的一部分填充至窗口24内并与压阻10形成欧姆接触。在本实施例中，金属电极9的形成方法包括：形成覆盖第二介质层22的金属材料层，该金属材料层的一部分填充至窗口24内，并与下方的压阻10形成欧姆接触；该金属材料层的形成方法可以为淀积或电镀；在该金属材料层的上方形成图形化掩膜层，以该图形化掩膜层为掩膜对该金属材料层进行刻蚀，以形成金属电极9，该刻蚀工艺可以为干法刻蚀或湿法刻蚀，该图形化掩膜层可以为光刻胶层。
如图14所示，在金属电极9上形成一具有图形27的保护层26，保护层26覆盖于第二介质层22之上，图形27位于金属电极9的外围。
保护层26的制造方法包括：采用低压化学气相沉积、等离子体化学气相沉积或热氧化等工艺在第二介质层22和金属电极9的上表面形成保护材料层(未图示)之后，然后采用光刻和湿法腐蚀工艺，或者光刻和干法刻蚀工艺去除部分保护材料层，形成具有图形27的保护层26。该具体实施方式中，保护层26的材料为氧化硅，在本发明的其他具体实施方式中，保护层26的材料还可以为氮化硅、碳化硅、氮氧化硅等介质材料，可以为单层或多层复合结构。
如图15所示，以保护层26为掩膜，刻蚀第二介质层22、第一介质层23至衬底1，以形成沟槽25以及由沟槽25环绕的感应本体6，沟槽25与第一真空腔16连通构成收容腔(未标识)。在本实施例中，该刻蚀工艺为干法刻蚀，具体为深反应离子硅刻蚀(DRIE)工艺。
具体地，第二真空腔7位于感应本体6内，压阻10和金属电极9均位于感应本体6内。感应本体6由沟槽25以及第一真空腔16围成，并可以沿着垂直于衬底1的方向运动，以在受到外力的作用时发生形变从而根据压阻10的阻值变化检测压力。
结合图15和图16所示，在本实施例中，沟槽25呈具有缺口(未标识)的环状，沟槽25的数量为两个，分别为外侧沟槽和内侧沟槽，其中，外侧沟槽的缺口与内侧沟槽的缺口呈180度间隔设置。更具体的，沟槽25为矩形，其中一条边设置有缺口。衬底1中位于外侧沟槽与内侧沟槽之间的部分构成一 支撑梁5，衬底1中位于该沟槽25的缺口的部分也构成另一支撑梁，该两个支撑梁均与感应本体6连接，使得感应本体6可以悬空。
需说明的是，参考图15所示，在本发明的实施例中，沟槽25的数量并不应局限于两个，其数量可以任意设置，例如，沟槽25可以仅为一个。每个沟槽25的缺口数量可以任意设置，例如可以为两个。另外，沟槽25的形状也不应局限于矩形，还可以设置为圆形、五边形、六边形等多边形。
另外，第一真空腔16的数量并不应局限于一个，其还可以为两个，两个第一真空腔16沿水平方向间隔设置，第二真空腔7位于两个第一真空腔16之间，各个第一真空腔均与垂直延伸的沟槽连通，在这种情况下，所有第一真空腔与所有沟槽围成感应本体。
再者，在本实施例的变换例中，形成第一真空腔16之后，可以省略形成器件层、第二真空腔的步骤，直接进行形成压阻、金属电极、沟槽的步骤，依据该变换方法形成的感应本体内没有第二悬空薄膜，根据第一热处理步骤形成的第一悬空薄膜即为感压薄膜。
下面结合附图接着对本发明提供的压力传感器的具体实施方式做详细说明。
如图15所示，该压力传感器包括衬底1。在本实施例中，衬底1为单晶硅衬底。当然，在其他实施例中，衬底1也可以选用其他合适的半导体材料。
衬底1内形成有悬空的第一真空腔16，所谓悬空是指第一真空腔16位于衬底1的内部，与衬底1的上表面(未标识)存在一定的间隔。第一真空腔16由若干间隔排列的第一槽经第一热处理合并而成，该第一槽位于衬底1的表面。换言之，通过先在衬底1的表面形成若干间隔排列的第一槽，再进行第一热处理，可以使得该些第一槽合并成悬空的第一真空腔16。
在所述第一热处理的作用下，该第一槽会沿水平方向扩大，使得各个第一槽之间相互连通，从而合并为一个完整的大孔，即为第一真空腔16。与此同时，在所述第一热处理的作用下，衬底1的上表面能量降低，使得衬底1的上表面发生迁移，各个第一槽之间的部分的端部得以相互结合为一个整体，从而在第一真空腔16的上方形成第一悬空薄膜(未标识)。通过该第一热处理工艺形成的第一悬空薄膜很平整，且厚度较薄，可以薄至1微米。在具体实施例中，第 一真空腔16位于衬底1内部的中心偏上位置。
具体的，所述第一热处理在不含氧、低压(低于大气压)的环境下进行，以防止衬底1被氧化。在一实施例中，该不含氧的环境为纯氢气环境。当然，在其他实施例中，该不含氧的环境也可以为惰性气体环境。所述第一热处理的环境压强可以小于1个大气压，使得形成的第一真空腔16内气压小于1个大气压。
在本实施例中，所述第一热处理的温度1100摄氏度。当然，在其他实施例中，所述第一热处理的温度也可以高于1100摄氏度。进一步的，在本实施例中，所述第一热处理为快速热退火。
在本实施例中，衬底1上形成有器件层18，器件层18通过外延生长的方式形成，即为外延层，具有与衬底1相同的材料，衬底1与器件层18构成半导体衬底(未标识)。
器件层18上形成有第一介质层23，其作为阻挡层，材料可以为氧化硅、氮化硅、氮氧化硅等，形成工艺可以为低压化学气相沉积、等离子体化学气相沉积或热氧化等工艺。
第一介质层23上形成有第二介质层22。第二介质层22的材料可以为氧化硅、氮化硅、氮氧化硅等，形成工艺可以为低压化学气相沉积、等离子体化学气相沉积或热氧化等工艺。
沟槽25穿过第一真空腔16上方的半导体衬底、第一介质层23以及第二介质层22，并与第一真空腔16连通。沟槽25与第一真空腔16围成感应本体6。
结合图15和图16所示，在本实施例中，沟槽25呈具有缺口(未标识)的环状，沟槽25的数量为两个，分别为外侧沟槽和内侧沟槽，其中，外侧沟槽的缺口与内侧沟槽的缺口呈180度间隔设置。更具体的，沟槽25为矩形，其中一条边设置有缺口。衬底1中位于外侧沟槽与内侧沟槽之间的部分构成一支撑梁5，衬底1中位于该沟槽25的缺口的部分也构成另一支撑梁，该两个支撑梁均与感应本体6连接，使得感应本体6可以悬空。
需说明的是，参考图15所示，在本发明的实施例中，沟槽25的数量并不应局限于两个，其数量可以任意设置，例如，沟槽25可以仅为一个。每个沟 槽25的缺口数量可以任意设置，例如可以为两个。另外，沟槽25的形状也不应局限于矩形，还可以设置为圆形、五边形、六边形等多边形。
在本实施例中，器件层18内形成有悬空的第二真空腔7，所谓悬空是指第二真空腔7位于器件层18的内部，与器件层18的上表面(未标识)存在一定的间隔。第二真空腔7位于感应本体6内，并位于第一真空腔16的正上方。
第二真空腔7由若干间隔排列的第二槽经第二热处理合并而成，该第二槽位于器件层18的表面。换言之，通过先在器件层18的表面形成若干间隔排列的第二槽，再进行第二热处理，可以使得该些第二槽合并成悬空的第二真空腔7。
在所述第二热处理的作用下，该第二槽会沿水平方向扩大，使得各个第二槽之间相互连通，从而合并为一个完整的大孔，即为第二真空腔7。与此同时，在所述第二热处理的作用下，器件层18的上表面能量降低，使得器件层18的上表面发生迁移，各个第二槽之间的部分的端部得以相互结合为一个整体，从而在第二真空腔7的上方形成第二悬空薄膜(未标识)。通过该第二热处理工艺形成的第二悬空薄膜很平整，且厚度较薄，可以薄至1微米。在具体实施例中，第二真空腔7位于器件层18内部的中心偏上位置。
具体的，所述第二热处理在不含氧、低压(低于大气压)的环境下进行，以防止器件层18和衬底1被氧化。在一实施例中，该不含氧的环境为纯氢气环境。当然，在其他实施例中，该不含氧的环境也可以为惰性气体环境。所述第二热处理的环境压强可以小于1个大气压，使得形成的第二真空腔7内气压小于1个大气压。
在本实施例中，所述第二热处理的温度1100摄氏度。当然，在其他实施例中，所述第二热处理的温度也可以高于1100摄氏度。进一步的，在本实施例中，所述第二热处理为快速热退火。
需说明的是，第一真空腔16的数量并不应局限于一个，其还可以为两个，两个第一真空腔16沿水平方向间隔设置，第二真空腔7位于两个第一真空腔16之间，各个第一真空腔均与垂直延伸的沟槽连通，在这种情况下，所有第一真空腔与所有沟槽围成感应本体。
在本发明的变换例中，压力传感器内没有第二真空腔，也没有器件层18 (使得半导体衬底仅由单纯的衬底构成)，第一介质层23直接覆盖在衬底1的表面，压阻10直接形成在衬底1的表面。
器件层18的表面形成有若干压阻10，压阻10位于第二真空腔7的正上方。在本实施例中，压阻10的形成工艺为离子注入，即通过对器件层18表层的特定区域进行离子注入以获得压阻10。金属电极9位于第二介质层22的上方，且其一端穿过第二介质层22和第一介质层23与下方的压阻10形成欧姆接触。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (17)

  1. 一种压力传感器的制造方法，其特征在于，包括：
    提供衬底；
    在所述衬底的表面形成若干间隔排列的第一孔；
    进行第一热处理，使得若干所述第一孔合并成悬空的第一真空腔；
    形成与所述第一真空腔连通的沟槽以及由所述沟槽环绕的感应本体。
  2. 根据权利要求1所述的制造方法，其特征在于，所述第一热处理为快速热退火。
  3. 根据权利要求1所述的制造方法，其特征在于，所述第一热处理的温度不小于1100摄氏度。
  4. 根据权利要求1所述的制造方法，其特征在于，还包括：
    通过外延工艺形成覆盖所述衬底的器件层。
  5. 根据权利要求4所述的制造方法，其特征在于，还包括：
    在所述器件层的表面形成若干间隔排列的第二孔；
    进行第二热处理，使得若干所述第二孔合并成悬空的第二真空腔，所述第二真空腔位于所述感应本体内。
  6. 根据权利要求5所述的制造方法，其特征在于，所述第二热处理为快速热退火。
  7. 根据权利要求5所述的制造方法，其特征在于，所述第二热处理的温度不小于1100摄氏度。
  8. 根据权利要求5所述的制造方法，其特征在于，所述第二孔的直径为0.5微米～1.5微米，所述第一孔的直径为0.5微米～1.5微米。
  9. 根据权利要求5所述的制造方法，其特征在于，所述第二真空腔位于所述第一真空腔的正上方。
  10. 根据权利要求1至9任一项所述的制造方法，其特征在于，所述沟槽为具有缺口的环状；
    所述沟槽的数量为两个，分别为第一、二沟槽，所述第一沟槽环绕在所述第二沟槽的外侧，且所述第一沟槽的缺口与第二沟槽的缺口呈180度间隔设置。
  11. 一种压力传感器，其特征在于，包括：
    半导体衬底；
    位于所述半导体衬底内的悬空的第一真空腔，所述第一真空腔由若干间隔排列的第一槽经第一热处理合并而成；
    位于所述半导体衬底内的沟槽，所述沟槽穿过部分半导体衬底直至与所述第一真空腔连通，所述沟槽与第一真空腔围成感应本体。
  12. 如权利要求11所述的压力传感器，其特征在于，所述半导体衬底包括衬底和位于所述衬底上的器件层，所述器件层为外延层。
  13. 根据权利要求12所述的压力传感器，其特征在于，所述器件层内具有悬空的第二真空腔，所述第二真空腔位于所述感应本体内，并由若干间隔排列的第二槽经第二热处理合并而成。
  14. 根据权利要求13所述的压力传感器，其特征在于，所述第二真空腔位于所述第一真空腔的正上方。
  15. 根据权利要求13所述的压力传感器，其特征在于，所述第二热处理为快速热退火。
  16. 根据权利要求11至15任一项所述的压力传感器，其特征在于，所述沟槽为具有缺口的环状；
    所述沟槽的数量为两个，分别为第一、二沟槽，所述第一沟槽环绕在所述第二沟槽的外侧，且所述第一沟槽的缺口与第二沟槽的缺口呈180度间隔设置。
  17. 根据权利要求11至15任一项所述的压力传感器，其特征在于，所述第一热处理为快速热退火。
PCT/CN2019/112938 2019-03-06 2019-10-24 压力传感器及其制造方法 WO2020177339A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910166629.6 2019-03-06
CN201910166629.6A CN109809355A (zh) 2019-03-06 2019-03-06 压力传感器及其制造方法

Publications (1)

Publication Number Publication Date
WO2020177339A1 true WO2020177339A1 (zh) 2020-09-10

Family

ID=66608218

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/112938 WO2020177339A1 (zh) 2019-03-06 2019-10-24 压力传感器及其制造方法

Country Status (2)

Country Link
CN (1) CN109809355A (zh)
WO (1) WO2020177339A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109809355A (zh) * 2019-03-06 2019-05-28 苏州敏芯微电子技术股份有限公司 压力传感器及其制造方法
CN112701128B (zh) * 2020-12-29 2022-04-19 上海烨映微电子科技股份有限公司 Son结构及其制备方法
CN113008420A (zh) * 2021-03-01 2021-06-22 苏州敏芯微电子技术股份有限公司 压力传感器及其制造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030168711A1 (en) * 2000-07-25 2003-09-11 Stmicroelectronics S.R.I. Process for manufacturing an SOI wafer by annealing and oxidation of buried channels
US20060063352A1 (en) * 2004-09-16 2006-03-23 Stmicroelectronics S.R.I Process for manufacturing wafers of semiconductor material by layer transfer
CN103991836A (zh) * 2013-02-19 2014-08-20 苏州敏芯微电子技术有限公司 微机电系统传感器及其制造方法
CN105036059A (zh) * 2015-06-24 2015-11-11 上海芯赫科技有限公司 一种电容式mems传感器的加工方法及传感器结构
CN106018879A (zh) * 2016-05-12 2016-10-12 上海芯赫科技有限公司 一种mems加速度传感器及制造方法
CN206126837U (zh) * 2016-03-31 2017-04-26 意法半导体股份有限公司 具有微机械结构的mems压力传感器
CN106744649A (zh) * 2015-11-19 2017-05-31 意法半导体股份有限公司 具有两个掩埋腔的微机电器件及其制造方法
CN109205549A (zh) * 2017-07-03 2019-01-15 无锡华润上华科技有限公司 双空腔结构的制备方法
CN109809355A (zh) * 2019-03-06 2019-05-28 苏州敏芯微电子技术股份有限公司 压力传感器及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105890827B (zh) * 2016-01-18 2019-05-21 广东合微集成电路技术有限公司 一种电容式压力传感器及其制造方法
CN210559358U (zh) * 2019-03-06 2020-05-19 苏州敏芯微电子技术股份有限公司 压力传感器

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030168711A1 (en) * 2000-07-25 2003-09-11 Stmicroelectronics S.R.I. Process for manufacturing an SOI wafer by annealing and oxidation of buried channels
US20060063352A1 (en) * 2004-09-16 2006-03-23 Stmicroelectronics S.R.I Process for manufacturing wafers of semiconductor material by layer transfer
CN103991836A (zh) * 2013-02-19 2014-08-20 苏州敏芯微电子技术有限公司 微机电系统传感器及其制造方法
CN105036059A (zh) * 2015-06-24 2015-11-11 上海芯赫科技有限公司 一种电容式mems传感器的加工方法及传感器结构
CN106744649A (zh) * 2015-11-19 2017-05-31 意法半导体股份有限公司 具有两个掩埋腔的微机电器件及其制造方法
CN206126837U (zh) * 2016-03-31 2017-04-26 意法半导体股份有限公司 具有微机械结构的mems压力传感器
CN106018879A (zh) * 2016-05-12 2016-10-12 上海芯赫科技有限公司 一种mems加速度传感器及制造方法
CN109205549A (zh) * 2017-07-03 2019-01-15 无锡华润上华科技有限公司 双空腔结构的制备方法
CN109809355A (zh) * 2019-03-06 2019-05-28 苏州敏芯微电子技术股份有限公司 压力传感器及其制造方法

Also Published As

Publication number Publication date
CN109809355A (zh) 2019-05-28

Similar Documents

Publication Publication Date Title
WO2020177339A1 (zh) 压力传感器及其制造方法
US6428713B1 (en) MEMS sensor structure and microfabrication process therefor
US6743654B2 (en) Method of fabricating pressure sensor monolithically integrated
KR100301097B1 (ko) 가속도센서용소자및그제조방법
KR100462569B1 (ko) 반도체 압력 센서 및 그 제조방법
KR101195297B1 (ko) 압력 센서 및 그 제조 방법
JP5426437B2 (ja) 圧力センサおよび圧力センサの製造方法
GB2274945A (en) Capacitive micromachined differential pressure sensor
CN111704104A (zh) 用于制造mems压力传感器的方法和相应的mems压力传感器
KR101178989B1 (ko) 압력 센서 및 그 제조 방법
CN114275731A (zh) 一种基于mems的双梁式微压感测芯体及其制备工艺
KR102163052B1 (ko) 압력 센서 소자 및 그 제조 방법
JP4918140B2 (ja) 半導体圧力センサ
JP2010199133A (ja) Ｍｅｍｓの製造方法、ｍｅｍｓ
CN210559358U (zh) 压力传感器
US7871894B2 (en) Process for manufacturing thick suspended structures of semiconductor material
US20230061430A1 (en) Method for manufacturing an integrated system including a capacitive pressure sensor and an inertial sensor, and integrated system
KR102297944B1 (ko) Mems 압저항 압력센서 및 그 제조방법
BG66488B1 (bg) Метод за изработване на прибори за мемс с електрически елементи в страничните им стени
CN110182753B (zh) 高灵敏度加速度传感器结构的制作方法
JPH11186567A (ja) 半導体力学量センサの製造方法
CN218381358U (zh) 一种mems压力传感器
CN218381359U (zh) 一种mems压力传感器
CN115321474B (zh) 一种基于soi硅片的硅纳米线陀螺仪的制备方法
JPH0323676A (ja) 半導体加速度センサおよびその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19918169

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19918169

Country of ref document: EP

Kind code of ref document: A1