WO2020177089A1 - 具有差分架构的2t2r阻变式存储器、mcu及设备 - Google Patents

具有差分架构的2t2r阻变式存储器、mcu及设备 Download PDF

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Publication number
WO2020177089A1
WO2020177089A1 PCT/CN2019/077093 CN2019077093W WO2020177089A1 WO 2020177089 A1 WO2020177089 A1 WO 2020177089A1 CN 2019077093 W CN2019077093 W CN 2019077093W WO 2020177089 A1 WO2020177089 A1 WO 2020177089A1
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Prior art keywords
switching device
resistive
resistive switching
transistor
voltage
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PCT/CN2019/077093
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English (en)
French (fr)
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姚国峰
沈健
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深圳市汇顶科技股份有限公司
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Priority to CN201980000337.3A priority Critical patent/CN111902873B/zh
Priority to PCT/CN2019/077093 priority patent/WO2020177089A1/zh
Publication of WO2020177089A1 publication Critical patent/WO2020177089A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM

Definitions

  • This application relates to the technical field of semiconductor memory, and in particular to a 2T2R resistive variable memory, a micro controller unit (MCU) and a device with a differential architecture.
  • MCU micro controller unit
  • Resistive Random Access Memory is a new type of non-volatile memory (Non-volatile Memory, NVM) that uses the variable resistance of the device to achieve data storage. Because of its low operating power consumption, The advantages of fast read and write speed have attracted much attention.
  • RRAM includes: an array composed of multiple memory cells.
  • Common memory cell structures include 1T1R, 1D1R, 1S1R, etc., where T refers to a transistor (Transistor), R refers to a resistive switching device (Resistive Switching Device), and D refers to It is a diode (Diode).
  • FIG. 1 is a schematic diagram of a memory cell array with a 1T1R structure provided by the prior art. As shown in FIG. 1, each memory cell 10 is composed of a transistor (T) 11 and a resistive switching device (R) 12 in series.
  • the resistive switching device 12 is usually composed of an electrode 120, a resistive switching layer 121 and an electrode 122, and its resistance changes with the applied voltage.
  • the resistance value can be divided into low resistance state (LRS) and high resistance.
  • High Resistance State (HRS) which can correspond to logical "1" and "0".
  • the process of writing the low-impedance state is called set. The specific steps are: select the corresponding row through the word line (WL), and apply a turn-on voltage on the word first to turn on the transistors in the row, and apply the operating voltage to the corresponding row.
  • the bit line (BL) of the column and the source line (SL) of the corresponding column are grounded, and the voltage on the bit line can complete the set process of the RRAM.
  • the process of writing a high-impedance state is called reset, and its steps are similar to writing a low-impedance state, except that the operating voltage is applied to the source line of the corresponding column, and the bit line is grounded.
  • the reading process of the state of the memory cell is: select the corresponding row through the word line, the source line of the corresponding column is grounded, and the read voltage is applied to the bit line to complete the low resistance State or high-impedance state.
  • the present application provides a 2T2R resistive memory, MCU, and device with a differential architecture.
  • the 2T2R resistive random access memory can offset the negative effects caused by various parasitic parameters and line noise in the memory, thereby improving the reliability of the 2T2R resistive random access memory.
  • the present application provides a 2T2R resistive memory with a differential architecture, including: a memory cell array composed of a plurality of 2T2R resistive memory cells; each 2T2R resistive memory cell includes a first transistor and a second transistor. Transistor, first resistive switching device and second resistive switching device; the gate of the first transistor and the gate of the second transistor are connected on the same word line, and the source of the first transistor and the source of the second transistor are respectively connected On the first bit line and the second bit line, the drain of the first transistor is connected to the first electrode of the first resistive switching device, and the drain of the second transistor is connected to the first electrode of the second resistive switching device.
  • the second electrode of the resistive switching device and the second electrode of the second resistive switching device are connected on the same source line; wherein, the first electrode of the first resistive switching device and the first electrode of the second resistive switching device are located on the same layer.
  • the second electrode of a resistive switching device and the second electrode of the second resistive switching device are located on the same layer.
  • the connection mode of the first resistive switching device and the second resistive switching device may be referred to as the same connection mode.
  • the structural design of the 2T2R resistive random access memory due to the structural design of the 2T2R resistive random access memory, the negative effects caused by various parasitic parameters and line noise inside the memory can be offset, making the reading of high and low resistance states more accurate and stable.
  • the structural design of the 2T2R resistive random access memory can effectively solve the problem of insufficient consistency of memory cells.
  • the memory cell of the 2T2R structure has lower requirements for process consistency.
  • the circuit design of the 2T2R resistive switching memory is simplified and the process is easy to implement.
  • the present application provides an MCU, which has the 2T2R resistive memory as in the first aspect.
  • the effect can refer to the effect of the aforementioned 2T2R resistive random access memory.
  • the MCU is used to control the charging unit to apply a turn-on voltage on the word line to turn on the first transistor and the second transistor, and to control the charging unit to apply the first operating voltage on the first bit line and the second A second operating voltage is applied to the bit line; wherein the first operating voltage is different from the second operating voltage, and the voltage difference between the first operating voltage and the voltage on the source line causes the first resistive switching device to change from a high resistance state to a low resistance
  • the voltage difference between the second operating voltage and the voltage on the source line causes the second resistive switching device to change from a low resistance state to a high resistance state; or, the voltage difference between the first operating voltage and the voltage on the source line makes the A resistance switching device changes from a low resistance state to a high resistance state, and the voltage difference between the second operating voltage and the voltage on the source line causes the second resistance switching device to change from a high resistance state to a low resistance state.
  • the MCU is used to control the charging unit to charge on the first bit line and the second bit line, so that the voltage on the first bit line and the second bit line reach the same read voltage, and control the charging
  • the unit stops charging the first bit line and the second bit line after a preset time, and controls the charging unit to apply a voltage on the source line and a turn-on voltage on the word line to turn on the first transistor and the second transistor to Start the discharge of the first bit line and the second bit line, and obtain the relative resistance value of the first resistive switching device and the second resistive switching device according to the discharge speed of the first bit line and the second bit line.
  • the relative resistance of the second resistive switching device determines the state of the 2T2R resistive switching memory cell.
  • the voltage applied on the source line is less than the read voltage, and the voltage difference between the read voltage and the voltage applied on the source line is less than a preset threshold, where the preset threshold It can be 0.2 volts or 0.1 volts. Therefore, it is possible to avoid the state change of the resistive switching device due to the excessive voltage difference.
  • the state of the 2T2R resistive switching memory cell is that the first resistive switching device is in a high resistance state relative to the second resistive switching device, and the second resistive switching device is in a low resistance state relative to the first resistive switching device.
  • the first resistance switching device is in a low resistance state relative to the second resistance switching device, and the second resistance switching device is in a high resistance state relative to the first resistance switching device.
  • the present application provides a device including: the 2T2R resistive memory as described in the first aspect.
  • the present application provides a device including: the MCU as described in the first aspect.
  • the present application provides a 2T2R resistive memory, MCU, and device with a differential architecture.
  • the 2T2R resistive random access memory due to the structural design of the 2T2R resistive random access memory, the negative effects caused by various parasitic parameters and line noise inside the memory can be offset, and the reading of high and low resistance states is more accurate and stable.
  • the problem of insufficient consistency of memory cells can be effectively solved.
  • the memory cell of the 2T2R structure has lower requirements for process consistency.
  • the circuit design of the 2T2R resistive switching memory is simplified and the process is easy to implement.
  • the 2T2R resistive random access memory with a differential architecture provided by the present application has the advantages of high storage density and data retention after power failure.
  • FIG. 1 is a schematic diagram of a memory cell array with a 1T1R structure provided by the prior art
  • 2A is a schematic diagram of a memory cell array with a 2T2R structure provided by this application;
  • 2B is a schematic diagram of a 2T2R resistive memory cell according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of an MCU provided by an embodiment of this application.
  • FIG. 4 is a timing diagram of the word line WL, the source line SL, the first bit line BL, and the second bit line BLB during the writing process of the storage state of the memory cell according to an embodiment of the application;
  • FIG. 5 is a timing diagram of the word line WL, the source line SL, the first bit line BL, and the second bit line BLB during the reading process of the storage state of the memory cell according to an embodiment of the application;
  • FIG. 6 is a schematic diagram of a device 60 provided by an embodiment of this application.
  • the resistive random access memory of the 1T1R structure is also more sensitive to process conditions. Even on the same wafer, memory cells at different locations may exhibit different resistive behavior due to process fluctuations, which further increases the resistance of high and low resistance states. Difficulty to read.
  • the present application provides a 2T2R resistive memory, MCU and device with a differential architecture.
  • the main idea of this application is: this application provides a 2T2R resistive random access memory with a differential architecture.
  • the 2T2R resistive random access memory has a 2T2R symmetrical structure, and specifically includes a first transistor (T1) and a second transistor (T2).
  • the gates (Gate) of T1 and T2 are connected to the same word line (WL), the source (Source) is connected to two different bit lines (BL and BLB), and the drain (Drain) is connected to R1 and R2 respectively.
  • An electrode such as BE.
  • the other electrodes of R1 and R2, such as TE, are connected to the same source line (SL).
  • the first resistive switching device (R1) and the second resistive switching device (R2) are connected in the same direction.
  • the MCU can determine the state of the memory cell through the relative magnitude of the resistance of the two resistive devices.
  • the structural design of the 2T2R resistive random access memory due to the structural design of the 2T2R resistive random access memory, the negative effects caused by various parasitic parameters and line noise inside the memory can be offset, making the reading of high and low resistance states more accurate and stable.
  • the structural design of the 2T2R resistive random access memory can effectively solve the problem of insufficient consistency of memory cells.
  • the memory cell of the 2T2R structure has lower requirements for process consistency.
  • the circuit design of the 2T2R resistive switching memory is simplified and the process is easy to implement.
  • a 2T2R resistive memory with a differential architecture includes a memory cell array composed of a plurality of 2T2R resistive memory cells.
  • 2A is a schematic diagram of a memory cell array with a 2T2R structure provided by this application. As shown in FIG. 2A, two ends of 2T2R resistive memory cells 20 located in the same row are connected to a WL and a SL respectively, and are located in the same column. Two ends of the 2T2R resistive memory cell 20 are respectively connected to a BL and a BLB.
  • 2B is a schematic diagram of a 2T2R resistance-switching memory cell according to an embodiment of the application. As shown in FIG.
  • the 2T2R resistance-switching memory cell includes a first transistor 21 and a second transistor 22, and a first resistance-switching device 23 And second resistive switching device 24.
  • the gate 210 of the first transistor 21 and the gate 220 of the second transistor 22 are connected to the word line 25; the source 211 of the first transistor 21 and the source 221 of the second transistor 22 are connected to the first bit line 26 and the first bit line, respectively.
  • Two bit line 27; the drain 212 of the first transistor 21 and the drain 222 of the second transistor 22 are respectively connected to the first electrode 231 of the first resistive switching device 23 and the first electrode 241 of the second resistive switching device 24;
  • the second electrode 232 of a resistive switching device 23 and the second electrode 242 of the second resistive switching device 24 are connected to the source line 28.
  • the first electrode 231 of the first resistive switching device 23 is connected to the second resistive switching device 24.
  • the first electrode 241 is located on the same layer, and the second electrode 232 of the first resistive switching device 23 and the second electrode 242 of the second resistive switching device 24 are on the same layer.
  • the first electrode 231 of the first resistive switching device 23 is prepared before the second electrode 232 of the first resistive switching device 23, and the first electrode 241 of the second resistive switching device 24 is prepared before the second electrode 232 of the second resistive switching device 24.
  • the second electrode 242 is prepared.
  • the first electrode 231 of the first resistive switching device 23 is prepared after the second electrode 232 of the first resistive switching device 23, and the first electrode 241 of the second resistive switching device 24 is succeeded by the first electrode 241 of the second resistive switching device 24.
  • the second electrode 242 is prepared.
  • the circuit design of this same-direction connection mode is more simplified, and the process is easy to realize.
  • the MCU can determine the state of the 2T2R resistive switching device by reading the relative resistance of the first resistive switching device 23 and the second resistive switching device 24, for example: the first resistive switching device 23 is relative to the second resistive switching device 24 In a high resistance state, the second resistance switching device 24 is in a low resistance state relative to the first resistance switching device 23, or the first resistance switching device 23 is in a low resistance state relative to the second resistance switching device 24, and the second resistance switching device 24 is in a high resistance state relative to the first resistive switching device 23.
  • This reading method can be called differential reading. Since the above-mentioned 2T2R resistive change memory cell can realize differential reading, the memory cell can be called a memory cell with a "differential architecture".
  • Reading error conditions for example, mistakenly mistake a high-resistance state with an abnormally low resistance value as a low-resistance state, or mistake a low-resistance state with an abnormally high resistance value as a high-resistance state.
  • the resistance states of the two resistive switching devices in the memory cell are always opposite, that is, "one low and one high” instead of "two Low” or "two high”.
  • FIG. 3 is a schematic diagram of an MCU provided by an embodiment of the application. As shown in FIG. 3, the 2T2R resistive memory 31 described above is integrated on the MCU 30.
  • the 2T2R resistive memory with a differential architecture includes: a memory cell array composed of multiple 2T2R resistive memory cells; each 2T2R resistive memory cell includes a first transistor, a second transistor, and a first resistor.
  • Variable device and second resistive switching device the gate of the first transistor and the gate of the second transistor are connected on the same word line, the source of the first transistor and the source of the second transistor
  • the electrodes are respectively connected to the first bit line and the second bit line, the drain of the first transistor is connected to the first electrode of the first resistive switching device, and the drain of the second transistor is connected to the second
  • the first electrode of the resistive switching device is connected, and the second electrode of the first resistive switching device and the second electrode of the second resistive switching device are connected on the same source line; wherein the first electrode of the first resistive switching device An electrode and the first electrode of the second resistive switching device are located on the same layer, and the second electrode of the first resistive switching device and the second electrode of the second resistive switching device are
  • the first electrode of the first resistive switching device is prepared before the second electrode of the first resistive switching device, and the first electrode of the second resistive switching device is prepared before the second electrode of the second resistive switching device.
  • the first electrode of the first resistive switching device is prepared after the second electrode of the first resistive switching device, and the first electrode of the second resistive switching device is prepared after the second electrode of the second resistive switching device.
  • the state of the memory cell in the 2T2R resistive switching memory is: the first resistive switching device is in a high resistance state relative to the second resistive switching device, and the second resistive switching device is in a high resistance state relative to the first resistive switching device.
  • a resistive switching device is in a low resistance state; or, the first resistance switching device is in a low resistance state relative to the second resistance switching device, and the second resistance switching device is in a high resistance state relative to the first resistance switching device. Resistance state.
  • the logic “0” indicates that the first resistance switching device is in a low resistance state relative to the second resistance switching state
  • the second resistance switching device is in a high resistance state relative to the first resistance switching device
  • the logic “1” indicates that the first resistance switching device is in a high resistance state.
  • the device is in a high resistance state relative to the second resistance switching state
  • the second resistance switching device is in a low resistance state relative to the first resistance switching device.
  • Logic “1” means that the first resistance switching device is in a low resistance state relative to the second resistance switching state, and the second resistance switching device is in a high resistance state relative to the first resistance switching device, and logic “0” means that the first resistance switching device is relatively In the second resistance switching state, the second resistance switching device is in a high resistance state, and the second resistance switching device is in a low resistance state relative to the first resistance switching device.
  • FIG. 4 shows the word line WL during the writing process of the storage state of the memory cell provided by an embodiment of the application.
  • the MCU controls the charging unit to apply a turn-on voltage VG on the word line 25 to turn on the first transistor 21 and the second transistor 22.
  • the MCU controls the charging unit to apply an operating voltage of VDD to the first bit line 26, and to apply an operating voltage of the same magnitude but the opposite direction -VDD to the second bit line 27.
  • the source line 28 is grounded.
  • the writing of logic "1" is completed.
  • the MCU controls the charging unit to apply a turn-on voltage VG on the word line 25 to turn on The first transistor 21 and the second transistor 22.
  • the MCU controls the charging unit to apply an operating voltage of ⁇ VDD on the first bit line 26, and an operating voltage VDD of the same magnitude but opposite directions on the second bit line 27.
  • the source line 28 is grounded.
  • the writing of logic "0" is completed.
  • FIG. 5 is a timing diagram of the word line WL, the source line SL, the first bit line BL, and the second bit line BLB during the reading process of the storage state of the memory cell provided by an embodiment of the application, wherein the horizontal axis in FIG. 5 represents Time, the vertical axis represents voltage. Description will be given in conjunction with FIG. 2B and FIG. 5.
  • the MCU controls the charging unit to precharge on the first bit line 26 and the second bit line 27 to the same read voltage VRD, and stop charging until t1. Then, a voltage is applied to the source line 28, and at the same time, a turn-on voltage VG is applied to the word line 25 to turn on the first transistor 21 and the second transistor 22. It should be noted that the voltage applied to the source line 28 should be slightly less than the read voltage, for example, the voltage applied to the source line 28 is VRD-0.2 volts, which can avoid the state of the resistive switching device due to excessive voltage difference change.
  • the first bit line 26 and the second bit line 27 are discharged from time t1.
  • the first resistive switching device 23 Since the first resistive switching device 23 is in a high resistance state, its discharge rate is relatively slow; while the second resistive switching device 24 is in a low resistance state, its discharge rate is relatively fast.
  • the potentials on the first bit line 26 and the second bit line 27 are detected synchronously, and the MCU compares these two potentials. Since the potential of the first bit line 26 is higher than the potential of the second bit line 27, it reads The storage unit data is "logic 1". Similarly, if the potential of the first bit line 26 is lower than the potential of the second bit line 27, the read data of the memory cell is "logic 0".
  • the 2T2R resistive random access memory with a differential architecture provided by this application is written and read in a manner similar to that of traditional static random access memory (SRAM), for example, write The process is to apply different voltages on the two bit lines. The reading process uses precharge, and then compares the discharge rate. Therefore, the 2T2R provided by this application can be used without changing or slightly changing the peripheral circuit design. Resistive memory replaces SRAM.
  • SRAM static random access memory
  • the 2T2R resistive random access memory with differential architecture provided by this application has the following advantages:
  • SRAM is usually a 6-transistor (6T) structure, while 2T2R resistive change memory has only 2 transistors, and the memory cell area is smaller.
  • SRAM must keep the power supply consistent to keep data, and the resistive random access memory will not lose data even when the power is off.
  • FIG. 6 is a schematic diagram of a device 60 provided by an embodiment of the application. As shown in FIG. 6, the device includes: MCU 61, the aforementioned 2T2R resistive variable memory 62 with a differential architecture, and a transceiver 63, wherein the transceiver 63 is used to communicate with Data transfer between other devices.
  • the 2T2R resistive memory with a differential architecture includes: a memory cell array composed of multiple 2T2R resistive memory cells; each 2T2R resistive memory cell includes a first transistor, a second transistor, and a first resistor.
  • Variable device and second resistive switching device the gate of the first transistor and the gate of the second transistor are connected to the same word line, and the source of the first transistor and the source of the second transistor are respectively connected to the first bit line
  • the drain of the first transistor is connected to the first electrode of the first resistive switching device
  • the drain of the second transistor is connected to the first electrode of the second resistive switching device
  • the first electrode of the first resistive switching device is connected to the The two electrodes and the second electrode of the second resistive switching device are connected to the same source line; wherein, the first electrode of the first resistive switching device and the first electrode of the second resistive switching device are located on the same layer, and the The second electrode and the second electrode of the second resistive switching device are located on the same layer.
  • the device further includes: an MCU and a charging unit, and the MCU is electrically connected to the 2T2R resistive memory with a differential architecture.
  • the MCU is used to control the charging unit to apply a turn-on voltage on the word line to turn on the first transistor and the second transistor, and to control the charging unit to apply the first operating voltage on the first bit line and the second A second operating voltage is applied to the bit line; wherein the first operating voltage is different from the second operating voltage, and the voltage difference between the first operating voltage and the voltage on the source line causes the first resistive switching device to change from a high resistance state to a low resistance
  • the voltage difference between the second operating voltage and the voltage on the source line causes the second resistive switching device to change from a low resistance state to a high resistance state; or, the voltage difference between the first operating voltage and the voltage on the source line makes the A resistance switching device changes from a low resistance state to a high resistance state, and the voltage difference between the second operating voltage and the voltage on the source line causes the second resistance switching device to change from a high resistance state to a low resistance state.
  • the MCU is used to control the charging unit to charge on the first bit line and the second bit line, so that the voltage on the first bit line and the second bit line reach the same read voltage, and control the charging
  • the unit stops charging the first bit line and the second bit line after a preset time, and controls the charging unit to apply a voltage on the source line and a turn-on voltage on the word line to turn on the first transistor and the second transistor to Start the discharge of the first bit line and the second bit line, and obtain the relative resistance value of the first resistive switching device and the second resistive switching device according to the discharge speed of the first bit line and the second bit line.
  • the relative resistance of the second resistive switching device determines the state of the 2T2R resistive switching memory cell.
  • the voltage applied on the source line is less than the read voltage, and the voltage difference between the read voltage and the voltage applied on the source line is less than a preset threshold, and the preset threshold can be The value is 0.2 volts or 0.1 volts.
  • the device provided by the embodiment of the present application includes: the 2T2R resistive random access memory with a differential architecture.
  • the foregoing embodiment please refer to the foregoing embodiment, which will not be repeated here.
  • the present application also provides a device, including: an MCU, on which the 2T2R resistive variable memory with a differential architecture is integrated, and the content and effect of the 2T2R resistive memory are integrated with reference to the above-mentioned embodiments, which will not be repeated here.

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Abstract

本申请提供一种具有差分架构的2T2R阻变式存储器、MCU及设备。该存储器包括多个存储单元构成的存储单元阵列；每个存储单元包括第一晶体管、第二晶体管、第一阻变器件和第二阻变器件；第一晶体管的栅极和第二晶体管的栅极连接在同一根字线上，第一晶体管的源极和第二晶体管的源极分别连接在第一位线和第二位线上，第一晶体管的漏极与第一阻变器件的第一电极连接，第二晶体管的漏极与第二阻变器件的第一电极连接，第一阻变器件的第二电极和第二阻变器件的第二电极连接在同一根源线上；第一阻变器件与第二阻变器件的第一电极位于同一层，第一阻变器件与第二阻变器件的第二电极位于同一层。从而可以保证所述存储器的可靠性。

Description

具有差分架构的2T2R阻变式存储器、MCU及设备 技术领域
本申请涉及半导体存储器技术领域，尤其涉及一种具有差分架构的2T2R阻变式存储器、微控制单元(Micro Controller Unit，MCU)及设备。
背景技术
阻变式存储器(Resistive Random Access Memory，RRAM)是一种利用器件电阻可变的特性来实现数据存储的新型非易失性存储器(Non-volatile Memory，NVM)，因其具有操作功耗低，读写速度快等优点而备受关注。
通常RRAM包括：多个存储单元构成的阵列，常见的存储单元结构包括1T1R，1D1R，1S1R等，其中T指的是晶体管(Transistor)，R指的是阻变器件(Resistive Switching Device)，D指的是二极管(Diode)。图1为现有技术提供的一种1T1R结构的存储单元阵列的示意图，如图1所示，每个存储单元10由一个晶体管(T)11和一个阻变器件(R)12串联组成。阻变器件12通常由电极120、阻变层121和电极122构成，其阻值会随施加电压的变化而改变，按阻值大小可分为低阻态(Low Resistance State，LRS)和高阻态(High Resistance State，HRS)，可对应逻辑的“1”和“0”。写入低阻态的过程被称为set，其具体步骤为：通过字线(WL)选中对应行，并在该字先上施加开启电压，以开启该行的晶体管，将操作电压作用于对应列的位线(BL)，而对应列的源线(SL)接地，位线上的电压即可完成对RRAM的set过程。写入高阻态的过程称为reset，其步骤与写入低阻态类似，只是将操作电压作用于对应列的源线，而位线接地。存储单元的状态(即阻变器件12为低阻态或高阻态)的读取过程为：通过字线选中对应行，对应列的源线接地，将读电压作用于位线上完成低阻态或高阻态的读取过程。
然而，目前阻变存储器在技术上还存在着诸多问题，例如：阻变存储器内部存在的各种寄生和线路噪声会对高阻态或者低阻态的读取产生不利影响，从而造成阻变存储器可靠性低的问题。
发明内容
本申请提供一种具有差分架构的2T2R阻变式存储器、MCU及设备。其中该2T2R阻变式存储器可以抵消存储器内部各种寄生参数和线路噪声所带来的负面影响，从而提高了2T2R阻变式存储器的可靠性。
第一方面，本申请提供一种具有差分架构的2T2R阻变式存储器，包括：多个2T2R阻变式存储单元构成的存储单元阵列；每个2T2R阻变式存储单元包括第一晶体管、第二晶体管、第一阻变器件和第二阻变器件；第一晶体管的栅极和第二晶体管的栅极连接在同一根字线上，第一晶体管的源极和第二晶体管的源极分别连接在第一位线和第二位线上，第一晶体管的漏极与第一阻变器件的第一电极连接，第二晶体管的漏极与第二阻变器件的第一电极连接，第一阻变器件的第二电极和第二阻变器件的第二电极连接在同一根源线上；其中，第一阻变器件的第一电极与第二阻变器件的第一电极位于同一层，第一阻变器件的第二电极与第二阻变器件的第二电极位于同一层。其中，第一阻变器件和第二阻变器件的连接方式可以被称为同向连接方式。
一方面，由于该2T2R阻变式存储器的结构设计，从而可以抵消存储器内部各种寄生参数和线路噪声所带来的负面影响，使高低阻态的读取更加准确和稳定。另一方面，通过该2T2R阻变式存储器的结构设计，可以有效解决存储单元一致性不够好的问题。此外，相比1T1R结构的存储单元，2T2R结构的存储单元对工艺一致性的要求也有所降低。进一步地，由于两个阻变器件的同向连接方式，使得2T2R阻变式存储器在电路设计上更为简化，工艺上易于实现。
第二方面，本申请提供一种MCU，该MCU上具有如第一方面的2T2R阻变式存储器。其效果可参考上述2T2R阻变式存储器的效果。
在一种可能的设计中，MCU用于控制充电单元在字线上施加开启电压，以开启第一晶体管和第二晶体管，控制充电单元在第一位线上施加第一操作电压，在第二位线上施加第二操作电压；其中，第一操作电压与第二操作电压不同，第一操作电压相对于源线上的电压的电压差使得第一阻变器件由高阻态变为低阻态，第二操作电压相对于源线上的电压的电压差使得第二阻变器件由低阻态变为高阻态；或者，第一操作电压相对于源线上的电压的电压差使得第一阻变器件由低阻态变为高阻态，第二操作电压相对于源线上的电 压的电压差使得第二阻变器件由高阻态变为低阻态。
在一种可能的设计中，MCU用于控制充电单元在第一位线和第二位线上充电，以使第一位线和第二位线上的电压达到同一读取电压，并控制充电单元在预设时间之后停止对第一位线和第二位线的充电，控制充电单元在源线上施加一个电压，在字线上施加开启电压，以开启第一晶体管、第二晶体管，以使第一位线和第二位线开始放电，根据第一位线和第二位线的放电速度获取第一阻变器件和第二阻变器件的相对阻值，根据第一阻变器件和第二阻变器件的相对阻值确定2T2R阻变式存储单元的状态。
在一种可能的设计中，在源线上施加的电压小于读取电压，且所述读取电压与在所述源线上施加的电压的电压差值小于预设阈值，其中该预设阈值可以为0.2伏或者0.1伏。从而可以避免因电压差过大而造成阻变器件的状态改变。
在一种可能的设计中，2T2R阻变式存储单元的状态为第一阻变器件相对于第二阻变器件呈高阻态，第二阻变器件相对于第一阻变器件呈低阻态；或者，第一阻变器件相对于第二阻变器件呈低阻态，第二阻变器件相对于第一阻变器件呈高阻态。
第三方面，本申请提供一种设备，包括：如第一方面所述的2T2R阻变式存储器。
第四方面，本申请提供一种设备，包括：如第一方面所述的MCU。
本申请提供一种具有差分架构的2T2R阻变式存储器、MCU及设备。第一，由于该2T2R阻变式存储器的结构设计，从而可以抵消存储器内部各种寄生参数和线路噪声所带来的负面影响，使高低阻态的读取更加准确和稳定。第二，通过该2T2R阻变式存储器的结构设计，可以有效解决存储单元一致性不够好的问题。第三，相比1T1R结构的存储单元，2T2R结构的存储单元对工艺一致性的要求也有所降低。第四，由于两个阻变器件的同向连接方式，使得2T2R阻变式存储器在电路设计上更为简化，工艺上易于实现。此外，相比于SRAM，本申请提供的具有差分架构的2T2R阻变式存储器具有存储密度高以及数据掉电保持的优点。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种1T1R结构的存储单元阵列的示意图；
图2A为本申请提供的一种2T2R结构的存储单元阵列的示意图；
图2B为本申请一实施例提供一种2T2R阻变式存储单元的示意图；
图3为本申请一实施例提供的MCU的示意图；
图4为本申请一实施例提供的存储单元的存储状态的写入过程中字线WL、源线SL、第一位线BL以及第二位线BLB的时序图；
图5为本申请一实施例提供的存储单元的存储状态的读取过程中字线WL、源线SL、第一位线BL以及第二位线BLB的时序图；
图6为本申请一实施例提供的设备60的示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例，例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
如上所述，目前阻变存储器在技术上还存在着诸多问题。第一，阻变存储器内部存在的各种寄生和线路噪声会对高阻态或者低阻态的读取产生不利 影响，从而造成阻变存储器可靠性低的问题。第二，目前阻变存储器一致性(uniformity)还不够好，这个和阻变存储器的工作机理—导电细丝(conductive filament)的产生和消失具有一定的随机性和不可控制性相关。尤其是在目前阻变存储器经历了成千上万次的循环(cycling，通常一次set加一次reset操作称为一个cycling)之后，高阻态阻值分布的一致性问题更加凸显。例如：对于一个1Kb阻变式存储器，随着循环次数的增加，高阻态阻值接近低组态阻值的存储单元的比例不断增加，高低阻态间差异的缩小对于高低阻态的读取提出了很高的要求。第三，1T1R结构的阻变式存储器对于工艺条件也较为敏感，甚至在同一片晶圆上，不同位置的存储单元可能会因为工艺波动而呈现迥异的阻变行为，进一步增加了高低阻态的读取难度。
为了解决上述技术问题，本申请提供一种具有差分架构的2T2R阻变式存储器、MCU及设备。
本申请的主旨思想是：本申请提供一种具有差分架构的2T2R阻变式存储器，该2T2R阻变式存储器具有2T2R的对称结构，具体包括第一晶体管(T1)和第二晶体管(T2)，第一阻变器件(R1)和第二阻变器件(R2)。T1和T2的栅极(Gate)连接到同一根字线(WL)，源极(Source)连接到不同的两根位线(BL和BLB)，漏极(Drain)分别连接到R1和R2的一个电极如BE。R1和R2的另一电极，如TE连接到同一根源线(SL)。第一阻变器件(R1)和第二阻变器件(R2)同向连接。针对这种2T2R阻变式存储器，其中，MCU可以通过两个阻变器件阻值的相对大小确定存储单元的状态。一方面，由于该2T2R阻变式存储器的结构设计，从而可以抵消存储器内部各种寄生参数和线路噪声所带来的负面影响，使高低阻态的读取更加准确和稳定。另一方面，通过该2T2R阻变式存储器的结构设计，可以有效解决存储单元一致性不够好的问题。此外，相比1T1R结构的存储单元，2T2R结构的存储单元对工艺一致性的要求也有所降低。进一步地，由于两个阻变器件的同向连接方式，使得2T2R阻变式存储器在电路设计上更为简化，工艺上易于实现。
具体地，具有差分架构的2T2R阻变式存储器，包括：多个2T2R阻变式存储单元构成的存储单元阵列。图2A为本申请提供的一种2T2R结构的存储单元阵列的示意图，如图2A所示，位于同一行的2T2R阻变式存储单元20 的两端分别与一条WL、一条SL连接，位于同一列的2T2R阻变式存储单元20的两端分别与一条BL、一条BLB连接。图2B为本申请一实施例提供一种2T2R阻变式存储单元的示意图，如图2B所示，该2T2R阻变式存储单元包括第一晶体管21和第二晶体管22，第一阻变器件23和第二阻变器件24。第一晶体管21的栅极210和第二晶体管22的栅极220连接到字线25；第一晶体管21的源极211和第二晶体管22的源极221分别连接到第一位线26和第二位线27；第一晶体管21的漏极212和第二晶体管22的漏极222分别连接到第一阻变器件23的第一电极231和第二阻变器件24的第一电极241；第一阻变器件23的第二电极232和第二阻变器件24的第二电极242连接到源线28，所述第一阻变器件23的第一电极231与所述第二阻变器件24的第一电极241位于同一层，所述第一阻变器件23的第二电极232与所述第二阻变器件24的第二电极242位于同一层。即第一阻变器件23的第一电极231先于第一阻变器件23的第二电极232被制备，且第二阻变器件24的第一电极241先于第二阻变器件24的第二电极242被制备。或者第一阻变器件23的第一电极231后于第一阻变器件23的第二电极232被制备，且第二阻变器件24的第一电极241后于第二阻变器件24的第二电极242被制备。这种同向连接方式的电路设计更为简化，工艺上易于实现。
其中，MCU可以通过读取第一阻变器件23和第二阻变器件24的相对阻值确定2T2R阻变式存储单元的状态，例如：第一阻变器件23相对于第二阻变器件24呈高阻态，第二阻变器件24相对于第一阻变器件23呈低阻态，或者，第一阻变器件23相对于第二阻变器件24呈低阻态，第二阻变器件24相对于第一阻变器件23呈高阻态。这种读取方式可以称之为差分读取，由于上述2T2R阻变式存储单元可实现差分读取，因而可将该存储单元称作具有“差分架构”的存储单元。
此外，相对于传统的1T1R结构的阻变式存储器，2T2R结构的阻变式存储器中的存储单元虽然面积增长了一倍，但是所带来的有益效果同样是巨大的，即通过这种结构设计可以大幅提高对存储单元的状态读取的可靠性和稳定性。具体地，对于1T1R结构的存储单元，读取的是单个阻变器件阻值的绝对值，由于受阻变器件阻值分布的一致性、线路噪声、工艺波动等诸多因素影响，因此往往会出现数据读取出错的情况，例如错把一个阻值异常低的 高阻态当做低阻态，或把一个阻值异常高的低阻态当做高阻态。而2T2R结构的阻变式存储器中的存储单元，只要经过一定的初始化之后，存储单元内两个阻变器件的阻态始终是相反的，即“一低一高”，而不可能是“两低”或“两高”。基于这种存储单元的结构设计，使得MCU读取的不再是单个阻变器件的阻值，而是两个阻变器件阻值的相对大小，因此可以将阻值分布的不均匀性带来的影响降到最低，同时不受各种寄生参数和线路噪声的影响(单元内部相互抵消)，通过这种结构设计可以大幅提高对存储单元的状态读取的可靠性和稳定性；另外，由于存储单元内部的两个阻变器件可视为等同工艺条件，因此采用差分架构的2T2R阻变式存储器对于工艺条件的一致性要求也有所放宽。
本申请还提供一种MCU，其中，该MCU包括：上述2T2R阻变式存储器。具体地，图3为本申请一实施例提供的MCU的示意图，如图3所示，上述2T2R阻变式存储器31集成在该MCU30上。
如上所述，具有差分架构的2T2R阻变式存储器，包括：多个2T2R阻变式存储单元构成的存储单元阵列；每个2T2R阻变式存储单元包括第一晶体管、第二晶体管、第一阻变器件和第二阻变器件；所述第一晶体管的栅极和所述第二晶体管的栅极连接在同一根字线上，所述第一晶体管的源极和所述第二晶体管的源极分别连接在第一位线和第二位线上，所述第一晶体管的漏极与所述第一阻变器件的第一电极连接，所述第二晶体管的漏极与所述第二阻变器件的第一电极连接，所述第一阻变器件的第二电极和所述第二阻变器件的第二电极连接在同一根源线上；其中，所述第一阻变器件的第一电极与所述第二阻变器件的第一电极位于同一层，所述第一阻变器件的第二电极与所述第二阻变器件的第二电极位于同一层。即第一阻变器件的第一电极先于第一阻变器件的第二电极被制备，且第二阻变器件的第一电极先于第二阻变器件的第二电极被制备。或者第一阻变器件的第一电极后于第一阻变器件的第二电极被制备，且第二阻变器件的第一电极后于第二阻变器件的第二电极被制备。
在本申请中，当2T2R阻变式存储器中的存储单元的状态为：第一阻变器件相对于所述第二阻变器件呈高阻态，所述第二阻变器件相对于所述第一 阻变器件呈低阻态；或者，所述第一阻变器件相对于所述第二阻变器件呈低阻态，所述第二阻变器件相对于所述第一阻变器件呈高阻态。
其中，逻辑“0”表示第一阻变器件相对于第二阻变状态呈低阻态，第二阻变器件相对于第一阻变器件呈高阻态，逻辑“1”表示第一阻变器件相对于第二阻变状态呈高阻态，第二阻变器件相对于第一阻变器件呈低阻态。
或者，
逻辑“1”表示第一阻变器件相对于第二阻变状态呈低阻态，第二阻变器件相对于第一阻变器件呈高阻态，逻辑“0”表示第一阻变器件相对于第二阻变状态呈高阻态，第二阻变器件相对于第一阻变器件呈低阻态。
下面介绍MCU对2T2R阻变式存储单元的存储状态的读写过程：
假设逻辑“0”表示第一阻变器件相对于第二阻变状态呈低阻态，第二阻变器件相对于第一阻变器件呈高阻态，逻辑“1”表示第一阻变器件相对于第二阻变状态呈高阻态，第二阻变器件相对于第一阻变器件呈低阻态。假设一2T2R阻变式存储单元的初始存储状态为逻辑“0”，以写入逻辑“1”为例，图4为本申请一实施例提供的存储单元的存储状态的写入过程中字线WL、源线SL、第一位线BL以及第二位线BLB的时序图，其中，图4中横轴表示时间，纵轴表示电压。结合图2B、图4进行说明。在t1时间，MCU控制充电单元，以在字线25上施加开启电压VG，以开启第一晶体管21和第二晶体管22。同样在t1时间，MCU控制充电单元，以在第一位线26上施加大小为VDD的操作电压，而在第二位线27上施加大小相同但方向相反的操作电压-VDD。源线28接地，此时跟第一位线26相连的第一阻变器件23在两个电极之间的电压差ΔV＝-VDD的作用下发生reset，由低阻态变为高阻态；第二位线27上的第二阻变器件34在两个电极之间的电压差ΔV＝VDD的作用下发生set，由高阻态变为低阻态。至此，逻辑“1”的写入完成。
写入逻辑“0”的方法是类似的，只是将施加于两根位线上的电压互换即可。
具体地，假设逻辑“0”表示第一阻变器件相对于第二阻变状态呈低阻态，第二阻变器件相对于第一阻变器件呈高阻态，逻辑“1”表示第一阻变器件相对于第二阻变状态呈高阻态，第二阻变器件相对于第一阻变器件呈低阻态。假设一2T2R阻变式存储单元的初始存储状态为逻辑“1”，以写入逻辑“0” 为例，在t1时间，MCU控制充电单元，以在字线25上施加开启电压VG，以开启第一晶体管21和第二晶体管22。同样在t1时间，MCU控制充电单元，以在第一位线26上施加大小为-VDD的操作电压，而在第二位线27上施加大小相同但方向相反的操作电压VDD。源线28接地，此时跟第一位线26相连的第一阻变器件23在两个电极之间的电压差ΔV＝VDD的作用下发生set，由高阻态变为低阻态；第二位线27上的第二阻变器件34在两个电极之间的电压差ΔV＝-VDD的作用下发生reset，由低阻态变为高阻态。至此，逻辑“0”的写入完成。
假设逻辑“0”表示第一阻变器件相对于第二阻变状态呈低阻态，第二阻变器件相对于第一阻变器件呈高阻态，逻辑“1”表示第一阻变器件相对于第二阻变状态呈高阻态，第二阻变器件相对于第一阻变器件呈低阻态。图5为本申请一实施例提供的存储单元的存储状态的读取过程中字线WL、源线SL、第一位线BL以及第二位线BLB的时序图，其中，图5中横轴表示时间，纵轴表示电压。结合图2B、图5进行说明。其中，读取逻辑“1”过程中，在t0时间，MCU控制充电单元在第一位线26和第二位线27上预充电(precharge)至同一读取电压VRD，直到t1时间停止充电，随即在源线28上施加一个电压，与此同时通过在字线25上施加开启电压VG，以开启第一晶体管21和第二晶体管22。需要注意的是，在源线28上施加的电压应略小于读取电压，例如在源线28上施加的电压为VRD-0.2伏，从而可以避免因电压差过大而造成阻变器件的状态改变。第一位线26和第二位线27从t1时间开始放电(discharge)。由于第一阻变器件23处在高阻态，其放电速率相对较慢；而第二阻变器件24处在低阻态，其放电速率相对较快。到t2时间同步探测第一位线26和第二位线27上的电位，MCU对应这两个电位进行比较，由于第一位线26的电位高于第二位线27的电位，因而读取该存储单元数据为“逻辑1”。类似的，若第一位线26的电位低于第二位线27的电位，则读取该存储单元数据为“逻辑0”。
需要说明的是，本申请提供的具有差分架构的2T2R阻变式存储器，其写入和读取的方式与传统的静态随机存取存储器(Static Random Access Memory，SRAM)比较接近，例如，写入过程都是在两根位线上施加不同的电压，读取过程都是采用预充电，然后比较放电速率的快慢，因此可在不改 变或小改变外围电路设计的前提下用本申请提供的2T2R阻变式存储器取代SRAM。
相比于SRAM，本申请提供的具有差分架构的2T2R阻变式存储器具有如下优点：
第一、存储密度高。SRAM通常是6晶体管(6T)结构，而2T2R阻变式存储器只有2个晶体管，存储单元面积更小。
第二、数据掉电保持。SRAM要保持数据必须一致保持供电，而阻变式存储器在断电的情况下数据依然不会丢失。
综上所述，本申请所提出的具有差分架构的2T2R阻变式存储器具有广泛的应用前景。
本申请还提供一种设备，该设备可以是手机、平板电脑、计算机、可穿戴设备等智能设备，一切具有存储器的设备都在本申请的保护范围之内，其中，该存储器为上述具有差分架构的2T2R阻变式存储器。图6为本申请一实施例提供的设备60的示意图，如图6所示，该设备包括：MCU61、上述具有差分架构的2T2R阻变式存储器62以及收发器63，其中收发器63用于与其他设备之间进行数据传输。
如上所述，具有差分架构的2T2R阻变式存储器，包括：多个2T2R阻变式存储单元构成的存储单元阵列；每个2T2R阻变式存储单元包括第一晶体管、第二晶体管、第一阻变器件和第二阻变器件；第一晶体管的栅极和第二晶体管的栅极连接在同一根字线上，第一晶体管的源极和第二晶体管的源极分别连接在第一位线和第二位线上，第一晶体管的漏极与第一阻变器件的第一电极连接，第二晶体管的漏极与第二阻变器件的第一电极连接，第一阻变器件的第二电极和第二阻变器件的第二电极连接在同一根源线上；其中，第一阻变器件的第一电极与第二阻变器件的第一电极位于同一层，第一阻变器件的第二电极与第二阻变器件的第二电极位于同一层。
在一种可能的设计中，该设备还包括：MCU以及充电单元，该MCU和所述具有差分架构的2T2R阻变式存储器电连接。
在一种可能的设计中，MCU用于控制充电单元在字线上施加开启电压，以开启第一晶体管和第二晶体管，控制充电单元在第一位线上施加第一操作 电压，在第二位线上施加第二操作电压；其中，第一操作电压与第二操作电压不同，第一操作电压相对于源线上的电压的电压差使得第一阻变器件由高阻态变为低阻态，第二操作电压相对于源线上的电压的电压差使得第二阻变器件由低阻态变为高阻态；或者，第一操作电压相对于源线上的电压的电压差使得第一阻变器件由低阻态变为高阻态，第二操作电压相对于源线上的电压的电压差使得第二阻变器件由高阻态变为低阻态。
在一种可能的设计中，MCU用于控制充电单元在第一位线和第二位线上充电，以使第一位线和第二位线上的电压达到同一读取电压，并控制充电单元在预设时间之后停止对第一位线和第二位线的充电，控制充电单元在源线上施加一个电压，在字线上施加开启电压，以开启第一晶体管、第二晶体管，以使第一位线和第二位线开始放电，根据第一位线和第二位线的放电速度获取第一阻变器件和第二阻变器件的相对阻值，根据第一阻变器件和第二阻变器件的相对阻值确定2T2R阻变式存储单元的状态。
在一种可能的设计中，在源线上施加的电压小于读取电压，所述读取电压与在所述源线上施加的电压的电压差值小于预设阈值，该预设阈值可以取值为0.2伏或者0.1伏。
本申请实施例提供的设备，其包括：所述具有差分架构的2T2R阻变式存储器，其内容和效果可参考上述实施例，对此不再赘述。
本申请还提供一种设备，包括：MCU，该MCU上集成有所述具有差分架构的2T2R阻变式存储器，其内容和效果可参考上述实施例，对此不再赘述。
虽然本申请是以MCU上集成上述阻变式存储器为例进行了说明，但是本领域技术人员可以理解，嵌入式存储器的应用不仅仅局限于MCU，还包括CPU、FPGA、DSP、ASIC等各种类型的电路或芯片，或者说本发明的阻变式存储器可以广泛应用于各类SoC。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并 不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (8)

  1. 一种具有差分架构的2T2R阻变式存储器，其特征在于，包括：多个2T2R阻变式存储单元构成的存储单元阵列；每个2T2R阻变式存储单元包括第一晶体管、第二晶体管、第一阻变器件和第二阻变器件；
    所述第一晶体管的栅极和所述第二晶体管的栅极连接在同一根字线上，所述第一晶体管的源极和所述第二晶体管的源极分别连接在第一位线和第二位线上，所述第一晶体管的漏极与所述第一阻变器件的第一电极连接，所述第二晶体管的漏极与所述第二阻变器件的第一电极连接，所述第一阻变器件的第二电极和所述第二阻变器件的第二电极连接在同一根源线上；
    其中，所述第一阻变器件的第一电极与所述第二阻变器件的第一电极位于同一层，所述第一阻变器件的第二电极与所述第二阻变器件的第二电极位于同一层。
  2. 一种微控制单元MCU，其特征在于，所述MCU上具有如权利要求1所述的具有差分架构的2T2R阻变式存储器。
  3. 根据权利要求2所述的MCU，其特征在于，
    所述MCU用于控制充电单元在所述字线上施加开启电压，以开启所述第一晶体管和所述第二晶体管，控制所述充电单元在所述第一位线上施加第一操作电压，在所述第二位线上施加第二操作电压；
    其中，所述第一操作电压与第二操作电压不同，所述第一操作电压相对于所述源线上的电压的电压差使得所述第一阻变器件由高阻态变为低阻态，所述第二操作电压相对于所述源线上的电压的电压差使得所述第二阻变器件由低阻态变为高阻态；或者，所述第一操作电压相对于所述源线上的电压的电压差使得所述第一阻变器件由低阻态变为高阻态，所述第二操作电压相对于所述源线上的电压的电压差使得所述第二阻变器件由高阻态变为低阻态。
  4. 根据权利要求2所述的MCU，其特征在于，
    所述MCU用于控制充电单元在所述第一位线和第二位线上充电，以使所述第一位线和所述第二位线上的电压达到同一读取电压，并控制充电单元在预设时间之后停止对所述第一位线和所述第二位线的充电，控制所述充电单元在所述源线上施加一个电压，在所述字线上施加开启电压，以开启所述第一晶体管、所述第二晶体管，以使所述第一位线和第二位线开始放电，根 据所述第一位线和第二位线的放电速度获取所述第一阻变器件和所述第二阻变器件的相对阻值，根据所述第一阻变器件和所述第二阻变器件的相对阻值确定所述2T2R阻变式存储单元的状态。
  5. 根据权利要求4所述的MCU，其特征在于，在所述源线上施加的电压小于所述读取电压，且所述读取电压与在所述源线上施加的电压的电压差值小于预设阈值。
  6. 根据权利要求4或5所述的MCU，其特征在于，所述2T2R阻变式存储单元的状态为所述第一阻变器件相对于所述第二阻变器件呈高阻态，所述第二阻变器件相对于所述第一阻变器件呈低阻态；或者，所述第一阻变器件相对于所述第二阻变器件呈低阻态，所述第二阻变器件相对于所述第一阻变器件呈高阻态。
  7. 一种设备，其特征在于，包括：如权利要求1所述的具有差分架构的2T2R阻变式存储器。
  8. 一种设备，其特征在于，包括：如权利要求2所述的MCU。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230209841A1 (en) * 2019-11-23 2023-06-29 Tetramem Inc. Crossbar array circuit with parallel grounding lines

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11388356B1 (en) * 2021-04-12 2022-07-12 Tetramem Inc. AI fusion pixel sensor using memristors

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1770319A (zh) * 2004-09-29 2006-05-10 索尼株式会社 存储装置及半导体装置
CN101872647A (zh) * 2009-04-27 2010-10-27 复旦大学 一次编程电阻随机存储单元、阵列、存储器及其操作方法
CN102169719A (zh) * 2010-02-25 2011-08-31 复旦大学 一次可编程电阻随机存储器、读写电路及其编程方法
CN102368536A (zh) * 2011-11-25 2012-03-07 北京大学 一种阻变式存储器单元
US20140241038A1 (en) * 2013-02-25 2014-08-28 Renesas Electronics Corporation Semiconductor device and method of controlling semiconductor device
US8947909B1 (en) * 2012-10-05 2015-02-03 Marvell International Ltd. System and method for creating a bipolar resistive RAM (RRAM)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8064248B2 (en) * 2009-09-17 2011-11-22 Macronix International Co., Ltd. 2T2R-1T1R mix mode phase change memory array
CN207009083U (zh) * 2017-07-13 2018-02-13 高科创芯(北京)科技有限公司 基于忆阻器的双差分负反馈数据读取电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1770319A (zh) * 2004-09-29 2006-05-10 索尼株式会社 存储装置及半导体装置
CN101872647A (zh) * 2009-04-27 2010-10-27 复旦大学 一次编程电阻随机存储单元、阵列、存储器及其操作方法
CN102169719A (zh) * 2010-02-25 2011-08-31 复旦大学 一次可编程电阻随机存储器、读写电路及其编程方法
CN102368536A (zh) * 2011-11-25 2012-03-07 北京大学 一种阻变式存储器单元
US8947909B1 (en) * 2012-10-05 2015-02-03 Marvell International Ltd. System and method for creating a bipolar resistive RAM (RRAM)
US20140241038A1 (en) * 2013-02-25 2014-08-28 Renesas Electronics Corporation Semiconductor device and method of controlling semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230209841A1 (en) * 2019-11-23 2023-06-29 Tetramem Inc. Crossbar array circuit with parallel grounding lines

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