WO2020172871A1 - Appareil de traitement de données - Google Patents

Appareil de traitement de données Download PDF

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Publication number
WO2020172871A1
WO2020172871A1 PCT/CN2019/076562 CN2019076562W WO2020172871A1 WO 2020172871 A1 WO2020172871 A1 WO 2020172871A1 CN 2019076562 W CN2019076562 W CN 2019076562W WO 2020172871 A1 WO2020172871 A1 WO 2020172871A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
clock
signal
circuit
synchronization
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Application number
PCT/CN2019/076562
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English (en)
Chinese (zh)
Inventor
胡敏杰
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2019/076562 priority Critical patent/WO2020172871A1/fr
Priority to CN201980093220.4A priority patent/CN113491082B/zh
Publication of WO2020172871A1 publication Critical patent/WO2020172871A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • the second clock frequency synthesis circuit is used for clock synchronization of the second clock signal by using the mother clock signal to generate a second synchronous clock signal.
  • the second clock signal is a clock signal of the second clock domain.
  • the frequency is different from that of the first clock signal and is less than the frequency of the mother clock signal.
  • the transition edge of the second synchronous clock signal when the transition occurs is aligned with the transition edge of the mother clock signal; the synchronization processing circuit is used to utilize the first
  • the synchronous clock signal controls the data writing of the buffer circuit, and synchronously uses the second synchronous clock signal to control the data reading of the buffer circuit, so as to realize the conversion of data in the first clock domain into data in the second clock domain.
  • the first clock frequency synthesis circuit includes a first control signal generating unit and a first gating unit, and the first control signal generating unit is configured to The frequency ratio relationship between a clock signal and the mother clock signal generates a first control signal, and the first gating control unit is used for fitting the mother clock signal to a first synchronous clock signal according to the first control signal.
  • the synchronization processing circuit further includes a first clock map configuration circuit and a first counter, and the first synchronization The clock signal triggers the first counter to generate a first indicator signal, the first indicator signal can instruct the buffer circuit under the control of the first synchronous clock signal to write the theoretical rate of data, the first clock map configuration circuit is used to configure the circuit according to the first indicator signal A valid read instruction signal is generated, and the valid read instruction signal is used to control the actual rate of data read by the buffer circuit under the control of the second clock signal.
  • the synchronization processing circuit is specifically configured to use the first synchronization clock signal to control the buffer when the valid write instruction signal is at a high level.
  • the circuit performs data writing, and when the valid read instruction signal is at a high level, the second synchronous clock signal is used to synchronously control the buffer circuit for data reading. Since the data writing and data reading performed by the buffer circuit are synchronous, timing closure through the back end can make the data transfer delay across clock domains fixed, avoiding the problem of uncertain delay when an asynchronous processing scheme is adopted.
  • the buffer circuit includes a synchronous FIFO or a register.
  • the first clock signal and the second clock signal are clocked by using the same mother clock signal, or after the first clock signal is clocked by using the second clock signal
  • the synchronous processing circuit can be used to convert the data in the first clock domain into the data in the second clock domain.
  • the circuit synchronization design is realized on the front end, replacing the asynchronous processing circuit in the original asynchronous processing scheme, thereby avoiding asynchronous processing With the introduction of delay uncertainty, the realization of circuit synchronization design can also avoid the design complexity and system performance risks introduced when using asynchronous processing circuits.
  • Figure 1 is a schematic diagram of the principle of a traditional asynchronous processing scheme
  • Figure 2 is a schematic diagram of the application structure of the application scheme
  • FIG. 5 is a schematic diagram of an embodiment of a first clock frequency synthesis circuit in an embodiment of the application.
  • FIG. 6 is a schematic diagram of an embodiment of a second clock frequency synthesis circuit in an embodiment of the application.
  • FIG. 7 is a schematic diagram of a circuit structure of the first or second clock frequency synthesis circuit in an embodiment of the application.
  • FIG. 9 is a schematic diagram of a valid write instruction signal and a valid read instruction signal in an embodiment of the application.
  • FIG. 12 is a schematic diagram of an embodiment of another data processing device in an embodiment of the application.
  • FIG. 14 is a schematic diagram of another embodiment of a synchronization processing circuit in an embodiment of this application.
  • Figure 2 is a schematic diagram of the application structure of the application scheme.
  • this solution uses sub-clock signals 1 to N (N is an integer greater than 1) generated by synthesizing a master clock signal through different clock frequencies as the clock signals from clock domain A to clock domain X. Realize the synchronization design of different clock domains, and then adopt the synchronization processing circuit to realize the data synchronization transition between different clock domains.
  • the process of using the mother clock signal to synchronize the first clock signal and the second clock signal is to use a mother clock signal as an input clock signal, the adjacent transition time interval of the mother clock signal is fixed, according to the mother clock signal The relationship between the frequency and the frequency of the first clock signal or the second clock signal, close part of the transition edge of the mother clock signal, so as to realize the fitting of the mother clock signal to the first synchronous clock signal or the second synchronous clock signal.
  • the synchronization processing circuit 303 includes a buffer circuit.
  • the synchronization processing circuit 303 is used to control the data writing of the buffer circuit by using the first synchronization clock signal, and synchronously use the second synchronization clock signal to control the buffer circuit.
  • Data readout is controlled, so as to realize the conversion of data in the first clock domain into data in the second clock domain, and the process of converting data in the first clock domain into data in the second clock domain is to transfer data from the first clock domain
  • the cross-clock domain data transfer process to the second clock domain uses the first synchronous clock signal and the second synchronous clock signal to synchronously perform data writing and data reading of the buffer circuit, and uses the mother clock signal at the back end to perform The timing is closed, so that the delay of data transfer across clock domains is fixed.
  • the first clock frequency synthesis circuit 301 can be divided into two modules according to functions, including a first control signal generating unit 3011 and a first gating unit 3012, as shown in FIG. 5.
  • the first control signal generating unit 3011 is specifically used for the above-mentioned process of generating the first control signal
  • the first gating control unit 3012 is specifically used for the process of fitting the first synchronous clock signal according to the first control signal.
  • the second clock frequency synthesis circuit 302 can be divided into two modules according to functions, including a second control signal generating unit 3021 and a second gating unit 3022, as shown in FIG. 6.
  • the second control signal generating unit 3021 is specifically used for the above-mentioned process of generating the second control signal
  • the second gating control unit 3022 is specifically used for the process of fitting the second synchronous clock signal according to the second control signal.
  • a clock frequency synthesis circuit includes a counter, a clock map configuration circuit, a comparator, Circuit elements such as D flip-flops and gate control circuits.
  • the mother clock signal is used as the input clock signal CLK_IN, which triggers the counter to generate a counting signal.
  • the clock map configuration circuit prestores the first synchronous clock signal or the second synchronous clock signal that needs to be generated. Parameter, the clock map configuration circuit generates the configuration signal according to the counting signal generated by the counter and the pre-stored signal parameters and the mother clock signal.
  • the first synchronous clock signal triggers the first counter 3033 to generate a first indication signal, which can instruct the buffer circuit 3031 to perform data writing theoretically under the control of the first synchronous clock signal.
  • the first clock map configuration circuit 3032 uses The effective read instruction signal is generated according to the first instruction signal, and the effective read instruction signal is used to control the actual data reading rate of the buffer circuit under the control of the second synchronous clock signal.
  • the synchronization processing circuit may further include a second clock map configuration circuit 3034 and a second counter 3035.
  • the transition of the first synchronous clock signal triggers the write operation, and the second synchronous clock signal
  • the read operation is triggered when the first transition occurs, but when the second synchronous clock signal undergoes a second transition, the first synchronous clock signal does not undergo a second transition, so there is no readable data in the buffer circuit 3031, so the first
  • the second transition of the second synchronous clock signal cannot trigger the read operation, and the function of the valid read indication signal is to prevent the partial transition edge of the second synchronous clock signal from triggering the read operation.
  • the specific implementation is that when the partial transition edge of the second synchronous clock signal that cannot trigger the read operation occurs, the valid write indication signal presents a low level, and the synchronization processing circuit 303 does not perform reading on the buffer circuit 3031.
  • the valid write instruction signal and the valid read instruction signal can be generated by the first clock map configuration circuit 3032 and the second clock map configuration circuit 3034, or can be generated by an external circuit and introduced into the buffer circuit 3031 from an external circuit for use, They are all feasible implementation methods, which are not specifically limited in this application.
  • the processing of the cross-clock domain data by the synchronous processing circuit is a synchronous sampling process, as shown in FIG. 10 as an example.
  • the input data segments D0, D1, D2, NA, D0, D1 of the first clock domain are synchronously sampled by the synchronization processing circuit and then output to the second clock domain, where NA is an empty data segment, and the input operation is synchronized with the output operation , So the output data segment also has the NA data segment, and the data delay from input to output is determined.
  • asynchronous FIFOs are usually used to process cross-clock domain data.
  • the processing process is an asynchronous sampling process, as shown in Figure 11 as an example.
  • the original clock signal of the first clock domain is the first clock signal
  • the original clock signal of the second clock domain is the second clock signal.
  • Another data processing device provided in this application can directly A clock signal with a higher frequency in the first clock signal or the second clock signal is used as the master clock signal, and an inter-frequency synchronous clock signal synchronized with it is fitted to replace the other clock signal to realize clock signals in two clock domains Synchronized design. The details are described below.
  • FIG. 12 is a schematic diagram of an embodiment of another data processing device in an embodiment of the application.
  • the clock frequency synthesis circuit 401 is used for clock synchronization of the first clock signal by using the second clock signal to generate the first synchronous clock signal.
  • the second clock signal is the clock signal of the second clock domain, which is generated at fixed time intervals Jumping clock signal
  • the first clock signal is the clock signal of the first clock domain
  • the frequency of the first clock signal is less than the frequency of the second clock signal
  • the first synchronous clock signal when the jump occurs, the jump edge and the second The transition edges of the clock signal are aligned.
  • the synchronization processing circuit 402 can use the first synchronization clock signal and the second synchronization signal to control the buffer circuit Data writing and data reading are realized, so as to realize the cross-clock domain data transfer between the first clock domain and the second clock domain.
  • the circuit synchronization design can be realized on the front end. Since the first synchronous clock signal and the second clock signal are homologous synchronous clock signals, the first synchronous clock signal is derived from the second clock signal, so the back end can use The second clock signal frequency is time-sequentially converged, so that the cross-clock domain data transfer delay from the first clock domain to the second clock domain is fixed, avoiding the delay uncertainty problem introduced by the traditional asynchronous processing scheme.
  • the clock frequency synthesis circuit 401 in this embodiment is specifically configured to generate a control signal according to the frequency proportional relationship between the first clock signal and the second clock signal, and to fit the second clock signal into the first clock signal according to the control signal. Synchronize the clock signal.
  • clock frequency synthesis circuit 401 in this embodiment is the same as that of the first clock frequency synthesis circuit 301 and the second clock frequency synthesis circuit 302 in the above-mentioned embodiment.
  • the related description of the synthesis circuit 301 and the second clock frequency synthesis circuit 302 will not be repeated here.
  • the synchronization processing circuit 402 may further include a first clock map configuration circuit 4022 and a first counter 4023.
  • the first synchronous clock signal triggers the first counter 4023 to generate a first indication signal.
  • the first indication signal can indicate the theoretical rate of data writing by the buffer circuit 4021 under the control of the first synchronous clock signal.
  • the first clock map configuration circuit 4022 uses A valid read instruction signal is generated according to the first instruction signal, and the valid read instruction signal is used to control the actual data read rate of the buffer circuit 4021 under the control of the second clock signal.
  • the second clock signal triggers the second counter 4025 to generate a second indicator signal.
  • the second indicator signal can instruct the buffer circuit 4021 to perform a theoretical data reading rate under the control of the second clock signal.
  • the second clock map configuration circuit 4024 is used for The second instruction signal generates a valid write instruction signal, and the valid write instruction signal is used to control the actual rate at which the buffer circuit 4021 performs data writing under the control of the first synchronous clock signal.
  • the functions of the effective read instruction signal and the effective write instruction signal generated in the synchronization processing circuit 402 are the same as those described in the previous description of the synchronization processing circuit 303.
  • the specific description of the effective write indication signal will not be repeated here.
  • the buffer circuit 4021 is the same as the aforementioned buffer circuit 3031.
  • the buffer circuit 4021 may be a synchronous FIFO or one or more registers, where When the data complexity of the continuous data from the first clock domain is low, one register or a register array composed of multiple registers can be used to write and read the continuous data, but when the continuous data When the data complexity is high, it is necessary to use a synchronous FIFO with a suitable depth to write and read the continuous data, which is not specifically limited in this application.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne un appareil de traitement de données. L'appareil de traitement de données comprend un premier circuit de synthèse de fréquence d'horloge, un second circuit de synthèse de fréquence d'horloge, et un circuit de traitement de synchronisation, le premier circuit de synthèse de fréquence d'horloge et le second circuit de synthèse de fréquence d'horloge étant respectivement utilisés pour effectuer une synchronisation d'horloge sur des signaux d'horloge d'un premier domaine d'horloge et d'un second domaine d'horloge au moyen d'un signal d'horloge parent, et générer un premier signal d'horloge synchrone et un second signal d'horloge synchrone ; et le circuit de traitement de synchronisation utilise le premier signal d'horloge synchrone pour commander l'écriture de données d'un circuit tampon, et utilise le second signal d'horloge synchrone pour commander de manière synchrone la lecture de données du circuit tampon, de façon à réaliser la fixation du retard de transfert de données traversant des domaines d'horloge. La présente invention concerne en outre un appareil de traitement de données, l'appareil de traitement de données utilisant un second signal d'horloge pour effectuer une synchronisation d'horloge sur un premier signal d'horloge, ce qui permet d'utiliser le circuit de traitement de synchronisation pour réaliser un transfert de données traversant des domaines d'horloge, et la fixation du retard de transmission traversant les domaines d'horloge peut également être réalisée.
PCT/CN2019/076562 2019-02-28 2019-02-28 Appareil de traitement de données WO2020172871A1 (fr)

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PCT/CN2019/076562 WO2020172871A1 (fr) 2019-02-28 2019-02-28 Appareil de traitement de données
CN201980093220.4A CN113491082B (zh) 2019-02-28 2019-02-28 一种数据处理装置

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PCT/CN2019/076562 WO2020172871A1 (fr) 2019-02-28 2019-02-28 Appareil de traitement de données

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CN112698363A (zh) * 2020-12-29 2021-04-23 成都国星通信有限公司 一种北斗抗干扰天线高精度数据采集方法及采集电路
US11532338B1 (en) 2021-04-06 2022-12-20 Habana Labs Ltd. Mediating between asynchronous clock domains while preventing false indications of FIFO occupancy

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CN1658546A (zh) * 2004-02-18 2005-08-24 华为技术有限公司 一种通信设备中实现主备时钟相位对齐的方法
WO2007143935A1 (fr) * 2006-06-12 2007-12-21 Huawei Technologies Co., Ltd. appareil de synchronisation d'horloge de réseau, système et procédé
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US7352836B1 (en) * 2001-08-22 2008-04-01 Nortel Networks Limited System and method of cross-clock domain rate matching
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CN1658546A (zh) * 2004-02-18 2005-08-24 华为技术有限公司 一种通信设备中实现主备时钟相位对齐的方法
WO2007143935A1 (fr) * 2006-06-12 2007-12-21 Huawei Technologies Co., Ltd. appareil de synchronisation d'horloge de réseau, système et procédé
CN101478308A (zh) * 2009-01-13 2009-07-08 北京时代民芯科技有限公司 基于延时锁定环的可配置频率合成电路
CN102843164A (zh) * 2012-08-27 2012-12-26 中国科学院国家授时中心 超宽带室内定位系统发射时序控制方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112698363A (zh) * 2020-12-29 2021-04-23 成都国星通信有限公司 一种北斗抗干扰天线高精度数据采集方法及采集电路
CN112698363B (zh) * 2020-12-29 2024-04-16 成都国星通信有限公司 一种北斗抗干扰天线高精度数据采集方法及采集电路
US11532338B1 (en) 2021-04-06 2022-12-20 Habana Labs Ltd. Mediating between asynchronous clock domains while preventing false indications of FIFO occupancy

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CN113491082A (zh) 2021-10-08
CN113491082B (zh) 2022-11-18

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