WO2020172871A1

WO2020172871A1 - Data processing apparatus

Info

Publication number: WO2020172871A1
Application number: PCT/CN2019/076562
Authority: WO
Inventors: 胡敏杰
Original assignee: 华为技术有限公司
Priority date: 2019-02-28
Filing date: 2019-02-28
Publication date: 2020-09-03
Also published as: CN113491082B; CN113491082A

Abstract

Provided in the present application is a data processing apparatus. The data processing apparatus comprises a first clock frequency synthesis circuit, a second clock frequency synthesis circuit, and a synchronization processing circuit, wherein the first clock frequency synthesis circuit and the second clock frequency synthesis circuit are respectively used for carrying out clock synchronization on clock signals of a first clock domain and a second clock domain by means of a parent clock signal, and generating a first synchronous clock signal and a second synchronous clock signal; and the synchronization processing circuit uses the first synchronous clock signal to control data writing of a buffer circuit, and uses the second synchronous clock signal to synchronously control data read-out of the buffer circuit, so as to realize fixing of delay of data transfer crossing clock domains. Further provided in the present application is a data processing apparatus, wherein the data processing apparatus uses a second clock signal to carry out clock synchronization on a first clock signal, thereby using the synchronization processing circuit to carry out data transfer crossing clock domains, and fixing of delay of transmission crossing the clock domains can also be realized.

Description

A data processing device

Technical field

This application relates to the field of data processing, in particular to a data processing device.

Background technique

With the continuous expansion of the design scale of modern integrated circuit chips, there are usually multiple clocks in an integrated system to drive different modules. The problem it brings is how to design interface circuits between different clock domains to achieve data slave One clock domain transitions to another clock domain.

In the current solutions, the asynchronous processing solution is a general technical means to solve this problem, and the asynchronous processing solution is usually implemented through asynchronous first input first output (FIFO), as shown in Figure 1. When transferring data across clock domains, the data in the first clock domain is an asynchronous signal to the second clock domain that receives the data. In the asynchronous processing scheme, the data of the first clock domain needs to be input to the asynchronous FIFO first, this process is called a write operation, and then the data is output from the asynchronous FIFO to the second clock domain, this process is called a read operation. Read and write operations are triggered by the transition edges of the clock signals CLK A and CLK B of the two clock domains. Since the phase relationship between the two clock signals is uncertain, when the write operation is triggered by the clock transition edge of the first clock domain When triggered, that is, when the asynchronous signal reaches the transition edge, the relative relationship between the transition edge of the clock in the second clock domain and the transition edge of the asynchronous signal is uncertain. The delay of data transfer is uncertain. In some application scenarios in the wireless communication field, such as large-scale multiple input multiple output (MMM) and large-bandwidth communications, they are very sensitive to the indefinite delay introduced by the asynchronous processing scheme, which will bring about Greater difficulty in analysis.

It can be seen that how to solve the indefinite delay introduced by the asynchronous processing scheme when transferring data across clock domains is a problem that needs to be solved.

Summary of the invention

The embodiment of the present application provides a data processing device, which can be applied to cross-clock domain data interaction between two clock domains, and can fix the cross-clock domain data transfer delay to avoid the disadvantages caused by uncertain delay influences.

A first aspect of the embodiments of the present application provides a data processing device, including: a first clock frequency synthesis circuit, a second clock frequency synthesis circuit, and a synchronization processing circuit, and the synchronization processing circuit includes a buffer circuit. The first clock frequency synthesizing circuit is used to clock the first clock signal by using a mother clock signal to generate a first synchronous clock signal, the mother clock signal is a clock signal that jumps according to a fixed time interval, the first clock The signal is a clock signal of the first clock domain, the frequency of the first clock signal is less than the frequency of the mother clock signal, and the transition edge of the first synchronous clock signal when a transition occurs is aligned with the transition edge of the mother clock signal. The second clock frequency synthesis circuit is used for clock synchronization of the second clock signal by using the mother clock signal to generate a second synchronous clock signal. The second clock signal is a clock signal of the second clock domain. The frequency is different from that of the first clock signal and is less than the frequency of the mother clock signal. The transition edge of the second synchronous clock signal when the transition occurs is aligned with the transition edge of the mother clock signal; the synchronization processing circuit is used to utilize the first The synchronous clock signal controls the data writing of the buffer circuit, and synchronously uses the second synchronous clock signal to control the data reading of the buffer circuit, so as to realize the conversion of data in the first clock domain into data in the second clock domain.

It can be seen from the above-mentioned first aspect that the first synchronous clock signal and the second synchronous clock signal are generated by clock synchronization between the first clock signal and the second clock signal, and the synchronous processing circuit can use the first synchronous clock signal and the second synchronous clock signal. The clock signal realizes the cross-clock domain data transfer between the first clock domain and the second clock domain, and avoids the delay uncertainty caused by the asynchronous processing circuit for cross-clock domain data transfer.

Optionally, in combination with the above first aspect, in a first possible implementation manner, the first clock frequency synthesis circuit includes a first control signal generating unit and a first gating unit, and the first control signal generating unit is configured to The frequency ratio relationship between a clock signal and the mother clock signal generates a first control signal, and the first gating control unit is used for fitting the mother clock signal to a first synchronous clock signal according to the first control signal.

Optionally, in combination with the above first aspect, in a second possible implementation manner, the second clock frequency synthesis circuit includes a second control signal generating unit and a second gating unit, and the second control signal generating unit is used to The frequency ratio relationship between the second clock signal and the mother clock signal generates a second control signal, and the second gating control unit is used for fitting the mother clock signal into a second synchronous clock signal according to the second control signal.

Optionally, in combination with the first aspect, the first or the second possible implementation manner of the first aspect, in a third possible implementation manner, the synchronization processing circuit further includes a first clock map configuration circuit and a first counter , The first synchronous clock signal triggers the first counter to generate a first indicator signal, the first indicator signal can instruct the buffer circuit to write data under the control of the first synchronous clock signal theoretical rate, the first clock map configuration circuit is used to The first instruction signal generates a valid read instruction signal, and the valid read instruction signal is used to control the actual rate of data read by the buffer circuit under the control of the second synchronous clock signal.

Optionally, in combination with the third possible implementation manner of the first aspect described above, in the fourth possible implementation manner, the synchronization processing circuit further includes a second clock map configuration circuit and a second counter, and the second synchronization clock signal triggers the second The second counter generates a second instruction signal, which can instruct the buffer circuit to perform a theoretical data read rate under the control of the second synchronous clock signal, and the second clock map configuration circuit is used to generate a valid write instruction according to the second instruction signal The effective write instruction signal is used to control the actual rate of data writing by the buffer circuit under the control of the first synchronous clock signal.

The function of the above valid read instruction signal and valid write instruction signal is to match the actual rate of data writing and data reading performed by the buffer circuit to avoid data errors caused by mismatching of read and write rates.

Optionally, in combination with the third possible implementation manner of the first aspect described above, in the fifth possible implementation manner, the synchronization processing circuit is specifically configured to use the first synchronization clock signal to control the buffer when the valid write instruction signal is at a high level. The circuit performs data writing, and when the valid read instruction signal is at a high level, the second synchronous clock signal is used to synchronously control the buffer circuit for data reading. Since the data writing and data reading performed by the buffer circuit are synchronous, timing closure through the back end can make the data transfer delay across clock domains fixed, avoiding the problem of uncertain delay when an asynchronous processing scheme is adopted.

Optionally, in combination with the foregoing first aspect and any one of the first to fifth possible implementation manners of the first aspect, in the sixth possible implementation manner, the buffer circuit includes a synchronous FIFO or a register.

A second aspect of the embodiments of the present application provides a data processing device, including a clock frequency synthesis circuit and a synchronization processing circuit, and the synchronization processing circuit includes a buffer circuit. The clock frequency synthesis circuit is used for clock synchronization of the first clock signal by using the second clock signal to generate a first synchronous clock signal. The second clock signal is in the second clock domain and hops at fixed time intervals. A clock signal, the first clock signal is a clock signal of the first clock domain, the frequency of the first clock signal is less than the frequency of the second clock signal, the transition edge of the first synchronous clock signal and the second clock signal when the transition occurs Alignment of the transition edge; the synchronization processing circuit is used for the first synchronization clock signal to control the data writing of the buffer circuit, and synchronously use the second clock signal to control the data readout of the buffer circuit, so as to realize the first clock The data of the domain is converted into the data of the second clock domain.

It can be seen from the above second aspect that the principle of this solution is the same as that of the above first aspect. In this solution, the second clock signal is used as the mother clock signal to clock the first clock signal to generate the first synchronous clock signal, so There is no need to synchronize the second clock signal. The synchronous processing circuit can use the first synchronous clock signal and the second clock signal to realize cross-clock domain data transfer between the first clock domain and the second clock domain, avoiding the use of asynchronous processing circuits The delay uncertainty caused by data transfer across clock domains.

Optionally, in combination with the second aspect described above, in a first possible implementation manner, the clock frequency synthesis circuit includes a control signal generation unit and a gating unit, and the control signal generation unit is configured to respond to the first clock signal and the second clock signal. A control signal is generated according to the frequency proportional relationship of, and the gating control unit is used to synthesize the second clock signal into the first synchronous clock signal according to the control signal.

Optionally, in combination with the second aspect or the first possible implementation manner of the second aspect, in the second possible implementation manner, the synchronization processing circuit further includes a first clock map configuration circuit and a first counter, and the first synchronization The clock signal triggers the first counter to generate a first indicator signal, the first indicator signal can instruct the buffer circuit under the control of the first synchronous clock signal to write the theoretical rate of data, the first clock map configuration circuit is used to configure the circuit according to the first indicator signal A valid read instruction signal is generated, and the valid read instruction signal is used to control the actual rate of data read by the buffer circuit under the control of the second clock signal.

Optionally, in combination with the second possible implementation manner of the second aspect described above, in a third possible implementation manner, the synchronization processing circuit further includes a second clock map configuration circuit and a second counter, and the second clock signal triggers the second The counter generates a second instruction signal, which can instruct the buffer circuit to perform a theoretical data read rate under the control of the second synchronous clock signal, and the second clock map configuration circuit is used to generate a valid write instruction signal according to the second instruction signal The effective write instruction signal is used to control the actual rate of data writing by the buffer circuit under the control of the first synchronous clock signal. The function of the effective read instruction signal and the effective write instruction signal is to match the actual rate of data writing and data reading performed by the buffer circuit, so as to avoid data errors when the read and write rates do not match.

Optionally, in combination with the second possible implementation manner of the second aspect described above, in the fourth possible implementation manner, the synchronization processing circuit is specifically configured to use the first synchronization clock signal to control the buffer when the valid write instruction signal is at a high level. The circuit performs data writing, and when the valid read instruction signal is at a high level, the second synchronous clock signal is used to synchronously control the buffer circuit for data reading. Since the data writing and data reading performed by the buffer circuit are synchronous, timing closure through the back end can make the data transfer delay across clock domains fixed, avoiding the problem of uncertain delay when an asynchronous processing scheme is adopted.

Optionally, in combination with the foregoing second aspect and any one of the first to fourth possible implementation manners of the second aspect, in the sixth possible implementation manner, the buffer circuit includes a synchronous FIFO or a register.

In the two technical solutions provided by the embodiments of the present application, the first clock signal and the second clock signal are clocked by using the same mother clock signal, or after the first clock signal is clocked by using the second clock signal, The synchronous processing circuit can be used to convert the data in the first clock domain into the data in the second clock domain. The circuit synchronization design is realized on the front end, replacing the asynchronous processing circuit in the original asynchronous processing scheme, thereby avoiding asynchronous processing With the introduction of delay uncertainty, the realization of circuit synchronization design can also avoid the design complexity and system performance risks introduced when using asynchronous processing circuits.

Description of the drawings

Figure 1 is a schematic diagram of the principle of a traditional asynchronous processing scheme;

Figure 2 is a schematic diagram of the application structure of the application scheme;

3 is a schematic diagram of an embodiment of a data processing device in an embodiment of the application;

4 is a schematic diagram of a mother clock signal, a first synchronous clock signal, and a second synchronous clock signal;

5 is a schematic diagram of an embodiment of a first clock frequency synthesis circuit in an embodiment of the application;

6 is a schematic diagram of an embodiment of a second clock frequency synthesis circuit in an embodiment of the application;

7 is a schematic diagram of a circuit structure of the first or second clock frequency synthesis circuit in an embodiment of the application;

FIG. 8 is a schematic diagram of an embodiment of a synchronization processing circuit in an embodiment of the application;

FIG. 9 is a schematic diagram of a valid write instruction signal and a valid read instruction signal in an embodiment of the application;

Figure 10 is a schematic diagram of the synchronous sampling process of the solution of the application;

Figure 11 is a schematic diagram of the asynchronous sampling process of the traditional asynchronous processing scheme;

FIG. 12 is a schematic diagram of an embodiment of another data processing device in an embodiment of the application;

FIG. 13 is a schematic diagram of an embodiment of a clock frequency synthesis circuit in an embodiment of the application;

FIG. 14 is a schematic diagram of another embodiment of a synchronization processing circuit in an embodiment of this application.

detailed description

The embodiment of the application provides a data processing device, which can be applied to data transfer between two clock domains, can avoid the delay uncertainty problem introduced by the asynchronous processing scheme, and is suitable for the part of wireless communication that is sensitive to indefinite delay In the solution, avoid the adverse effects of uncertain delay in these scenarios.

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of this application.

The embodiments of the present application can be applied to a cross-clock domain data transfer scenario between two clock domains with different frequencies. For ease of understanding, the clock domain as the data sender can be regarded as the first clock domain, and the clock domain as the data receiver can be regarded as the second clock domain. It should be understood that one clock domain can be used as a data sender and a data receiver. Therefore, the first clock domain and the second clock domain are only representative of the two clock domains as the data sender and the data receiver, respectively.

Figure 2 is a schematic diagram of the application structure of the application scheme.

As shown in Figure 2, this solution uses sub-clock signals 1 to N (N is an integer greater than 1) generated by synthesizing a master clock signal through different clock frequencies as the clock signals from clock domain A to clock domain X. Realize the synchronization design of different clock domains, and then adopt the synchronization processing circuit to realize the data synchronization transition between different clock domains.

Figure 3 is a schematic diagram of an embodiment of a data processing device in an embodiment of the application.

As shown in FIG. 3, the data processing device 30 in the embodiment of the present application may include a first clock frequency synthesis circuit 301: a second clock frequency synthesis circuit 302 and a synchronization processing circuit 303;

The first clock frequency synthesis circuit 301 is used for clock synchronization of the first clock signal by using the mother clock signal to generate a first synchronous clock signal, the first clock signal is a clock signal of the first clock domain, and the first clock signal The frequency of is less than the frequency of the mother clock signal, and the transition edge of the first synchronous clock signal when the transition occurs is aligned with the transition edge of the mother clock signal;

The second clock frequency synthesizing circuit 302 is used for clock synchronization of the second clock signal by using the above-mentioned mother clock signal to generate a second synchronous clock signal. The second clock signal is a clock signal of the second clock domain. The frequency of the signal is different from the frequency of the first clock signal and is smaller than the frequency of the mother clock signal, and the transition edge of the second synchronous clock signal when the transition occurs is aligned with the transition edge of the mother clock signal;

The process of using the mother clock signal to synchronize the first clock signal and the second clock signal is to use a mother clock signal as an input clock signal, the adjacent transition time interval of the mother clock signal is fixed, according to the mother clock signal The relationship between the frequency and the frequency of the first clock signal or the second clock signal, close part of the transition edge of the mother clock signal, so as to realize the fitting of the mother clock signal to the first synchronous clock signal or the second synchronous clock signal. The adjacent transition time interval of the first synchronous clock signal and the second synchronous clock signal formed by the fitting of the clock signal is not fixed, but each time the first synchronous clock signal and the second synchronous clock signal jump, their transition The edge is aligned with the transition edge of the mother clock signal, so the first synchronous clock signal and the second synchronous clock signal can be regarded as synchronous clock signals. Taking Figure 4 as an example, the mother clock signal is a clock signal that jumps at fixed time intervals. Assuming that the frequency of the mother clock signal is A, the frequency of the first synchronous clock signal is 0.8A, and the frequency of the second synchronous clock signal is 0.6A. , The frequency ratio of the mother clock signal, the first synchronous clock signal and the second synchronous clock signal is 5:4:3, so the clock cycles of the 5 mother clock signals can be regarded as a training cycle, according to the corresponding ratio, in each Part of the transition edges of the mother clock signal are turned off during the training cycle, so as to realize the clock synchronization of the first clock signal and the second clock signal using the mother clock signal to generate the first synchronous clock signal and the second synchronous clock signal. Figure 4 shows a schematic diagram of the clock signal in one training cycle. In each subsequent training cycle, the alignment of the transition edges of the first synchronous clock signal and the second synchronous clock signal with the mother clock signal is the same as that shown in Figure 4. Shows the same, so the backend can converge the timing interface of the two clock signals according to the mother clock frequency, so as to realize the synchronization design of different frequency clock signals, so that the synchronous processing circuit can be used to replace the asynchronous processing circuit in the traditional asynchronous processing scheme. Data transfer across clock domains;

The synchronization processing circuit 303 includes a buffer circuit. The synchronization processing circuit 303 is used to control the data writing of the buffer circuit by using the first synchronization clock signal, and synchronously use the second synchronization clock signal to control the buffer circuit. Data readout is controlled, so as to realize the conversion of data in the first clock domain into data in the second clock domain, and the process of converting data in the first clock domain into data in the second clock domain is to transfer data from the first clock domain The cross-clock domain data transfer process to the second clock domain uses the first synchronous clock signal and the second synchronous clock signal to synchronously perform data writing and data reading of the buffer circuit, and uses the mother clock signal at the back end to perform The timing is closed, so that the delay of data transfer across clock domains is fixed.

In this embodiment, by using the mother clock signal to synchronize the first clock signal and the second clock signal, after generating the first synchronous clock signal and the second synchronous clock signal, the synchronization processing circuit 303 can perform clock synchronization according to the first synchronous clock signal. Signal and the second synchronous clock signal to control the data writing and data reading process of the continuous data across the clock domain in the buffer circuit, so as to realize the data conversion of the first clock domain into the second clock domain with a fixed delay data.

Through the above design scheme, the circuit synchronization design can be realized on the front end. Since the first synchronous clock signal and the second synchronous clock signal are homologous synchronous clock signals, they are all derived from the same mother clock signal, so the back end can adopt the mother clock signal. The timing of the clock signal frequency is converged, so that the cross-clock domain data transmission delay from the first clock domain to the second clock domain is fixed, and the delay uncertainty problem introduced by the traditional asynchronous processing scheme is avoided.

Furthermore, the realization of circuit synchronization design on the front end can avoid the design complexity and system performance risks brought by asynchronous circuit design, and can also avoid the problem of high power consumption of asynchronous FIFO in practical applications.

Optionally, the first clock frequency synthesis circuit 301 is specifically configured to generate the first control signal according to the frequency ratio relationship between the first clock signal and the mother clock signal, and to fit the mother clock signal into the first synchronous clock according to the first control signal signal.

The above-mentioned first control signal can be regarded as a polling table, which can control to turn off part of the clock transition edge of the mother clock signal according to the corresponding polling period, so as to realize the fitting process from the mother clock signal to the first synchronous clock signal. Since the first synchronous clock signal is fitted by the mother clock signal, the jumping edge when the first synchronous clock signal jumps is aligned with the jumping edge of the mother clock signal.

The first clock frequency synthesis circuit 301 can be divided into two modules according to functions, including a first control signal generating unit 3011 and a first gating unit 3012, as shown in FIG. 5. The first control signal generating unit 3011 is specifically used for the above-mentioned process of generating the first control signal, and the first gating control unit 3012 is specifically used for the process of fitting the first synchronous clock signal according to the first control signal.

Similar to the first clock frequency synthesis circuit 301, the second clock frequency synthesis circuit 302 is specifically configured to generate a second control signal according to the frequency proportional relationship between the second clock signal and the mother clock signal, and to convert the mother clock signal according to the second control signal Fit the second synchronous clock signal.

The second clock frequency synthesis circuit 302 can be divided into two modules according to functions, including a second control signal generating unit 3021 and a second gating unit 3022, as shown in FIG. 6. The second control signal generating unit 3021 is specifically used for the above-mentioned process of generating the second control signal, and the second gating control unit 3022 is specifically used for the process of fitting the second synchronous clock signal according to the second control signal.

The above-mentioned second control signal can be regarded as another polling table, which can control to turn off part of the clock transition edge of the mother clock signal according to the same polling cycle as the first control signal, thereby realizing the mother clock signal to the second synchronous clock signal The fitting process. Since the second synchronous clock signal is fitted by the mother clock signal, the transition edge when the second synchronous clock signal jumps is aligned with the transition edge of the mother clock signal.

The specific circuit structures of the first clock frequency synthesis circuit 301 and the second clock frequency synthesis circuit 302 are the same. Taking the circuit shown in FIG. 7 as an example, a clock frequency synthesis circuit includes a counter, a clock map configuration circuit, a comparator, Circuit elements such as D flip-flops and gate control circuits. The mother clock signal is used as the input clock signal CLK_IN, which triggers the counter to generate a counting signal. The clock map configuration circuit prestores the first synchronous clock signal or the second synchronous clock signal that needs to be generated. Parameter, the clock map configuration circuit generates the configuration signal according to the counting signal generated by the counter and the pre-stored signal parameters and the mother clock signal. The comparator compares the configuration signal with an externally connected Gating enable signal to obtain the comparison signal, and the mother clock signal at the same time As the CP terminal pulse signal of the D flip-flop, trigger the D flip-flop to generate a corresponding control signal according to the input comparison signal. The control signal is input to the enable terminal EN of the gate control circuit, and the mother clock signal is input to the input of the gate control circuit At the terminal IN, the gate control circuit can perform operations based on the control signal and the mother clock signal, and perform clock synchronization at the output terminal OUT to obtain the clock signal CLK_OUT.

A circuit composed of a counter, a clock map configuration circuit, a comparator, and a D flip-flop corresponds to the first control signal generating unit 3011 or the second control signal generating unit 3021, and the gating circuit corresponds to the first gating unit 3012 or the second gating Unit 3022.

Optionally, as shown in FIG. 8, the synchronization processing circuit 303 may further include a first clock map configuration circuit 3032 and a first counter 3033.

The first synchronous clock signal triggers the first counter 3033 to generate a first indication signal, which can instruct the buffer circuit 3031 to perform data writing theoretically under the control of the first synchronous clock signal. The first clock map configuration circuit 3032 uses The effective read instruction signal is generated according to the first instruction signal, and the effective read instruction signal is used to control the actual data reading rate of the buffer circuit under the control of the second synchronous clock signal.

Optionally, referring to FIG. 8, the synchronization processing circuit may further include a second clock map configuration circuit 3034 and a second counter 3035.

The second synchronous clock signal triggers the second count 3035 to generate a second indicator signal, which can instruct the buffer circuit 3031 to perform a theoretical data reading rate under the control of the second synchronous clock signal. The second clock map configuration circuit 3034 uses The effective write instruction signal is generated according to the second instruction signal, and the effective write instruction signal is used to control the actual rate of data writing by the buffer circuit under the control of the first synchronous clock signal.

The process in which the synchronization processing circuit 303 uses the first synchronization clock signal to control the buffer circuit 3031 to write data is referred to as a write operation, and the process in which the synchronization processing circuit 303 uses the second synchronization clock signal to control the buffer circuit 3031 to read data is referred to as a read operation. The maximum rate of the write operation is determined by the frequency of the first synchronous clock signal, and the maximum rate of the read operation is determined by the frequency of the second synchronous clock signal. Because the frequencies of the first synchronous clock signal and the second synchronous clock signal are different Equal, so the maximum rate of read operation and write operation is not equal, this situation may bring about the problem is that when the read operation rate is greater than the write operation, it is easy to produce a situation of read empty, that is, there is nothing in the buffer circuit 3031. Valid data that continues to be read; when the read operation rate is lower than the write operation, it is likely to be full, that is, the amount of valid data buffered by the buffer circuit 3031 has reached a saturated state. If the read operation is continued when the read is empty, or the write operation is continued when the write is full, data errors will occur.

The function of the above valid read instruction signal and valid write instruction signal is to match the actual rate of the write operation and the read operation, thereby avoiding data errors. For ease of understanding, an example is given below.

Assuming that the frequency of the first synchronous clock signal is 100MHz and the frequency of the second synchronous clock signal is 200MHz, the first synchronous clock signal and the second synchronous clock signal are obtained by clock synchronization of a master clock signal with a frequency of 300MHz, and the second synchronous clock The frequency of the signal is twice that of the first synchronous clock signal. When the first synchronous clock signal undergoes a transition and waits for the next transition, the second synchronous clock signal will undergo two transitions. The transition of the first synchronous clock signal triggers the write operation, and the second synchronous clock signal The read operation is triggered when the first transition occurs, but when the second synchronous clock signal undergoes a second transition, the first synchronous clock signal does not undergo a second transition, so there is no readable data in the buffer circuit 3031, so the first The second transition of the second synchronous clock signal cannot trigger the read operation, and the function of the valid read indication signal is to prevent the partial transition edge of the second synchronous clock signal from triggering the read operation. As shown in FIG. 9, the specific implementation is that when the partial transition edge of the second synchronous clock signal that cannot trigger the read operation occurs, the valid write indication signal presents a low level, and the synchronization processing circuit 303 does not perform reading on the buffer circuit 3031. Operation; when a partial transition edge of the second synchronous clock signal that can trigger a read operation occurs, the valid read indication signal presents a high level, and the synchronization processing circuit 303 can perform a read operation on the buffer circuit 3031. It should be understood that the functions of the effective read indication signal showing a high level or a low level can be interchanged, and this application does not specifically limit it.

When the frequency of the first synchronous clock signal is 200MHz and the frequency of the second synchronous clock signal is 100MHz, the situation is reversed. In this case, a valid write instruction signal is required, and its function is to make part of the first synchronous clock signal The edge cannot trigger a write operation. In a specific embodiment, the specific implementation is that when a partial transition edge of the first synchronous clock signal that cannot trigger a write operation occurs, the valid write indication signal presents a low level to indicate that the cache circuit 3031 cannot perform Data writing; when a transition edge of the first synchronous clock signal that can trigger a write operation occurs, it presents a high level to indicate that the first synchronous clock signal has a valid transition, and the synchronous processing circuit 303 can write to the buffer circuit 3031 operating.

Optionally, the valid write instruction signal and the valid read instruction signal can be generated by the first clock map configuration circuit 3032 and the second clock map configuration circuit 3034, or can be generated by an external circuit and introduced into the buffer circuit 3031 from an external circuit for use, They are all feasible implementation methods, which are not specifically limited in this application.

Optionally, in a specific embodiment, the buffer circuit 3031 may include a synchronous FIFO, or may include one or more registers, wherein, when the buffer circuit 3031 needs to process the cross-clock domain data, the data complexity is relatively high. When it is low, one register or a register array composed of multiple registers can be used to realize the data writing and data reading processing of the cross-clock domain data, but when the data complexity of the cross-clock domain data is high, you need to use A synchronous FIFO with a suitable depth is used to write and read the data, which is not specifically limited in this application.

In this embodiment, the processing of the cross-clock domain data by the synchronous processing circuit is a synchronous sampling process, as shown in FIG. 10 as an example.

The input data segments D0, D1, D2, NA, D0, D1 of the first clock domain are synchronously sampled by the synchronization processing circuit and then output to the second clock domain, where NA is an empty data segment, and the input operation is synchronized with the output operation , So the output data segment also has the NA data segment, and the data delay from input to output is determined.

In traditional asynchronous processing schemes, asynchronous FIFOs are usually used to process cross-clock domain data. The processing process is an asynchronous sampling process, as shown in Figure 11 as an example.

The input data segments D0, D1, D2, NA, D3 of the first clock domain are asynchronously sampled by the asynchronous FIFO and then output to the second clock domain. The input operation and output operation are asynchronous, and the output operation will not output the input in the input operation For the NA data segment, the data delay from input to output is uncertain.

To sum up, when the data processing device provided in the embodiments of the present application is applied to a cross-clock domain data transfer scenario between two different frequency clock domains, in the traditional asynchronous processing scheme, the asynchronous FIFO represented by asynchronous The processing circuit is used to realize the cross-clock-domain data transfer between the two different-frequency clock domains. Since the clock signals of the two different-frequency clock domains are asynchronous clock signals, their phase relationship is uncertain, and only asynchronous processing circuits can be used. For data interaction across clock domains, the delay introduced by this solution is uncertain. The embodiment of the application does not use an asynchronous processing circuit to transfer data across clock domains, but synchronizes the clocks of the two clock domains, so that the synchronous processing circuit can be used to implement cross-clock domain data interaction between the two clock domains. , The circuit synchronization design is realized on the front end, and the back end adopts the mother clock signal frequency for timing convergence, so that the cross-clock domain data transmission delay introduced by the solution of this application is determined, avoiding some application scenarios that are sensitive to untimed delay The adverse effects of irregular delays.

In a specific embodiment, the original clock signal of the first clock domain is the first clock signal, and the original clock signal of the second clock domain is the second clock signal. Another data processing device provided in this application can directly A clock signal with a higher frequency in the first clock signal or the second clock signal is used as the master clock signal, and an inter-frequency synchronous clock signal synchronized with it is fitted to replace the other clock signal to realize clock signals in two clock domains Synchronized design. The details are described below.

FIG. 12 is a schematic diagram of an embodiment of another data processing device in an embodiment of the application.

As shown in FIG. 12, the data processing device 40 in the embodiment of the present application may include: a clock frequency synthesis circuit 401 and a synchronization processing circuit 402;

The clock frequency synthesis circuit 401 is used for clock synchronization of the first clock signal by using the second clock signal to generate the first synchronous clock signal. The second clock signal is the clock signal of the second clock domain, which is generated at fixed time intervals Jumping clock signal, the first clock signal is the clock signal of the first clock domain, the frequency of the first clock signal is less than the frequency of the second clock signal, the first synchronous clock signal when the jump occurs, the jump edge and the second The transition edges of the clock signal are aligned.

In this embodiment, the second clock signal is a clock signal with a frequency greater than that of the first clock signal, the second clock signal is a real clock signal in the second clock domain, and the time interval during which the second clock signal transitions is fixed. It is equivalent to the master clock signal described in the above embodiment, so the second clock signal can be used to synchronize the first clock signal without using other master clock signals to synchronize the first clock signal and the second clock signal. , It reduces the design difficulty and saves circuit components. The implementation principle of this embodiment is similar to the embodiment shown in FIG. 3, and the relationship between the first synchronous clock signal and the second clock signal can also be referred to that described in FIG. Since the first synchronous clock signal is aligned with the transition edge of the second clock signal when the transition occurs, and the second clock signal is the mother clock signal of the first synchronous clock signal, the back end can follow the second clock signal The frequency converges the timing interface of the two clock signals, and then realizes the synchronization design of different frequency clock signals, so that synchronous processing circuits can be used to replace asynchronous processing circuits in traditional asynchronous processing schemes to realize data transfer across clock domains;

The synchronization processing circuit 402 includes a buffer circuit. The synchronization processing circuit 402 is used for the first synchronization clock signal to control the data writing of the buffer circuit, and to synchronously use the second clock signal to control the data reading of the buffer circuit, thereby achieving Convert the data of the first clock domain into the data of the second clock domain.

In this embodiment, by using the second clock signal to synchronize the first clock signal, after the first synchronization clock is generated, the synchronization processing circuit 402 can use the first synchronization clock signal and the second synchronization signal to control the buffer circuit Data writing and data reading are realized, so as to realize the cross-clock domain data transfer between the first clock domain and the second clock domain.

Through the above design scheme, the circuit synchronization design can be realized on the front end. Since the first synchronous clock signal and the second clock signal are homologous synchronous clock signals, the first synchronous clock signal is derived from the second clock signal, so the back end can use The second clock signal frequency is time-sequentially converged, so that the cross-clock domain data transfer delay from the first clock domain to the second clock domain is fixed, avoiding the delay uncertainty problem introduced by the traditional asynchronous processing scheme.

Optionally, the clock frequency synthesis circuit 401 in this embodiment is specifically configured to generate a control signal according to the frequency proportional relationship between the first clock signal and the second clock signal, and to fit the second clock signal into the first clock signal according to the control signal. Synchronize the clock signal.

The clock frequency synthesis circuit 401 can be divided into two modules according to functions, including a control signal generation unit 4011 and a gate control unit 4012, as shown in FIG. 13. The control signal generating unit 4011 is specifically used for the above process of generating the control signal, and the gating unit 4012 is specifically used for the process of fitting the first synchronous clock signal according to the control signal.

It should be understood that the implementation of the clock frequency synthesis circuit 401 in this embodiment is the same as that of the first clock frequency synthesis circuit 301 and the second clock frequency synthesis circuit 302 in the above-mentioned embodiment. The related description of the synthesis circuit 301 and the second clock frequency synthesis circuit 302 will not be repeated here.

Optionally, as shown in FIG. 14, the synchronization processing circuit 402 may further include a first clock map configuration circuit 4022 and a first counter 4023.

The first synchronous clock signal triggers the first counter 4023 to generate a first indication signal. The first indication signal can indicate the theoretical rate of data writing by the buffer circuit 4021 under the control of the first synchronous clock signal. The first clock map configuration circuit 4022 uses A valid read instruction signal is generated according to the first instruction signal, and the valid read instruction signal is used to control the actual data read rate of the buffer circuit 4021 under the control of the second clock signal.

Optionally, the synchronization processing circuit 402 may further include a second clock map configuration circuit 4024 and a second counter 4025.

The second clock signal triggers the second counter 4025 to generate a second indicator signal. The second indicator signal can instruct the buffer circuit 4021 to perform a theoretical data reading rate under the control of the second clock signal. The second clock map configuration circuit 4024 is used for The second instruction signal generates a valid write instruction signal, and the valid write instruction signal is used to control the actual rate at which the buffer circuit 4021 performs data writing under the control of the first synchronous clock signal.

The functions of the effective read instruction signal and the effective write instruction signal generated in the synchronization processing circuit 402 are the same as those described in the previous description of the synchronization processing circuit 303. For details, please refer to the previous description of the synchronization processing circuit 303 for the effective read instruction signal And the specific description of the effective write indication signal, will not be repeated here.

Optionally, the buffer circuit 4021 is the same as the aforementioned buffer circuit 3031. As described above, in a specific embodiment, the buffer circuit 4021 may be a synchronous FIFO or one or more registers, where When the data complexity of the continuous data from the first clock domain is low, one register or a register array composed of multiple registers can be used to write and read the continuous data, but when the continuous data When the data complexity is high, it is necessary to use a synchronous FIFO with a suitable depth to write and read the continuous data, which is not specifically limited in this application.

In summary, the main difference between the data processing device 40 in this embodiment and the data processing device 30 in the foregoing embodiment is that the data processing device 40 directly uses the second clock signal with a higher frequency as the mother clock signal, so There is no need to synchronize the second clock signal, but only need to use the second clock signal to synchronize the first clock signal to generate the first synchronized clock signal to realize the clock signals of the first clock domain and the second clock domain Synchronization, so that the asynchronous processing circuit in the traditional asynchronous processing scheme can be replaced by the synchronous processing circuit to realize the cross-clock domain data exchange between the first clock domain and the second clock domain, and realize the circuit synchronization design on the front end. The synchronous clock signal is a clock signal derived from the second clock signal, so the first synchronous clock signal and the second clock signal are homologous synchronous clock signals, and their phase relationship is determined. The back end can use the second clock signal frequency for timing Convergence, so that the cross-clock domain data transfer delay introduced by the solution of the present application is determined, avoiding the adverse effects caused by the irregular delay in some application scenarios that are sensitive to the irregular delay.

It should be understood that, as an embodiment, when the frequency of the first clock signal is greater than that of the second clock signal, the first clock signal may also be used as the mother clock signal to perform clock synchronization on the second clock signal to generate the second synchronous clock signal, The second synchronous clock signal and the first clock signal are synchronous clock signals. This solution can also realize the clock signal synchronization design of the first clock domain and the second clock domain. The realization principle of this solution is similar to the foregoing embodiment. The details are not repeated here.

The two data processing devices provided in the embodiments of the application are described in detail above. Specific examples are used in this article to illustrate the principles and implementations of the application. The descriptions of the above embodiments are only used to help understand the methods of the application. And its core ideas; at the same time, for those of ordinary skill in the art, according to the ideas of this application, there will be changes in the specific implementation and the scope of application. In summary, the content of this specification should not be construed as a reference to this application limits.

Claims

A data processing device, characterized by comprising: a first clock frequency synthesis circuit, used for clock synchronization of the first clock signal using a mother clock signal to generate a first synchronous clock signal, the frequency of the first clock signal Less than the frequency of the mother clock signal, the transition edge of the first synchronous clock signal when a transition occurs is aligned with the transition edge of the mother clock signal;

The second clock frequency synthesis circuit is used for clock synchronization of a second clock signal by using the mother clock signal to generate a second synchronous clock signal, the frequency of the second clock signal is different from the frequency of the first clock signal , And less than the frequency of the mother clock signal, the transition edge of the second synchronous clock signal when a transition occurs is aligned with the transition edge of the mother clock signal;

The synchronization processing circuit includes a buffer circuit, the synchronization processing circuit is configured to use the first synchronization clock signal to control the data writing of the buffer circuit, and to synchronize the use of the second synchronization clock signal to the buffer The data readout of the circuit is controlled.
The data processing device according to claim 1, wherein the first clock frequency synthesis circuit is specifically configured to generate a first control signal according to a frequency proportional relationship between the first clock signal and the mother clock signal, and Fit the mother clock signal to the first synchronous clock signal according to the first control signal.
The data processing device according to claim 1, wherein the second clock frequency synthesis circuit is specifically configured to generate a second control signal according to a frequency proportional relationship between the second clock signal and the mother clock signal, and Fitting the mother clock signal to the second synchronous clock signal according to the second control signal.
The data processing device according to any one of claims 1 to 3, wherein the synchronization processing circuit further comprises a first clock map configuration circuit and a first counter, and the first synchronization clock signal triggers the first counter A first indication signal is generated, and the first clock map configuration circuit is configured to generate a valid read indication signal according to the first indication signal.
The data processing device according to claim 4, wherein the synchronization processing circuit further comprises a second clock map configuration circuit and a second counter, and the second synchronization clock signal triggers the second counter to generate a second instruction Signal, the second clock map configuration circuit is used to generate a valid write instruction signal according to the second instruction signal.
The data processing device according to claim 5, wherein the synchronization processing circuit is specifically configured to use the first synchronization clock signal to control the buffer circuit to perform the buffer circuit when the valid write instruction signal is at a high level. Data is written, and when the valid read instruction signal is at a high level, the second synchronous clock signal is used to synchronously control the buffer circuit to read the data.
The data processing device according to any one of claims 1-6, wherein the buffer circuit comprises a synchronous first-in-first-out memory FIFO or register.
A data processing device, characterized by comprising: a clock frequency synthesizing circuit for clock synchronization of a first clock signal using a second clock signal to generate a first synchronous clock signal, the frequency of the first clock signal is less than The frequency of the second clock signal, the transition edge of the first synchronous clock signal when a transition occurs is aligned with the transition edge of the second clock signal;

The synchronization processing circuit includes a buffer circuit, the synchronization processing circuit is used for the first synchronization clock signal to control the data writing of the buffer circuit, and to synchronously use the second clock signal to control the buffer circuit Data readout is controlled.
8. The data processing device according to claim 8, wherein the clock frequency synthesis circuit is specifically configured to generate a control signal according to the frequency proportional relationship between the first clock signal and the second clock signal, and according to the control signal Fitting the second clock signal to the first synchronous clock signal.
The data processing device according to claim 8 or 9, wherein the synchronization processing circuit further comprises a first clock map configuration circuit and a first counter, and the first synchronization clock signal triggers the first counter to generate a An indication signal, and the first clock map configuration circuit is used to generate a valid read indication signal according to the first indication signal.
The data processing device according to claim 10, wherein the synchronization processing circuit further comprises a second clock map configuration circuit and a second counter, and the second clock signal triggers the second counter to generate a second indication signal The second clock map configuration circuit is used to generate a valid write instruction signal according to the second instruction signal.
The data processing device according to claim 11, wherein the synchronization processing circuit is specifically configured to use the first synchronization clock signal to control the buffer circuit to perform the processing when the valid write instruction signal is at a high level. Data is written, and when the valid read instruction signal is at a high level, the second clock signal is synchronously used to control the buffer circuit to perform the data read.
The data processing device according to any one of claims 8-12, wherein the buffer circuit comprises a synchronous FIFO or a register.