WO2007143935A1 - appareil de synchronisation d'horloge de réseau, système et procédé - Google Patents

appareil de synchronisation d'horloge de réseau, système et procédé Download PDF

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Publication number
WO2007143935A1
WO2007143935A1 PCT/CN2007/001858 CN2007001858W WO2007143935A1 WO 2007143935 A1 WO2007143935 A1 WO 2007143935A1 CN 2007001858 W CN2007001858 W CN 2007001858W WO 2007143935 A1 WO2007143935 A1 WO 2007143935A1
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WO
WIPO (PCT)
Prior art keywords
time information
time
local
frequency
clock signal
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Application number
PCT/CN2007/001858
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English (en)
Chinese (zh)
Inventor
Qing Zhang
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Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2007143935A1 publication Critical patent/WO2007143935A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0644—External master-clock

Definitions

  • Network clock synchronization device system and method
  • the present invention relates to the field of communications technologies, and in particular, to a network clock synchronization apparatus, system, and method. Background technique
  • the network transmission mode is constantly evolving, from the initial TDM (Time Division Multiplexing) to the ATM (Asynchronous Transfer Mode) to the IP (Internet Protocol).
  • TDM Time Division Multiplexing
  • ATM Asynchronous Transfer Mode
  • IP Internet Protocol
  • the service equipment is mainly synchronized by extracting the clock information from the service code stream; however, in the IP network transmission mode, the scheme of extracting the clock information from the service code stream for synchronization is difficult to implement. Therefore, in the IP network transmission mode, the clock of the service equipment is mainly used in the scheme of FIG. 1 or FIG. 2 .
  • the solution for the existing synchronous clock is as follows: a GPS (Global Positioning System) and a constant temperature crystal oscillator are used as clock references on the service device to obtain a good clock synchronization reference. Not affected by the specific transmission line.
  • GPS Global Positioning System
  • a constant temperature crystal oscillator is used as clock references on the service device to obtain a good clock synchronization reference. Not affected by the specific transmission line.
  • the shortcomings of this solution are: increased engineering complexity and cost of the entire equipment.
  • the addition of GPS functions involves GPS antennas, feeders, lightning protection, brackets, three defenses, etc.; GPS signals cannot be received underground or in special occasions.
  • FIG. 2 it is another existing synchronous clock scheme: a micro-synchronization device dedicated to providing a timing reference is used to provide a clock reference for a service device.
  • this scheme eliminates the need to make additional changes to the clock design of existing equipment and obtain a clock reference that meets the requirements.
  • the disadvantage of this solution is that the cost is too high, and there is a certain difficulty in integrating the operation and maintenance systems of the synchronous device and the service device. Summary of the invention
  • the embodiment of the invention provides a network clock synchronization device, system and method, which can meet the requirements of clock synchronization of service devices at a lower cost.
  • An embodiment of the present invention provides a network clock synchronization apparatus, including: a filter selector, a synthesis and adjustment algorithm module, a frequency adjuster, an oscillator, and a time synthesizer, wherein the filter selector is configured to receive a time server.
  • the synthesizing and adjusting algorithm module is configured to obtain a frequency deviation by comparing the reference time information output by the filter selector and the local time information output by the time synthesizer; a regulator for adjusting a local clock signal of the output according to a frequency offset provided by the synthesis and adjustment algorithm module, the local clock signal originating from an oscillation source clock signal provided by the oscillator; a time synthesizer for The local clock signal originating from the frequency adjuster synthesizes local time information.
  • the embodiment of the invention further provides a network clock synchronization system, comprising: a network clock synchronization device and at least one time server, wherein the network clock synchronization device obtains reference time information from the time server, and compares the reference time information And the local time information obtains a frequency deviation between the two, and further adjusts the local clock signal output by the network clock synchronization device according to the frequency deviation.
  • a network clock synchronization system comprising: a network clock synchronization device and at least one time server, wherein the network clock synchronization device obtains reference time information from the time server, and compares the reference time information And the local time information obtains a frequency deviation between the two, and further adjusts the local clock signal output by the network clock synchronization device according to the frequency deviation.
  • the embodiment of the present invention further provides a network clock synchronization method, including the following steps: obtaining reference time information from a time server; obtaining frequency deviations of the two by comparing the reference time information with local time information; adjusting according to the frequency deviation Local clock signal.
  • the embodiment of the present invention obtains the reference time information from the upper time server, and then obtains the local frequency deviation by comparing the reference time information and the local time information, that is, the drift of the local oscillator, and further according to the frequency deviation.
  • the local clock signal is adjusted to eliminate the drift of the local clock, and a relatively accurate local clock signal is obtained, which finally meets the requirements of the clock synchronization of the service device. Since the related device or the micro-synchronous device that does not need to increase the GPS function is required, the cost required for realizing the clock synchronization purpose by the embodiment of the present invention is low.
  • FIG. 1 is a schematic diagram of a clock synchronization device of the prior art
  • FIG. 2 is a schematic diagram of another clock synchronization device of the prior art
  • 3 is a schematic diagram of an embodiment of a network clock synchronization apparatus according to the present invention
  • FIG. 4 is a flow chart of an embodiment of a network clock synchronization method according to the present invention.
  • the time is obtained from the upper-level time server through the NTP (Network Transfer Protocol). Since the time server does not have time drift, the NTP introduces only jitter when the network response capability changes during the IP network transmission process.
  • the local oscillator generates mainly drift, and its own jitter can be neglected. According to the time information obtained from different time servers, the drift of the local oscillator can be calculated, and the frequency adjuster can be adjusted to eliminate the drift of the local clock and finally reach the service device clock. Synchronization requirements.
  • FIG. 3 is a schematic diagram of an embodiment of a network clock synchronization system according to the present invention.
  • the network clock synchronization system includes a time server 31 and a clock synchronization device 32 that communicates therewith over an IP transmission network.
  • the clock synchronization device 32 includes a high stability oscillator 326, a frequency adjuster 325, a frequency multiplier 324, a time synthesizer 323, a filter selector 321, and a synthesis and adjustment algorithm module 322.
  • Filter selector 321 receiving time information of the time server on the IP transmission network from at least one time server (only FIG. 3 shows only the IP transmission network and one IP time server, and the IP transmission network can also be connected to multiple time servers) The following description is convenient.
  • the time information that the filter selector 321 receives directly from the time server 31 is referred to as reference source time information), and then the reference time information is output to the synthesis and adjustment algorithm module 322.
  • the filter selector 321 can receive a plurality of reference source time information from the plurality of time servers 31 through the IP transmission network, the filter selector 321 also acquires the local time information from the time synthesizer 323 at the same time. Further, the filter selector 321 selects the best samples from the reference source time information sent back by all the time servers 31, compares them with the local time information, and performs parameters such as round trip delay, dispersion, and offset through the selection and clustering algorithms. Analysis, select a number of (usually one) more accurate time server reference source time information for conventional filtering (mainly remove jitter) and other processing, generate a more accurate time information (for the convenience of description, the cylinder is called reference time information And transmitting the reference time information to the synthesis and adjustment algorithm module 322. Filter selector The 321 can be integrated in the CPU of the business device or set separately.
  • the filter selector 321 can only receive the reference source time information of one time server 31 through the IP transmission network, the filter selector 321 does not need to obtain the local time information from the time synthesizer 323 (because there is only one reference source).
  • the time information has no optional space.
  • the filter selector 321 generates the accurate reference time information by filtering the reference source time information, and outputs the reference time information to the synthesis and adjustment algorithm module 322. .
  • the reference time information output by the filter selector 321 to the synthesis and adjustment algorithm module 322 is obtained from the time server 31, except that the reference time information is obtained by directly receiving the reference from the time server 31.
  • the time information after the source time information has been processed (such as filtering).
  • the synthesis and adjustment algorithm module 322 receives the accurate reference time information output by the filter selector 321 and the local time information output by the time synthesizer 323, compares the time information of the reference time server 31 with the local time information, and obtains the local clock and Time deviation of the time server; Then, according to the time deviation data obtained multiple times, the time drift of the local clock signal output by the frequency adjuster 325 and the corresponding frequency deviation (referred to as frequency) can be obtained by filtering and scaling.
  • the output of the frequency adjuster 325 ie, the local clock signal
  • the local clock signal is adjusted based on the frequency offset, so that the local clock signal output by the frequency adjuster 325 can lock the upper time server, thereby achieving more accurate time synchronization.
  • the synthesis and adjustment algorithm module 322 can be integrated into the CPU of the business device or set separately. It should be noted that, in general, the synthesis and adjustment algorithm module 322 comprehensively obtains the frequency offset within a period of time according to the multiple time offset data, but does not exclude the synthesis and adjustment algorithm module 322 from obtaining the frequency based on only one time deviation data. The case where the bias is output to the frequency adjuster 325.
  • the frequency adjuster 325 receives the adjustment signal (ie, the frequency offset) output by the synthesis and adjustment algorithm module 322 and the oscillation source clock signal output by the high-stability oscillator 326, and the frequency adjuster 325 performs the current output local clock signal according to the frequency offset. Adjustment. It can be understood that if the adjustment to be performed by the frequency adjuster 325 is the initial adjustment, the local clock signal frequency output by the current frequency adjuster 325 is the frequency of the oscillation source clock signal output by the high-stability oscillator 326, and further, according to the frequency offset adjustment.
  • the adjustment signal ie, the frequency offset
  • the frequency of the local clock signal after the change becomes the frequency of the oscillation source clock signal plus the frequency of the frequency offset (which may be positive or negative), thereby completing the synchronization of the local clock signal.
  • the local clock signal of the current output is adjusted according to the frequency offset output by the synthesis and adjustment algorithm module 322.
  • the current local clock signal may have been adjusted differently from the oscillation source clock signal because it has been previously adjusted. It is.
  • the frequency adjuster 325 adjusts the current local clock signal according to the frequency offset output by the synthesis and adjustment algorithm module 322.
  • the local clock signal output by the frequency adjuster 325 is a clock signal used as a local system (such as a service device).
  • the frequency adjuster adjusts the output of the frequency adjuster by adjusting the frequency register set in it.
  • the frequency adjuster can be selected from devices such as DDS (Direct Digital Synthesize).
  • Frequency multiplier 324 The frequency of the local clock signal output by the frequency adjuster 325 is multiplied to a higher frequency and then supplied to the time synthesizer 323. The higher the frequency at which the frequency multiplier 324 performs frequency multiplication, the higher the resolution of the time synthesizer 323, and the higher the accuracy of synthesizing the time code.
  • the frequency multiplier 324 uses a dedicated frequency doubling device.
  • the time synthesizer 323 synthesizes an unsigned 64-bit second time code (ie, local time information) by using a clock signal output from the frequency multiplier 324 (the clock signal is derived from the local clock signal output from the frequency adjuster 325), for example, this time
  • the code represents the description starting from 0:00 on January 1, 1900.
  • the first 32 bits are the integer part, and the last 32 bits are the fractional part.
  • the theoretical counting accuracy is 2 - 32 seconds.
  • the logic count pulse comes from the clock signal after multiplier 324 multiplier, and the frequency is generally 100MHz.
  • the filter selector 321 and the synthesis and adjustment algorithm module 322 can obtain current local time information from the time synthesizer 323 in real time.
  • the time synthesizer 323 can be implemented in a logic (FPGA) device. Since the time synthesizer 323 uses the clock signal output by the frequency adjuster 325 and is multiplied, the accuracy of the time code synthesized by the time synthesizer 323 is directly The accuracy of the local clock signal output by the frequency adjuster 325 is reflected. It can be understood that if the accuracy of the local clock signal output by the frequency adjuster 325 is already high, the frequency multiplier 324 may not be needed, that is, the time synthesizer 323 directly receives the current local clock signal output by the frequency adjuster 325, and then according to the The local clock signal synthesizes the corresponding local time information.
  • FPGA logic
  • the high-stability oscillator 326 outputs the oscillation source clock signal to the frequency adjuster 325, which is equivalent to providing the frequency adjuster 325 with an output local clock signal, in other words, although the local clock signal currently output by the frequency adjuster 325 may Different from the oscillation source clock signal (eg, adjusted according to the frequency offset), but the local clock signal is derived from the oscillation source clock signal.
  • the high-temperature oscillator is generally selected as the constant temperature crystal oscillator (OCXO) device, the aging rate Typically 5* 10-1G / day: Without adjustment, the OCXO's ability to maintain can achieve a clock accuracy of 0.05ppm for at least half a month.
  • the clock synchronizing device 32 of the above construction can be provided inside the service device or separately. If the clock synchronization device 32 is disposed inside the service device, many of the modules in the clock synchronization device 32 can extend the modules within the existing service device, such as the high stability oscillator 326 and the frequency adjuster 325, that is, only for existing services.
  • the service device with the clock synchronization function in the all-IP transmission mode shown in the embodiment of the present invention can be implemented by the device. This kind of service equipment only needs to synchronize the calibration of its own clock according to the reference source time information provided by the time server, without adding equipment such as GPS antenna, feeder, lightning protection, bracket, three defense or higher cost. Micro-synchronous devices, etc., can save the cost of clock synchronization.
  • the clock synchronization device is not excluded from the service device.
  • the clock synchronization device can be used to provide an accurate local clock signal for the service device, and thus, the service device can This local clock signal is used as the clock signal used by its system.
  • FIG. 4 it is a flowchart of an embodiment of a network clock synchronization method of the present invention.
  • the network clock synchronization method process in this embodiment includes the following steps:
  • Step 10 The reference time selection source (ie, the filter selector 321) in the service device (which can be considered as being directly implemented in the service device by the network clock synchronization device 32) can be set at intervals (the interval time can be set and The adjustment, for example, setting the interval time to 64 seconds, sends a time request to the at least one time server through the IP transmission network; of course, the service device may not actively request, but the time interval between the server 31 is actively transmitted (for example, broadcast) Way) Your own reference source time information.
  • the filter selector 321 in the service device which can be considered as being directly implemented in the service device by the network clock synchronization device 32
  • the adjustment for example, setting the interval time to 64 seconds, sends a time request to the at least one time server through the IP transmission network; of course, the service device may not actively request, but the time interval between the server 31 is actively transmitted (for example, broadcast) Way) Your own reference source time information.
  • Step 20 The time server 31 sends its own reference source time information to the filter selector 321 through the IP transmission network. If there are multiple time servers 31, the filter selector 321 also sends back the reference source time from all the time servers 31. The best sample is selected in the information, compared with the local time information, and the parameters such as round trip delay, dispersion and offset are analyzed by the selection and clustering algorithm, and several (generally one) more accurate time server references are selected.
  • the source time information generates more accurate time information (referred to as reference time information), wherein the local time information is acquired from the time synthesizer 323. As already mentioned, if the filter selector 321 receives only the reference source time information of a time server 31, it is no longer necessary to obtain it from the time synthesizer 323. Current local time information.
  • steps 10 and 20 above are to obtain reference time information from the time server 31. Specifically, at least one reference source time information is received first, and then reference time information is generated accordingly.
  • Step 30 The filter selector 321 sends the reference time information to the synthesis and adjustment algorithm module 322.
  • the synthesis and adjustment algorithm module 322 compares the reference time information with the current local time information to obtain a time offset between the local clock and the time server.
  • Step 40 According to the time deviation data obtained multiple times, the drift of the output clock of the frequency adjuster 325 and the corresponding frequency offset are obtained by filtering and scaling, and the frequency adjuster 325 is adjusted according to the frequency adjuster. The output of 325 locks the clock of the upper time server 31.
  • the synthesis and adjustment algorithm module can output the frequency adjuster 325 according to the previously adjusted empirical value. Adjustments are made to ensure that the clock of the business device can also achieve higher accuracy in this case.
  • the NTP introduces only jitter in the network network transmission process during the IP network transmission process; and the local high-stability oscillator 326 mainly generates drift, and its own jitter can be ignored.
  • This can combine the long-term stability of the time server 31 with the good anti-shake capability of the local high-stability oscillator 326 soft phase-locked loop to achieve the clock synchronization of the service device, that is, using NTP to compensate for the time caused by the aging of the OCXO device. drift. In this way, the purpose of clock synchronization in the IP network transmission mode at a lower cost is achieved.
  • the technical solution of the embodiment of the present invention is applicable not only to the IP network transmission mode but also to other transmission modes.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Electric Clocks (AREA)

Abstract

L'invention concerne un appareil de synchronisation d'horloge de réseau (32) se rapportant au domaine de la technologie de communication comprenant un sélecteur de filtre (321), un module d'algorithme de synthèse et d'ajustement (322), un régulateur de fréquence (325), un oscillateur (326) et un synthétiseur temporel (323). Le sélecteur de filtre (321) reçoit les informations temporelles de source de référence d'un serveur temporel (31) et génère de cette manière les informations temporelles standard; le module d'algorithme de synthèse et d'ajustement (322) obtient une différence de fréquence en comparant la sortie d'informations temporelles standard provenant du sélecteur de filtre (321) avec la sortie d'informations temporelles locales provenant du synthétiseur temporel (323); le régulateur de fréquence (325) régule son signal d'horloge locale de sortie selon la différence de fréquence fournie par le module d'algorithme de synthèse et d'ajustement (322), la source de signal d'horloge locale provenant du signal d'horloge de source d'oscillation fourni par l'oscillateur (326); le synthétiseur temporel (323) synthétise les informations temporelles locales à partir du signal d'horloge locale provenant du régulateur de fréquence (325). L'invention concerne également un système et un procédé pouvant répondre à l'exigence de synchronisation d'horloge du dispositif de service pour un coût réduit.
PCT/CN2007/001858 2006-06-12 2007-06-12 appareil de synchronisation d'horloge de réseau, système et procédé WO2007143935A1 (fr)

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CN2006100610629A CN101043315B (zh) 2006-06-12 2006-06-12 一种网络时钟同步装置、系统及方法
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WO2020172871A1 (fr) * 2019-02-28 2020-09-03 华为技术有限公司 Appareil de traitement de données
CN115134905A (zh) * 2022-06-27 2022-09-30 国网青海省电力公司信息通信公司 频率校准方法、装置、非易失性存储介质及计算机设备

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CN101425891B (zh) * 2008-12-09 2012-09-12 中兴通讯股份有限公司 时间同步方法、系统和客户端
CN102025704B (zh) * 2009-09-14 2015-05-13 中兴通讯股份有限公司 一种可重用票据使用方法及终端
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