WO2020161995A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2020161995A1
WO2020161995A1 PCT/JP2019/046014 JP2019046014W WO2020161995A1 WO 2020161995 A1 WO2020161995 A1 WO 2020161995A1 JP 2019046014 W JP2019046014 W JP 2019046014W WO 2020161995 A1 WO2020161995 A1 WO 2020161995A1
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WIPO (PCT)
Prior art keywords
film
inorganic
semiconductor layer
display device
gate insulating
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PCT/JP2019/046014
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English (en)
Japanese (ja)
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優次 前出
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株式会社ジャパンディスプレイ
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Publication of WO2020161995A1 publication Critical patent/WO2020161995A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • Embodiments of the present invention relate to a display device.
  • the display device includes pixels in a display area for displaying an image and a drive circuit in a non-display area around the display area.
  • a thin film transistor (TFT) used as a switching element of a pixel needs to have a small leak current.
  • a TFT including an oxide semiconductor can reduce leakage current.
  • it is desirable that the TFT used in the driving circuit has high mobility. Since the TFT formed of LTPS (Low Temperature Poly-Si) has high mobility, it can be used for a driving circuit. As described above, there is known a configuration in which an oxide semiconductor is used for the TFT of the pixel in the display region and LTPS is used for the TFT of the peripheral drive circuit.
  • the purpose of this embodiment is to provide a display device capable of reducing power consumption.
  • a polysilicon semiconductor layer having a display region for displaying an image and a non-display region surrounding the display region, and a first gate electrode located on the polysilicon semiconductor layer are provided.
  • a first thin film transistor located in the non-display region, an oxide semiconductor layer, and a second gate electrode located on the oxide semiconductor layer, and a first thin film transistor located in the display region.
  • a display device in which the second gate insulating film covers the entire oxide semiconductor layer.
  • FIG. 1 is a diagram showing a configuration and an equivalent circuit of the display device of this embodiment.
  • FIG. 2 is a plan view showing the positional relationship of the second thin film transistors.
  • FIG. 3 is a cross-sectional view showing the display device along the line AB shown in FIG.
  • FIG. 4 is a cross-sectional view showing the first thin film transistor in the non-display area and the second thin film transistor in the display area.
  • FIG. 5 is a cross-sectional view showing the first substrate taken along the line CD shown in FIG.
  • FIG. 6 is a cross-sectional view showing a step of forming a contact hole of the first thin film transistor and a contact hole of the second thin film transistor.
  • FIG. 7 is a table showing the results of measuring the film thickness and optical characteristics of each display device.
  • FIG. 8 is a table showing the results of measuring the film thickness and optical characteristics of each display device.
  • the main configuration of this embodiment can be used for a display device.
  • the display device can be used in various devices such as a smartphone, a tablet terminal, a mobile phone terminal, a notebook-type personal computer, an in-vehicle device, and a game device.
  • the present embodiment is a liquid crystal display device, a self-luminous display device such as an organic electroluminescence display device, a micro LED display device, an electronic paper type display device having an electrophoretic element, a MEMS (Micro Electro Mechanical Systems).
  • the present invention can be applied to various display devices such as a display device to which is applied or a display device to which electrochromism is applied. Further, the present invention can be applied to a wearable display device and a display device having an irregular shape.
  • FIG. 1 is a diagram showing a configuration and an equivalent circuit of the display device DSP of this embodiment.
  • the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees.
  • the first direction X and the second direction Y correspond to the directions parallel to the main surface of the substrate forming the display device DSP
  • the third direction Z corresponds to the thickness direction of the display device DSP.
  • the direction toward the tip of the arrow indicating the third direction Z is referred to as upward (or simply upward), and the direction opposite from the tip of the arrow is referred to as downward (or simply downward).
  • the display device DSP includes a display panel PNL and a wiring board WB mounted on the display panel PNL.
  • the display panel PNL is a liquid crystal display panel, and includes a first substrate SUB1, a second substrate SUB2 facing the first substrate SUB1, a sealing material SE, a liquid crystal layer LC, a source line S, and a gate line G.
  • the first thin film transistor TR1 and the second thin film transistor TR2, the pixel electrode PE, the common electrode CE and the like are provided.
  • the display panel PNL includes a display area DA for displaying an image and a non-display area NDA surrounding the display area DA.
  • the first substrate SUB1 has a mounting portion MA exposed outside the second substrate SUB2.
  • the sealing material SE is located in the non-display area NDA and bonds the first substrate SUB1 and the second substrate SUB2 together.
  • the region where the seal material SE is arranged is shown by a diagonal line rising to the right.
  • the display area DA is located inside surrounded by the seal material SE.
  • the display panel PNL includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y in the display area DA.
  • the first thin film transistor TR1 functions as a switching element of a drive circuit for driving the pixel PX, and is located in the non-display area NDA.
  • the first thin film transistor TR1 includes a semiconductor layer made of low temperature polysilicon (LTPS).
  • the second thin film transistor TR2 functions as a switching element of the pixel PX and is located in the display area DA.
  • the second thin film transistor TR2 includes an oxide semiconductor layer. That is, the display device DSP of the present embodiment has a hybrid structure including both the first thin film transistor TR1 using the LTPS and the second thin film transistor TR2 using the oxide semiconductor layer. The effect of applying the hybrid structure to the display device DSP will be described below.
  • the first thin film transistor TR1 using LTPS having a high carrier mobility is suitable for the drive circuit of the non-display area NDA.
  • an oxide semiconductor has low carrier mobility and thus may be difficult to use in a driver circuit. Therefore, the first thin film transistor TR1 using LTPS is used as the TFT of the drive circuit.
  • the second thin film transistor TR2 using an oxide semiconductor is suitable for the pixel PX in the display area DA.
  • the voltage is held for one frame by the holding capacitor CS formed between the pixel electrode PE and the electrode having the same potential as the common electrode CE.
  • the leak current of the TFT is large, the voltage of the pixel electrode PE changes, and flicker or the like occurs to make it impossible to form a good image. That is, it is desirable that the TFT of the pixel PX has a small leak current.
  • a TFT including an oxide semiconductor can reduce leakage current.
  • the second thin film transistor TR2 including an oxide semiconductor is used as the TFT of the pixel PX.
  • the first thin film transistor TR1 using LTPS is used for the driving circuit
  • the second thin film transistor TR2 using oxide semiconductor is used for the pixel PX. Since such a display device DSP can reduce leakage current by the oxide semiconductor, it is excellent in low frequency driving, and power required for driving the display device DSP can be reduced.
  • the above-mentioned source line S, gate line G, pixel electrode PE, common electrode CE, and liquid crystal layer LC are located in the display area DA.
  • the source line S extends along the second direction Y
  • the gate line G extends along the first direction X.
  • the second thin film transistor TR2 is electrically connected to the gate line G and the source line S.
  • the pixel electrode PE is electrically connected to the second thin film transistor TR2.
  • Each of the pixel electrodes PE faces the common electrode CE and drives the liquid crystal layer LC by an electric field generated between the pixel electrode PE and the common electrode CE.
  • the flexible wiring board WB is mounted on the mounting portion MA. Further, the wiring board WB includes a drive IC chip 2 that drives the display panel PNL. The drive IC chip 2 may be mounted on the mounting portion MA.
  • the display panel PNL of the present embodiment is a transmissive type having a transmissive display function of displaying an image by selectively transmitting light from the back surface side of the first substrate SUB1, light from the front surface side of the second substrate SUB2. It may be either a reflective type having a reflective display function of displaying an image by selectively reflecting light or a semi-transmissive type having a transmissive display function and a reflective display function.
  • the display panel PNL displays a display mode utilizing a lateral electric field along the main surface of the substrate and a vertical electric field along a normal line of the main surface of the substrate. It corresponds to the display mode to be used, the display mode to use the tilt electric field inclined in the oblique direction with respect to the main surface of the substrate, and the display mode to use the lateral electric field, the vertical electric field, and the tilt electric field in appropriate combination. It may have any configuration.
  • the main surface of the substrate here is a surface parallel to the XY plane defined by the first direction X and the second direction Y.
  • FIG. 2 is a plan view showing the positional relationship of the second thin film transistor TR2.
  • the source lines S1 and S2 extend substantially in the second direction Y and are arranged in parallel in the first direction X.
  • the gate lines G11 and G21 overlap each other and extend in the first direction X.
  • the second thin film transistor TR2 is electrically connected to the gate line G21 and the source line S2.
  • the second thin film transistor TR2 includes an oxide semiconductor layer OSC, source/drain electrodes EL21 and EL22, and protective electrodes 101 and 102.
  • the oxide semiconductor layer OSC is arranged so that a part thereof overlaps the source line S2, and the other part extends between the source lines S1 and S2.
  • the oxide semiconductor layer OSC intersects the gate lines G11 and G21 between the source lines S1 and S2. That is, the oxide semiconductor layer OSC overlaps with part of each of the gate lines G11 and G21.
  • the gate line G11 has a light shielding film LS that is wide in the second direction Y.
  • the oxide semiconductor layer OSC overlaps with the light shielding film LS.
  • a region overlapping with the oxide semiconductor layer OSC functions as a second gate electrode GE2 described later.
  • Protective electrode 101 overlaps one end SCA of oxide semiconductor layer OSC.
  • the protective electrode 102 overlaps the source line S2 and the other end SCB of the oxide semiconductor layer OSC.
  • the source/drain electrode EL21 is formed in an island shape and is arranged between the source line S1 and the source line S2.
  • the source/drain electrode EL21 overlaps the protective electrode 101 and the one end portion SCA of the oxide semiconductor layer OSC.
  • the source/drain electrode EL21 is electrically connected to the one end SCA through the through hole CH1.
  • the source/drain electrode EL22 is formed integrally with the source line S2.
  • the source/drain electrode EL22 overlaps the protective electrode 102 and the other end SCB of the oxide semiconductor layer OSC.
  • the source/drain electrode EL22 is electrically connected to the other end SCB through the through hole CH2.
  • FIG. 3 is a cross-sectional view showing the display device DSP taken along the line AB shown in FIG.
  • the illustrated example corresponds to an example in which a display mode using a lateral electric field is applied to the display panel PNL.
  • the display device DSP includes a first optical element OD1, a second optical element OD2, and an illumination device IL in addition to the display panel PNL.
  • the first substrate SUB1 includes the insulating substrate 10, the undercoat layer UC, the first gate insulating film GI1, the first inorganic film IL1, the second inorganic film IL2, the second gate insulating film GI2, the third inorganic film IL3, and the fourth inorganic film.
  • the film IL4 the first organic film 11, the second organic film 12, the capacitive insulating film 13, the oxide semiconductor layer OSC, the protective electrode 102, the source lines S1 and S2, the metal wirings ML1 and ML2, the common electrode CE, the pixel electrode PE,
  • the alignment film AL1 is provided.
  • the insulating substrate 10 is a light transmissive substrate such as a glass substrate or a flexible resin substrate.
  • the undercoat layer UC is located on the insulating substrate 10.
  • the first gate insulating film GI1 is located on the undercoat layer UC.
  • the first inorganic film IL1 is located on the first gate insulating film GI1.
  • the second inorganic film IL2 is located on the first inorganic film IL1.
  • the oxide semiconductor layer OSC is located on the second inorganic film IL2.
  • the protective electrode 102 covers the oxide semiconductor layer OSC.
  • the second gate insulating film GI2 covers the protective electrode 102.
  • the third inorganic film IL3 is located on the second gate insulating film GI2.
  • the fourth inorganic film IL4 is located on the third inorganic film IL3.
  • the source lines S1 and S2 are located on the fourth inorganic film IL4 and covered with the first organic film 11.
  • the metal wirings ML1 and ML2 are located on the first organic film 11 and covered with the second organic film 12.
  • the metal wirings ML1 and ML2 are located directly above the source lines S1 and S2, respectively.
  • the common electrode CE is located on the second organic film 12 and covered with the capacitive insulating film 13.
  • the pixel electrode PE is located on the capacitive insulating film 13 and covered with the alignment film AL1.
  • the common electrode CE and the pixel electrode PE are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).
  • the undercoat layer UC, the first gate insulating film GI1, the first inorganic film IL1, the second inorganic film IL2, the second gate insulating film GI2, the third inorganic film IL3, the fourth inorganic film IL4, and the capacitance insulating film 13 are made of silicon.
  • the first organic film 11 and the second organic film 12 are organic insulating films formed of an organic insulating material such as acrylic resin, for example.
  • the second substrate SUB2 includes an insulating substrate 20, a light shielding layer BM, a color filter CF, an overcoat layer OC, an alignment film AL2 and the like.
  • the insulating substrate 20 is a light-transmissive substrate such as a glass substrate or a resin substrate.
  • the light blocking layer BM and the color filter CF are located on the side of the insulating substrate 20 that faces the first substrate SUB1.
  • the area where the light shielding layer BM is not located corresponds to the opening OP of the pixel.
  • the color filter CF is arranged at a position facing the pixel electrode PE, and a part thereof overlaps the light shielding layer BM.
  • the color filter CF has a red color filter CFR, a green color filter CFG, and a blue color filter CFB.
  • the overcoat layer OC covers the color filter CF.
  • the overcoat layer OC is formed of a transparent resin.
  • the alignment film AL2 covers the overcoat layer OC.
  • the alignment films AL1 and AL2 are formed of, for example, a material exhibiting horizontal alignment.
  • the above-described first substrate SUB1 and second substrate SUB2 are arranged so that the alignment films AL1 and AL2 face each other.
  • the first substrate SUB1 and the second substrate SUB2 are adhered by a sealing material with a predetermined cell gap formed.
  • the liquid crystal layer LC is held between the alignment films AL1 and AL2.
  • the liquid crystal layer LC includes liquid crystal molecules LM.
  • the liquid crystal layer LC is made of a positive type (dielectric anisotropy is positive) liquid crystal material or a negative type (dielectric anisotropy is negative) liquid crystal material.
  • the first optical element OD1 including the polarizing plate PL1 is adhered to the insulating substrate 10.
  • the second optical element OD2 including the polarizing plate PL2 is adhered to the insulating substrate 20.
  • the first optical element OD1 and the second optical element OD2 may be provided with a retardation plate, a scattering layer, an antireflection layer, etc., if necessary.
  • the liquid crystal molecules LM are initially in a predetermined direction between the alignment films AL1 and AL2 in an off state where an electric field is not formed between the pixel electrode PE and the common electrode CE. It is oriented. In such an off state, the light emitted from the illumination device IL toward the display panel PNL is absorbed by the first optical element OD1 and the second optical element OD2, resulting in a dark display.
  • the liquid crystal molecules LM are aligned in a direction different from the initial alignment direction by the electric field, and the alignment direction is controlled by the electric field. .. In such an ON state, a part of the light from the illumination device IL is transmitted through the first optical element OD1 and the second optical element OD2, resulting in bright display.
  • FIG. 4 is a cross-sectional view showing the first thin film transistor TR1 in the non-display area NDA and the second thin film transistor TR2 in the display area DA. Both the first thin film transistor TR1 and the second thin film transistor TR2 are top gates.
  • first inorganic film IL1 and the second inorganic film IL2 are combined to form a first inorganic laminated film LF1.
  • third inorganic film IL3 and the fourth inorganic film IL4 are combined to form a second inorganic laminated film LF2.
  • the first thin film transistor TR1 includes a polysilicon semiconductor layer PSC, a first gate electrode GE1 located on the polysilicon semiconductor layer PSC, and electrodes EL11 and EL12.
  • the polysilicon semiconductor layer PSC is located on the undercoat layer UC and is covered with the first gate insulating film GI1.
  • the undercoat layer UC is formed of, for example, two layers of SiO and SiN.
  • the undercoat layer UC prevents impurities contained in the glass of the insulating substrate 10 from contaminating the polysilicon semiconductor layer PSC.
  • the first gate insulating film GI1 is also located between the polysilicon semiconductor layer PSC and the first gate electrode GE1.
  • the first gate insulating film GI1 is formed using, for example, tetraethoxysilane (TEOS).
  • the first gate electrode GE1 is covered with the first inorganic film IL1.
  • the first gate electrode GE1 is formed integrally with the gate line G11 shown in FIG.
  • the electrodes EL11 and EL12 are located on the fourth inorganic film IL4 and are electrically connected to the polysilicon semiconductor layer PSC through the contact holes CH11 and CH12.
  • the contact holes CH11 and CH12 overlap the polysilicon semiconductor layer PSC and penetrate the first gate insulating film GI1, the first inorganic laminated film LF1, the second gate insulating film GI2, and the second inorganic laminated film LF2 to the polysilicon semiconductor layer PSC. doing.
  • the second thin film transistor TR2 includes an oxide semiconductor layer OSC, a second gate electrode GE2 located on the oxide semiconductor layer OSC, and source/drain electrodes EL21 and EL22.
  • the light shielding film LS is located on the first gate insulating film GI1 and is covered with the first inorganic film IL1.
  • the light shielding film LS is located below the oxide semiconductor layer OSC. Therefore, exposure of the oxide semiconductor layer OSC to light from the lighting device can be suppressed, and a photocurrent can be suppressed from flowing to the oxide semiconductor layer OSC.
  • the light shielding film LS is located in the same layer as the first gate electrode GE1 and is made of the same material.
  • TAOS Transparent Amorphous Oxide Semiconductor
  • IGZO Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide
  • ZnON Zinc Oxide Nitride
  • IGO Indium Gallium Oxide
  • the first inorganic film IL1 is in contact with the light shielding film LS and the first gate insulating film GI1.
  • the second inorganic film IL2 is stacked on the first inorganic film IL1 and is in contact with the oxide semiconductor layer OSC.
  • the first inorganic film IL1 is made of, for example, SiN.
  • the second inorganic film IL2 is made of, for example, SiO.
  • the first inorganic film IL1 may be formed of SiON instead of SiN.
  • the film thickness of the first inorganic film IL1 and the second inorganic film IL2 either one may be thicker than the other depending on the purpose.
  • the third inorganic film IL3 is in contact with the second gate electrode GE2 and the second gate insulating film GI2.
  • the fourth inorganic film IL4 is stacked on the third inorganic film IL3.
  • the third inorganic film IL3 is made of, for example, SiN.
  • the fourth inorganic film IL4 is made of, for example, SiO.
  • the lower inorganic film be SiN and the upper inorganic film be SiO.
  • the third inorganic film IL3 may be formed of SiON instead of SiN.
  • the film thickness of the third inorganic film IL3 and the fourth inorganic film IL4 either one may be thicker than the other depending on the purpose.
  • the second gate insulating film GI2 is also located between the oxide semiconductor layer OSC and the second gate electrode GE2. That is, the second gate insulating film GI2 covers the entire oxide semiconductor layer OSC and is also formed in regions other than the contact holes CH1, CH2, CH11, and CH12. The second gate insulating film GI2 is also located in the opening OP, as shown in FIG. The second gate insulating film GI2 is in contact with the second inorganic film IL2, but since it is formed of SiO similarly to the second inorganic film IL2, the second gate insulating film GI2 has the same refractive index and is unlikely to affect thin film interference.
  • the source/drain electrodes EL21, EL22 are located on the fourth inorganic film IL4 and are in contact with the protective electrodes 101, 102 through the contact holes CH1, CH2, respectively.
  • the contact holes CH1 and CH2 overlap the oxide semiconductor layer OSC and penetrate the second gate insulating film GI2 and the second inorganic laminated film LF2 to the protective electrodes 101 and 102.
  • the first organic film 11 covers the electrodes EL11, EL12 and the source/drain electrodes EL21, EL22.
  • the pixel electrode PE is connected to the source/drain electrode EL21 through a contact hole CH3 penetrating the first organic film 11, the second organic film 12, and the capacitive insulating film 13.
  • the second gate insulating film GI2 is uniformly formed not only under the second gate electrode GE2 but also in a region other than the contact hole. Therefore, in implantation of the oxide semiconductor layer OSC, the resistance of the oxide semiconductor layer OSC can be stably reduced.
  • the inorganic film in contact with the oxide semiconductor layer OSC is SiN, hydrogen in the oxide semiconductor layer OSC may be released. Since the second gate insulating film GI2 is in contact with the oxide semiconductor layer OSC and formed of SiO, release of hydrogen from the oxide semiconductor layer OSC can be suppressed. Therefore, deterioration of the characteristics of the oxide semiconductor layer OSC can be suppressed.
  • the total thickness of the first gate insulating film GI1 and the second gate insulating film GI2 is smaller than the total thickness of the first inorganic laminated film LF1 and the second inorganic laminated film LF2.
  • the thickness of the first inorganic laminated film LF1 is larger than that of the first gate electrode GE1 and the thickness of the second inorganic laminated film LF2 is larger than that of the second gate electrode GE2, the insulation properties of the gate line and the gate electrode are secured. it can.
  • FIG. 5 is a cross-sectional view showing the first substrate SUB1 taken along the line CD shown in FIG.
  • the oxide semiconductor layer OSC and the gate line G11 intersect with each other, a capacitance is generated between them.
  • the gate line G21 intersects the source lines S1 and S2, capacitance is generated between the gate line G21 and the source line S1 and between the gate line G21 and the source line S2. If these capacities are large, there is a risk that the power for driving the pixels will increase.
  • the thickness T1 of the first inorganic laminated film LF1 is set to 300 nm or more in order to reduce the capacitance between the oxide semiconductor layer OSC and the gate line G11. Further, in order to reduce the capacitance between the gate line G21 and the source line S1 and between the gate line G21 and the source line S2, the film thickness T2 of the second inorganic laminated film LF2 is set to 400 nm or more. By reducing the capacity, the original power reduction effect of the hybrid structure can be obtained.
  • FIG. 6 is a cross-sectional view showing a step of forming the contact holes CH11, CH12 of the first thin film transistor TR1 and the contact holes CH1, CH2 of the second thin film transistor TR2.
  • Contact holes CH1, CH2, CH11, CH12 are formed in the same process by dry etching. Dry etching is performed using a CF-based (CF4) or CHF-based (CHF3) gas. At the time of dry etching, the oxide semiconductor layer OSC is protected by the protective electrodes 101 and 102 and is not removed.
  • the contact holes CH11 and CH12 penetrate the first gate insulating film GI1, the first inorganic laminated film LF1, the second gate insulating film GI2, and the second inorganic laminated film LF2, and the contact holes CH1 and CH2 are the second It penetrates through the gate insulating film GI2 and the second inorganic laminated film LF2. Therefore, the contact holes CH11 and CH12 are cut deeper than the contact holes CH1 and CH2 by the film thickness of the first gate insulating film GI1 and the first inorganic laminated film LF1.
  • the contact holes CH1, CH2 may be overcut while the contact holes CH11, CH12 are cut.
  • the contact holes CH1 and CH2 are excessively cut, the source/drain electrodes are not able to follow the shapes of the contact holes CH1 and CH2 and are broken, or the source/drain electrodes are formed according to the sizes of the contact holes CH1 and CH2. Since it is necessary, the aperture ratio of the pixel may decrease. In addition, the strength of the lighting device must be increased as the aperture ratio decreases, which may increase power consumption.
  • the film thickness T1 of the first inorganic laminated film LF1 is set to the second inorganic laminated film. It is formed thinner than the film thickness T2 of LF2. More specifically, the film thickness of the first inorganic laminated film LF1 is 500 nm or less. Furthermore, in order to secure the processability of the contact holes CH11 and CH12, the total thickness of the first gate insulating film GI1, the first inorganic laminated film LF1, the second gate insulating film GI2, and the second inorganic laminated film LF2 is It is 1100 nm or less.
  • the etching rate of the first inorganic laminated film LF1 is higher.
  • SiN has a faster etching rate than SiO. Therefore, it is desirable that the first inorganic laminated film LF1 satisfy the relationship that the film thickness of SiN is larger than the film thickness of SiO.
  • the film thickness T11 of the first inorganic film IL1 is formed larger than the film thickness T12 of the second inorganic film IL2. .. Therefore, excessive etching of the contact holes CH1 and CH2 can be suppressed. Therefore, it is possible to suppress disconnection of the source/drain electrodes, decrease in pixel aperture ratio, and increase in power consumption.
  • FIG. 7 is a table showing the results of measuring the film thickness and optical characteristics of each display device.
  • the second gate insulating film GI2 and the second inorganic laminated film LF2 are not formed.
  • the film thickness condition of the second embodiment satisfies the film thickness of the first inorganic laminated film LF1 of 300 nm or more and the film thickness of the second inorganic laminated film LF2 of 400 nm or more.
  • the film thickness of the first inorganic laminated film LF1 which is the film thickness condition of the third embodiment is 500 nm or less, the first gate insulating film GI1, the first inorganic laminated film LF1, the second gate insulating film GI2, The total thickness of the second inorganic laminated film LF2 satisfies 1100 nm or less.
  • the transmittance Y is lower than in LTPS, and the values of chromaticity x and y are also changed.
  • the film thickness conditions of the second embodiment and the third embodiment may not be satisfied.
  • x is preferably 0.006 or less and y is preferably 0.01 or less.
  • Case1, Case3, Case5, Case6, Case7 satisfy this.
  • Case 1 has a better 4 ⁇ than Case 6, but has a drawback that it is difficult to use because x of the optical type is 0.003 smaller than LTPS.
  • Case 5 and Case 7 are inferior to Case 6 in both Type and 4 ⁇ . Therefore, Case3 and Case6 are optimal from the viewpoint of optical type and optical 4 ⁇ .
  • the transmittance can be improved over LTPS while maintaining the chromaticity close to LTPS.
  • the number of laminated insulating films having different refractive indexes is larger than that in the case of only LTPS. Therefore, the thin film interference may reduce the transmittance, which may increase the power consumption of the lighting device.
  • optical interference is optimized and optical characteristics are improved by changing the total thickness of the first inorganic laminated film LF1, the total thickness of the second inorganic laminated film LF2, and the film thickness ratio of SiN and SiO. be able to.
  • the first inorganic film IL1 has a thickness of 275 nm
  • the second inorganic film IL2 has a thickness of 225 nm
  • the thickness of the first inorganic film IL1 is thicker than that of the second inorganic film IL2.
  • the total thickness of the first inorganic laminated film LF1 is 500 nm
  • the film thickness ratio of SiO and SiN is 9:11. That is, SiN has a film thickness of about 1.2 times that of SiO.
  • the third inorganic film IL3 has a thickness of 150 nm
  • the fourth inorganic film IL4 has a thickness of 250 nm
  • the film thickness of the third inorganic film IL3 is thinner than the film thickness of the fourth inorganic film IL4.
  • the total thickness of the second inorganic laminated film LF2 is 400 nm
  • the film thickness ratio of SiO and SiN is 5:3. That is, SiN is 0.6 times as large as SiO.
  • the first inorganic film IL1 has a thickness of 150 nm
  • the second inorganic film IL2 has a thickness of 250 nm
  • the thickness of the first inorganic film IL1 is smaller than that of the second inorganic film IL2.
  • the total thickness of the first inorganic laminated film LF1 is 400 nm
  • the film thickness ratio of SiO and SiN is 5:3. That is, SiN has a film thickness 0.6 times that of SiO.
  • the film thickness of the second inorganic laminated film LF2 and the film thickness ratio of SiO and SiN are the same as in Case 3.
  • the optical interference may be further optimized by changing SiN to SiON.
  • FIG. 8 is a table showing the results of measuring the film thickness and optical characteristics of each display device.
  • Base Case Case 2, Case 3, Case 4, and Case 6 are preferable.
  • the chromaticity deviation amount ⁇ xy is large.
  • Case2, Case3, Case4, and Case6, Case4 is optimal from the viewpoint of optical type and optical 4 ⁇ .
  • the first inorganic film IL1 is 420 nm
  • the second inorganic film IL2 is 100 nm
  • the film thickness of the first inorganic film IL1 is thicker than the film thickness of the second inorganic film IL2.
  • the total thickness of the first inorganic laminated film LF1 is 520 nm, and the film thickness ratio of SiO and SiN is 5:21. That is, SiN has a film thickness 4.2 times that of SiO.
  • the third inorganic film IL3 has a thickness of 280 nm
  • the fourth inorganic film IL4 has a thickness of 120 nm
  • the film thickness of the third inorganic film IL3 is thicker than the film thickness of the fourth inorganic film IL4.
  • the total thickness of the second inorganic laminated film LF2 is 400 nm
  • the film thickness ratio of SiO and SiN is 3:7. That is, SiN is about 2.3 times as much as SiO.
  • the display device capable of reducing the power consumption.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un dispositif d'affichage comprenant : une zone d'affichage pour afficher une image ; une zone non d'affichage entourant la zone d'affichage ; une couche semi-conductrice en polysilicium ; une première électrode grille située sur la couche semi-conductrice en polysilicium ; un premier transistor à couches minces situé dans la zone non d'affichage ; une couche d'oxyde semi-conducteur ; et une seconde électrode grille située sur la couche d'oxyde semi-conducteur. Le dispositif d'affichage comprend : un second transistor à couches minces situé dans la zone d'affichage ; un premier film isolant de grille situé entre la couche semi-conductrice en polysilicium et la première électrode grille ; et un second film isolant de grille situé entre la couche semi-conductrice oxyde et la seconde électrode grille. Le second film isolant de grille recouvre la totalité de la couche semi-conductrice oxyde.
PCT/JP2019/046014 2019-02-06 2019-11-25 Dispositif d'affichage WO2020161995A1 (fr)

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JP2011048339A (ja) * 2009-08-25 2011-03-10 Samsung Mobile Display Co Ltd 有機発光表示装置及びその製造方法
JP2012048270A (ja) * 2011-12-05 2012-03-08 Semiconductor Energy Lab Co Ltd 半導体装置
KR20150101414A (ko) * 2014-02-24 2015-09-03 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
JP2016219818A (ja) * 2010-12-28 2016-12-22 株式会社半導体エネルギー研究所 半導体装置
JP2017037316A (ja) * 2006-04-06 2017-02-16 株式会社半導体エネルギー研究所 表示装置
JP2017126693A (ja) * 2016-01-15 2017-07-20 株式会社ジャパンディスプレイ 半導体装置
JP2017208473A (ja) * 2016-05-19 2017-11-24 株式会社ジャパンディスプレイ 表示装置
US20180076238A1 (en) * 2016-09-12 2018-03-15 Samsung Display Co., Ltd. Transistor and display device having the same
WO2018180617A1 (fr) * 2017-03-27 2018-10-04 シャープ株式会社 Substrat matriciel actif, dispositif d'affichage à cristaux liquides et dispositif d'affichage électroluminescent organique
JP2018195747A (ja) * 2017-05-19 2018-12-06 株式会社ジャパンディスプレイ 半導体装置及び表示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017037316A (ja) * 2006-04-06 2017-02-16 株式会社半導体エネルギー研究所 表示装置
JP2011048339A (ja) * 2009-08-25 2011-03-10 Samsung Mobile Display Co Ltd 有機発光表示装置及びその製造方法
JP2016219818A (ja) * 2010-12-28 2016-12-22 株式会社半導体エネルギー研究所 半導体装置
JP2012048270A (ja) * 2011-12-05 2012-03-08 Semiconductor Energy Lab Co Ltd 半導体装置
KR20150101414A (ko) * 2014-02-24 2015-09-03 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
JP2017126693A (ja) * 2016-01-15 2017-07-20 株式会社ジャパンディスプレイ 半導体装置
JP2017208473A (ja) * 2016-05-19 2017-11-24 株式会社ジャパンディスプレイ 表示装置
US20180076238A1 (en) * 2016-09-12 2018-03-15 Samsung Display Co., Ltd. Transistor and display device having the same
WO2018180617A1 (fr) * 2017-03-27 2018-10-04 シャープ株式会社 Substrat matriciel actif, dispositif d'affichage à cristaux liquides et dispositif d'affichage électroluminescent organique
JP2018195747A (ja) * 2017-05-19 2018-12-06 株式会社ジャパンディスプレイ 半導体装置及び表示装置

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