WO2020156300A1 - 阵列基板及其制作方法、驱动方法以及触控显示装置 - Google Patents

阵列基板及其制作方法、驱动方法以及触控显示装置 Download PDF

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Publication number
WO2020156300A1
WO2020156300A1 PCT/CN2020/073108 CN2020073108W WO2020156300A1 WO 2020156300 A1 WO2020156300 A1 WO 2020156300A1 CN 2020073108 W CN2020073108 W CN 2020073108W WO 2020156300 A1 WO2020156300 A1 WO 2020156300A1
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Prior art keywords
touch
electrode
thin film
film transistor
line
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PCT/CN2020/073108
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English (en)
French (fr)
Inventor
木素真
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/254,319 priority Critical patent/US11366557B2/en
Publication of WO2020156300A1 publication Critical patent/WO2020156300A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, a driving method, and a touch display device.
  • the embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a driving method, and a touch display device.
  • an embodiment of the present disclosure provides an array substrate including a plurality of data lines, a plurality of touch lines, a plurality of touch electrodes, and a plurality of first switching devices.
  • Each of the touch electrodes is electrically connected to at least one of the touch wires
  • each of the first switching devices is electrically connected to one of the data wires and one of the touch electrodes
  • each of the first switches The device is configured to selectively conduct or disconnect the connected data line and the touch electrode.
  • the first switching device includes: a first thin film transistor, a first electrode of the first thin film transistor is electrically connected to the corresponding data line, and a second electrode of the first thin film transistor is electrically connected to the corresponding data line.
  • the corresponding touch electrodes are electrically connected.
  • the first switching device includes: a second thin film transistor, the first electrode of the second thin film transistor is electrically connected to the corresponding data line, and the second electrode of the thin film transistor is electrically connected to the corresponding data line.
  • One of the touch wires connected to the touch electrodes is electrically connected.
  • the array substrate further includes a plurality of second switch devices, each of the touch wires is electrically connected to the corresponding touch electrode through one of the second switch devices, and each The second switch device is configured to selectively conduct or disconnect the connected touch wire and the touch electrode.
  • the second switching device includes: a third thin film transistor, a first electrode of the third thin film transistor is electrically connected to one touch wire, and a second electrode of the third thin film transistor is electrically connected to one The touch electrode.
  • the touch wire and the touch electrode are located on different layers, and the touch wire is connected to the corresponding touch electrode through a via; or, the touch wire is connected to the touch electrode.
  • the touch electrodes are in the same layer, and the touch wires are directly connected to the corresponding touch electrodes.
  • each touch electrode has at least two signal input points on the touch electrode, and the at least two signal input points include a point electrically connected to the data line and a point connected to the touch control electrode. At least one of the points of electrical connection of the wire.
  • the array substrate further includes a plurality of gate lines, the plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions, and each sub-pixel region includes a switching thin film transistor and a first electrode
  • the first electrode of the switching thin film transistor is electrically connected to the data line
  • the second electrode of the switching thin film transistor is electrically connected to the first electrode
  • the switching thin film transistor is electrically connected to the first electrode.
  • the control electrode of the transistor is electrically connected to the gate line
  • the first electrode is a pixel electrode
  • the first electrode is an electrode of an organic light emitting diode.
  • the switch thin film transistor, the touch electrode and the first electrode are arranged in sequence in a direction away from the array substrate, the touch electrode has an opening, and the second electrode of the switch thin film transistor passes The via hole located in the opening is connected to the first electrode.
  • the array substrate further includes a plurality of control lines connected to the first switching device, and the control lines and the gate lines extend in the same direction.
  • control line and the gate line are arranged in the same layer.
  • the array substrate further includes a plurality of second control lines connected to the plurality of second switching devices, the plurality of gate lines and the plurality of data lines intersect, and the second control lines are The extension directions of the gate lines are the same.
  • the touch line and the data line are located on different layers, and the projection of the touch on the base substrate and the projection of the data on the base substrate satisfy any one of the following relationships Species:
  • the projection of the touch line on the base substrate is within the projection of the corresponding data line on the base substrate;
  • the projection of the data line on the base substrate is within the projection of the corresponding touch line on the base substrate.
  • the plurality of touch electrodes are arranged in a matrix, and the orthographic projection of each of the touch electrodes on the array substrate covers a plurality of sub-pixel regions.
  • an embodiment of the present disclosure also provides an array substrate, including: a base substrate and a first conductive pattern layer, a gate insulating layer, and a second conductive pattern layer on the base substrate in order in a direction away from the base substrate.
  • the first conductive pattern layer includes multiple gate lines, multiple first control lines, multiple control electrodes of the first thin film transistors, multiple control electrodes of the switching thin film transistors, and extension directions of the multiple first control lines Same as the extension direction of the plurality of gate lines, the control electrode of the first thin film transistor is electrically connected to the first control line, and the control electrode of the plurality of switching thin film transistors is electrically connected to the gate line;
  • the first semiconductor pattern layer includes active layers of the plurality of first thin film transistors and active layers of the plurality of switching thin film transistors;
  • the second conductive pattern layer includes a plurality of data lines, first electrodes and second electrodes of the plurality of first thin film transistors, first electrodes and second electrodes of the plurality of switching thin film transistors, the first The first pole of the thin film transistor and the first pole of the switch thin film transistor are respectively electrically connected to the corresponding data line;
  • the touch electrode layer includes a plurality of touch electrodes arranged in a matrix, and each of the touch electrodes is electrically connected to a second electrode of at least one of the first thin film transistors;
  • the third conductive pattern layer includes a plurality of touch wires, the extending direction of the plurality of touch wires is the same as the extending direction of the data wire, and each of the touch electrodes is connected to at least one of the touch wires Electrical connection
  • the first electrode layer includes a plurality of first electrodes, and the first electrodes are pixel electrodes or electrodes of organic light emitting diodes;
  • each sub-pixel region has one switch thin film transistor and one first electrode, and each switch thin film transistor The second electrode is electrically connected to the corresponding first electrode.
  • the first conductive pattern layer further includes a plurality of second control lines and a plurality of control electrodes of second thin film transistors, the second control lines and the gate lines extend in the same direction, and the second The control electrode of the thin film transistor is electrically connected to the corresponding second control line;
  • the third conductive pattern layer further includes first and second electrodes of the plurality of second thin film transistors, and the first electrode of the first electrode of each second thin film transistor corresponds to the touch line Electrically connected, the second electrode of each second thin film transistor is electrically connected to the corresponding touch electrode;
  • the array substrate further includes a second semiconductor pattern layer, and the second semiconductor pattern layer includes an active layer of the plurality of second thin film transistors.
  • an embodiment of the present disclosure also provides a touch display device, which includes the aforementioned array substrate.
  • an embodiment of the present disclosure also provides a driving method of an array substrate, and the driving method includes:
  • the switch device In the touch phase, the switch device is controlled so that the electrical connection between the data line and the touch electrode is conducted, and the data line and the touch line simultaneously provide touch for the touch electrode Control signal.
  • the driving method further includes: in the display phase, providing a common voltage signal to the touch electrode through the touch line.
  • the embodiments of the present disclosure also provide a method for manufacturing an array substrate, including: providing a base substrate; forming multiple data lines, multiple touch lines, and multiple touch controls on the base substrate. Electrodes and a plurality of first switching devices. Each of the touch electrodes is electrically connected to at least one of the touch wires, each of the first switching devices is electrically connected to one of the data lines and one of the touch electrodes, and each of the first switching devices is electrically connected to A switch device is configured to selectively conduct or disconnect the connected data line and the touch electrode.
  • FIG. 1 is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a partial top view structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a partial enlarged schematic diagram of the array substrate shown in FIG. 2;
  • FIG. 4 is a schematic cross-sectional structure diagram along line a-a in FIG. 3 of the array substrate provided by an embodiment of the present disclosure
  • FIG. 5 is another partial enlarged schematic diagram of the array substrate shown in FIG. 2;
  • FIG. 6 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the present disclosure along line b-b in FIG. 5;
  • FIG. 7 is another schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional structure diagram of the array substrate provided by an embodiment of the present disclosure along the line c-c in FIG. 3;
  • FIG. 9 is a schematic diagram of a first conductive pattern layer of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a first semiconductor pattern layer of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a second conductive pattern layer of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of touch electrodes of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a third conductive pattern layer of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the disclosure at a third thin film transistor;
  • FIG. 15 is a flowchart of a driving method of a touch display device provided by an embodiment of the present disclosure.
  • FIG. 16 is a timing diagram of a touch display device provided by an embodiment of the present disclosure.
  • FIG. 17 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 18 is a flowchart of another manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • In-Cell touch solutions mainly include self-capacitance touch and mutual-capacitance touch.
  • the touch display panel usually multiplexes the common electrode and the touch electrode.
  • the touch display panel includes a plurality of touch electrodes distributed in a matrix, and each touch electrode is connected to a touch wire.
  • the touch wires provide common voltage signals to the touch electrodes, and the touch electrodes are the common electrodes at this time; in the touch phase, the touch wires provide touch signals to the touch electrodes and feedback detection to the touch chip signal.
  • the width of the touch line needs to be wider to reduce the resistance of the touch line, thereby reducing the voltage drop (IR drop) phenomenon, that is, the phenomenon that the near-end voltage is greater than the far-end voltage.
  • IR drop voltage drop
  • FIG. 1 is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate includes a plurality of data lines D (for example, D1 to D15 in FIG. 1), a plurality of touch lines M (for example, M1 to M5 in FIG. 1), and a plurality of touch electrodes S (each The dashed frame represents a touch electrode S).
  • Each touch electrode S is electrically connected to at least one touch wire M, and each touch electrode S is connected to a different touch wire M.
  • the array substrate also includes a plurality of first switching devices (not shown in FIG. 1). Each first switching device is electrically connected to a data line D and a touch electrode S, and each first switching device is configured to selectively conduct or disconnect the connected data line D and the touch electrode S open.
  • the first component and the second component are electrically connected, which means that electrical signals can be transmitted between the first component and the second component.
  • the touch electrode S is electrically connected to the touch wire M. It means that electrical signals can be transmitted between the touch electrode S and the touch wire M.
  • the electrical connection methods include, but are not limited to, direct connection, connection through vias, connection through other conductive components, and so on.
  • Selectively conducting or disconnecting the data line D and the touch electrode S refers to conducting or disconnecting the electrical connection between the data line D and the touch electrode S under the control of a control signal.
  • the array substrate may further include a plurality of first control lines C1, each first switching device is connected to one first control line C1, and one first control line C1 may be connected to a plurality of first switching devices.
  • the first control line C1 is used to provide a control signal for the connected first switching device.
  • the first switch device can be controlled to electrically connect the data line and the touch electrode during the touch phase, and the data line is connected to the touch electrode.
  • the touch wires are electrically connected to the touch electrodes, so the touch wires can also provide touch signals to the touch electrodes at the same time, so as to realize the parallel connection of the data wires and the touch wires without widening the touch wires.
  • the resistance of the touch line is reduced, so that the resistance of the touch line can be reduced without sacrificing the aperture ratio of the product, which is beneficial to increase the aperture ratio of the product.
  • the first switching device is controlled to disconnect the electrical connection between the data line and the touch electrode, and a common voltage signal is provided to the touch electrode through the touch line.
  • the touch electrode can be reused as a common
  • the electrodes provide data voltages for each sub-pixel through the data lines to achieve normal display functions.
  • the embodiments of the present disclosure integrate the touch electrodes on the array substrate, which is beneficial to the lightness and thinness of the touch display device.
  • the touch chip and the display chip can be integrated into a single chip to realize TDDI (Touch and Display Driver Integration).
  • the array substrate adopts a single-layer self-capacitive touch structure.
  • the multiple touch electrodes S are arranged in a matrix. It should be noted that the number of touch electrodes in FIG. 1 is only an example, and the number of touch electrodes on the array substrate can be set according to actual needs.
  • the touch wires M may be arranged in the same layer as the touch electrodes S, or may be arranged in different layers.
  • the same layer may mean that it is located on the same side of the same layer, or is formed by the same patterning process, or is close to the surface of the base substrate in contact with the same layer.
  • different layers may refer to being located on different sides of the same layer, or formed by different patterning processes, or close to the surface of the base substrate in contact with different layers, etc.
  • the touch wire M and the touch electrode S may be directly connected, or may be connected through a via hole, or the touch wire M and the touch electrode S may also be connected through a second switch device.
  • the second switching device may be a thin film transistor, the first electrode of the thin film transistor is connected to the touch line, the second electrode is connected to the touch electrode, and the control electrode is connected to the second control line C2.
  • the second control line C2 is used to provide control signals for the connected thin film transistors.
  • each touch electrode S is electrically connected to at least one data line D through a first switching device, and the number of data lines D electrically connected to each touch electrode S is equal to ensure that each The voltages of the touch electrodes are equal.
  • each touch electrode S is connected to one data line D, or each touch electrode S is connected to two data lines D.
  • the projections of the electrically connected data line D and the touch electrode S on the base substrate overlap to facilitate wiring.
  • the array substrate may further include multiple gate lines SG (for example, SG1 to SG8 in FIG. 1) and multiple switching thin film transistors (not shown in FIG. 1), multiple data lines D and multiple gate lines SG The intersection defines a plurality of sub-pixel regions.
  • Each sub-pixel area has a switching thin film transistor, the switching thin film transistor is located at the intersection of the gate line SG and the data line D, and each switching thin film transistor is used to control the corresponding sub-pixel area to emit light.
  • the control electrode of the switching thin film transistor is connected to the corresponding gate line
  • the first electrode of the switching thin film transistor is connected to the corresponding data line
  • the second electrode of the switching thin film transistor is connected to the corresponding first electrode.
  • the control electrode of the switching thin film transistor may be a gate
  • the first electrode may be one of the source and the drain
  • the second electrode may be the other of the source and the drain.
  • the first electrode is a pixel electrode
  • the first electrode is an electrode of an organic light emitting diode, such as a cathode or an anode.
  • the extension direction of the first control line C1 may be the same as the extension direction of the gate line SG, and the extension direction of the touch line M and the extension direction of the data line D are the same. Since the display resolution is generally greater than the touch resolution, the number of data lines D is greater than the number of touch lines M. Therefore, in the embodiment of the present disclosure, only part of the data lines D are connected to the first switching device SW1.
  • the data line connected to the first switching device may be referred to as the first data line, and data lines other than the first data line (ie, the data line not connected to the first switching device) may be referred to as It is the second data line.
  • the first switching device may be located at the intersection of the first control line and the first data line.
  • the first switching device can electrically connect the data line and the touch electrode in two ways, one is direct connection, that is, the first switching device is connected to the data line and the touch electrode respectively , Refer to the embodiment shown in Figures 2 to 8; the other is indirect connection, that is, the first switch device connects the touch line with the corresponding data line, so that the data line and the touch line are connected through the first switch device and the touch line.
  • direct connection that is, the first switching device is connected to the data line and the touch electrode respectively
  • the other is indirect connection, that is, the first switch device connects the touch line with the corresponding data line, so that the data line and the touch line are connected through the first switch device and the touch line.
  • the control electrode For electrical connection of the control electrode, refer to the embodiment shown in FIG. 14.
  • liquid crystal display device will be taken as an example to describe in detail the structure of the array substrate provided by the embodiment of the present disclosure.
  • the array substrate includes multiple data lines D, multiple touch lines M, multiple touch electrodes S (only one is shown in the figure), and multiple first switching devices SW1 (see Figure 3 ).
  • Each touch electrode S is connected to at least one touch wire M, and each touch electrode S is connected to a different touch wire M.
  • each first switching device SW1 is correspondingly connected to a data line D and a touch electrode S, that is, the first switching device SW1 is directly connected to the data line D and the touch electrode.
  • FIG. 3 is a partial enlarged schematic diagram of the array substrate shown in FIG. 2.
  • the first switching device SW1 includes a first thin film transistor Q1, a first electrode Q11 of the first thin film transistor Q1 is electrically connected to a corresponding data line D, and a second electrode Q12 of the first thin film transistor Q1 is connected to a contact
  • the control electrode S is connected.
  • the control electrode Q13 of the first thin film transistor Q1 is electrically connected to the first control line C1.
  • the first control line C1 is used to provide a control signal to control the on and off of the first thin film transistor Q1, and thereby control the on or off of the electrical connection between the data line D and the touch electrode S.
  • the first electrode Q11 of the first thin film transistor Q1 may be one of the source and drain
  • the second electrode Q12 of the first thin film transistor Q1 is the other of the source and drain
  • the gate Q13 is a gate.
  • the first electrode Q11 of the first thin film transistor Q1 is electrically connected to the corresponding data line D, and one of the following two ways can be adopted: the first electrode Q11 of the first thin film transistor Q1 is connected to the corresponding data line D Or, the first electrode Q11 of the first thin film transistor Q1 is a part of the corresponding data line D.
  • the electrical connections between other electrodes and corresponding wires are the same, and will not be described again.
  • the first thin film transistor Q1 In the display phase, the first thin film transistor Q1 is turned off, the data signal is provided through the data line D, and the common voltage signal is provided to the touch electrode S through the touch line M; in the touch phase, the first thin film transistor Q1 is turned on, and the data The line D and the touch line M provide touch signals to the touch electrodes S at the same time, thereby realizing the time division multiplexing of the data lines.
  • FIG. 4 is a schematic cross-sectional structure view of the array substrate along the line a-a in FIG. 3 provided by an embodiment of the present disclosure, which is used to show the cross-sectional structure of the first switching device (ie, the first thin film transistor Q1).
  • the first switching device ie, the first thin film transistor Q1
  • the touch electrode S and the touch line M are arranged in sequence, and the second electrode Q12 of the first thin film transistor Q1 and one touch electrode S connection.
  • the array substrate includes a base substrate 200, and a first conductive pattern layer 201, a gate insulating layer 202, and a gate insulating layer 202 that are sequentially arranged in a direction away from the base substrate 200.
  • the third electrode Q13 of the first thin film transistor Q1 is located on the first conductive pattern layer 201.
  • the active layer Q14 of the first thin film transistor Q1 is located on the first semiconductor pattern layer 203.
  • the first electrode Q11 and the second electrode Q12 of the first thin film transistor Q1 are located on the second conductive pattern layer 204.
  • the touch electrode S is located on the touch electrode layer 206.
  • the second electrode Q12 of the first thin film transistor Q1 is connected to a touch electrode S through a first via H1.
  • the first via hole H1 is located in the first insulating layer 205.
  • the touch wires and the touch electrodes may be indirectly connected through a second switching device (such as a thin film transistor), and each touch electrode is connected to each other through a second switching device.
  • the corresponding touch wire is electrically connected, and the second switch device is configured to selectively turn on or disconnect the connected touch wire and the touch electrode.
  • the touch wire and the touch electrode are indirectly connected through the second switching device SW2 (see FIG. 5) (for example, the second thin film transistor Q2), and the second thin film transistor Q2 is configured to be selective
  • the ground conducts or breaks the electrical connection between the touch electrode S and the touch wire M.
  • FIG. 5 is a partial enlarged schematic diagram of the array substrate shown in FIG. 2.
  • the first electrode Q21 of the second thin film transistor Q2 is connected to the corresponding touch electrode S, and the second electrode Q22 of the second thin film transistor Q2 is electrically connected to a touch wire M.
  • the control electrode Q23 of the second thin film transistor Q2 is electrically connected to the second control line C2.
  • the second control line C2 is used to provide a control signal to control the on and off of the second thin film transistor Q2, and then to control the on or off of the touch line M and the touch electrode S.
  • the first electrode Q21 of the second thin film transistor Q2 may be one of the source and drain
  • the second electrode Q22 of the second thin film transistor Q2 is the other of the source and drain
  • the gate Q23 is a gate.
  • the second thin film transistor Q2 is turned on so as to provide a common voltage signal to the touch electrodes through the touch wires in the display phase, and provide touch electrodes to the touch electrodes through the touch wires in the touch phase. Control signal.
  • FIG. 6 is a schematic diagram of a cross-sectional structure of the array substrate provided by an embodiment of the present disclosure along the line b-b in FIG. 5, for showing the cross-sectional structure of the second thin film transistor Q2.
  • the control electrode Q23 of the second thin film transistor Q2 is located on the first conductive pattern layer 201.
  • the data line D is located on the second conductive pattern layer 204.
  • the active layer Q24 of the second thin film transistor Q2 is located on the second semiconductor pattern layer 208.
  • the first electrode Q21 and the second electrode Q22 of the second thin film transistor Q2 are located on the third conductive pattern layer 209.
  • the second electrode Q22 of the second thin film transistor Q2 and the touch electrode S are connected through the second via H2.
  • the second via hole H2 is located in the second insulating layer 207.
  • the touch wire and the touch electrode when the touch wire and the touch electrode are arranged in different layers, the touch wire and the touch electrode can be connected through a via hole, and the touch signal input to each touch wire can be controlled by The timing is to input touch signals to the corresponding touch electrodes.
  • the touch wire M is connected to the touch electrode S through a via H2'.
  • the array substrate can remove the layer dedicated to the structure of the second thin film transistor Q2, such as the second semiconductor pattern layer 208.
  • the touch wire and the touch electrode may also be arranged in the same layer.
  • the touch wire and the touch electrode may be directly connected.
  • each touch electrode S is arranged in a matrix.
  • each touch electrode S may be rectangular, for example, it may be a square with a length and a width of 4 mm.
  • Each touch electrode can cover multiple sub-pixel areas.
  • the number of sub-pixel regions corresponding to a single touch electrode can be determined by the resolution of the display device. For a fixed-size display device, the higher the resolution, the smaller the area of each pixel area, and the greater the number of sub-pixel areas corresponding to a touch electrode; conversely, the lower the resolution, the larger the area of each pixel area , The smaller the number of sub-pixel regions corresponding to one touch electrode.
  • the shape and size of the touch electrode can be set according to actual needs.
  • each touch electrode has at least two signal input points on the touch electrode, and the signal input point on each touch electrode includes an electrical connection point with the data line and an electrical connection point with the touch line At least one of the points.
  • Each touch electrode receives the touch signal through at least two signal input points, which is beneficial to improve the uniformity of the voltage on the touch electrode.
  • each touch electrode S includes two electrical connection points with the data line D (respectively corresponding to the two first via holes H1) and two contact lines M The electrical connection points (respectively corresponding to the two second via holes H2).
  • Two points electrically connected to the data line D are arranged at intervals along the extension direction of the first control line C1
  • two points electrically connected to the touch line M are arranged at intervals along the extension direction of the second control line C2.
  • the number and positions of signal input points on the touch electrode can be set according to actual needs. In the embodiments of the present disclosure, the number and positions of signal input points on each touch electrode are the same.
  • the array substrate further includes a plurality of gate lines SG, the plurality of data lines D extend in a first direction, and the plurality of gate lines SG extend in a second direction, the first direction and the second direction intersect, for example, perpendicular.
  • the extension direction of the gate line SG is the same as the extension direction of the first control line C1. That is, the first control line C1 is arranged in parallel with the gate line SG.
  • the first control line C1 extends along the extension direction of the gate line SG, which can avoid occupying The space between adjacent sub-pixel regions in the extending direction of the gate line facilitates wiring.
  • the first control line C1 and the gate line SG are arranged in the same layer. Since the control line and the gate line are arranged in the same layer, they can be made by a patterning process with the gate line, simplifying the manufacturing process.
  • the extension direction of the second control line C2 and the gate line SG are the same.
  • the second control line C2 and the first control line C1 may also be arranged in the same layer.
  • the plurality of gate lines SG and the plurality of data lines D define a plurality of sub-pixel regions, and each sub-pixel region includes a switching thin film transistor Q3 and a pixel electrode P. 3 and 5, in each sub-pixel area, the first electrode Q31 of the switching thin film transistor Q3 is electrically connected to the data line D, the second electrode Q32 of the switching thin film transistor Q3 is electrically connected to the pixel electrode P, and the switching thin film transistor Q3
  • the gate electrode Q33 is electrically connected to the gate line SG.
  • the first electrode Q31 of the switching thin film transistor Q3 can be one of the source and drain
  • the second electrode Q32 of the switching thin film transistor Q3 is the other of the source and the drain
  • the control electrode Q33 of the switching thin film transistor Q3 For the grid.
  • FIG. 8 is a schematic cross-sectional structure diagram of the array substrate provided by an embodiment of the present disclosure along the line c-c in FIG. 3, which is used to show the cross-sectional structure of the switching thin film transistor Q3.
  • the control electrode Q33 of the switching thin film transistor Q3 is located on the first conductive pattern layer 201.
  • the active layer Q34 of the switching thin film transistor Q3 is located on the first semiconductor pattern layer 203.
  • the first electrode Q31 and the second electrode Q32 of the switching thin film transistor Q3 are located on the second conductive pattern layer 204.
  • the pixel electrode P is located on the first electrode layer 211 (may also be referred to as a pixel electrode layer).
  • the touch electrode S and the pixel electrode P are arranged in sequence, that is, the touch electrode layer 206 is located between the pixel electrode layer 211 and the base substrate 200.
  • the switching thin film transistor Q3 is located between the touch electrode S and the pixel electrode P. Since the second electrode Q32 of the switching thin film transistor Q3 needs to be connected to the pixel electrode P, the touch electrode S has a plurality of openings S0, and the openings S0 and The sub-pixel regions are arranged in a one-to-one correspondence.
  • the pixel electrode P and the switching thin film transistor Q3 in each sub-pixel region are connected through a third via H3, and each third via H1 is located in the opening S0 of the corresponding sub-pixel region. As shown in FIG. 8, the third via hole H3 penetrates the first insulating layer 205 and the second insulating layer 207.
  • FIG. 9 is a schematic structural diagram of a first conductive pattern layer provided by an embodiment of the present disclosure.
  • the first conductive pattern layer includes the aforementioned gate line SG, the first control line C1, the second control line C2, the control electrode Q13 of the first thin film transistor Q1, the control electrode Q23 of the second thin film transistor Q2, and the switch.
  • the gate insulating layer 201 covers the first conductive pattern layer.
  • FIG. 10 is a schematic diagram of the structure of a first semiconductor pattern layer provided by an embodiment of the present disclosure. As shown in FIG. 10, the first semiconductor pattern layer includes the active layer Q14 of the first thin film transistor Q1 and the active layer Q34 of the switching thin film transistor Q3.
  • FIG. 11 is a schematic structural diagram of a second conductive pattern layer provided by an embodiment of the present disclosure.
  • the second conductive pattern layer includes a data line D, a first electrode Q11 and a second electrode Q12 of the first thin film transistor Q1, and a first electrode Q31 and a second electrode Q32 of the switching thin film transistor Q3.
  • the first insulating layer 202 covers the second conductive pattern layer.
  • the touch electrode layer 203 includes a plurality of touch electrodes S arranged in an array.
  • the second insulating layer 204 covers the touch electrode layer 203.
  • the second semiconductor pattern layer includes the active layer Q24 of the second thin film transistor Q2.
  • FIG. 12 is a schematic structural diagram of a touch electrode layer provided by an embodiment of the present disclosure. As shown in FIG. 12, the touch electrode S has a plurality of openings S0. Each opening S0 corresponds to a sub-pixel area.
  • FIG. 13 is a schematic structural diagram of a third conductive pattern layer provided by an embodiment of the present disclosure.
  • the third conductive pattern layer includes the touch line M and the first electrode Q21 and the second electrode Q22 of the second thin film transistor Q2.
  • the third insulating layer 205 covers the third conductive pattern layer.
  • the order between the layers can be adjusted.
  • the pixel electrode and the touch electrode are arranged in sequence, that is, the layer where the pixel electrode is located is located on the layer where the touch electrode is located. Between and the base substrate.
  • the position of the via hole needs to be adjusted to realize the electrical connection relationship shown in FIG. 2.
  • the base substrate is a transparent substrate, which may be made of materials such as glass and plastic.
  • the gate lines, data lines and control lines are all made of conductors, such as metal materials.
  • the metal material may be a single metal material, such as Al, Cu, Mu, etc., or an alloy material, such as an alloy of at least two of Al, Cu, and Mu.
  • the materials used for the gate lines, data lines and control lines can be the same or different.
  • the touch electrodes are made of transparent conductive materials, such as ITO, IZO, etc., to avoid affecting the display function of the display device.
  • the pixel electrodes are also made of transparent conductive materials, such as ITO, IZO, etc.
  • the active layer can be made of InGaZnO, InGaO, ITZO, AlZnO and other materials.
  • the gate insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer can all be made of silicon nitride, silicon dioxide, and other materials.
  • the thin film transistors with bottom gate structure are all described as examples. In other embodiments, the thin film transistors may also adopt top gate structure or double gate structure. Thin film transistors are not limited in this disclosure. That is to say, in other embodiments, the hierarchical relationship in FIGS. 4 and 6 to 8 can be changed, new layers can be added, and the relative positions between layers can be adjusted.
  • the touch line M and the data line D are located in different layers, and the projection of the touch line M on the base substrate is within the projection of the corresponding data line D on the base substrate, or , The projection of the data line D on the base substrate is within the projection of the corresponding touch line M on the base substrate.
  • the projection of the data line D on the base substrate and the projection of the corresponding touch line M on the base substrate may completely overlap.
  • This arrangement can further reduce the pixel area occupied by the data line and the touch line, increase the aperture ratio, and thereby increase the overall transmittance of the product.
  • the second switch device when the data line and the touch electrode are indirectly connected through the second switch device and the touch line, the second switch device is correspondingly connected to a touch line and a data line.
  • the second switching device includes a third thin film transistor, the third thin film transistor is correspondingly connected to a data line and a touch line, and each touch line is connected to a data line through a third thin film transistor .
  • the control electrode of the third thin film transistor is connected to a control line, and the control line is used to provide a control signal to control the on and off of the third thin film transistor, thereby controlling the connection or disconnection between the data line and the touch line.
  • controlling the connection or disconnection between the data wire and the touch wire can control the conduction or disconnection of the electrical connection between the data wire and the touch electrode.
  • the first electrode of the third thin film transistor may be one of the source and the drain
  • the second electrode of the third thin film transistor is the other of the source and the drain
  • the control electrode of the third thin film transistor is the gate
  • the third thin film transistor is turned off, the data line provides a data signal, and the touch line provides a common voltage signal to the touch electrode.
  • the third thin film transistor is turned on, the data line and the touch line are electrically connected, and then the touch signal is provided to the touch electrode through the data line and the touch line at the same time.
  • the structure of the array substrate of this embodiment is similar to the structure of the array substrate shown in FIG. 2 except that the first thin film transistor in FIG. 2 is removed, and the touch line and the data line are added.
  • the third thin film transistor which may be added at A in FIG. 2, for example.
  • FIG. 2 please refer to the related description of FIG. 2, which will not be repeated here.
  • FIG. 14 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the disclosure at a third thin film transistor.
  • the array substrate includes a base substrate 200, and a first conductive pattern layer 201, a gate insulating layer 202, a first semiconductor pattern layer 203, and a second conductive pattern layer 201, a gate insulating layer 202, a first semiconductor pattern layer 203, and a second conductive pattern layer 201 sequentially arranged in a direction away from the base substrate 200
  • the control electrode Q43 of the third thin film transistor Q4 is located on the first conductive pattern layer 201.
  • the active layer Q44 of the third thin film transistor Q4 is located on the first semiconductor pattern layer 203.
  • the first electrode Q41 and the second electrode Q42 of the third thin film transistor Q4 are located on the second conductive pattern layer 204.
  • the touch electrode S is located on the touch electrode layer 206.
  • the touch wire M is located on the third conductive pattern layer 209.
  • the second electrode Q42 of the third thin film transistor Q4 is connected to the touch line M through the fourth via H4.
  • the fourth via hole H4 is located in the first insulating layer 205 and the second insulating layer 207.
  • the touch electrode S has a corresponding opening S1, and the fourth via hole H4 passes through the opening S1.
  • the first conductive pattern layer 201 includes the aforementioned gate line SG, the first control line C1, the second control line C2, the control electrode Q43 of the third thin film transistor Q4, the control electrode Q23 of the second thin film transistor Q2, and the switch.
  • the gate insulating layer 202 covers the first conductive pattern layer 201.
  • the first semiconductor pattern layer 203 includes the active layer Q44 of the third thin film transistor Q4 and the active layer Q34 of the switching thin film transistor Q3.
  • the second conductive pattern layer 204 includes the data line D, the first electrode Q41 and the second electrode Q42 of the third thin film transistor Q4, and the first electrode Q31 and the second electrode Q32 of the switching thin film transistor Q3.
  • the first insulating layer 205 covers the second conductive pattern layer 204.
  • the touch electrode layer 206 includes a plurality of touch electrodes S arranged in an array.
  • the second insulating layer 207 covers the touch electrode layer 206.
  • the second semiconductor pattern layer 208 includes the active layer Q24 of the second thin film transistor Q2.
  • the third conductive pattern layer 209 includes the touch line M, the first electrode Q21 and the second electrode Q22 of the second thin film transistor Q2.
  • the third insulating layer 210 covers the third conductive pattern layer 209.
  • the first electrode layer 211 includes a plurality of pixel electrodes P, and each pixel electrode P is located in a sub-pixel area.
  • the first switching device and the second switching device are thin film transistors as an example for description. In other embodiments, the first switching device and the second switching device can also be field-effected. Tubes, etc., as long as they can achieve switching under the control of the control signal.
  • the embodiments of the present disclosure also provide a touch display device, which includes any of the aforementioned array substrates.
  • the touch display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
  • the embodiment of the present disclosure also provides a driving method of a touch display device, which is suitable for driving the aforementioned touch display device.
  • the driving method includes:
  • step 1501 in the display phase, the first switching device is controlled to disconnect the electrical connection between the corresponding data line and the touch electrode, and the data signal is provided through the data line.
  • the step S1501 includes: in the display stage, providing data signals to the pixel electrodes through the data lines.
  • this step 1501 includes: in the display stage, providing a data signal to the electrode (cathode or anode) of the OLED through the data line.
  • this step 1501 may further include: in the display stage, providing a common voltage signal to the touch electrodes through the touch wires. Therefore, the touch electrodes can be multiplexed as common electrodes to simplify the structure of the display device.
  • step 1502 in the touch phase, the first switch device is controlled to make the electrical connection between the corresponding data line and the touch electrode conductive, and simultaneously provide touch signals for the touch electrode through the data line and the touch line.
  • the common voltage signal may be a level signal
  • the touch signal may be a high-frequency pulse signal.
  • the display phase and the touch phase alternate periodically.
  • the first period is the display phase
  • the latter period is the touch phase.
  • the touch display device may be driven by the timing signal in FIG. 16.
  • each gate line SG1 to SGn sequentially inputs scanning signals to perform progressive scanning;
  • the control signal on the second control line C2 is high level VGH, the second thin film transistor is turned on, and the touch The wire is electrically connected to the corresponding touch electrode, and provides a common voltage signal to the touch electrode through the touch wire;
  • the control signal on the first control line C1 is a low level VGL, so that the first thin film transistor is disconnected, and the data line is The electrical connection between the touch electrodes is broken.
  • the scan signals on the gate lines SG1 to SGn are all low, the switching thin film transistor is off; the control signal on the second control line C2 is high VGH, the second thin film transistor is turned on, and the touch
  • the control line is electrically connected to the corresponding touch electrode, and provides a touch signal to the touch electrode through the touch line; the control signal on the first control line C1 becomes a high level VGH, so that the first thin film transistor is turned on, and then
  • the electrical connection between the data line and the touch electrode is realized through the first thin film transistor and the control line, and the data line and the touch line provide touch signals for the touch electrode at the same time.
  • FIG. 17 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the disclosure. As shown in Figure 17, the manufacturing method includes:
  • step 1701 a base substrate is provided.
  • step 1702 multiple data lines, multiple touch wires, multiple touch electrodes, and multiple first switching devices are formed on the base substrate.
  • each touch electrode is connected to at least one touch wire
  • each first switch device is electrically connected to a data line and one touch electrode
  • each first switch device is configured to selectively switch The connected data line is connected to or disconnected from the touch electrode.
  • FIG. 18 is a flowchart of another manufacturing method of an array substrate provided by an embodiment of the present disclosure. This method is used to fabricate the array substrate as shown in FIG. 2. As shown in Figure 18, the method includes:
  • step 1801 a base substrate is provided.
  • the base substrate may be a transparent substrate, and may be made of materials such as glass or plastic.
  • step 1802 a first conductive pattern layer is formed on the base substrate.
  • FIG. 9 is a schematic diagram of the first conductive pattern layer.
  • the first conductive pattern layer may include a gate line SG, a first control line C1 and a second control line C2, a control electrode Q13 of the first thin film transistor Q1, a control electrode Q23 of the second thin film transistor Q2, and a switch The control electrode Q33 of the thin film transistor Q3.
  • a first conductive material layer may be formed on a base substrate, and then the first conductive material layer is processed through a patterning process to obtain the first conductive pattern layer.
  • the first conductive material layer may be a metal thin film, and the first conductive material layer may be formed by sputtering or the like.
  • step 1803 a gate insulating layer is formed on the first conductive pattern layer.
  • the gate insulating layer covers the first conductive pattern layer.
  • the gate insulating layer may be formed by vapor deposition.
  • the gate insulating layer can be made of insulating materials such as silicon nitride and silicon oxide.
  • step 1804 a first semiconductor pattern layer is formed on the gate insulating layer.
  • a semiconductor material film may be formed on the gate insulating layer first.
  • a deposition method can be used to form a thin film of semiconductor material on the gate insulating layer.
  • the semiconductor material film may be at least one of InGaZnO, InGaO, ITZO, and AlZnO. Then, the semiconductor material film is patterned through a patterning process to obtain the first semiconductor pattern layer.
  • FIG. 10 is a schematic diagram of the first semiconductor pattern layer. As shown in FIG. 10, the first semiconductor pattern layer includes the active layer Q14 of the first thin film transistor Q1 and the active layer Q34 of the switching thin film transistor Q3.
  • step 1805 a second conductive pattern layer is formed on the first semiconductor pattern layer.
  • a second conductive material layer is formed on the base substrate on which the first semiconductor pattern layer is formed, and then the second conductive material layer is processed through a patterning process to obtain the second conductive pattern layer.
  • the second conductive material layer may be a metal thin film, and the second conductive material layer may be formed by sputtering or the like.
  • FIG. 11 is a schematic diagram of the second conductive pattern layer.
  • the second conductive pattern layer includes a data line D, a first electrode Q11 and a second electrode Q12 of the first thin film transistor Q1, and a first electrode Q31 and a second electrode Q32 of the switching thin film transistor Q3.
  • step 1806 a first insulating layer is formed on the second conductive pattern layer.
  • the first insulating layer covers the second conductive pattern layer.
  • the first insulating layer may be formed by vapor deposition.
  • the first insulating layer can be made of insulating materials such as silicon nitride and silicon oxide.
  • the method further includes: opening a first via hole in the first insulating layer at a position corresponding to the second electrode of the second thin film transistor.
  • a touch electrode layer is formed on the first insulating layer.
  • the touch electrode layer includes a plurality of touch electrodes arranged in a matrix.
  • FIG. 12 is a schematic diagram of the touch electrodes. As shown in FIG. 12, the touch electrode S has a plurality of openings S0.
  • a transparent conductive material layer may be formed on the first insulating layer, and then the transparent conductive material layer may be processed through a patterning process to obtain the touch electrode layer.
  • the transparent conductive material layer can be formed by deposition.
  • the transparent conductive material layer may be an ITO, IZO layer, or the like.
  • step 1808 a second insulating layer is formed on the touch electrode layer.
  • the second insulating layer may be formed in the same manner as the first insulating layer, and detailed description is omitted here.
  • step 1809 a second semiconductor pattern layer is formed on the second insulating layer.
  • the second semiconductor pattern layer may be formed in the same manner as the first semiconductor pattern layer.
  • the second semiconductor pattern layer includes the active layer of the second thin film transistor.
  • a via hole is correspondingly opened in the first insulating layer and the second insulating layer corresponding to each opening.
  • the via in this step 1810 is the aforementioned third via.
  • step 1811 a third conductive pattern layer is formed on the second insulating layer.
  • a third conductive material layer is formed on the second insulating layer, and then the third conductive material layer is processed through a patterning process to obtain the third conductive pattern layer.
  • the third conductive material layer may be a metal thin film, and the third conductive material layer may be formed by sputtering or the like.
  • FIG. 13 is a schematic diagram of the third conductive pattern layer.
  • the third conductive pattern layer includes the touch line M, the first electrode Q21 and the second electrode Q22 of the second thin film transistor Q2.
  • step 1812 a third insulating layer is formed on the third conductive pattern layer.
  • this step 1812 it further includes opening a via hole (that is, the aforementioned second via hole) in the third insulating layer.
  • the third insulating layer is formed in the same manner as the second insulating layer.
  • step 1813 a pixel electrode layer is formed on the third insulating layer.
  • a transparent conductive material layer may be formed on the third insulating layer, and then the transparent conductive material layer may be processed through a patterning process to obtain the pixel electrode layer.
  • the transparent conductive material layer can be formed by deposition.
  • the transparent conductive material layer may be an ITO, IZO layer, or the like.
  • the pixel electrode layer includes a plurality of pixel electrodes, and each pixel electrode is connected to a second electrode of a corresponding second thin film transistor through a second via hole.

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Abstract

提供了一种阵列基板及其制作方法、驱动方法以及触控显示装置，属于显示技术领域。所述阵列基板包括多根数据线、多根触控线、多个触控电极和多个第一开关器件。每个所述触控电极与至少一根所述触控线电连接，每个第一开关器件分别与一根所述数据线和一个所述触控电极电连接，每个所述第一开关器件被配置为选择性地将所连接的所述数据线与所述触控电极导通或断开。该阵列基板可以将在触控阶段采用数据线为对应的触控电极提供触控信号，因此，无需加宽触控线即可降低触控线的电阻，有利于提高产品的开口率。

Description

阵列基板及其制作方法、驱动方法以及触控显示装置
本申请要求于2019年1月31日提交的申请号为201910095797.0、发明名称为“阵列基板及其制作方法、触控显示装置及其驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其制作方法、驱动方法以及触控显示装置。
背景技术
目前，为了实现触控面板的薄型化和轻量化，将触控面板和液晶显示面板一体化的研究日渐盛行。其中，将触控面板嵌入到液晶显示面板内部的内嵌式(In-Cell)触控方案受到人们的广泛关注。
发明内容
本公开实施例提供了一种阵列基板及其制作方法、驱动方法以及触控显示装置。
一方面，本公开实施例提供了一种阵列基板，包括多根数据线、多根触控线、多个触控电极和多个第一开关器件。每个所述触控电极与至少一根所述触控线电连接，每个第一开关器件分别与一根所述数据线和一个所述触控电极电连接，每个所述第一开关器件被配置为选择性地将所连接的所述数据线与所述触控电极导通或断开。
在一些实施例中，所述第一开关器件包括：第一薄膜晶体管，所述第一薄膜晶体管的第一极与对应的所述数据线电连接，所述第一薄膜晶体管的第二极与对应的所述触控电极电连接。
在另一些实施例中，所述第一开关器件包括：第二薄膜晶体管，所述第二薄膜晶体管的第一极与对应的所述数据线电连接，所述薄膜晶体管的第二极与对应的所述触控电极所连接的一根所述触控线电连接。
在一种可能的实施方式中，所述阵列基板还包括多个第二开关器件，每根 所述触控线通过一个所述第二开关器件与对应的所述触控电极电连接，每个所述第二开关器件被配置为选择性地将所连接的所述触控线和所述触控电极导通或者断开。
可选地，所述第二开关器件包括：第三薄膜晶体管，所述第三薄膜晶体管的第一极电连接一根所述触控线，所述第三薄膜晶体管的第二极电连接一个所述触控电极。
在另一种可能的实施方式中，所述触控线与所述触控电极位于不同层，所述触控线与对应的触控电极通过过孔连接；或者，所述触控线与所述触控电极同层，所述触控线与对应的触控电极直接连接。
可选地，每个触控电极具有在所述触控电极上的至少两个信号输入点，所述至少两个信号输入点包括与所述数据线的电连接的点和与所述触控线的电连接的点中的至少一种。
可选地，所述阵列基板还包括多根栅线，所述多根栅线和所述多根数据线限定出多个子像素区域，每个子像素区域均包括一个开关薄膜晶体管和一个第一电极，在每个所述子像素区域中，所述开关薄膜晶体管的第一极与所述数据线电连接，所述开关薄膜晶体管的第二极与所述第一电极电连接，所述开关薄膜晶体管的控制极与栅线电连接；所述第一电极为像素电极，或者，所述第一电极为有机发光二极管的电极。
可选地，所述开关薄膜晶体管、所述触控电极和所述第一电极在远离阵列基板的方向上依次布置，所述触控电极上具有开口，所述开关薄膜晶体管的第二极通过位于所述开口内的过孔与所述第一电极连接。
可选地，所述阵列基板还包括与第一开关器件连接的多根控制线，所述控制线与所述栅线的延伸方向相同。
可选地，所述控制线与所述栅线同层布置。
可选地，所述阵列基板还包括与所述多个第二开关器件连接的多根第二控制线，所述多根栅线和所述多根数据线相交，所述第二控制线与所述栅线的延伸方向相同。
可选地，所述触控线和所述数据线位于不同层，且所述触控在衬底基板上的投影和所述数据在所述衬底基板上的投影满足以下关系中的任一种：
所述触控线在衬底基板上的投影在对应的所述数据线在所述衬底基板上的 投影内；
所述数据线在所述衬底基板上的投影在对应的触控线在所述衬底基板上的投影内。
可选地，所述多个触控电极呈矩阵布置，每个所述触控电极在阵列基板上的正投影覆盖多个子像素区域。
另一方面，本公开实施例还提供了一种阵列基板，包括：衬底基板和沿远离衬底基板的方向依次位于所述衬底基板上的第一导电图案层、栅极绝缘层、第一半导体图案层、第二导电图案层、第一绝缘层、触控电极层、第二绝缘层、第三导电图案层、第三绝缘层和第一电极层；
所述第一导电图案层包括多根栅线、多根第一控制线、多个第一薄膜晶体管的控制极、多个开关薄膜晶体管的控制极，所述多根第一控制线的延伸方向与所述多根栅线的延伸方向相同，所述第一薄膜晶体管的控制极与所述第一控制线电连接，所述多个开关薄膜晶体管的控制极与所述栅线电连接；
所述第一半导体图案层包括所述多个第一薄膜晶体管的有源层、以及所述多个开关薄膜晶体管的有源层；
所述第二导电图案层包括多根数据线、所述多个第一薄膜晶体管的第一极和第二极、所述多个开关薄膜晶体管的第一极和第二极，所述第一薄膜晶体管的第一极和所述开关薄膜晶体管的第一极分别与对应的所述数据线电连接；
所述触控电极层包括呈矩阵布置的多个触控电极，每个所述触控电极与至少一个所述第一薄膜晶体管的第二极电连接；
所述第三导电图案层包括多根触控线，所述多根触控线的延伸方向与所述数据线的延伸方向相同，每个所述触控电极与至少一根所述触控线电连接；
所述第一电极层包括多个第一电极，所述第一电极为像素电极或者有机发光二极管的电极；
其中，所述多根栅线和所述多根数据线交叉限定出多个子像素区域，每个子像素区域中具有一个所述开关薄膜晶体管和一个所述第一电极，每个所述开关薄膜晶体管的第二极与对应的所述第一电极电连接。
可选地，所述第一导电图案层还包括多根第二控制线和多个第二薄膜晶体管的控制极，所述第二控制线与所述栅线的延伸方向相同，所述第二薄膜晶体管的控制极与对应的所述第二控制线电连接；
所述第三导电图案层还包括所述多个第二薄膜晶体管的第一极和第二极，每个所述第二薄膜晶体管的第一极的第一极与对应的所述触控线电连接，每个所述第二薄膜晶体管的第二极与对应的触控电极电连接；
所述阵列基板还包括第二半导体图案层，所述第二半导体图案层包括所述多个第二薄膜晶体管的有源层。
另一方面，本公开实施例还提供了一种触控显示装置，所述触控显示装置包括前述阵列基板。
另一方面，本公开实施例还提供了一种阵列基板的驱动方法，所述驱动方法包括：
在显示阶段，控制所述第一开关器件使得所述数据线与所述触控电极之间的电连接断开，并通过所述数据线提供数据信号；
在触控阶段，控制所述开关器件使得所述数据线与所述触控电极之间的电连接导通，并通过所述数据线和所述触控线同时为所述触控电极提供触控信号。
可选地，所述驱动方法还包括：在所述显示阶段，通过所述触控线为所述触控电极提供公共电压信号。
另一方面，本公开实施例还提供了一种阵列基板的制作方法，包括：提供一衬底基板；在所述衬底基板上形成多根数据线、多根触控线、多个触控电极和多个第一开关器件。每个所述触控电极与至少一根所述触控线电连接，每个所述第一开关器件分别与一根所述数据线和一个所述触控电极电连接，每个所述第一开关器件被配置为选择性地将所连接的所述数据线与所述触控电极导通或断开。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种阵列基板的局部结构示意图；
图2是本公开实施例提供的一种阵列基板的局部俯视结构示意图；
图3是图2所示阵列基板的局部放大示意图；
图4本公开实施例提供的阵列基板的沿图3中的a-a线的截面结构示意图；
图5是图2所示阵列基板的另一局部放大示意图；
图6是本公开实施例提供的阵列基板沿图5中的b-b线的截面结构示意图；
图7是本公开实施例提供的阵列基板的另一截面结构示意图；
图8是本公开实施例提供的阵列基板沿图3中的c-c线的截面结构示意图；
图9是本公开实施例提供的阵列基板的第一导电图案层的示意图；
图10是本公开实施例提供的阵列基板的第一半导体图案层的示意图；
图11是本公开实施例提供的阵列基板的第二导电图案层的示意图；
图12是本公开实施例提供的阵列基板的触控电极的示意图；
图13是本公开实施例提供的阵列基板的第三导电图案层的示意图；
图14为本公开实施例提供的阵列基板在第三薄膜晶体管处的截面结构示意图；
图15是本公开实施例提供的触控显示装置的驱动方法的流程图；
图16是本公开实施例提供的触控显示装置的时序示意图；
图17是本公开实施例提供的一种阵列基板的制作方法的流程图；
图18是本公开实施例提供的另一种阵列基板的制作方法的流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
In-Cell触控方案主要包括自电容触控和互电容触控两种方式。在自电容触控方式中，触控显示面板通常会将公共电极和触控电极复用。这种触控显示面板包括多个呈矩阵分布的触控电极，每个触控电极连接一根触控线。在显示阶段，触控线向触控电极提供公共电压信号，此时触控电极即为公共电极；在触控阶段，触控线向触控电极提供触控信号，并向触控芯片反馈检测信号。
通常，触控线的宽度需要较宽，以减小触控线的电阻，进而减小电压降(IR drop)现象，即近端电压大于远端电压的现象。在这种情况下，需要增加黑矩阵的宽度对触控线进行遮挡，导致产品开口率较低。
图1是本公开实施例提供的一种阵列基板的局部结构示意图。参见图1，该阵列基板包括多根数据线D(例如图1中的D1～D15)、多根触控线M(例如图 1中的M1～M5)和多个触控电极S(每个虚线框表示一个触控电极S)。每个触控电极S与至少一根触控线M电连接，且每个触控电极S所连接的触控线M不同。该阵列基板还包括多个第一开关器件(图1中未示出)。每个第一开关器件分别与一根数据线D和一个触控电极S电连接，每个第一开关器件被配置为选择性地将所连接的数据线D与触控电极S导通或者断开。
在本公开实施例中，第一部件和第二部件电连接，是指第一部件和第二部件之间能够进行电信号的传递，例如，触控电极S与触控线M电连接，是指触控电极S和触控线M之间能够传递电信号。电连接的方式包括但不限于直接连接、通过过孔连接、通过其他导电的元器件连接等等。
选择性地将数据线D与触控电极S导通或断开，是指在控制信号的控制下，将数据线D和触控电极S之间的电连接导通或者断开。相应地，该阵列基板还可以包括多根第一控制线C1，每个第一开关器件连接一根第一控制线C1，一根第一控制线C1可以连接多个第一开关器件。第一控制线C1用于为所连接的第一开关器件提供控制信号。
由于第一开关器件选择性地将数据线与触控电极导通或断开，所以可以在触控阶段，控制第一开关器件将数据线与触控电极电连接，通过数据线向触控电极提供触控信号，而触控线与触控电极电连接，所以触控线也可以同时为触控电极提供触控信号，从而实现数据线与触控线并联，无需加宽触控线即可减小触控线的电阻，因此可以在不牺牲产品开口率的前提下减小触控线的电阻，有利于产品开口率的提高。而在显示阶段，控制第一开关器件将数据线与触控电极之间的电连接断开，通过触控线向触控电极提供公共电压信号，此时即可将触控电极复用为公共电极，同时通过数据线为各个子像素提供数据电压，实现正常显示功能。此外，本公开实施例将触控电极集成在阵列基板上，有利于触控显示装置的轻薄化。
通过在显示阶段和触控阶段复用触控电极和数据线，可以将触控芯片与显示芯片整合进单一芯片中，实现TDDI(Touch and Display Driver Integration，触控与显示驱动器集成)。
在本公开实施例中，阵列基板采用的是单层自电容式触控结构。示例性地，如图1所示，多个触控电极S呈矩阵布置。需要说明的是，图1中的触控电极的数量仅为举例，阵列基板上触控电极的数量可以根据实际需要设置。
可选地，触控线M可以与触控电极S同层布置，也可以不同层布置。在本公开实施例中，同层可以是指可以是指位于同一层的同一侧，或者，通过同一构图工艺形成，或者靠近衬底基板的表面与同一层接触等。相应地，不同层可以是指位于同一层的不同侧，或者，通过不同的构图工艺形成，或者靠近衬底基板的表面与不同的层接触等。
可选地，触控线M与触控电极S可以直接连接，或者，可以通过过孔连接，或者，触控线M与触控电极S还可以通过第二开关器件连接。该第二开关器件可以是薄膜晶体管，该薄膜晶体管的第一极与触控线连接，第二极与触控电极连接，控制极与第二控制线C2连接。第二控制线C2用于为所连接的薄膜晶体管提供控制信号。
可选地，每个触控电极S均通过第一开关器件与至少一根数据线D电连接，且与每个触控电极S电连接的数据线D的数量相等，以保证作用于每个触控电极的电压相等。例如，每个触控电极S均与1根数据线D连接，或者，每个触控电极S均与2根数据线D连接。
示例性地，电连接的数据线D和触控电极S在衬底基板上的投影部分重叠，以便于布线。
示例性地，阵列基板还可以包括多根栅线SG(例如图1中的SG1～SG8)和多个开关薄膜晶体管(图1中未示出)，多根数据线D和多根栅线SG相交，限定出多个子像素区域。每个子像素区域中具有一个开关薄膜晶体管，开关薄膜晶体管位于栅线SG和数据线D的交叉处，每个开关薄膜晶体管用于控制对应子像素区域发光。示例性地，开关薄膜晶体管的控制极与对应的栅线连接，开关薄膜晶体管的第一极与对应的数据线连接，开关薄膜晶体管的第二极与对应的第一电极连接。其中，开关薄膜晶体管的控制极可以为栅极，第一极可以为源极和漏极中的一个，第二极为源极和漏极中的另一个。
对于液晶显示装置的阵列基板而言，第一电极为像素电极，对于有机发光二极管显示装置的阵列基板而言，第一电极为有机发光二极管的电极，例如阴极或者阳极。
如图1所示，在本公开实施例中，第一控制线C1的延伸方向可以与栅线SG的延伸方向相同，触控线M的延伸方向和数据线D的延伸方向相同。由于显示分辨率通常大于触控分辨率，所以数据线D的数量大于触控线M的数量， 因此，在本公开实施例中，只有部分数据线D与第一开关器件SW1连接。在本公开实施例中，与第一开关器件连接的数据线可以被称为第一数据线，除第一数据线以外的数据线(即未与第一开关器件连接的数据线)可以被称为第二数据线。第一开关器件可以位于第一控制线和第一数据线交叉处。
可选地，在本公开实施例中，第一开关器件将数据线与触控电极电连接可以有两种方式，一种是直接连接，即第一开关器件分别与数据线和触控电极连接，参见图2～图8所示实施例；另一种是间接连接，即第一开关器件将触控线与对应的数据线连接，从而通过第一开关器件和触控线将数据线与触控电极电连接，参见图14所示实施例。
下面将以液晶显示装置为例，对本公开实施例提供的阵列基板的结构进行详细说明。
图2为本公开实施例提供的一种阵列基板的局部俯视结构示意图。如图2所示，该阵列基板包括多根数据线D、多根触控线M、多个触控电极S(图中仅示出了一个)和多个第一开关器件SW1(参见图3)。每个触控电极S与至少一根触控线M连接，且每个触控电极S所连接的触控线M不同。在图2所示实施例中，每个第一开关器件SW1对应连接一根数据线D和一个触控电极S，即，第一开关器件SW1直接与数据线D和触控电极连接。
图3为图2所示阵列基板的局部放大示意图。如图3所示，第一开关器件SW1包括第一薄膜晶体管Q1，第一薄膜晶体管Q1的第一极Q11与对应的数据线D电连接，第一薄膜晶体管Q1的第二极Q12与一个触控电极S连接。第一薄膜晶体管Q1的控制极Q13与第一控制线C1电连接。第一控制线C1用于提供控制信号，以控制第一薄膜晶体管Q1的通断，进而控制数据线D与触控电极S之间电连接的导通或断开。
其中，第一薄膜晶体管Q1的第一极Q11可以为源极和漏极中的一个，第一薄膜晶体管Q1的第二极Q12为源极和漏极中的另一个，第一薄膜晶体管Q1的控制极Q13为栅极。
示例性地，第一薄膜晶体管Q1的第一极Q11与对应的数据线D电连接，可以采用以下两种方式的一种：第一薄膜晶体管Q1的第一极Q11与对应的数据线D连接，或者，第一薄膜晶体管Q1的第一极Q11为对应的数据线D的一部分。其他电极与对应的导线(例如控制线等)的电连接均与此相同，下文将不 再赘述。
在显示阶段，第一薄膜晶体管Q1断开，通过数据线D提供数据信号，通过触控线M向触控电极S提供公共电压信号；在触控阶段，第一薄膜晶体管Q1导通，通过数据线D和触控线M同时向触控电极S提供触控信号，从而实现对数据线的分时复用。
示例性地，图4本公开实施例提供的阵列基板的沿图3中的a-a线的截面结构示意图，用于展示第一开关器件处(即第一薄膜晶体管Q1处)的截面结构。如图4所示，在远离衬底基板200的方向上，第一薄膜晶体管Q1、触控电极S和触控线M依次布置，且第一薄膜晶体管Q1的第二极Q12与一个触控电极S连接。
示例性地，如图4所示，在本公开实施例中，阵列基板包括衬底基板200和在远离衬底基板200的方向上依次布置的第一导电图案层201、栅极绝缘层202、第一半导体图案层203、第二导电图案层204、第一绝缘层205、触控电极层206、第二绝缘层207、第二半导体图案层208(参见图6)、第三导电图案层209、第三绝缘层210和第一电极层211(参见图8)。第一薄膜晶体管Q1的第三极Q13位于第一导电图案层201。第一薄膜晶体管Q1的有源层Q14位于第一半导体图案层203。第一薄膜晶体管Q1的第一极Q11和第二极Q12位于第二导电图案层204。触控电极S位于触控电极层206。
结合图3和图4，第一薄膜晶体管Q1的第二极Q12与一个触控电极S通过第一过孔H1连接。该第一过孔H1位于第一绝缘层205中。
可选地，当触控线与触控电极不同层布置时，触控线与触控电极可以通过第二开关器件(例如薄膜晶体管)间接连接，每个触控电极通过一个第二开关器件与对应的触控线电连接，第二开关器件被配置为选择性地将所连接的触控线和触控电极导通或断开。例如，在图2所示实施例中，触控线与触控电极通过第二开关器件SW2(参见图5)(例如第二薄膜晶体管Q2)间接连接，第二薄膜晶体管Q2被配置为选择性地将触控电极S和触控线M之间的电连接导通或断开。
图5为图2所示阵列基板的局部放大示意图。如图5所示，第二薄膜晶体管Q2的第一极Q21与对应的触控电极S连接，第二薄膜晶体管Q2的第二极Q22与一根触控线M电连接。第二薄膜晶体管Q2的控制极Q23与第二控制线 C2电连接。第二控制线C2用于提供控制信号，以控制第二薄膜晶体管Q2的通断，进而控制触控线M与触控电极S的导通或断开。
其中，第二薄膜晶体管Q2的第一极Q21可以为源极和漏极中的一个，第二薄膜晶体管Q2的第二极Q22为源极和漏极中的另一个，第二薄膜晶体管Q2的控制极Q23为栅极。
在显示阶段和触控阶段，第二薄膜晶体管Q2均导通，以便于在显示阶段通过触控线向触控电极提供公共电压信号，而在触控阶段通过触控线向触控电极提供触控信号。
图6是本公开实施例提供的阵列基板沿图5中的b-b线的截面结构示意图，用于展示第二薄膜晶体管Q2处的截面结构。
如图6所示，第二薄膜晶体管Q2的控制极Q23位于第一导电图案层201。数据线D位于第二导电图案层204。第二薄膜晶体管Q2的有源层Q24位于第二半导体图案层208。第二薄膜晶体管Q2的第一极Q21和第二极Q22位于第三导电图案层209。
结合图5和图6，第二薄膜晶体管Q2的第二极Q22与触控电极S通过第二过孔H2连接。该第二过孔H2位于第二绝缘层207中。
可替代地，在其他实施方式中，当触控线与触控电极不同层布置时，触控线与触控电极可以通过过孔连接，通过控制输入到各根触控线的触控信号的时序来向对应的触控电极输入触控信号。例如，如图7所示，触控线M通过过孔H2'与触控电极S连接。需要说明的是，当触控线M通过过孔H2'与触控电极S连接时，该阵列基板可以去除专用于形成第二薄膜晶体管Q2的结构的层，例如第二半导体图案层208。
可替代地，在本公开的其他实施方式中，触控线与触控电极也可以同层布置，此时，触控线与触控电极可以直接连接。
在本公开实施例中，多个触控电极S呈矩阵布置。示例性地，每个触控电极S可以呈矩形，例如，可以为长和宽均为4mm的正方形。每个触控电极可以覆盖多个子像素区域。单个触控电极对应的子像素区域的数量可以由显示装置的分辨率决定。对于固定大小的显示装置，分辨率越高，每个像素区域的面积越小，一个触控电极对应的子像素区域的数量越多；反之，分辨率越低，每个像素区域的面积越大，一个触控电极对应的子像素区域的数量越少。实际应用 中，触控电极的形状和大小均可以根据实际需要设置。
可选地，每个触控电极具有在触控电极上的至少两个信号输入点，每个触控电极上的信号输入点包括与数据线的电连接的点和与触控线的电连接的点中的至少一种。每个触控电极通过至少两个信号输入点接收触控信号，有利于提高触控电极上电压的均一性。
示例性地，在图2所示实施例中，每个触控电极S包括两个与数据线D的电连接的点(分别对应两个第一过孔H1)和两个与触控线M的电连接的点(分别对应两个第二过孔H2)。两个与数据线D电连接的点沿第一控制线C1的延伸方向间隔布置，两个与触控线M电连接的点沿第二控制线C2的延伸方向间隔布置。
需要说明的是，触控电极上信号输入点的数量和位置可以根据实际需要设置。在本公开实施例中，各个触控电极上信号输入点的数量和位置均相同。
再次参见图2，该阵列基板还包括多根栅线SG，多根数据线D沿第一方向延伸，多个栅线SG沿第二方向延伸，第一方向和第二方向相交，例如垂直。
在图2所示实施例中，栅线SG的延伸方向和第一控制线C1的延伸方向相同。即第一控制线C1与栅线SG平行设置。对于显示装置而言，通常栅线的延伸方向上，子像素区域的数量较多，相邻子像素之间的空间比较紧张，第一控制线C1沿栅线SG的延伸方向延伸，可以避免占用在栅线的延伸方向上相邻的子像素区域之间的空间，便于布线。
可选地，第一控制线C1与栅线SG同层布置。由于控制线与栅线同层布置，所以可以与栅线采用一次构图工艺制成，简化制作工艺。
可选地，在本公开实施例中，第二控制线C2与栅线SG的延伸方向相同，为了进一步简化制作工艺，第二控制线C2与第一控制线C1也可以同层布置。
多根栅线SG和多根数据线D限定出多个子像素区域，每个子像素区域均包括一个开关薄膜晶体管Q3和一个像素电极P。参见图3和图5，在每个子像素区域中，开关薄膜晶体管Q3的第一极Q31与数据线D电连接，开关薄膜晶体管Q3的第二极Q32与像素电极P电连接，开关薄膜晶体管Q3的控制极Q33与栅线SG电连接。
其中，开关薄膜晶体管Q3的第一极Q31可以为源极和漏极中的一个，开关薄膜晶体管Q3的第二极Q32为源极和漏极中的另一个，开关薄膜晶体管Q3 的控制极Q33为栅极。
图8是本公开实施例提供的阵列基板沿图3中的c-c线的截面结构示意图，用于展示开关薄膜晶体管Q3处的截面结构。
如图8所示，开关薄膜晶体管Q3的控制极Q33位于第一导电图案层201。开关薄膜晶体管Q3的有源层Q34位于第一半导体图案层203。开关薄膜晶体管Q3的第一极Q31和第二极Q32位于第二导电图案层204。像素电极P位于第一电极层211(也可以称为像素电极层)。
在远离衬底基板200的方向上，触控电极S和像素电极P依次布置，即触控电极层206位于像素电极层211与衬底基板200之间。而开关薄膜晶体管Q3位于触控电极S和像素电极P之间，由于开关薄膜晶体管Q3的第二极Q32需要与像素电极P连接，因此，触控电极S上具有多个开口S0，开口S0与子像素区域一一对应布置，每个子像素区域中的像素电极P和开关薄膜晶体管Q3通过第三过孔H3连接，且每个第三过孔H1均位于对应的子像素区域的开口S0中。如图8所示，第三过孔H3穿过第一绝缘层205和第二绝缘层207。
图9是本公开实施例提供的第一导电图案层的结构示意图。如图9所示，第一导电图案层包括前述栅线SG、第一控制线C1、第二控制线C2、第一薄膜晶体管Q1的控制极Q13、第二薄膜晶体管Q2的控制极Q23和开关薄膜晶体管Q3的控制极Q33。栅极绝缘层201覆盖在第一导电图案层上。
图10是本公开实施例提供的第一半导体图案层的结构示意图。如图10所示，第一半导体图案层包括第一薄膜晶体管Q1的有源层Q14和开关薄膜晶体管Q3的有源层Q34。
图11是本公开实施例提供的第二导电图案层的结构示意图。如图11所示，第二导电图案层包括数据线D、第一薄膜晶体管Q1的第一极Q11和第二极Q12和开关薄膜晶体管Q3的第一极Q31和第二极Q32。
第一绝缘层202覆盖在第二导电图案层上。触控电极层203包括阵列布置的多个触控电极S。第二绝缘层204覆盖在触控电极层203上。第二半导体图案层包括第二薄膜晶体管Q2的有源层Q24。
图12是本公开实施例提供的触控电极层的结构示意图。如图12所示，触控电极S上具有多个开口S0。每个开口S0对应一个子像素区域。
图13是本公开实施例提供的第三导电图案层的结构示意图。如图13所示， 第三导电图案层包括触控线M以及第二薄膜晶体管Q2的第一极Q21和第二极Q22。第三绝缘层205覆盖在第三导电图案层上。
可替代地，在其他实施例中，各层之间的顺序可以调整，例如，在远离衬底基板的方向上，像素电极和触控电极依次布置，即像素电极所在层位于触控电极所在层与衬底基板之间。相应的，需要调整过孔的位置，以实现图2所示的电连接关系。
示例性地，在本公开实施例中，衬底基板为透明基板，可以采用例如玻璃、塑料等材料制成。栅线、数据线和控制线均采用导体，例如金属材料制成。金属材料可以为单金属材料，例如Al、Cu、Mu等，也可以为合金材料，例如Al、Cu、Mu中至少两种的合金。栅线、数据线和控制线所采用的材料可以相同，也可以不同。触控电极采用透明导电材料制成，例如ITO、IZO等，以避免影响显示装置的显示功能。像素电极也采用透明导电材料制成，例如ITO、IZO等。有源层可以采用InGaZnO、InGaO、ITZO、AlZnO等材料制成。栅极绝缘层、第一绝缘层、第二绝缘层和第三绝缘层均可以采用氮化硅、二氧化硅等材料制成。
需要说明的是，在图2至图13所示实施例中，均以底栅结构的薄膜晶体管为例进行了说明，在其他实施例中，薄膜晶体管也可以采用顶栅结构或者双栅结构的薄膜晶体管，本公开对此不作限制。也就是说，在其他实施例中，图4、图6至图8中的层级关系是可以变化的，可以增加新的层、调整层与层之间的相对位置等。
可选地，在本公开实施例中，触控线M和数据线D位于不同层，触控线M在衬底基板上的投影在对应的数据线D在衬底基板上的投影内，或者，数据线D在衬底基板上的投影在对应的触控线M在衬底基板上的投影内。
示例性地，数据线D在衬底基板上的投影和对应的触控线M在衬底基板上的投影可以完全重合。这种布置可以进一步减小数据线和触控线占用的像素面积，提高开口率，进而提高产品的整体透过率。
在本公开实施例的另一种可能的实施方式中，当数据线与触控电极通过第二开关器件和触控线间接连接时，第二开关器件对应连接一根触控线和一根数据线。示例性地，第二开关器件包括第三薄膜晶体管，第三薄膜晶体管对应连接一根数据线和一根触控线，且每根触控线均通过一个第三薄膜晶体管与一根 数据线连接。第三薄膜晶体管的控制极与控制线连接，该控制线用于提供控制信号，以控制第三薄膜晶体管的通断，进而控制数据线与触控线之间的连接或断开。在触控线与触控电极连接的情况下，控制数据线与触控线之间的连接或断开，即可控制数据线与触控电极之间的电连接的导通或断开。
其中，第三薄膜晶体管的第一极可以为源极和漏极中的一个，第三薄膜晶体管的第二极为源极和漏极中的另一个，第三薄膜晶体管的控制极为栅极。
在显示阶段，第三薄膜晶体管断开，数据线提供数据信号，触控线向触控电极提供公共电压信号。在触控阶段，第三薄膜晶体管导通，数据线和触控线电连接，进而同时通过数据线和触控线向触控电极提供触控信号。
需要说明的是，该实施例的阵列基板的结构与图2所示阵列基板的结构类似，区别仅在于去除了图2中的第一薄膜晶体管，并在触控线和数据线之间添加了第三薄膜晶体管，该第三薄膜晶体管可以添加在例如图2中的A处。该实施例的阵列基板的其他结构可参见图2相关描述，在此不再赘述。
图14为本公开实施例提供的阵列基板在第三薄膜晶体管处的截面结构示意图。如图14所示，该阵列基板包括衬底基板200和沿远离衬底基板200的方向上依次布置的第一导电图案层201、栅极绝缘层202、第一半导体图案层203、第二导电图案层204、第一绝缘层205、触控电极层206、第二绝缘层207、第二半导体图案层208(参见图6)、第三导电图案层209、第三绝缘层210和第一电极层211(参见图8)。
第三薄膜晶体管Q4的控制极Q43位于第一导电图案层201。第三薄膜晶体管Q4的有源层Q44位于第一半导体图案层203。第三薄膜晶体管Q4的第一极Q41和第二极Q42位于第二导电图案层204。触控电极S位于触控电极层206。触控线M位于第三导电图案层209。
第三薄膜晶体管Q4的第二极Q42与触控线M通过第四过孔H4连接。该第四过孔H4位于第一绝缘层205和第二绝缘层207中。为了便于设置第四过孔H4，触控电极S上具有对应的开口S1，第四过孔H4穿过该开口S1。
在图14所示实施例中，除了将图2所示实施例中的第一薄膜晶体管替换为第三薄膜晶体管之外，其他结构与图2所示实施例相同。也即是说，第一导电图案层201包括前述栅线SG、第一控制线C1、第二控制线C2、第三薄膜晶体管Q4的控制极Q43、第二薄膜晶体管Q2的控制极Q23和开关薄膜晶体管Q3 的控制极Q33。栅极绝缘层202覆盖在第一导电图案层201上。第一半导体图案层203包括第三薄膜晶体管Q4的有源层Q44和开关薄膜晶体管Q3的有源层Q34。第二导电图案层204包括数据线D、第三薄膜晶体管Q4的第一极Q41和第二极Q42以及开关薄膜晶体管Q3的第一极Q31和第二极Q32。第一绝缘层205覆盖在第二导电图案层204上。触控电极层206包括阵列布置的多个触控电极S。第二绝缘层207覆盖在触控电极层206上。第二半导体图案层208包括第二薄膜晶体管Q2的有源层Q24。第三导电图案层209包括触控线M、第二薄膜晶体管Q2的第一极Q21和第二极Q22。第三绝缘层210覆盖在第三导电图案层209上。第一电极层211包括多个像素电极P，每个像素电极P位于一个子像素区域中。
需要说明的是，在本公开实施例中，均以第一开关器件和第二开关器件为薄膜晶体管为例进行说明，在其他实施例中，第一开关器件和第二开关器件还可以场效应管等，只要能够在控制信号的控制下实现开关动作即可。
本公开实施例还提供了一种触控显示装置，该触控显示装置包括前述任一种阵列基板。
示例性地，该触控显示装置可以为手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种触控显示装置的驱动方法，适用于驱动前述触控显示装置。如图15所示，该驱动方法包括：
在步骤1501中，在显示阶段，控制第一开关器件使得对应的数据线与触控电极之间的电连接断开，并通过数据线提供数据信号。
对于液晶显示装置而言，该步骤S1501包括：在显示阶段，通过数据线为像素电极提供数据信号。对于OLED显示装置而言，该步骤1501包括：在显示阶段，通过数据线为OLED的电极(阴极或阳极)提供数据信号。
可选地，该步骤1501还可以包括：在显示阶段，通过触控线为触控电极提供公共电压信号。从而可以将触控电极复用为公共电极，以简化显示装置的结构。
在步骤1502中，在触控阶段，控制第一开关器件使得对应的数据线与触控 电极之间的电连接导通，并通过数据线和触控线同时为触控电极提供触控信号。
示例性地，公共电压信号可以为电平信号，触控信号可以为高频脉冲信号。
在本公开实施例中，显示阶段和触控阶段是周期性交替出现的。例如，在一帧画面的显示时间内，前一段时间为显示阶段，后一段时间为触控阶段。
可选地，对于图2所示实施例，触控显示装置可以采用图16中的时序信号进行驱动。
如图16所示，在显示阶段，各栅线SG1～SGn依次输入扫描信号，进行逐行扫描；第二控制线C2上的控制信号为高电平VGH，第二薄膜晶体管导通，触控线与对应的触控电极电连接，并通过触控线为触控电极提供公共电压信号；第一控制线C1上的控制信号为低电平VGL，使得第一薄膜晶体管断开，数据线与触控电极之间的电连接断开。
在触控阶段，各栅线SG1～SGn上的扫描信号均为低电平，开关薄膜晶体管断开；第二控制线C2上的控制信号为高电平VGH，第二薄膜晶体管导通，触控线与对应的触控电极电连接，并通过触控线为触控电极提供触控信号；第一控制线C1上的控制信号变为高电平VGH，使得第一薄膜晶体管导通，进而通过第一薄膜晶体管和控制线实现数据线与触控电极之间的电连接导通，数据线与触控线同时为触控电极提供触控信号。
本公开实施例还提供了一种阵列基板的制作方法。图17为本公开实施例提供的一种阵列基板的制作方法的流程图。如图17所示，该制作方法包括：
在步骤1701中，提供一衬底基板；
在步骤1702中，在衬底基板上形成多根数据线、多根触控线、多个触控电极和多个第一开关器件。
其中，每个触控电极与至少一根触控线连接，每个第一开关器件分别与一根数据线和一个触控电极电连接，每个第一开关器件被配置为选择性地将所连接的数据线与触控电极导通或断开。
图18是本公开实施例提供的另一种阵列基板的制作方法流程图。该方法用于制作如图2所示的阵列基板。如图18所示，该方法包括：
在步骤1801中，提供一衬底基板。
衬底基板可以为透明基板，可以采用例如玻璃、塑料等材料制成。
在步骤1802中，在衬底基板上形成第一导电图案层。
图9为第一导电图案层的示意图。如图9所示，第一导电图案层可以包括栅线SG、第一控制线C1和第二控制线C2、第一薄膜晶体管Q1的控制极Q13、第二薄膜晶体管Q2的控制极Q23和开关薄膜晶体管Q3的控制极Q33。
示例性地，可以在衬底基板上形成第一导电材料层，再通过构图工艺对第一导电材料层进行处理，得到该第一导电图案层。第一导电材料层可以是金属薄膜，第一导电材料层可以采用溅射等方式形成。
在步骤1803中，在第一导电图案层上形成栅极绝缘层。
栅极绝缘层覆盖在第一导电图案层上。示例性地，可以通过气相沉积的方式形成栅极绝缘层。栅极绝缘层可以采用氮化硅、氧化硅等绝缘材料制作。
在步骤1804中，在栅极绝缘层上形成第一半导体图案层。
在该步骤1804中，可以先在栅极绝缘层上形成半导体材料薄膜。例如可以采用沉积的方式在栅极绝缘层上形成半导体材料薄膜。半导体材料薄膜可以是InGaZnO、InGaO、ITZO、AlZnO中的至少一种。然后通过构图工艺对半导体材料薄膜进行图形化处理，得到第一半导体图案层。
图10是第一半导体图案层的示意图。如图10所示，第一半导体图案层包括第一薄膜晶体管Q1的有源层Q14和开关薄膜晶体管Q3的有源层Q34。
在步骤1805中，在第一半导体图案层上形成第二导电图案层。
在该步骤1805中，在形成有第一半导体图案层的衬底基板上形成第二导电材料层，再通过构图工艺对第二导电材料层进行处理，得到该第二导电图案层。第二导电材料层可以是金属薄膜，第二导电材料层可以采用溅射等方式形成。
示例性地，图11为第二导电图案层的示意图。如图11所示，第二导电图案层包括数据线D、第一薄膜晶体管Q1的第一极Q11和第二极Q12以及开关薄膜晶体管Q3的第一极Q31和第二极Q32。
在步骤1806中，在第二导电图案层上形成第一绝缘层。
第一绝缘层覆盖在第二导电图案层上。示例性地，可以通过气相沉积的方式形成第一绝缘层。第一绝缘层可以采用氮化硅、氧化硅等绝缘材料制作。
可选地，在本公开实施例中，该方法还包括：在第一绝缘层中对应第二薄膜晶体管的第二极的位置开设第一过孔。
在步骤1807中，在第一绝缘层上形成触控电极层。
触控电极层包括呈矩阵布置的多个触控电极，图12为触控电极的示意图。如图12所示，触控电极S上具有多个开口S0。
示例性地，可以在第一绝缘层上形成透明导电材料层，再通过构图工艺对透明导电材料层进行处理，得到该触控电极层。透明导电材料层可以采用沉积的方式形成。透明导电材料层可以为ITO、IZO层等。
在步骤1808中，在触控电极层上形成第二绝缘层。
第二绝缘层的形成方式可以与第一绝缘层相同，在此省略详细描述。
在步骤1809中，在第二绝缘层上形成第二半导体图案层。
第二半导体图案层的形成方式可以与第一半导体图案层相同。
在本公开实施例中，第二半导体图案层包括第二薄膜晶体管的有源层。
在步骤1810中，在每个开口对应的第一绝缘层和第二绝缘层中对应开设过孔。
该步骤1810中的过孔即为前述第三过孔。
在步骤1811中，在第二绝缘层上形成第三导电图案层。
在该步骤1811中，在第二绝缘层上形成第三导电材料层，再通过构图工艺对第三导电材料层进行处理，得到该第三导电图案层。第三导电材料层可以是金属薄膜，第三导电材料层可以采用溅射等方式形成。
示例性地，图13为第三导电图案层的示意图。如图13所示，第三导电图案层包括触控线M、第二薄膜晶体管Q2的第一极Q21、第二极Q22。
在步骤1812中，在第三导电图案层上形成第三绝缘层。
在该步骤1812中，还包括在第三绝缘层中开设过孔(即前述第二过孔)。第三绝缘层的形成方式与第二绝缘层的形成方式相同。
在步骤1813中，在第三绝缘层上形成像素电极层。
示例性地，可以在第三绝缘层上形成透明导电材料层，再通过构图工艺对透明导电材料层进行处理，得到该像素电极层。透明导电材料层可以采用沉积的方式形成。透明导电材料层可以为ITO、IZO层等。
像素电极层包括多个像素电极，每个像素电极通过第二过孔与对应的第二薄膜晶体管的第二极连接。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的 精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括：多根数据线(D)、多根触控线(M)、多个触控电极(S)和多个第一开关器件(SW1)，每个所述触控电极(S)与至少一根所述触控线(M)电连接，每个所述第一开关器件(SW1)分别与一根所述数据线(D)和一个所述触控电极(S)电连接，每个所述第一开关器件(SW1)被配置为选择性地将所连接的所述数据线(D)与所述触控电极(S)导通或者断开。
  2. 根据权利要求1所述的阵列基板，其中，所述第一开关器件(SW1)包括：第一薄膜晶体管(Q1)，所述第一薄膜晶体管(Q1)的第一极(Q11)与对应的所述数据线(D)电连接，所述第一薄膜晶体管(Q1)的第二极(Q12)与对应的所述触控电极(S)电连接。
  3. 根据权利要求1所述的阵列基板，其中，所述第一开关器件(SW1)包括：第二薄膜晶体管(Q4)，所述第二薄膜晶体管(Q4)的第一极(Q41)与对应的所述数据线(D)电连接，所述第二薄膜晶体管(Q4)的第二极(Q42)与对应的所述触控电极(S)所连接的一根所述触控线(M)电连接。
  4. 根据权利要求1至3任一项所述的阵列基板，还包括：多个第二开关器件(SW2)，每根所述触控线(M)通过一个所述第二开关器件(SW2)与对应的所述触控电极(S)电连接，每个所述第二开关器件(SW2)被配置为选择性地将所连接的所述触控线(M)和所述触控电极(S)导通或者断开。
  5. 根据权利要求4所述的阵列基板，其中，所述第二开关器件(SW2)包括：
    第三薄膜晶体管(Q2)，所述第三薄膜晶体管(Q2)的第一极(Q21)电连接一根所述触控线(M)，所述第三薄膜晶体管(Q2)的第二极电连接一个所述触控电极(S)。
  6. 根据权利要求1至3任一项所述的阵列基板，其中，所述触控线(M)与所述触控电极(S)位于不同层，所述触控线(M)与对应的触控电极(S)通过过孔连接；
    或者，所述触控线(M)与所述触控电极(S)同层，所述触控线(M)与对应的触控电极(S)直接连接。
  7. 根据权利要求1至5任一项所述的阵列基板，其中，每个触控电极(S)具有在所述触控电极(S)上的至少两个信号输入点，所述至少两个信号输入点 包括与所述数据线(D)电连接的点和与所述触控线(M)电连接的点中的至少一种。
  8. 根据权利要求1至6任一项所述的阵列基板，还包括多根栅线(SG)，所述多根栅线(SG)和所述多根数据线(D)限定出多个子像素区域，每个子像素区域均包括一个开关薄膜晶体管(Q3)和一个第一电极，在每个所述子像素区域中，所述开关薄膜晶体管(Q3)的第一极(Q31)与所述数据线(D)电连接，所述开关薄膜晶体管(Q3)的第二极(Q32)与所述第一电极电连接，所述开关薄膜晶体管(Q3)的控制极(Q33)与所述栅线(SG)电连接；
    所述第一电极为像素电极(P)，或者，所述第一电极为有机发光二极管的电极。
  9. 根据权利要求8所述的阵列基板，其中，所述开关薄膜晶体管(Q3)、所述触控电极(S)和所述第一电极在远离阵列基板(200)的方向上依次布置，所述触控电极(S)上具有开口(S0)，所述开关薄膜晶体管(Q3)的第二极(Q32)通过位于所述开口(S0)内的过孔(H3)与所述第一电极连接。
  10. 根据权利要求1至9任一项所述的阵列基板，还包括多根栅线(SG)和与所述多个第一开关器件(SW1)连接的多根第一控制线(C1)，所述多根栅线(SG)和所述多根数据线(D)相交，所述第一控制线(C1)与所述栅线(SG)的延伸方向相同。
  11. 根据权利要求10所述的阵列基板，其中，所述第一控制线(C1)与所述栅线(SG)同层布置。
  12. 根据权利要求4或5所述的阵列基板，还包括多根栅线(SG)和与所述多个第二开关器件(SW2)连接的多根第二控制线(C2)，所述多根栅线(SG)和所述多根数据线(D)相交，所述第二控制线(C1)与所述栅线(SG)的延伸方向相同。
  13. 根据权利要求1至12任一项所述的阵列基板，其中，所述触控线(M)和所述数据线(D)位于不同层，且所述触控线(M)在衬底基板上的投影和所述数据线(D)在所述衬底基板上的投影满足以下关系中的任一种：
    所述触控线(M)在衬底基板上的投影在对应的所述数据线(D)在所述衬底基板上的投影内；
    所述数据线(D)在所述衬底基板上的投影在对应的触控线(M)在所述衬 底基板上的投影内。
  14. 根据权利要求1至13任一项所述的阵列基板，其中，所述多个触控电极(S)呈矩阵布置，每个所述触控电极(S)在阵列基板(200)上的正投影覆盖多个子像素区域。
  15. 一种阵列基板，包括：衬底基板(200)和沿远离衬底基板(200)的方向依次位于所述衬底基板(200)上的第一导电图案层(201)、栅极绝缘层(202)、第一半导体图案层(203)、第二导电图案层(204)、第一绝缘层(205)、触控电极层(206)、第二绝缘层(207)、第三导电图案层(209)、第三绝缘层(210)和第一电极层(211)；
    所述第一导电图案层(201)包括多根栅线(SG)、多根第一控制线(C1)、多个第一薄膜晶体管(Q1)的控制极(Q13)、多个开关薄膜晶体管(Q3)的控制极(Q33)，所述多根第一控制线(C1)的延伸方向与所述多根栅线(SG)的延伸方向相同，所述第一薄膜晶体管(Q1)的控制极(Q13)与所述第一控制线(C1)电连接，所述多个开关薄膜晶体管(Q3)的控制极(Q33)与所述栅线(SG)电连接；
    所述第一半导体图案层(203)包括所述多个第一薄膜晶体管(Q1)的有源层(Q14)、以及所述多个开关薄膜晶体管(Q3)的有源层(Q34)；
    所述第二导电图案层(204)包括多根数据线(D)、所述多个第一薄膜晶体管(Q1)的第一极(Q11)和第二极(Q12)、所述多个开关薄膜晶体管(Q3)的第一极(Q31)和第二极(Q32)，所述第一薄膜晶体管(Q1)的第一极(Q11)和所述开关薄膜晶体管(Q3)的第一极(Q31)分别与对应的所述数据线(D)电连接；
    所述触控电极层(206)包括呈矩阵布置的多个触控电极(S)，每个所述触控电极(S)与至少一个所述第一薄膜晶体管(Q1)的第二极(Q12)电连接；
    所述第三导电图案层(209)包括多根触控线(M)，所述多根触控线(M)的延伸方向与所述数据线(D)的延伸方向相同，每个所述触控电极(S)与至少一根所述触控线(M)电连接；
    所述第一电极层(211)包括多个第一电极，所述第一电极为像素电极(P)或者有机发光二极管的电极；
    其中，所述多根栅线(SG)和所述多根数据线(D)交叉限定出多个子像素区域，每个子像素区域中具有一个所述开关薄膜晶体管(Q3)和一个所述第一电极，每个所述开关薄膜晶体管(Q3)的第二极(Q32)与对应的所述第一电极电连接。
  16. 根据权利要求15所述的阵列基板，其中，所述第一导电图案层(201)还包括多根第二控制线(C2)和多个第二薄膜晶体管(Q2)的控制极(Q23)，所述第二控制线(C2)与所述栅线(SG)的延伸方向相同，所述第二薄膜晶体管(Q2)的控制极(Q23)与对应的所述第二控制线(C2)电连接；
    所述第三导电图案层(209)还包括所述多个第二薄膜晶体管(Q2)的第一极(Q21)和第二极(Q22)，每个所述第二薄膜晶体管(Q2)的第一极(Q21)的第一极(Q21)与对应的所述触控线(M)电连接，每个所述第二薄膜晶体管(Q2)的第二极(Q22)与对应的所述触控电极(S)电连接；
    所述阵列基板还包括第二半导体图案层(208)，所述第二半导体图案层(208)包括所述多个第二薄膜晶体管(Q2)的有源层(Q24)。
  17. 一种触控显示装置，包括权利要求1至14任一项或者权利要求15至16任一项所述的阵列基板。
  18. 一种阵列基板的驱动方法，适用于驱动如权利要求1至14任一项所述的阵列基板，所述驱动方法包括：
    在显示阶段，控制所述第一开关器件使得所述数据线与所述触控电极之间的电连接断开，并通过所述数据线提供数据信号；
    在触控阶段，控制所述第一开关器件使得所述数据线与所述触控电极之间的电连接导通，并通过所述数据线和所述触控线同时为所述触控电极提供触控信号。
  19. 根据权利要求18所述的驱动方法，还包括：
    在所述显示阶段，通过所述触控线为所述触控电极提供公共电压信号。
  20. 一种阵列基板的制作方法，包括：
    提供一衬底基板；
    在所述衬底基板上形成多根数据线、多根触控线、多个触控电极和多个第一开关器件，每个所述触控电极与至少一根所述触控线电连接，每个第一开关器件分别与一根所述数据线和一个所述触控电极电连接，每个所述第一开关器件被配置为选择性地将所连接的所述数据线与所述触控电极导通或断开。
PCT/CN2020/073108 2019-01-31 2020-01-20 阵列基板及其制作方法、驱动方法以及触控显示装置 WO2020156300A1 (zh)

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