WO2020155096A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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WO2020155096A1
WO2020155096A1 PCT/CN2019/074396 CN2019074396W WO2020155096A1 WO 2020155096 A1 WO2020155096 A1 WO 2020155096A1 CN 2019074396 W CN2019074396 W CN 2019074396W WO 2020155096 A1 WO2020155096 A1 WO 2020155096A1
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buffer layer
transition metal
concentration
doping
substrate
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PCT/CN2019/074396
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English (en)
French (fr)
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程凯
刘凯
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苏州晶湛半导体有限公司
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Priority to CN201980090925.0A priority Critical patent/CN113439342B/zh
Priority to PCT/CN2019/074396 priority patent/WO2020155096A1/zh
Publication of WO2020155096A1 publication Critical patent/WO2020155096A1/zh
Priority to US17/143,877 priority patent/US11469101B2/en

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Definitions

  • the invention relates to the field of microelectronics technology, in particular to a semiconductor structure and a manufacturing method thereof.
  • High Electron Mobility Transistor is a heterojunction field effect transistor. Take the AlGaN/GaN HEMT structure as an example. The band gap of AlGaN is larger than that of GaN. When they form a heterojunction, A two-dimensional electron gas (2DEG) is formed at the interface of AlGaN and GaN, so HEMT is also called 2DEG field effect transistor.
  • 2DEG two-dimensional electron gas
  • doping transition metals such as iron or other impurities into the region located below the 2DEG can improve the pinch-off characteristics or increase the cut-off voltage, but the electrons trapped by the charge traps composed of impurities hinder the formation of 2DEG, especially Prone to current collapse.
  • reducing the impurity doping concentration is beneficial to suppress the current collapse, the thickness of the buffer layer is not adjusted accurately to eliminate the current collapse.
  • a semiconductor structure which is characterized by including:
  • the first buffer layer is co-doped with transition metal and impurities, the doping concentration of the transition metal is kept constant, and the impurity doping concentration is periodically modulated;
  • the doping concentration of the transition metal in the first buffer layer is not less than the peak concentration of impurity doping
  • the second buffer layer is doped with transition metal, and the concentration of the transition metal in the second buffer layer is less than the concentration of the transition metal in the first buffer layer.
  • the concentration of the transition metal doped in the second buffer layer can be reduced in a direction away from the substrate.
  • the semiconductor structure further includes doping impurities in the second buffer layer, and the doping concentration of the transition metal on the upper surface of the second buffer layer is not less than the doping concentration of the impurities , wherein the upper surface of the second buffer layer is the side of the second buffer layer away from the substrate.
  • the semiconductor structure further includes a nucleation layer disposed between the substrate and the buffer layer.
  • the present invention also provides a method for preparing a semiconductor structure, including:
  • the buffer layer includes a first buffer layer and a second buffer layer in order from the substrate upward;
  • the first buffer layer is co-doped with transition metal and impurities, the doping concentration of the transition metal is kept constant, and the impurity doping concentration is periodically modulated;
  • the doping concentration of the transition metal in the first buffer layer is not less than the peak concentration of impurity doping
  • the second buffer layer is doped with transition metal, and the concentration of the transition metal in the second buffer layer is less than the concentration of the transition metal in the first buffer layer.
  • the concentration of the transition metal doped in the second buffer layer can be reduced in a direction away from the substrate.
  • the semiconductor structure further includes doping impurities in the second buffer layer, and the doping concentration of the transition metal on the upper surface of the second buffer layer is not less than the doping concentration of the impurities , wherein the upper surface of the second buffer layer is the side of the second buffer layer away from the substrate.
  • the semiconductor structure further includes a nucleation layer disposed between the substrate and the buffer layer.
  • a buffer layer is provided on the substrate layer.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is doped with a transition metal to form a deep level Traps, capture background electrons, and can effectively avoid the diffusion of free electrons to the substrate; reducing the transition metal concentration in the second buffer layer can avoid the tailing effect of transition metals and prevent current collapse; periodic doping in the buffer layer
  • the impurity impurity makes the impurity as the acceptor impurity to compensate the background electrons and reduce the background concentration.
  • the periodic doping method can effectively reduce the dislocation caused by the doping in the buffer layer.
  • FIG. 1 is a schematic diagram of the semiconductor structure involved in the present invention.
  • 2a-2h are the doping modes of the transition metal concentration and impurity concentration relative to the depth in the semiconductor structure of the present invention.
  • FIG. 3 is a semiconductor structure related to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the semiconductor structure of the present invention applied to a HEMT device.
  • FIG. 5 shows the doping situation of transition metal concentration and impurity concentration in the HEMT device shown in FIG. 4.
  • the manufacturing method of the semiconductor structure includes:
  • a substrate 1 is provided, and a buffer layer 3 is prepared on the substrate 1, wherein the buffer layer 3 includes a first buffer layer 31 and a second buffer layer 32 in order from the substrate upward;
  • the substrate 1 includes semiconductor materials, ceramic materials, and polymer materials, preferably sapphire, silicon carbide, silicon, lithium niobate, silicon insulator (SOI), gallium nitride, aluminum nitride .
  • the first buffer layer 31 is co-doped with transition metal and impurities, the doping concentration of the transition metal is kept constant, and the impurity doping concentration is periodically modulated;
  • the peak concentration of the impurity periodically modulated and doped is not less than 1E17cm -3 , and the valley value is not more than 50% of the peak.
  • the valley value of the periodic modulation and doping of the impurity is not greater than 5e16cm -3 ; further preferably, the valley value of the periodic modulation and doping of the impurity is not greater than 3E16cm -3 .
  • the impurities are used as acceptor impurities in the first buffer layer 31 to compensate for background electrons introduced by other impurities (such as oxygen, etc.).
  • low pressure and low temperature growth conditions are required to achieve high concentration impurity doping. A large number of dislocations are introduced, so periodic impurity doping can effectively reduce the dislocation of the buffer layer.
  • the doping concentration of the transition metal in the first buffer layer 31 is not less than the peak concentration of impurity doping, and the transition metal forms a deep level trap in the buffer layer to trap background electrons.
  • the second buffer layer 32 is doped with a transition metal, and the concentration of the transition metal in the second buffer layer 32 is less than the concentration of the transition metal in the first buffer layer 31.
  • the concentration of the transition metal doped in the second buffer layer 32 decreases toward the direction away from the substrate 1 to avoid the tailing effect of the transition metal and prevent current collapse; the lowest concentration of the transition metal in the second buffer layer 32 Not more than 3E16cm -3 , otherwise the deep level traps formed by the excessively high concentration of transition metals will cause impurities to scatter and reduce mobility.
  • the semiconductor structure further includes doping impurities in the second buffer layer 32, the doping concentration of the transition metal on the upper surface of the second buffer layer 32 is not less than the doping concentration of the impurities, wherein the second buffer layer 32 The upper surface of the buffer layer 32 is the side of the second buffer layer 32 away from the substrate 1.
  • the transition metal includes at least one of Ti, Cr, Mn, Fe, Co, Ni, Cu, Zn, Mo, Ag, Cd, preferably Fe; the impurity is C.
  • the thickness of the first buffer layer 31 is 0.01 ⁇ m to 5 ⁇ m
  • the thickness of the second buffer layer 32 is 0.05 ⁇ m to 5 ⁇ m.
  • the abscissa represents the thickness of the buffer layer 3. Taking the upper surface of the second buffer layer 32 as 0 nm, the thickness of the abscissa increases toward the direction of the substrate; the ordinate represents the doping The concentration of atoms; in this embodiment, the abscissa 0nm-600nm is the second buffer layer 32; 600nm-900nm is the first buffer layer 31, wherein the first buffer layer 31 is doped with transition metal Fe and impurities C, Fe The doping concentration is constant, 1E18cm -3 ; the doping concentration of C changes periodically, with the peak value being 2E17cm -3 and the valley value being 2E16cm -3 . The second buffer layer 32 is not doped with C, and the doping concentration of Fe gradually decreases to 2E16 cm ⁇ 3 .
  • C can be constantly doped in the second buffer layer 32.
  • the first buffer layer 31 is doped with transition metal Fe and impurity C, and the doping concentration of Fe is constant, 1E18 cm -3 ;
  • C The doping concentration changes periodically, with the peak value being 2E17cm -3 and the valley value being 2E16cm -3 ;
  • the second buffer layer 32 is doped with transition metal Fe and impurity C, and the Fe doping concentration gradually decreases to 2E16cm -3 ,
  • the doping concentration of C is constant, 2E16cm -3 .
  • the concentration of C in the second buffer layer 32 may still partly maintain a periodic change.
  • the first buffer layer 31 is doped with transition metal Fe and impurity C, and the doping concentration of Fe is constant. 1E18cm -3 ;
  • the doping concentration of C changes periodically, the peak value is 2E17cm -3 and the valley value is 2E16cm -3 ;
  • the second buffer layer 32 is doped with transition metal Fe and impurity C, and the doping concentration of Fe gradually When it drops to 2E16cm -3 , the concentration of C keeps periodically changing, and keeps a constant value between 0-350nm, which is 2E16cm - 3.
  • the concentration of C is guaranteed to be within the range of 0-350 nm, and no doping can be selected. There is no restriction on the doping mode of C in the second buffer layer, as long as it is close to the second buffer layer 32.
  • the doping concentration of Fe at the upper surface of the middle is not less than the doping concentration of C.
  • the decreasing slope of the Fe concentration in the second buffer layer 32 is variable.
  • the first buffer layer 31 is doped with transition metal Fe and impurity C, and the doping concentration of Fe is constant, which is 1E18cm ⁇ 3 ; C doping concentration changes periodically, the peak value of C doping concentration is 2E17cm -3 , and the valley value is 2E16cm -3 .
  • 32 Fe concentration in the second buffer layer decreases from the 1E18cm -3 600nm is at 9E17cm -3 500nm, then sequentially decreased to at 7E17cm -3 300nm, 5E17cm -3 200nm at, 100 nm or at 3E17cm -3, and finally Lower the upper surface of the second buffer layer to 2E16cm -3 .
  • the temperature of the preparation environment, the thickness of the buffer layer, the bond energy of the doped transition metal, the diffusion activation energy in the doped buffer layer, the metal doping method, and the difference between the buffer layer and the substrate layer The dislocation density and the like will affect the decreasing slope of the Fe doping concentration in the second buffer layer 32 and the minimum concentration value. Therefore, in this case, there are no specific restrictions on the decline trend, manner, and process of the Fe doping concentration in the second buffer layer 32, as long as the Fe doping concentration in the second buffer layer 32 is kept away from the substrate 1. Decrease, and the downward trend and downward slope will become larger and larger.
  • the doping period of C impurity is not fixed.
  • the doping of C impurity takes a thickness of 100 nm as a period
  • the doping of C impurity can Take the thickness of 50nm as a period.
  • the doping concentration of C impurity in the buffer layer changes with the depth to present a rectangular shape periodic modulation; in other embodiments, the doping concentration of the C impurity in the buffer layer changes with the depth.
  • the preparation method may be through atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy), or plasma Enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or physical vapor deposition (PVD, Physical Vapor Deposition), or metal organic source molecular beam epitaxy ( MOMBE, metal-organic molecular beam epitaxy, or metal-organic chemical vapor deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD Atomic layer deposition
  • CVD Chemical Vapor Deposition
  • MBE molecular beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • the method for preparing a semiconductor structure further includes:
  • a nucleation layer 2 is provided between the substrate 1 and the buffer layer 3.
  • the nucleation layer 2 may be one of AlN, GaN, and AlGaN.
  • an embodiment of the present application provides a schematic diagram of a semiconductor structure.
  • the semiconductor structure includes: a substrate 1, a buffer layer 3 provided on the substrate 1, wherein the buffer layer 3 extends from the substrate 1
  • the bottom up includes a first buffer layer 31 and a second buffer layer 32 in sequence.
  • the first buffer layer 31 is co-doped with transition metal and impurities, the doping concentration of the transition metal is kept constant, and the impurity doping concentration is periodically modulated;
  • the peak value of the impurity concentration of the periodic modulation doping is not less than 1E17cm -3 , and the valley value is not more than 50% of the peak value.
  • the valley of the impurity periodically modulated doping concentration is not greater than 5e16 cm -3 ; further preferably, the valley of the impurity periodically modulated doping concentration is not greater than 3E16 cm -3 .
  • the impurities are used as acceptor impurities in the first buffer layer 31 to compensate for background electrons introduced by other impurities (such as oxygen, etc.).
  • low pressure and low temperature growth conditions are required to achieve high concentration impurity doping. A large number of dislocations are introduced, so periodic impurity doping can effectively reduce the dislocation of the buffer layer.
  • the doping concentration of the transition metal in the first buffer layer 31 is not less than the peak concentration of impurity doping, and the transition metal forms a deep level trap in the buffer layer to trap background electrons.
  • the second buffer layer 32 is doped with a transition metal, and the concentration of the transition metal in the second buffer layer 32 is less than the concentration of the transition metal in the first buffer layer 31.
  • the concentration of the transition metal doped in the second buffer layer 32 decreases toward the direction away from the substrate 1, to avoid the tailing effect of the transition metal and prevent current collapse; the minimum concentration of the transition metal in the second buffer layer is not More than 3E16cm -3 , otherwise the deep-level traps formed by the excessively high concentration of transition metals will cause impurities to scatter and reduce mobility.
  • the semiconductor structure further includes: impurities that can be doped in the second buffer layer 32, and the impurity concentration is not greater than the doping concentration of the transition metal in the second buffer layer 32.
  • the transition metal includes at least one of Ti, Cr, Mn, Fe, Co, Ni, Cu, Zn, Mo, Ag, Cd, preferably Fe; the impurity is C.
  • the thickness of the first buffer layer 31 is 0.01 ⁇ m to 5 ⁇ m
  • the thickness of the second buffer layer 32 is 0.05 ⁇ m to 5 ⁇ m.
  • the semiconductor structure may further include a nucleation layer 2 disposed between the substrate 1 and the buffer layer 3.
  • the semiconductor structure can be applied to a variety of device structures, such as high electron mobility transistors, high electron mobility transistors made of aluminum gallium indium nitride/gallium nitride heterostructures, and aluminum nitride/gallium nitride heterostructures.
  • High mobility triode, gallium nitride MOSFET, LED, photodetector, hydrogen generator or solar cell when applied to an LED device, a light-emitting structure can be prepared on the semiconductor structure; when applied to a HEMT device, a heterojunction structure can be epitaxially grown on the semiconductor structure, as shown in FIG. 4.
  • Figure 4 shows a schematic diagram of the semiconductor structure applied to the HEMT device structure, where the HEMT device includes: a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, and a passivation layer 6. , The gate 7, the source 8, and the drain 9, wherein the buffer layer 3 includes a first buffer layer 31 and a second buffer layer 32.
  • the substrate 1 may be a Si substrate, and in other embodiments, the substrate 1 may also be a sapphire substrate or a SiC substrate;
  • the nucleation layer 2 can be AlN; the buffer layer 3 can be AlGaN; the channel layer 4 can be GaN; the barrier layer 5 is AlGaN, and the channel layer 4 and the barrier layer 5 interface 2DEG is formed at the place.
  • the passivation layer 630 may include silicon nitride, silicon dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, and the like.
  • the source 8 and the drain 9 form an ohmic contact with the barrier layer 5, and the gate 7 forms a Schottky contact with the passivation layer 6.
  • the first buffer layer 31 is co-doped with transition metal and impurities, the doping concentration of the transition metal is kept constant, the doping concentration of the impurity is periodically modulated, and the transition metal The doping concentration is greater than the doping concentration of the impurities; the second buffer layer 32 is doped with a transition metal, and the concentration of the transition metal is less than the concentration of the transition metal in the first buffer layer 31; the second buffer layer 32 The concentration of the doped transition metal may decrease in a direction away from the substrate 1.
  • the abscissa represents the thickness of the semiconductor layer, and the upper surface of the second buffer layer 32 is 0 nm, and the upper surface of the second buffer layer 32 is the distance of the second buffer layer 32 away from the substrate 1. That side; the ordinate is the concentration of doping atoms; in this embodiment, the negative axis of the abscissa is the direction of the channel layer, 0nm-600nm is the second buffer layer 32, 600nm-900nm is the first buffer layer 31, and greater than 900nm is Direction of nucleation layer.
  • the first buffer layer 31 is doped with transition metal Fe and impurity C.
  • the doping concentration of Fe is constant, 1E18cm -3 , and the Fe forms a deep main energy level in the first buffer layer AlGaN. , Forming an electron trap to capture background electrons; it can also effectively prevent free electrons in the 2DEG from escaping toward the substrate; the C doping concentration changes periodically, the peak C doping concentration is 2E17cm -3 and the valley value is 2E16cm -3 .
  • the doping concentration of Fe in the second buffer layer 32 gradually decreases to 2E16 cm ⁇ 3 , and the doping of Fe is stopped at the upper surface (0 nm) of the second buffer layer 32, and the doping concentration of Fe drops rapidly.
  • the first buffer layer in the semiconductor structure is doped with transition metal to form deep-level traps, trap background electrons, and can effectively prevent the diffusion of free electrons to the substrate; in the second buffer layer Decreasing the transition metal concentration can avoid the tailing effect of transition metals and prevent current collapse; periodically doping impurities in the buffer layer makes the impurities act as acceptor impurities, compensating for background electrons, reducing background concentration, and adopting periodic doping The method can effectively reduce the dislocation caused by doping in the buffer layer.

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Abstract

本发明提出了一种半导体结构及其制备方法，在衬底层之上设置缓冲层，所述缓冲层包括第一缓冲层和第二缓冲层，在第一缓冲层掺杂过渡金属可以形成深能级陷阱，捕获背景电子，还可避免自由电子向衬底方向的扩散；第二缓冲层中降低过渡金属浓度避免拖尾效应，防止电流崩塌；在缓冲层中周期性的掺杂杂质，使得杂质作为受主杂质，补偿背景电子，减小背景浓度，采用周期性掺杂的方法，可以有效减少缓冲层中因为掺杂而引起的位错。

Description

一种半导体结构及其制造方法 技术领域
本发明涉及微电子技术领域，具体涉及一种半导体结构及其制造方法。
发明背景
高电子迁移率晶体管(HEMT，High Electron Mobility Transistor)是一种异质结场效应晶体管，以AlGaN/GaN HEMT结构为例，AlGaN的禁带宽度比GaN的大，它们形成异质结时，在AlGaN和GaN界面处形成二维电子气(2DEG)，因此HEMT又被称为2DEG场效应晶体管。
对于GaN类的HEMT来说，将铁等过渡金属或其它杂质向位于2DEG下部的区域掺杂可以改善夹断特性或提高截止电压，但是由杂质构成的电荷陷阱捕获的电子妨碍2DEG的形成，特别容易产生电流崩塌。虽然降低杂质掺杂浓度有利于抑制电流崩塌，但是调控不准缓冲层的厚度依然不能够消除电流崩塌。
发明内容
有鉴于此，急需提出一种半导体结构及其制备方法，可以在抑制泄漏电流、提升器件夹断特性的同时避免电流崩塌，使得应用该半导体结构的器件在动态特性时漏电流保持平衡。
本发明在一实施例中提供了一种半导体结构，其特征在于，包括：
衬底；
设于所述衬底上的缓冲层，所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
其中，所述第一缓冲层中共掺杂过渡金属和杂质，所述过渡金属的掺杂浓度保持恒定，所述杂质掺杂浓度呈周期性调制；
其中，所述第一缓冲层中过渡金属的掺杂浓度不小于杂质掺杂的峰值浓度；
其中，所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓 度小于第一缓冲层中过渡金属的浓度。
进一步的，在本发明一实施例中，所述第二缓冲层掺杂的过渡金属浓度可向远离衬底的方向降低。
进一步的，在本发明一实施例中，所述半导体结构还包括在所述第二缓冲层中掺杂杂质，所述第二缓冲层上表面过渡金属的掺杂浓度不小于杂质的掺杂浓度，其中所述第二缓冲层上表面为第二缓冲层中远离衬底的一面。
进一步的，在本发明一实施例中，所述的半导体结构还包括成核层，设于所述衬底与所述缓冲层之间。
本发明还提供一种制备半导体结构的方法，包括：
提供一衬底；
在所述衬底上制备缓冲层，其中所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
其中，所述第一缓冲层中共掺杂过渡金属和杂质，所述过渡金属的掺杂浓度保持恒定，所述杂质掺杂浓度呈周期性调制；
其中，所述第一缓冲层中过渡金属的掺杂浓度不小于杂质掺杂的峰值浓度；
其中，所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层中过渡金属的浓度。
进一步的，在本发明一实施例中，所述第二缓冲层掺杂的过渡金属浓度可向远离衬底的方向降低。
进一步的，在本发明一实施例中，所述半导体结构还包括在所述第二缓冲层中掺杂杂质，所述第二缓冲层上表面过渡金属的掺杂浓度不小于杂质的掺杂浓度，其中所述第二缓冲层上表面为第二缓冲层中远离衬底的一面。
进一步的，在本发明一实施例中，所述半导体结构还包括成核层，设于所述衬底与所述缓冲层之间。
本发明所提供的半导体结构及其制备方法，在衬底层之上设置缓冲层，所述缓冲层包括第一缓冲层和第二缓冲层，在第一缓冲层掺杂过渡金属可以形成深能级陷阱，捕获背景电子，此外还可以有效避免自由电子向衬底方向的扩散； 第二缓冲层中降低过渡金属浓度可以避免过渡金属的拖尾效应，防止电流崩塌；在缓冲层中周期性的掺杂杂质，使得杂质作为受主杂质，补偿背景电子，减小背景浓度，采用周期性掺杂的方法，可以有效减少缓冲层中因为掺杂而引起的位错。
附图简要说明
图1为本发明涉及的半导体结构示意图。
图2a-2h为本发明半导体结构中过渡金属浓度和杂质浓度相对于深度变化的掺杂方式。
图3为本发明另一实施例涉及的半导体结构。
图4为本发明半导体结构应用于HEMT器件的示意图。
图5为图4所示的HEMT器件中过渡金属浓度和杂质浓度的掺杂情况。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例和/或结构之间具有任何关联性。
所述半导体结构的制备方法包括：
如图1所示，提供一衬底1，在所述衬底1上制备缓冲层3，其中所述缓冲层3从衬底向上依次包括第一缓冲层31、第二缓冲层32；
本实施例中，所述衬底1包括半导体材料、陶瓷材料、高分子材料，优选的是蓝宝石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓、氮化铝。
其中，所述第一缓冲层31中共掺杂过渡金属和杂质，所述过渡金属的掺杂浓度保持恒定，所述杂质掺杂浓度呈周期性调制；
本实施例中，所述杂质周期性调制掺杂的浓度峰值不小于1E17cm -3，谷值不大于峰值的50％。优选的是，所述杂质周期性调制掺杂的谷值不大于5e16cm -3；进一步优选的是，所述杂质周期性调制掺杂的谷值不大于3E16cm -3。所述杂质在第一缓冲层31中作为受主杂质，补偿其它部分杂质(例如氧等)引入的背景电子，此外，要想实现高浓度的杂质掺杂需要低压、低温等生长条件，通常会引入大量的位错，因而周期性的杂质掺杂可以有效减少缓冲层的位错。
进一步的，所述第一缓冲层31中过渡金属的掺杂浓度不小于杂质掺杂的峰值浓度，过渡金属在缓冲层内形成深能级陷阱，俘获背景电子。
进一步的，所述第二缓冲层32中掺杂过渡金属，所述第二缓冲层32中过渡金属的浓度小于第一缓冲层31中过渡金属的浓度。
进一步的，所述第二缓冲层32掺杂的过渡金属浓度向远离衬底1的方向降低，避免过渡金属的拖尾效应，防止电流崩塌；所述第二缓冲层32中过渡金属的最低浓度不大于3E16cm -3，否则过高浓度的过渡金属形成的深能级陷阱会导致杂质散射，降低迁移率。
进一步的，所述半导体结构还包括在所述第二缓冲层32中掺杂杂质，所述第二缓冲层32上表面过渡金属的掺杂浓度不小于杂质的掺杂浓度，其中所述第二缓冲层32上表面为第二缓冲层32中远离衬底1的一面。
进一步的，所述的过渡金属包括Ti、Cr、Mn、Fe、Co、Ni、Cu、Zn、Mo、Ag、Cd中的至少一种，优选为Fe；所述的杂质为C。
进一步的，所述第一缓冲层31的厚度为0.01μm～5μm，所述第二缓冲层32的厚度为0.05μm～5μm。
具体的，如图2a所示，横坐标表示缓冲层3的厚度，以第二缓冲层32的上表面为0nm，越向衬底的方向，横坐标的厚度值越大；纵坐标为掺杂原子的浓度；本实施例中横坐标0nm-600nm为第二缓冲层32；600nm-900nm为第一缓冲层31，其中所述第一缓冲层31中掺杂过渡金属Fe和杂质C，Fe的掺杂浓度恒定，为1E18cm -3；C的掺杂浓度呈周期性变化，其中峰值为2E17cm -3，谷值为2E16cm -3。所述第二缓冲层32中不掺杂C，Fe的掺杂浓度逐渐下降至2E16cm -3。
进一步的，在第二缓冲层32中可恒定掺杂C，如图2b所示，第一缓冲层31中掺杂过渡金属Fe和杂质C，Fe的掺杂浓度恒定，为1E18cm -3；C的掺杂浓度呈周期性变化，其中峰值为2E17cm -3，谷值为2E16cm -3；在第二缓冲层32中掺杂过渡金属Fe和杂质C，Fe的掺杂浓度逐渐下降至2E16cm -3，C的掺杂浓度恒定，为2E16cm -3。
进一步的，第二缓冲层32中C的浓度也可以依然部分保持周期性变化，如图2c所示，第一缓冲层31中掺杂过渡金属Fe和杂质C，Fe的掺杂浓度恒定，为1E18cm -3；C的掺杂浓度呈周期性变化，其中峰值为2E17cm -3，谷值为2E16cm -3；在第二缓冲层32中掺杂过渡金属Fe和杂质C，Fe的掺杂浓度逐渐下降至2E16cm -3，C的浓度部分保持周期性变化，在0-350nm之间保持恒定值，为2E16cm -3。可以理解的是，所述的C的浓度保证在在0-350nm之间也可以选择不掺杂，在此不对第二缓冲层中C的掺杂方式做限制，只要保证靠近第二缓冲层32中的上表面处(即远离第一缓冲层31的表面)Fe的掺杂浓度不小于C的掺杂浓度即可。
进一步的，第二缓冲层32中Fe浓度的下降斜率是可变化的，如图2d所示，第一缓冲层31中掺杂过渡金属Fe和杂质C，Fe的掺杂浓度恒定，为1E18cm -3；C的掺杂浓度呈周期性变化，C掺杂浓度的峰值为2E17cm -3，谷值为2E16cm -3。在第二缓冲层32中Fe浓度从600nm处的1E18cm -3下降为500nm处的9E17cm -3，再依次下降至300nm处的7E17cm -3，200nm处的5E17cm -3，100nm处3E17cm -3，最后在第二缓冲层的上表面下降至2E16cm -3。
可以理解的是，制备环境的温度、缓冲层的厚度、所掺杂过渡金属的键能、所掺杂缓冲层中的扩散激活能、金属的掺杂方式、以及缓冲层与衬底层之间的位错密度等都会影响所述第二缓冲层32中Fe掺杂浓度的下降斜率以及最低浓度值。因此，本案对于第二缓冲层32中Fe掺杂浓度的下降趋势、下降方式、下降过程不做具体限制，只要保证所述第二缓冲层32中Fe的掺杂浓度向远离衬底1的方向降低，并且下降趋势、下降斜率越来越大即可。
可以理解的是，C杂质的掺杂周期并不是固定的，如图2a-2d中，C杂质 的掺杂是以100nm的厚度作为一个周期，而在图2e中，C杂质的掺杂可以是以50nm的厚度作为一个周期。
上述实施例中，C杂质的掺杂浓度在缓冲层中随着深度变化呈现出矩形形状的周期调制；在其它实施例中，所述C杂质的掺杂浓度在缓冲层中随着深度变化可以呈现出梯形(如图2f)或者三角形(如图2g)或者其结合(如图2h)的周期调制。可以理解的是，本案对杂质周期调制掺杂所呈现的形状不做限制，只要保证第一缓冲层31中杂质是周期掺杂即可。
进一步的，所述的制备方法可以是通过原子层沉积(ALD,Atomic layer deposition)、或化学气相沉积(CVD，Chemical Vapor Deposition)、或分子束外延生长(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积(LPCVD，Low Pressure Chemical Vapor Deposition)，或物理气相沉积(PVD，Physical Vapor Deposition)，或金属有机源分子束外延(MOMBE，metal-organic molecular beam epitaxy)，或金属有机化合物化学气相沉积(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式制得。
进一步的，所述制备半导体结构的方法还包括：
如图3所示，在所述衬底1与所述缓冲层3之间设置成核层2，所述成核层2可为AlN，GaN，AlGaN中的一种。
如图3所示，本申请实施例提供了一种半导体结构的示意图，该半导体结构包括：衬底1，设于所述衬底1上的缓冲层3，其中所述的缓冲层3从衬底向上依次包括第一缓冲层31和第二缓冲层32。
其中，所述第一缓冲层31中共掺杂过渡金属和杂质，所述过渡金属的掺杂浓度保持恒定，所述杂质掺杂浓度呈周期性调制；
其中所述周期性调制掺杂的杂质浓度的峰值不小于1E17cm -3，谷值不大于峰值的50％。优选的是，所述杂质周期性调制掺杂浓度的谷值不大于5e16cm -3；进一步优选的是，所述杂质周期性调制掺杂浓度的谷值不大于3E16cm -3。所述杂质在第一缓冲层31中作为受主杂质，补偿其它部分杂质(例如氧等)引入 的背景电子，此外，要想实现高浓度的杂质掺杂需要低压、低温等生长条件，通常会引入大量的位错，因而周期性的杂质掺杂可以有效减少缓冲层的位错。
进一步的，所述第一缓冲层31中过渡金属的掺杂浓度不小于杂质掺杂的峰值浓度，过渡金属在缓冲层内形成深能级陷阱，俘获背景电子。
进一步的，所述第二缓冲层32中掺杂过渡金属，所述第二缓冲层32中过渡金属的浓度小于第一缓冲层31中过渡金属的浓度。
进一步的，所述第二缓冲层32掺杂的过渡金属浓度向远离衬底1的方向降低，避免过渡金属的拖尾效应，防止电流崩塌；所述第二缓冲层中过渡金属的最低浓度不大于3E16cm -3，否则过高浓度的过渡金属形成的深能级陷阱会导致杂质散射，降低迁移率。
进一步的，所述半导体结构还包括：所述第二缓冲层32中可掺杂杂质，所述杂质浓度不大于第二缓冲层32中过渡金属的掺杂浓度。
进一步的，所述的过渡金属包括Ti、Cr、Mn、Fe、Co、Ni、Cu、Zn、Mo、Ag、Cd中的至少一种，优选为Fe；所述的杂质为C。
进一步的，所述的第一缓冲层31的厚度为0.01μm～5μm，所述的第二缓冲层32的厚度为0.05μm～5μm。
本实施例中，为了降低位错密度和缺陷密度，防止回熔，该半导体结构还可以进一步包括设置于衬底1和缓冲层3之间的成核层2。
该半导体结构可应用于多种器件结构当中，例如高电子迁移率晶体管、铝镓铟氮/氮化镓异质结构成的高电子迁移率晶体管、氮化铝/氮化镓异质结构成的高迁移率三极管、氮化镓MOSFET、LED、光电探测器、氢气产生器或太阳能电池。例如应用于LED器件时，可在该半导体结构上制备发光结构；而应用于HEMT器件时，可在该半导体结构上外延生长异质结结构，如图4。
图4给出了在该半导体结构应用于HEMT器件结构的示意图，其中该HEMT器包括：衬底1、成核层2、缓冲层3、沟道层4、势垒层5、钝化层6、栅极7、源极8、漏极9，其中缓冲层3包括第一缓冲层31和第二缓冲层32。
本实施例中，所述的衬底1可以为Si衬底，在其他实施例中，所述的衬 底1也可以是蓝宝石衬底或者SiC衬底；
本实施例中，所述的成核层2可以是AlN；缓冲层3可以是AlGaN；沟道层4可以是GaN；势垒层5为AlGaN，所述沟道层4与势垒层5界面处形成2DEG。
本实施例中，所述钝化层630可以包括氮化硅、二氧化硅、氮化铝、氧化铝、氧氮铝等。
本实施例中，所述的源极8、漏极9与势垒层5形成欧姆接触，所述的栅极7与钝化层6形成肖特基接触。
本实施例中，所述第一缓冲层31中共掺杂过渡金属和杂质，所述的过渡金属的掺杂浓度保持恒定，所述的杂质掺杂浓度呈周期性调制，所述的过渡金属的掺杂浓度大于所述杂质的掺杂浓度；所述第二缓冲层32中掺杂过渡金属，所述过渡金属的浓度小于第一缓冲层31中过渡金属的浓度；所述第二缓冲层32掺杂的过渡金属浓度可向远离衬底1的方向降低。
具体的，如图5所示，横坐标表示半导体层的厚度，以第二缓冲层32的上表面为0nm，所述第二缓冲层32的上表面为第二缓冲层32远离衬底1的那一面；纵坐标为掺杂原子的浓度；本实施例中横坐标负轴方向为沟道层方向，0nm-600nm为第二缓冲层32，600nm-900nm为第一缓冲层31，大于900nm为成核层方向。本实施例中，所述第一缓冲层31中掺杂过渡金属Fe和杂质C，Fe的掺杂浓度恒定，为1E18cm -3，所述Fe在第一缓冲层AlGaN中形成深受主能级，形成电子陷阱俘获背景电子；还可以有效避免2DEG中的自由电子向衬底方向逃逸；C的掺杂浓度呈周期性变化，C掺杂浓度的峰值为2E17cm -3，谷值为2E16cm -3。所述第二缓冲层32中Fe的掺杂浓度逐渐下降至2E16cm -3，在第二缓冲层32的上表面(0nm)处停止Fe的掺杂，Fe的掺杂浓度急速下降。
通过本实施例技术方案，该半导体结构中的第一缓冲层掺杂过渡金属可以形成深能级陷阱，捕获背景电子，此外还可以有效避免自由电子向衬底方向的扩散；第二缓冲层中降低过渡金属浓度可以避免过渡金属的拖尾效应，防止电流崩塌；在缓冲层中周期性的掺杂杂质，使得杂质作为受主杂质，补偿背景电子，减小背景浓度，采用周期性掺杂的方法，可以有效减少缓冲层中因为掺杂 而引起的位错。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    设于所述衬底上的缓冲层，其中所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
    其中，所述第一缓冲层中共掺杂过渡金属和杂质，所述过渡金属的掺杂浓度保持恒定，所述杂质掺杂呈周期性调制；
    其中，所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层中过渡金属的浓度；
    其中，所述第一缓冲层中过渡金属的掺杂浓度不小于杂质掺杂的峰值浓度。
  2. 根据权利要求1所述的半导体器件，其特征在于：所述的半导体结构还包括在所述第二缓冲层中掺杂杂质，所述第二缓冲层上表面过渡金属的掺杂浓度不小于杂质的掺杂浓度，其中所述第二缓冲层上表面为第二缓冲层中远离衬底的一面。
  3. 根据权利要求1或2所述的半导体器件，其特征在于：所述第二缓冲层掺杂的过渡金属浓度向远离衬底的方向降低；
  4. 根据权利要求1或2所述的半导体器件，其特征在于：所述杂质周期性调制掺杂的浓度峰值不小于1E17cm -3，谷值不大于峰值的50％。
  5. 根据权利要求1或2所述的半导体器件，其特征在于：所述第二缓冲层中过渡金属的最低浓度不大于3E16cm -3。
  6. 根据权利要求1或2所述的半导体器件，其特征在于：所述的过渡金属为Ti、Cr、Mn、Fe、Co、Ni、Cu、Zn、Mo、Ag、Cd中的至少一种。
  7. 根据权利要求1或2所述的半导体器件，其特征在于：所述的杂质为C。
  8. 根据权利要求1或2所述的半导体器件，其特征在于：所述第一缓冲层的厚度为0.01μm～5μm，所述第二缓冲层的厚度为0.05μm～5μm。
  9. 根据权利要求1或2所述的半导体器件，其特征在于：所述衬底为半导 体材料、陶瓷材料、高分子材料，包括蓝宝石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓、氮化铝。
  10. 一种制备半导体结构的方法，包括：
    提供一衬底；
    在所述衬底上制备缓冲层，其中所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
    其中，所述第一缓冲层中共掺杂过渡金属和杂质，所述过渡金属的掺杂浓度保持恒定，所述杂质掺杂呈周期性调制；
    其中，所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层中过渡金属的浓度；
    其中，所述第一缓冲层中过渡金属的掺杂浓度不小于杂质掺杂的峰值浓度。
  11. 根据权利要求10所述的制备半导体结构的方法，其特征在于：所述半导体结构的制备方法还包括在所述第二缓冲层中掺杂杂质，所述第二缓冲层上表面过渡金属的掺杂浓度不小于杂质的掺杂浓度，其中所述第二缓冲层上表面为第二缓冲层中远离衬底的一面。
  12. 根据权利要求10或11所述的制备半导体结构的方法，其特征在于：所述第二缓冲层掺杂的过渡金属浓度向远离衬底的方向降低。
  13. 根据权利要求10或11所述的制备半导体结构的方法，其特征在于：所述周期性调制掺杂的杂质浓度的峰值为不小于1E17cm -3，谷值不大于峰值的50％。
  14. 根据权利要求10或11所述的制备半导体结构的方法，其特征在于：所述第二缓冲层中过渡金属的最低浓度不大于3E16cm -3。
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