WO2020152522A1 - 半導体装置および当該半導体装置を有する電気機器 - Google Patents

半導体装置および当該半導体装置を有する電気機器 Download PDF

Info

Publication number
WO2020152522A1
WO2020152522A1 PCT/IB2019/059906 IB2019059906W WO2020152522A1 WO 2020152522 A1 WO2020152522 A1 WO 2020152522A1 IB 2019059906 W IB2019059906 W IB 2019059906W WO 2020152522 A1 WO2020152522 A1 WO 2020152522A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
oxide
insulator
layer
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2019/059906
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
大貫達也
八窪裕人
岡本佑樹
齋藤聖矢
加藤清
山崎舜平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN201980089579.4A priority Critical patent/CN113330552A/zh
Priority to KR1020217024567A priority patent/KR20210120003A/ko
Priority to US17/422,312 priority patent/US12426378B2/en
Priority to JP2020567657A priority patent/JP7462575B2/ja
Publication of WO2020152522A1 publication Critical patent/WO2020152522A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024050247A priority patent/JP2024083377A/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors

Definitions

  • a semiconductor device is a device that utilizes semiconductor characteristics, and includes a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. In addition, it refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including the integrated circuit, and an electronic component in which the chip is housed in a package are examples of semiconductor devices.
  • a memory device, a display device, a light-emitting device, a lighting device, an electronic device, or the like is a semiconductor device in its own right and may have a semiconductor device.
  • IGZO In-Ga-Zn oxides called "IGZO” and "Igzo” are typical multi-element metal oxides.
  • CAAC c-axis aligned crystalline
  • nc nanocrystalline
  • a transistor including a metal oxide semiconductor in a channel formation region (hereinafter also referred to as an “oxide semiconductor transistor” or an “OS transistor”) has been reported to have a minimum off-state current (eg, non-electric current).
  • Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).
  • Patent Document 1 discloses a configuration in which a plurality of layers of a memory cell array having OS transistors are stacked on a substrate provided with Si transistors.
  • Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure in which a semiconductor device which functions as a memory device utilizing an extremely low off-state current has small fluctuations in electrical characteristics of a transistor and which is highly reliable.
  • One embodiment of the present invention is a silicon substrate having a first element layer having a first memory cell, a second element layer having a second memory cell, a third element layer having a switching circuit, and a driver circuit. And the first element layer is provided between the silicon substrate and the second element layer, the third element layer is provided between the silicon substrate and the first element layer,
  • the first memory cell has a first transistor and a first capacitor, the second memory cell has a second transistor and a second capacitor, and the switching circuit has a first memory cell or a first capacitor.
  • a second transistor having a function of controlling conduction between the two memory cells and the driver circuit, one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are respectively provided.
  • the third transistor is electrically connected to a wiring for electrically connecting to one of a source and a drain of the third transistor, the other of the source and the drain of the third transistor is electrically connected to a drive circuit, and the wiring is a first wiring.
  • a semiconductor device is provided in contact with a first semiconductor layer of a transistor and a second semiconductor layer of a second transistor, and provided in a direction perpendicular or substantially perpendicular to the surface of a silicon substrate.
  • a semiconductor device in which the first semiconductor layer and the second semiconductor layer each include a metal oxide in a channel formation region is preferable.
  • a semiconductor device in which the first capacitor is provided below the first semiconductor layer and the second capacitor is provided below the second semiconductor layer is preferable.
  • a semiconductor device in which the first capacitor is provided on the upper layer of the first semiconductor layer and the second capacitor is provided on the upper layer of the second semiconductor layer is preferable.
  • one electrode of the first capacitor is provided in the same layer as the first semiconductor layer and one electrode of the second capacitor is provided in the same layer as the second semiconductor layer. preferable.
  • One embodiment of the present invention includes a first element layer having a first memory cell, a second element layer having a second memory cell, a third element layer having a first control circuit, and a driver circuit.
  • a silicon substrate, the first element layer is provided between the silicon substrate and the second element layer, and the third element layer is the silicon substrate and the first element.
  • the first memory cell includes a first transistor and a first capacitor, and the second memory cell includes a second transistor and a second capacitor.
  • the first control circuit has a third transistor for amplifying a signal read from the first memory cell, and one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are Each of them is electrically connected to a first wiring for electrically connecting to the gate of the third transistor, and one of a source and a drain of the third transistor is electrically connected to a second wiring for electrically connecting to the driving circuit. Electrically connected to each other, the first wiring is in contact with the first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor, and is in a vertical direction or a substantially vertical direction with respect to the surface of the silicon substrate. And the second wiring is provided in a direction parallel or substantially parallel to the first wiring.
  • the first control circuit includes a fourth transistor, one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the third transistor, A semiconductor device in which the other of the source and the drain of the fourth transistor is electrically connected to the second wiring is preferable.
  • the first control circuit includes a fifth transistor and a sixth transistor, one of a source and a drain of the fifth transistor is electrically connected to a gate of the third transistor, The other of the source and the drain of the fifth transistor is electrically connected to the second wiring, and the one of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the third transistor. It is preferable that the semiconductor device has the other of the source and the drain of the sixth transistor electrically connected to the ground line.
  • the first semiconductor layer and the second semiconductor layer each include a metal oxide in a channel formation region.
  • the metal oxide is preferably a semiconductor device containing In, Ga, and Zn.
  • the first capacitor is provided in a lower layer of the first semiconductor layer, and the second capacitor is provided in a lower layer of the second semiconductor layer.
  • the first capacitor is provided on an upper layer of the first semiconductor layer, and the second capacitor is provided on an upper layer of the second semiconductor layer.
  • one electrode of the first capacitor is provided in the same layer as the first semiconductor layer, and one electrode of the second capacitor is provided in the same layer as the second semiconductor layer.
  • Semiconductor devices are preferred.
  • One embodiment of the present invention includes a first element layer having a first memory cell and a second element layer having a second memory cell, and the first element layer and the second element layer.
  • the first memory cell has a first transistor and a first capacitor
  • the second memory cell has a second transistor and a third transistor.
  • a second capacitor one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor
  • one of a source and a drain of the second transistor is A semiconductor device electrically connected to the gate of the third transistor and one electrode of the second capacitor.
  • a semiconductor device having a substrate and the second element layer provided between the substrate and the first element layer is preferable.
  • the first transistor has a first semiconductor layer
  • the second transistor has a second semiconductor layer
  • the first semiconductor layer and the second semiconductor layer each form a channel.
  • a semiconductor device having a metal oxide in the region is preferable.
  • the metal oxide is preferably a semiconductor device containing In, Ga, and Zn.
  • a semiconductor device or the like having a novel structure can be provided.
  • a semiconductor device or the like having a novel structure which can reduce manufacturing cost can be provided in a semiconductor device which functions as a memory device utilizing a minimum off-state current.
  • a semiconductor device or the like which has a novel structure and is excellent in low power consumption can be provided in a semiconductor device which functions as a memory device utilizing a minimum off-state current.
  • a semiconductor device or the like which has a novel structure and can be downsized in a semiconductor device which functions as a memory device utilizing a minimum off-state current can be provided.
  • a semiconductor device which functions as a memory device utilizing a minimum off-state current
  • a semiconductor device or the like having a novel structure in which variation in electric characteristics of a transistor is small and reliability is excellent can be provided. ..
  • FIG. 1A and 1B are a block diagram and a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 3 is a schematic view (A) and a schematic view (B) showing a configuration example of a semiconductor device.
  • FIG. 4 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 5 is a timing chart showing a configuration example of a semiconductor device.
  • FIG. 6 is an (A) block diagram and a (B) schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 7 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 1A and 1B are a block diagram and a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 3 is
  • FIG. 9 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 10 is a schematic view (A) and a schematic view (B) showing a configuration example of a semiconductor device.
  • FIG. 11 is a block diagram (A) and a schematic diagram (B) showing a configuration example of a semiconductor device.
  • FIG. 12 is an (A) block diagram and a (B) circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 13 is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 14 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 15 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 16 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 17 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 18 is an (A) circuit diagram and a (B) circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 19 is an (A) circuit diagram and a (B) circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 20 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 21 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 22 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 23 is a timing chart showing a configuration example of a semiconductor device.
  • FIG. 24 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 24 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 25 is an (A) block diagram and a (B) schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 26 is a schematic diagram showing a configuration example of a semiconductor device.
  • 27A and 27B are a schematic diagram and a schematic diagram, respectively, illustrating a configuration example of a semiconductor device.
  • FIG. 28 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 29 is a timing chart showing a configuration example of a semiconductor device.
  • FIG. 30 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • FIG. 31 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 32 is a schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 33 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • FIG. 34 is a schematic sectional view showing a configuration example of a semiconductor device.
  • FIG. 35 is a schematic sectional view (A) and a schematic sectional view (B) showing a configuration example of a semiconductor device.
  • 36A and 36B are an (A) cross-sectional schematic diagram, a (B) cross-sectional schematic diagram, and a (C) cross-sectional schematic diagram showing a configuration example of a semiconductor device.
  • FIG. 37 is a schematic sectional view showing a configuration example of a semiconductor device.
  • FIG. 38 is a schematic sectional view showing a configuration example of a semiconductor device.
  • 39A is a top view
  • FIG. 39B is a schematic cross-sectional view
  • FIG. 39C is a schematic cross-sectional view.
  • 40A to 40D are top views illustrating a structural example of a semiconductor device.
  • 41A and 41B are diagrams illustrating classification of crystal structures of (A) IGZO, (B) a diagram illustrating an XRD spectrum of a CAAC-IGZO film, and (C) a diagram illustrating a micro electron diffraction pattern of the CAAC-IGZO film.
  • Is. 42 is a block diagram illustrating a structural example of a semiconductor device.
  • FIG. 43 is a conceptual diagram showing a configuration example of a semiconductor device.
  • FIG. 44 is an (A) graph and a (B) graph showing a configuration example of a semiconductor device.
  • FIG. 45 is a schematic diagram (A) and a schematic diagram (B) illustrating an example of an electronic component.
  • FIG. 46 is a diagram illustrating an example of an electronic device.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion among constituent elements. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. Further, for example, a constituent element referred to as “first” in one of the embodiments of the present specification and the like is a constituent element referred to as “second” in another embodiment or in the claims. There is a possibility. Further, for example, the component referred to as “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or the claims.
  • the power supply potential VDD may be abbreviated as the potentials VDD, VDD, and the like. This also applies to other components (eg, signals, voltages, circuits, elements, electrodes, wirings, etc.).
  • the codes are used for identifying "_1”, “_2”, “[n]”, “[m,n]”, etc. In some cases, the symbol is added.
  • the second wiring GL is described as a wiring GL[2].
  • a semiconductor device is a device that uses semiconductor characteristics, and is a circuit that includes semiconductor elements (transistors, diodes, photodiodes, etc.), and a device that has the same circuit.
  • the semiconductor device described in this embodiment can function as a semiconductor device which functions as a memory device using a transistor with a minimum off-state current.
  • FIG. 1A is a block diagram of a semiconductor device described in this embodiment.
  • the semiconductor device 10 illustrated in FIG. 1A includes a peripheral circuit 20 and a memory cell array 30.
  • the peripheral circuit 20 has a row driver 21 and a column driver 22.
  • the row driver 21 and the column driver 22 may be simply called a drive circuit or a driver.
  • the row driver 21 is a circuit having a function of outputting a signal for driving the memory cell array 30 to the word line WL. Specifically, the row driver 21 has a function of transmitting a word signal to a word line WL (WL_1 and WL_N are illustrated in FIG. 1A; N is a natural number of 2 or more).
  • the row driver 21 may be referred to as a word line side driving circuit.
  • the row driver 21 includes a decoder circuit for selecting the word line WL corresponding to the designated address, a buffer circuit, and the like.
  • the word line WL may be simply referred to as a wiring.
  • the column driver 22 is a circuit having a function of outputting a signal for driving the memory cell array 30 to the bit line BL. Specifically, the column driver 22 has a function of transmitting a data signal to the bit line BL (BL_1 and BL_2 in FIG. 1A).
  • the column driver 22 may be referred to as a bit line side driving circuit.
  • the column driver 22 includes a sense amplifier, a precharge circuit, a decoder circuit for selecting a bit line according to a designated address, and the like.
  • the bit line BL may be simply referred to as a wiring. In the drawings, the bit line BL may be illustrated by a thick line, a thick dotted line, or the like in order to improve visibility.
  • the data signal given to the bit line BL corresponds to a signal written to the memory cell or a signal read from the memory cell.
  • the data signal will be described as a binary signal having a high-level or low-level potential corresponding to data 1 or data 0. It should be noted that the data signal may be multivalued with three or more values.
  • the high-level potential is VDD
  • the low-level potential is VSS
  • the ground potential (GND) As the signal applied to the bit line BL, there are a data signal, a precharge potential for reading data, and the like.
  • the precharge potential can be VDD/2.
  • the memory cell array 30 has a plurality of, for example, N layer (N is a natural number of 2 or more) element layers 34_1 to 34_N.
  • the element layer 34_1 includes one or more memory cells 31_1.
  • the memory cell 31_1 includes the transistor 32_1 and the capacitor 33_1.
  • the element layer 34_N includes one or more memory cells 31_N.
  • the memory cell 31_N includes a transistor 32_N and a capacitor 33_N.
  • the capacitor may be called a capacitive element.
  • the element layer is a layer in which elements such as capacitors and transistors are provided, and is a layer formed of a member such as a conductor, a semiconductor, or an insulator.
  • the transistors 32_1 to 32_N function as switches whose on or off are controlled according to the word signals given to the word lines WL_1 to WL_N.
  • one of a source and a drain is connected to one of the bit lines BL (BL_1 in the drawing).
  • each of the transistors 32_1 to 32_N includes a transistor including an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor).
  • an OS transistor a transistor including an oxide semiconductor in a channel formation region
  • a memory cell including an OS transistor is used, so that a desired leakage current (hereinafter referred to as off current) flowing between a source and a drain at the time of off is used, which is desired.
  • off current a desired leakage current flowing between a source and a drain at the time of off
  • the charge depending on the voltage can be held in the capacitors 33_1 to 33_N in the other of the source and the drain. That is, once written data can be held in the memory cells 31_1 to 31_N for a long time. Therefore, it is possible to reduce the frequency of data refresh and reduce power consumption.
  • the memory cells 31_1 to 31_N including the OS transistors data can be rewritten and read by charging or discharging electric charge, so that data can be written and read virtually unlimited times.
  • the memory cells 31_1 to 31_N using the OS transistors have excellent rewriting resistance because they do not involve structural changes at the atomic level unlike magnetic memories or resistance change type memories. Further, in the memory cells 31_1 to 31_N including the OS transistors, instability due to an increase in electron trap centers is not recognized even when a rewriting operation is repeatedly performed like a flash memory.
  • the memory cells 31_1 to 31_N each including an OS transistor can be freely arranged over a silicon substrate having a transistor including silicon (hereinafter referred to as a Si transistor) in a channel formation region, and thus can be easily integrated. it can.
  • the OS transistor can be manufactured at low cost because it can be manufactured using a manufacturing apparatus similar to that of the Si transistor.
  • the OS transistor can be made into a four-terminal semiconductor element by including a back gate electrode in addition to the gate electrode, the source electrode and the drain electrode.
  • the OS transistor can be configured by an electric circuit network in which input/output of a signal flowing between a source and a drain can be independently controlled according to a voltage applied to a gate electrode or a back gate electrode. Therefore, it is possible to design a circuit with the same idea as an LSI.
  • the OS transistor has better electrical characteristics than the Si transistor in a high temperature environment. Specifically, since the ratio of the on-current to the off-current is large even at a high temperature of 125° C. or higher and 150° C. or lower, good switching operation can be performed.
  • the memory cell illustrated in FIG. 1A can be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) that uses an OS transistor as a memory. Since it can be configured with one transistor and one capacitor, high density memory can be realized. Further, by using the OS transistor, the data retention period can be extended.
  • the capacitors 33_1 to 33_N have a structure in which an insulator is sandwiched between conductors serving as electrodes. As the conductor forming the electrodes, a semiconductor layer having conductivity can be used in addition to metal.
  • a part of a semiconductor layer, an electrode, or the like forming the transistors 32_1 to 32_N is provided in one of the capacitors 33_1 to 33_N. Can be used as an electrode.
  • FIG. 1A the element layers 34_1 to 34_N which are one embodiment of the present invention will be described with reference to the schematic diagram illustrated in FIG. 1B.
  • the schematic diagram shown in FIG. 1B corresponds to a perspective view defining the x-axis, y-axis, and z-axis directions in order to explain the arrangement of the components described in FIG. 1A.
  • the x-axis direction may be referred to as the depth direction
  • the y-axis direction may be referred to as the horizontal direction
  • the z-axis direction may be referred to as the vertical direction in the specification.
  • the element layers 34_1 to 34_N are provided by stacking N layers.
  • the element layers 34_1 to 34_N including the memory cells 31_1 to 31_N each have a region overlapping with the column driver 22 provided in the silicon substrate 11. It can be said that the element layer 34_1 is provided between the silicon substrate 11 and the element layer 34_N as illustrated in FIG.
  • the transistor of the memory cell 31_1 included in the element layer 34_1 and the transistor of the memory cell 31_N included in the element layer 34_N are connected to each other through a bit line BL provided in a vertical direction.
  • the bit line BL is connected to the column driver 22 provided on the silicon substrate 11.
  • the bit line BL_1 is provided in contact with the semiconductor layer of the transistor included in the memory cell 31_1 and the semiconductor layer of the transistor included in the memory cell 31_N.
  • the bit line BL_1 is provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 31_1 and a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 31_N.
  • the bit line BL_1 includes a conductor provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 31_1 and a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 31_N.
  • bit line BL is a wiring for electrically connecting one of a source and a drain of a transistor included in the memory cell 31_1, one of a source and a drain of a transistor included in the memory cell 31_N, and the column driver 22 in a vertical direction. You can say that.
  • the bit line BL is provided so as to extend in a vertical direction or a substantially vertical direction on the surface of the silicon substrate 11 on which the column driver 22 is provided. That is, as illustrated in FIG. 1B, the bit line BL is connected to a transistor included in the memory cell 31_1 and a transistor included in the memory cell 31_N and is perpendicular to or substantially perpendicular to the surface (xy plane) of the silicon substrate. It is provided in the vertical direction' (z direction).
  • the term “generally vertical” means a state in which they are arranged at an angle of 85 degrees or more and 95 degrees or less.
  • the row driver 21 provided on the silicon substrate 11 and the word line WL provided extending in the depth direction of the element layers 34_1 to 34_N are provided with the memory cells 31_1 to 31_N in the element layers 34_1 to 34_N.
  • the regions may be connected to each other, for example, via the openings in the outer peripheral portions of the element layers 34_1 to 34_N.
  • the row driver 21 provided in the silicon substrate 11 and the word line WL provided in each element layer may be connected to each other through a wiring provided in an upper layer of the element layers 34_1 to 34_N.
  • an OS transistor with extremely low off-state current is used as a transistor provided in each element layer. Therefore, the frequency of refreshing data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be obtained.
  • the OS transistors can be provided in a stacked structure and can be manufactured by repeating the same manufacturing process in the vertical direction, so that manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • the OS transistor since the OS transistor has less variation in electrical characteristics than the Si transistor even in a high temperature environment, the variation in electrical characteristics of the transistor when stacked and integrated is small and a semiconductor device which functions as a highly reliable memory device.
  • a bit line extending from the memory cell array is provided in a vertical direction, whereby the length of the bit line between the memory cell array and the column driver can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced, so that the potential can be read even when the data signal held in the memory cell is multivalued.
  • FIG. 2 shows a schematic view of a cross section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10 described with reference to FIGS. 1A and 1B.
  • the memory cells 31_1 to 31_N provided in the element layers of the respective layers and the column driver 22 provided in the silicon substrate 11 are provided in the bit line provided in the vertical direction which is the shortest distance. It can be configured to be connected via BL.
  • the number of bit lines BL is increased as compared with the configuration in which the bit lines BL are arranged in the plane direction, the number of memory cells 31_1 to 31_N connected to one bit line can be reduced, and thus the bit line BL can be reduced.
  • the parasitic capacitance of can be reduced. Therefore, even if the capacitance of the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N is reduced, the potential of the bit line BL can be changed due to the movement of charges.
  • the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N can be reduced in capacity, the capacitors 33_1 to 33_N can be provided in the same layer as the transistors 32_1 to 32_N.
  • the element layers 34_1 to 34_N for each layer can be thinned. Therefore, the semiconductor device 10 can be downsized.
  • the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N may have a structure provided in the same layer as the transistors 32_1 to 32_N, but may have another structure.
  • the capacitor 33A of the memory cell 31 included in the element layers 34_1 to 34_N is provided above the transistor 32 in the vertical direction.
  • the capacity can be increased, so that reliability of data to be read and data retention time can be improved.
  • the electrode of the capacitor 33A since the electrode of the capacitor 33A, one electrode of which is connected to a fixed potential, can be arranged above the transistor 32, the influence of noise from the outside can be suppressed.
  • the schematic diagram shown in FIG. 3B shows a structure in which the capacitor 33B of the memory cell 31 included in the element layers 34_1 to 34_N is provided below the transistor 32 in the vertical direction.
  • the capacity can be increased, so that reliability of data to be read and data retention time can be improved.
  • the electrode of the capacitor 33B whose one electrode is connected to a fixed potential can be disposed between the transistor 32 and the column driver 22, the noise of the column driver 22 is reduced. The influence on the memory cell 31 can be suppressed.
  • FIG. 4 illustrates a circuit configuration example of the memory cell array 30 including the element layers 34_1 to 34_N described in FIG. 1A and a specific circuit configuration example of the column driver 22 connected to the memory cells.
  • FIG. 4 illustrates a circuit configuration example of the memory cell array 30 including the element layers 34_1 to 34_N described in FIG. 1A and a specific circuit configuration example of the column driver 22 connected to the memory cells.
  • FIG. 4 illustrates the element layers 34_1 to 34_N as the memory cell array 30.
  • a memory cell 31_N_A is illustrated as a memory cell connected to the bit line BL_A.
  • the memory cell 31_N_A includes a transistor 32A whose gate is connected to the word line WL_A and a capacitor 33.
  • a memory cell 31_N_B is illustrated as a memory cell connected to the bit line BL_B.
  • the memory cell 31_N_B has a transistor 32B whose gate is connected to the word line WL_B and a capacitor 33.
  • the capacitor 33 of each element layer is connected to the wiring VL to which a fixed potential, for example, the ground potential is given.
  • FIG. 4 shows, as circuits included in the column driver 22, a precharge circuit 22_1, a sense amplifier 22_2, a selection switch 22_3, and a write/read circuit 29 on the silicon substrate side.
  • Si transistors are used as transistors included in the precharge circuit 22_1 and the sense amplifier 22_2.
  • a Si transistor can also be used for the selection switch 22_3.
  • the precharge circuit 22_1 is composed of n-channel type transistors 24_1 to 24_3.
  • the precharge circuit 22_1 precharges the bit line BL_A and the bit line BL_B to an intermediate potential VPC corresponding to the potential VDD/2 between VDD and VSS in response to a precharge signal applied to the precharge line PCL. Circuit.
  • the sense amplifier 22_2 includes p-channel transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 connected to the wiring VHH or the wiring VLL.
  • the wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS.
  • the transistors 25_1 to 25_4 are transistors that form an inverter loop.
  • the sense amplifier 22_2 sets the potentials of the bit line BL_A and the bit line BL_B which are changed by selecting the memory cells 31_N_A and 31_N_B by setting the word lines WL_A and WL_B at high level to the high power supply potential VDD or the low power supply potential VSS.
  • the potentials of the bit line BL_A and the bit line BL_B can be output to the outside through the writing and reading circuit 29.
  • the bit line BL_A and the bit line BL_B correspond to a bit line pair.
  • FIG. 5 shows a timing chart for explaining the operation of the circuit diagram shown in FIG.
  • the period T1 corresponds to the initialization operation
  • the period T2 corresponds to the writing operation
  • the period T3 corresponds to the non-access operation
  • the period T4 corresponds to the reading operation.
  • description of the switches 23_A and 23_B included in the selection switch 22_3 is omitted in the description of FIG. 5, the switches 23_A and 23_B are selected to be appropriately turned on during the writing operation and the reading operation.
  • the arrows attached between the waveforms are for facilitating the understanding of the operation.
  • the high level (H level) of the wiring PCL is VDD.
  • the high level of WL is VHM (>VDD), but it may be VDD.
  • the wiring VPC, the wiring VHH, and the wiring VLL are set to VDD/2.
  • the bit line BL_A is precharged to VDD/2.
  • the precharge of the bit line BL_A is performed by the precharge circuit 22_1.
  • the precharge circuit 22_1 By setting the wiring PCL to a high level (H level), the bit line BL_A (or the bit line BL_B) is precharged and the potential is smoothed.
  • the bit line BL_A (or the bit line BL_B) is changed from the precharged state to the floating state. This is done by changing the wiring PCL from the H level to the L level.
  • the word line WL_A is set to H level. After WL_A is selected, VHH is set to VDD and VLL is set to GND.
  • the data DA1 is written to the bit line BL_A by turning on the transistor 32A. After the word line WL_A is set to the L level, the precharge operation of the bit line BL_A (or the bit line BL_B) is started and these are precharged to VDD/2.
  • the wiring PCL is at H level and the word line WL_A is at L level.
  • VPC, VHH and VLL are VDD/2.
  • the bit line pair and the local bit line pair are precharged to VDD/2.
  • the bit line BL_A (or the bit line BL_B) is changed from the precharged state to the floating state.
  • the word line WL_A is set to H level to turn on the transistor 32A.
  • the data DA1 will be written to the bit line BL_A.
  • VHH is set to VDD and VLL is set to GND
  • the sense amplifier 22_2 functions as a differential amplifier circuit, and the data DA1 of the bit line BL_A is amplified.
  • the data DA1 on the bit line BL_A is read by the write/read circuit 29.
  • the semiconductor device of one embodiment of the present invention uses an OS transistor with extremely low off-state current as a transistor provided in each element layer.
  • the OS transistor can be provided by being stacked over a silicon substrate provided with a Si transistor. Therefore, the same manufacturing process can be repeated in the vertical direction, and the manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • FIG. 6A shows a block diagram of the semiconductor device 10A.
  • the peripheral circuit 20 has an element layer 26 provided with a row driver 21, a column driver 22, and a switching circuit.
  • the switching circuit may be simply referred to as a drive circuit.
  • the switching circuit has a transistor having a function of controlling a conductive state between the memory cell and the column driver.
  • the element layer 26 provided with the switching circuit has a function of selectively connecting the column driver 22 to the bit line BL.
  • the switching circuit has a function as a multiplexer that connects a predetermined bit line to a drive circuit such as a sense amplifier of the column driver 22 in accordance with a selection signal output from the column driver 22.
  • the switching circuit is a circuit having a function of outputting a signal for driving the memory cell array 30 to the bit line BL selected by the switching circuit.
  • the element layer 26 provided with the switching circuit reduces the number of bit lines BL connected to the column driver 22 in the vertical direction, shortens the data writing time, and improves the reading accuracy. It is possible to improve.
  • the transistor forming the switching circuit is an OS transistor. Since the element layer 26 having the switching circuit using the OS transistor can be freely arranged on the circuit using the Si transistor or the like, integration can be easily performed. Further, the OS transistor can be manufactured at low cost because it can be manufactured using a manufacturing apparatus similar to that of the Si transistor.
  • FIG. 6B a schematic diagram illustrated in FIG. 6B is used.
  • the schematic diagram shown in FIG. 6B corresponds to a perspective view defining the x-axis, y-axis, and z-axis directions in order to explain the arrangement of the components described in FIG. 6A.
  • the element layer 26 provided with a transistor included in the switching circuit is a V layer (V is a natural number of 1 or more) and the element layers 34_1 to 34_N are N layers.
  • Layers having a total of (N+V) layers of OS transistors are stacked on the silicon substrate 11.
  • the memory cells 31_1 to 31_N included in the element layers 34_1 to 34_N and the element layer 26 in which transistors included in the switching circuit are provided each have a region overlapping with the column driver 22 provided in the silicon substrate 11. It can be said that the element layer 26 is provided between the silicon substrate 11 and the element layer 34_1 as illustrated in FIG. 6B. It can also be said that the element layer 34_1 is provided between the silicon substrate 11 and the element layer 34_N as illustrated in FIG. 6B.
  • the transistor of the memory cell 31_1 included in the element layer 34_1 and the transistor of the memory cell 31_N included in the element layer 34_N are connected to each other through a bit line BL provided in a vertical direction.
  • the bit line BL is connected to the element layer 26 in which the transistor included in the switching circuit is provided.
  • the element layer 26 is connected to the column driver 22 provided on the silicon substrate 11.
  • the bit line BL_1 is provided in contact with the semiconductor layer of the transistor included in the memory cell 31_1.
  • the bit line BL_1 is provided in contact with a region functioning as a source or a drain of a semiconductor layer of a transistor included in the memory cell 31_1.
  • the bit line BL_1 is provided in contact with a conductor provided in contact with a region functioning as a source or a drain of a semiconductor layer of a transistor included in the memory cell 31_1. That is, the bit line BL is a wiring for electrically connecting one of the source and the drain of the transistor included in the memory cell 31_1, one of the source and the drain of the transistor included in the memory cell 31_N, and the element layer 26 in the vertical direction. You can say that.
  • an OS transistor with extremely low off-state current is used as a transistor provided in each element layer. Therefore, the frequency of refreshing data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be obtained.
  • the OS transistors can be provided in a stacked structure and can be manufactured by repeating the same manufacturing process in the vertical direction, so that manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • the OS transistor since the OS transistor has less variation in electrical characteristics than the Si transistor even in a high temperature environment, the variation in electrical characteristics of the transistor when stacked and integrated is small and a semiconductor device which functions as a highly reliable memory device. Can be
  • one embodiment of the present invention includes an element layer having a switching circuit.
  • the switching circuit can reduce the number of bit lines BL connected to the sense amplifier included in the column driver. Therefore, the load on the bit line BL can be reduced.
  • the switching circuit can reduce the number of bit lines BL connected to the column driver in the vertical direction, shorten the data writing time, and improve the reading accuracy. In addition, charging and discharging of unnecessary bit lines can be avoided, and a semiconductor device with low power consumption can be obtained. Since the memory cell can be arranged directly above the circuit such as the sense amplifier, the size of the semiconductor device can be reduced. Further, it becomes possible to operate even if the capacity of the capacitor included in the memory cell is reduced.
  • a bit line extending from the memory cell array is provided in a vertical direction, whereby the length of the bit line between the memory cell array and the column driver can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced, so that the potential can be read even when the data signal held in the memory cell is multivalued.
  • FIG. 7 shows a schematic diagram of a cross section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10A described with reference to FIGS. 6A and 6B.
  • the memory cells 31_1 to 31_N provided in the element layers of the respective layers, the element layer 26, and the column driver 22 provided in the silicon substrate 11 are arranged in the vertical direction which is the shortest distance. Can be connected via the bit line BL provided in the. Although the number of element layers 26 including the switching circuit 27 increases, the number of bit lines BL connected to the sense amplifier included in the column driver 22 can be reduced. Therefore, the load on the bit line BL can be reduced.
  • the transistors 28_1 to 28_n (n is a natural number of 2 or more) included in the switching circuit 27 signal the potential of the bit line BL selected according to the selection signal MUX output from the column driver 22. It can be output to the column driver 22 as BL_OUT.
  • the semiconductor device 10A illustrated in FIG. 7 can be represented as a unit 30_1.
  • FIG. 8 illustrates a circuit diagram in which the element layers 34_1 to 34_N as well as the element layer 26 having the transistors 28_a and 28_b are added as the memory cell array 30.
  • Element layers 34_1 to 34_N are provided over the element layer 26 including the transistors 28_a and 28_b illustrated in FIG. 8 and the bit lines BL_A and BL_B are provided in the vertical direction. That is, the element layer including the switching circuit which forms part of the peripheral circuit can be stacked and provided similarly to the element layers 34_1 to 34_N.
  • the bit lines BL_A and BL_B are connected to one of the sources or drains of the transistors 28_a and 28_b.
  • FIG. 8 shows, as circuits included in the column driver 22, a precharge circuit 22_1, a sense amplifier 22_2, a switch circuit 22_3, and a write/read circuit 29 on the silicon substrate side.
  • Si transistors are used as transistors included in the precharge circuit 22_1 and the sense amplifier 22_2.
  • a Si transistor can also be used for the selection switch 22_3.
  • the other of the sources or drains of the transistors 28_a and 28_b is connected to the transistors included in the precharge circuit 22_1 and the sense amplifier 22_2.
  • the bit line BL_A or BL_B is selected and connected to one of the pair of wirings connected to the precharge circuit 22_1 and the sense amplifier 22_2 and the switch 23_A. Also in the element layer 26 having another pair of switching circuits, the bit line BL is selected and connected to the other of the pair of wirings connected to the precharge circuit 22_1 and the sense amplifier 22_2 and the switch 23_B.
  • the word line of the memory cell connected to the selected bit line as the high level, the potential of the precharged bit line changes, and according to the change, the precharge circuit 22_1 and the sense amplifier 22_2 are connected.
  • the potential of the pair of wirings thus formed becomes the high power supply potential VDD or the low power supply potential VSS. The potential can be output to the outside through the switch circuit 22_3 and the writing/reading circuit 29.
  • any one of the plurality of bit lines BL can be selected and connected to the column driver 22. Therefore, a small number of bit lines BL can be connected to the sense amplifier 22_2, and the load on the bit lines BL can be reduced.
  • FIG. 9 illustrates a semiconductor device 10A having a configuration in which the unit 30_1 described in FIG. 7 is stacked in M stages (units 30_1 to 30_M, M is 2 or more).
  • FIG. 9 corresponds to a schematic view of a cross section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device. That is, the configuration of the semiconductor device 10A shown in FIG. 9 is a configuration in which the lamination of the element layers shown in FIG. 7 is a total of M ⁇ (N+V) layers.
  • the semiconductor device 10A includes switching circuits 27_1 to 27_M in the units 30_1 to 30_M, respectively.
  • the switching circuits 27_1 to 27_M output the signal BL_OUT when the selection signal MUX is input. Any one of the plurality of wirings through which the signal BL_OUT is output is selected by the switch circuit 98 that can be switched by the selection signal SEL and is connected to the column driver 22 through the wiring GBL different from the bit line BL.
  • the switch circuit 98 can use an OS transistor included in the switching circuits 27_1 to 27_M.
  • the wiring GBL may be illustrated as a thick line, a thick dotted line, or the like in order to increase visibility.
  • the wiring GBL may be called a global bit line.
  • the wiring GBL illustrated in FIG. 9 can be provided after an element layer including an OS transistor is manufactured.
  • an element layer having an OS transistor is formed, an opening is provided in the outer periphery of a sealing layer 70A surrounding each element layer, and wiring is provided in the opening.
  • GBL can be provided.
  • an element layer having an OS transistor is formed, and an opening is provided in the outer periphery of a sealing layer 70B which collectively surrounds each element layer,
  • the wiring GBL can be provided in the opening. Note that details of each element layer provided with the wiring GBL will be described in detail in Embodiment 3.
  • the semiconductor device of one embodiment of the present invention uses an OS transistor with extremely low off-state current as a transistor provided in each element layer.
  • the OS transistor can be provided by being stacked over a silicon substrate provided with a Si transistor. Therefore, the same manufacturing process can be repeated in the vertical direction, and the manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • one embodiment of the present invention includes an element layer having a switching circuit.
  • the switching circuit can reduce the number of bit lines BL connected to the column driver in the vertical direction, shorten the data writing time, and improve the reading accuracy. In addition, charging and discharging of unnecessary bit lines can be avoided, and a semiconductor device with low power consumption can be obtained.
  • FIG. 11A shows a block diagram of the semiconductor device 10B.
  • the peripheral circuit 20 has a row driver 21, a column driver 22, and an element layer 40 provided with a control circuit.
  • the control circuit has a circuit which functions as a sense amplifier including an OS transistor.
  • the element layer 40 provided with the control circuit has a circuit functioning as a sense amplifier including an OS transistor.
  • the sense amplifier including an OS transistor functions as a switching circuit for writing or reading a data signal to or from each memory cell and selecting a unit 50_1 to 50_M including the memory cells 31_1 to 31_N.
  • the element layer 40 is supplied with control signals WE, RE, and MUX from the column driver 22 for driving a sense amplifier formed of an OS transistor.
  • a circuit functioning as a sense amplifier has a transistor for controlling reading or writing of a data signal to a memory cell, and thus may be referred to as a control circuit.
  • the control circuit can function as an amplifier. With such a structure, a slight potential difference of the bit line BL can be amplified at the time of reading and a sense amplifier including a Si transistor can be driven.
  • the transistor forming the control circuit is an OS transistor. Since the element layer 40 having the control circuit using the OS transistor can be freely arranged on the circuit using the Si transistor or the like, integration can be easily performed. Further, the OS transistor can be manufactured at low cost because it can be manufactured using a manufacturing apparatus similar to that of the Si transistor.
  • FIG. 11B is used to describe the element layers 34_1 to 34_N and the element layer 40 including a control circuit in one embodiment of the present invention in each structure described in FIG. 11A. explain.
  • the schematic diagram shown in FIG. 11B corresponds to a perspective view defining the x-axis, y-axis, and z-axis directions in order to explain the arrangement of the components described in FIG. 11A.
  • the element layer 40 provided with a transistor included in the control circuit is a V layer (V is a natural number of 1 or more), and the element layers 34_1 to 34_N are N layers.
  • Layers having a total of (N+V) layers of OS transistors are stacked on the silicon substrate 11.
  • the memory cells 31_1 to 31_N included in the element layers 34_1 to 34_N and the element layer 40 in which transistors included in the control circuit are provided each have a region overlapping with the column driver 22 provided in the silicon substrate 11. It can be said that the element layer 40 is provided between the silicon substrate 11 and the element layer 34_1 as illustrated in FIG. It can also be said that the element layer 34_1 is provided between the silicon substrate 11 and the element layer 34_N as illustrated in FIG.
  • the transistor of the memory cell 31_1 included in the element layer 34_1 and the transistor of the memory cell 31_N included in the element layer 34_N are connected to each other through a bit line BL provided in a vertical direction.
  • the bit line BL is connected to the element layer 40 in which the transistor included in the control circuit is provided.
  • the element layer 40 is connected to the column driver 22 provided on the silicon substrate 11 via a wiring GBL (not shown) provided separately from the bit line BL.
  • the wiring GBL may be illustrated as a thick line, a thick dotted line, or the like in order to increase visibility.
  • the bit line BL_1 is provided in contact with the semiconductor layer of the transistor included in the memory cell 31_1.
  • the bit line BL_1 is provided in contact with a region functioning as a source or a drain of a semiconductor layer of a transistor included in the memory cell 31_1.
  • the bit line BL_1 is provided in contact with a conductor provided in contact with a region functioning as a source or a drain of a semiconductor layer of a transistor included in the memory cell 31_1. That is, the bit line BL is a wiring for electrically connecting one of the source and the drain of the transistor included in the memory cell 31_1, the one of the source and the drain of the transistor included in the memory cell 31_N, and the element layer 40 in the vertical direction. You can say that.
  • the semiconductor device 10B has one type of memory cell, but may have two or more types of memory cells.
  • FIG. 12A is a block diagram showing a configuration example of the semiconductor device 10C, which is a modification of the semiconductor device 10B.
  • the semiconductor device 10C differs from the semiconductor device 10B in that the memory cell array 30 is provided with a memory cell 31 and a memory cell 51 having a different configuration from the memory cell 31.
  • the semiconductor device 10C has an element layer 54 composed of one or more memory cells 51.
  • the element layer 54 can be provided between the element layer 34_i (i is an integer of 1 or more and N-1 or less) and the element layer 34_i+1.
  • the element layer 54 may be provided in two or more layers.
  • the element layer 34 may or may not be provided between the first element layer 54 and the second element layer. Good.
  • the row driver 21 is electrically connected to the memory cell 51 via the word line WL2.
  • the row driver 21 included in the semiconductor device 10C has a function of outputting a signal for driving the memory cell array 30 to the word line WL2 in addition to the word line WL.
  • the row driver 21 has a function of transmitting a word signal to the word line WL2 as well as the word line WL.
  • the row driver having the function of transmitting the word signal to the word line WL2 may be provided separately from the row driver having the function of transmitting the word signal to the word line WL.
  • the word line WL2 may be simply referred to as a wiring.
  • FIG. 12B is a circuit diagram showing a configuration example of the memory cell 51.
  • the memory cell 51 includes a transistor 55, a transistor 56, and a capacitor 57.
  • One of the source and the drain of the transistor 55 is electrically connected to the gate of the transistor 56.
  • the gate of the transistor 56 is electrically connected to one electrode of the capacitor 57.
  • the other of the source and the drain of the transistor 55 and the one of the source and the drain of the transistor 56 are electrically connected to the wiring BL.
  • the other of the source and the drain of the transistor 56 is electrically connected to the wiring SL.
  • the other electrode of the capacitor 57 is electrically connected to the wiring CAL.
  • a node where one of the source and the drain of the transistor 55, the gate of the transistor 56, and one electrode of the capacitor 57 is electrically connected is a node N.
  • the wiring CAL has a function as a wiring for applying a predetermined potential to the other electrode of the capacitive element 57.
  • the potential of the wiring CAL at the time of reading data from the memory cell 51 is made different from the potential of the wiring CAL at the time of writing data in the memory cell 51 and while the data is held in the memory cell 51.
  • the apparent threshold voltage of the transistor 56 at the time of reading data from the memory cell 51 is set to the apparent threshold voltage of the transistor 56 at the time of writing data in the memory cell 51 and during holding the data in the memory cell 51. Threshold voltage can be different.
  • the memory cell 51 has the structure illustrated in FIG. 12B
  • data is written to the memory cell 51 at the time of writing data and while the data is held in the memory cell 51. Therefore, no current flows between the wiring SL and the wiring BL.
  • a current corresponding to the data held in the memory cell 51 flows between the wiring SL and the wiring BL.
  • the transistor 55 is preferably an OS transistor.
  • the OS transistor has an extremely low off-state current. Therefore, the charge corresponding to the data written in the memory cell 51 can be held in the node N for a long time. That is, once written data can be held in the memory cell 51 for a long time. Therefore, the frequency of data refresh can be reduced and power consumption of the semiconductor device of one embodiment of the present invention can be reduced.
  • the memory cell 51 using the OS transistor can be freely arranged on a silicon substrate or the like, so that the integration can be easily performed.
  • the transistor 56 is preferably an OS transistor from the viewpoint of integration of the memory cell 51.
  • the transistor 55 preferably has a back gate electrode. By controlling the potential applied to the back gate electrode, the threshold voltage of the transistor 55 can be controlled. Accordingly, for example, the on-state current of the transistor 55 can be increased and the off-state current can be reduced. Note that when the transistor 56 is an OS transistor, the transistor 56 is preferably provided with a back gate electrode.
  • the memory cell 51 having the configuration shown in FIG. 12B can be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM) using an OS transistor as a memory.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the NOSRAM has a feature that it can perform nondestructive read.
  • the DOSRAM that can be applied to the memory cell 31 performs destructive read when reading the held data.
  • the operation of the semiconductor device 10C will be described.
  • the data written in the memory cell array 30 from the column driver 22 is held in the memory cell 31.
  • the data having a high read frequency is transferred from the memory cell 31 to the memory cell 51.
  • the NOSRAM memory cell 51 can perform nondestructive read, the frequency of data refresh can be reduced. Therefore, power consumption of the semiconductor device of one embodiment of the present invention can be reduced.
  • the potential of the node N varies depending on not only the data written in the memory cell 51 but also the potential of the wiring CAL. Therefore, the data held in the memory cell 51 can be corrected by adjusting the potential of the wiring CAL after writing the data in the memory cell 51. For example, when correcting the data held in the memory cell 51, the potential of the wiring CAL when reading the data from the memory cell 51 is read, and when the data held in the memory cell 51 is not corrected, the data is read from the memory cell 51. The potential of the wiring CAL at that time can be different. Therefore, for example, when the data written in the memory cell is image data, the semiconductor device 10C can perform image processing. Therefore, the semiconductor device 10C can be, for example, an image engine.
  • i is preferably N/2 or a value in the vicinity thereof. Accordingly, for example, the wiring distance from the memory cell 51 to the memory cell 31_1 or the wiring distance from the memory cell 51 to the memory cell 31_N can be shortened. Thus, when data is transferred from the memory cell 51 to, for example, the memory cell 31_1 or the memory cell 31_N, a decrease in data potential due to wiring resistance of the wiring BL or the like can be suppressed.
  • FIG. 13 is a block diagram showing a configuration example of the semiconductor device 10D, which is a modification of the semiconductor device 10C.
  • the configuration of the semiconductor device 10D differs from the configuration of the semiconductor device 10C in that the element layer 54 is provided before the element layer 34_1, that is, between the element layer 34_1 and the element layer 40.
  • the semiconductor device 10D is characterized in that the wiring distance between the element layer 40 provided with a sense amplifier and the like and the element layer 54 is short. This makes it possible to eliminate the difficulty of operation due to the increase in the wiring resistance of the memory cell 51, and it becomes easier to control the operation of the memory cell 51.
  • the element layer 54 may be provided after the element layer 34_N, that is, for example, over the element layer 34_N.
  • FIG. 14 is a perspective view in which the x-axis, y-axis, and z-axis directions are defined in order to explain the arrangement of the components of the semiconductor device 10C shown in FIG. 12(A).
  • FIG. 15 is a perspective view in which x-axis, y-axis, and z-axis directions are defined in order to explain the arrangement of the components of the semiconductor device 10D shown in FIG.
  • the element layer 40 in which the transistors included in the control circuit are provided is a V layer
  • the element layers 34_1 to 34_N are N layers
  • the memory cell 51 included in the element layer 54 has a region overlapping with the column driver 22 provided in the silicon substrate 11.
  • the element layer 54 may be provided in two or more layers.
  • the element layer 54 may be provided as an H layer (H is an integer of 1 or more).
  • the semiconductor device 10C is provided with a layer having a total of (N+V+H) layers of OS transistors.
  • FIG. 16 is a perspective view for explaining a configuration example of the semiconductor device 10E, which defines x-axis, y-axis, and z-axis directions.
  • the element layer 40 having the sense amplifier can be provided between the element layer 34_i that can have the DOSRAM and the element layer 34_i+1.
  • an element layer 541 which can have a NOSRAM can be provided between the element layer 34 — i and the element layer 40 and between the element layer 40 and the element layer 34 — i+1. That is, the element layer 40 and the element layer 54 can be provided between the two element layers 34.
  • only one element layer 54 may be provided, or three or more element layers 54 may be provided.
  • an OS transistor with extremely low off-state current is used as a transistor provided in each element layer. Therefore, the frequency of refreshing data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be obtained.
  • the OS transistors can be provided in a stacked structure and can be manufactured by repeating the same manufacturing process in the vertical direction, so that manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • the OS transistor since the OS transistor has less variation in electrical characteristics than the Si transistor even in a high temperature environment, the variation in electrical characteristics of the transistor when stacked and integrated is small and a semiconductor device which functions as a highly reliable memory device. Can be
  • one embodiment of the present invention includes an element layer having a control circuit.
  • the control circuit can function as an amplifier.
  • a slight potential difference of the bit line BL can be amplified at the time of reading and a sense amplifier including a Si transistor can be driven. Since a circuit such as a sense amplifier including a Si transistor can be downsized, a semiconductor device can be downsized. Further, it becomes possible to operate even if the capacity of the capacitor included in the memory cell is reduced.
  • a bit line extending from the memory cell array is provided in a vertical direction, whereby the length of the bit line between the memory cell array and the column driver can be shortened.
  • the parasitic capacitance of the bit line can be significantly reduced, so that the potential can be read even when the data signal held in the memory cell is multivalued.
  • data held in a memory cell can be read as a current; therefore, data can be easily read even when multivalued.
  • FIG. 17 shows a schematic diagram of a cross section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10B described with reference to FIGS. 11A and 11B.
  • the memory cells 31_1 to 31_N provided in the respective element layers, the element layer 40, and the column driver 22 provided in the silicon substrate 11 are arranged in the vertical direction which is the shortest distance. Can be connected through the bit line BL and the wiring GBL provided in the. Although the number of element layers 40 having transistors forming the control circuit is increased, the number of wirings provided in the vertical direction and connected to the column driver 22 can be reduced. By reducing the load on the bit line BL, writing time can be shortened and data can be read easily.
  • the transistors 41 to 44 included in the element layer 40 are controlled according to the control signals WE and RE output from the column driver 22 and the selection signal MUX.
  • Each transistor can output the potential of the bit line BL to the column driver 22 via the wiring GBL in accordance with the control signal and the selection signal.
  • the semiconductor device 10B illustrated in FIG. 17 can be represented as a unit 50_1.
  • FIGS. 18A and 18B and FIGS. 19A and 19B a specific structural example of a circuit which functions as a sense amplifier including an OS transistor included in the element layer 40 is described with reference to FIGS. 18A and 18B and FIGS. 19A and 19B. To do.
  • the element layer 40A includes transistors 41 to 44.
  • Each of the transistors 41 to 44 can be an OS transistor and is illustrated as an n-channel transistor.
  • the transistor 41 is a transistor that constitutes a source follower for amplifying the wiring GBL to a potential corresponding to the potential of the bit line BL in a period in which a data signal is read from the memory cell.
  • the transistor 42 is a transistor that functions as a switch that controls on/off between the source and the drain in accordance with the selection signal MUX input to the gate.
  • the transistor 43 is a transistor that functions as a switch that controls on/off between the source and the drain in accordance with the write control signal WE input to the gate.
  • the transistor 44 is a transistor that functions as a switch that controls ON/OFF between the source and the drain according to the read control signal RE input to the gate. Note that the source side of the transistor 44 is supplied with the ground potential GND which is a fixed potential.
  • the configuration of the element layer 40A shown in FIG. 18A can be applied to the modified examples shown in FIGS. 18B and 19A and 19B.
  • the element layer 40B in FIG. 18B has a structure in which one of a source and a drain of the transistor 43 is switched from the wiring GBL to one of a source and a drain of the transistor 41.
  • the element layer 40C in FIG. 19A corresponds to a structure in which the transistor 42 is omitted by performing the function of the transistor 42 in the column driver 22.
  • the element layer 40D in FIG. 19B corresponds to a structure in which the transistor 44 is omitted.
  • FIG. 20 shows a schematic diagram of a configuration in which the units 50_1 described in FIG. 17 are laminated.
  • the semiconductor device 10B illustrated in FIG. 20 includes memory cells 31_1 to 31_N provided in each element layer.
  • the memory cells 31_1 to 31_N and the element layers 40_1 to 40_M are connected via a bit line BL provided in the vertical direction which is the shortest distance, and the element layer is connected via a wiring GBL. 40 is connected to the column driver 22.
  • the M-stage units 50_1 to 50_M in the semiconductor device 10B illustrated in FIG. 18 can be configured to be stacked in the vertical direction.
  • the semiconductor device 10B includes element layers 40_1 to 40_M each including a circuit functioning as a sense amplifier formed of an OS transistor in each of the units 50_1 to 50_M. That is, the configuration of the semiconductor device 10B illustrated in FIG. 20 is a configuration in which the stack of element layers illustrated in FIG. 17 is a total of M ⁇ (N+V) layers.
  • FIG. 21 shows a schematic diagram of a configuration in which the semiconductor device 10D shown in FIG. 14 is applied as the unit 50.
  • the element layer 40, the element layer 54, and the element layers 34_1 to 34_N are provided in a vertically stacked manner.
  • the semiconductor device 10C and the semiconductor device 10E may be applied as the unit 50.
  • an OS transistor with extremely low off-state current is used as a transistor provided in each element layer. Therefore, the frequency of refreshing data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be obtained.
  • the OS transistors can be provided in a stacked structure and can be manufactured by repeating the same manufacturing process in the vertical direction, so that manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • the OS transistor since the OS transistor has less variation in electrical characteristics than the Si transistor even in a high temperature environment, the variation in electrical characteristics of the transistor when stacked and integrated is small and a semiconductor device which functions as a highly reliable memory device. Can be
  • one embodiment of the present invention includes an element layer having a control circuit.
  • the control circuit since the bit line BL is connected to the gate of the transistor 41, the transistor 41 can function as an amplifier. With such a structure, a slight potential difference of the bit line BL can be amplified at the time of reading and a sense amplifier including a Si transistor can be driven. Since a circuit such as a sense amplifier including a Si transistor can be downsized, a semiconductor device can be downsized. Further, it becomes possible to operate even if the capacity of the capacitor included in the memory cell is reduced.
  • FIG. 22 illustrates an element layer 40 including transistors 41_a, 41_b, 42_a, 42_b, 43_a, 43_b, 44_a, and 44_b. Is shown. Element layers 34_1 to 34_N are provided on the element layer 40 having the transistors 41_a, 41_b, 42_a, 42_b, 43_a, 43_b, 44_a, and 44_b illustrated in FIG. 22, and the bit lines BL_A and BL_B are provided in the vertical direction. .. That is, the element layer including the switching circuit which forms part of the peripheral circuit can be stacked and provided similarly to the element layers 34_1 to 34_N. The bit lines BL_A and BL_B are connected to the gates of the transistors 41_a and 41_b.
  • the transistors 42_a, 42_b, 43_a, and 43_b included in the element layer 40 are connected to the wirings GBL_A and GBL_B.
  • the wirings GBL_A and GBL_B are provided in the vertical direction similarly to the bit lines BL_A and BL_B, and are connected to the transistors included in the column driver 22.
  • the control signals WE, RE, and MUX are applied to the gates of the transistors 42_a, 42_b, 43_a, 43_b, 44_a, and 44_b included in the element layer 40.
  • FIG. 22 shows, as circuits included in the column driver 22, a precharge circuit 22_A, a precharge circuit 22_B, a sense amplifier 22_C, a switch circuit 22_D, a switch circuit 22_E, and a write/read circuit 29 on the silicon substrate side.
  • Si transistors are used as transistors included in the precharge circuit 22_A, the precharge circuit 22_B, and the sense amplifier 22_C.
  • the switch circuits 22_D and the switches 23_A to 23_D included in the switch circuit 22_E can also use Si transistors.
  • One of a source and a drain of the transistors 42_a, 42_b, 43_a, and 43_b is connected to transistors included in the precharge circuit 22_A, the precharge circuit 22_B, the sense amplifier 22_C, and the switch circuit 22_D.
  • the precharge circuit 22_A is composed of n-channel type transistors 24_1 to 24_3.
  • the precharge circuit 22_A precharges the bit line BL_A and the bit line BL_B to an intermediate potential VPC corresponding to the potential VDD/2 between VDD and VSS according to the precharge signal applied to the precharge line PCL1. Circuit.
  • the precharge circuit 22_B is composed of n-channel type transistors 24_4 to 24_6.
  • the precharge circuit 22_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC corresponding to the potential VDD/2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL2. is there.
  • the sense amplifier 22_C includes p-channel transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 connected to the wiring VHH or the wiring VLL.
  • the wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS.
  • the transistors 25_1 to 25_4 are transistors that form an inverter loop.
  • the sense amplifier 22_C sets the potential of the wiring GBL_A and the wiring GBL_B to the high power supply potential VDD in accordance with the potentials of the bit line BL_A and the bit line BL_B which are changed by selecting the memory cells 31_N_A and 31_N_B by setting the word lines WL_A and WL_B at a high level.
  • the low power supply potential VSS is set.
  • the potentials of the wiring GBL_A and the wiring GBL_B can be output to the outside through the switch circuit 22_D and the switch circuit 22_E and the writing/reading circuit 25.
  • the bit line BL_A and the bit line BL_B, and the wiring GBL_A and the wiring GBL_B correspond to a bit line pair.
  • writing of the data signal is controlled according to the signal EN_data.
  • the switch circuit 22_D is a circuit for controlling the conduction state between the sense amplifier 22_C and the wiring GBL_A and the wiring GBL_B.
  • the switch circuit 22_D is switched on or off by the control of the switching signal CSEL1.
  • the switches 23_A and 23_B are n-channel transistors, the switches 23_A and 23_B are turned on when the switching signal CSEL1 is at high level, and the switches 23_A and 23_B are turned off when at low level.
  • the switch circuit 22_E is a circuit for controlling the conduction state between the write/read circuit 29 and the bit line pair connected to the sense amplifier 22_C.
  • the switch circuit 22_D is switched on or off by the control of the switching signal CSEL1.
  • the switches 23_C and 23_D may be turned on or off under the control of the CSEL2, similarly to the switches 23_A and 23_B.
  • FIG. 23 shows a timing chart for explaining the operation of the circuit diagram shown in FIG.
  • a period T11 is a write operation
  • a period T12 is a bit line BL precharge operation
  • a period T13 is a wiring GBL precharge operation
  • a period T14 is a charge sharing operation
  • a period T15 is a read standby.
  • the period T16 corresponds to the period for explaining the read operation.
  • the word line connected to the gate of the transistor included in the memory cell in which the data signal is to be written is set to high level.
  • the control signal WE and the signal EN_data are set to a high level, and the data signal is written into the memory cell through the wiring GBL and the bit line BL.
  • the precharge line PCL1 is set to high level while the control signal WE is set to high level.
  • the bit line BL is precharged to the precharge potential.
  • both the wiring VHH and the wiring VLL which supply a power supply voltage to the sense amplifier 22_C be VDD/2 to suppress power consumption due to a through current.
  • the wiring GBL is precharged, so that the precharge line PCL2 is set to the high level.
  • the wiring GBL is precharged to the precharge potential.
  • the wiring VHH and the wiring VLL are both set to VDD, whereby the wiring GBL having a large load can be precharged in a short time.
  • the control signal WL and the control signal MUX are set to the high level for charge sharing for balancing the charges precharged on the bit line BL and the wiring GBL.
  • the bit line BL and the wiring GBL have the same potential.
  • both the wiring VHH and the wiring VLL which supply the power supply voltage to the sense amplifier 22_C be VDD/2 to suppress power consumption due to a through current.
  • the control signal RE is set to high level.
  • a current flows through the transistor 41 in accordance with the potential of the bit line BL, and the potential of the wiring GBL changes in accordance with the amount of the current.
  • the switching signal CSEL1 is set to a low level so that variation in the potential of the wiring GBL is not influenced by the sense amplifier 22_C.
  • the wiring VHH or the wiring VLL is the same as in the period T14.
  • the switching signal CSEL1 is set to a high level, and the fluctuation of the potential of the wiring GBL is amplified by the bit line pair connected to the sense amplifier 22_C to read the data signal written in the memory cell.
  • the configuration of the semiconductor device 10B shown in FIG. 17 can be rewritten as shown in the circuit diagram of FIG. 24 when the circuit configuration of the element layer 40B of FIG. 18B is adopted.
  • the transistor 42 of the element layers 40_1 to 40_M included in each unit is extracted, and a switching circuit 49 including the transistor 42 is illustrated. That is, the element layers 40_1 to 40_M select one of the memory cells 31_1 to 31_M selected by one of the element layers 40_1 to 40_M selected by the switching circuit 49 to write or read a data signal. be able to.
  • the semiconductor device of one embodiment of the present invention uses an OS transistor with extremely low off-state current as a transistor provided in each element layer.
  • the OS transistor can be provided by being stacked over a silicon substrate provided with a Si transistor. Therefore, the same manufacturing process can be repeated in the vertical direction, and the manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • one embodiment of the present invention includes an element layer having a control circuit. Since the control circuit connects the bit line BL to the gate of the transistor 41, the transistor 41 can function as an amplifier. With such a structure, a slight potential difference of the bit line BL can be amplified at the time of reading and a sense amplifier including a Si transistor can be driven. Since a circuit such as a sense amplifier including a Si transistor can be downsized, a semiconductor device can be downsized. Further, it becomes possible to operate even if the capacity of the capacitor included in the memory cell is reduced.
  • FIG. 25A is a block diagram of a semiconductor device described in this embodiment.
  • a semiconductor device 10F illustrated in FIG. 1A includes a peripheral circuit 20 and a memory cell array 30.
  • the memory cell array 30 has a plurality of or single element layers 34.
  • the element layer 34 has one or more memory cells 31_1 to 31_N (N is a natural number of 2 or more).
  • the memory cell 31_1 includes the transistor 32_1 and the capacitor 33_1.
  • the memory cell 31_N includes a transistor 32_N and a capacitor 33_N.
  • the capacitor may be called a capacitive element.
  • the element layer is a layer in which elements such as capacitors and transistors are provided, and is a layer formed of a member such as a conductor, a semiconductor, or an insulator.
  • FIG. 25A the element layer 34 which is one embodiment of the present invention will be described with reference to the schematic diagram illustrated in FIG. 25B.
  • the schematic view shown in FIG. 25B corresponds to a perspective view defining the x-axis, y-axis, and z-axis directions in order to explain the arrangement of the components described in FIG. 25A.
  • the element layer 34 including the memory cells 31_1 to 31_N has a region overlapping with the column driver 22 provided in the silicon substrate 11.
  • the transistor of the memory cell 31_1 included in the element layer 34 is connected to the column driver 22 via the bit line BL_1 provided in the vertical direction.
  • the transistor of the memory cell 31_N included in the element layer 34 is connected to the column driver 22 through the bit line BL_N provided in the vertical direction.
  • the bit lines BL_1 and BL_N and the other bit lines BL are connected to the column driver 22 provided on the silicon substrate 11.
  • an OS transistor with extremely low off-state current is used as a transistor provided in each element layer. Therefore, the frequency of refreshing data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be obtained.
  • the OS transistors can be provided in a stacked structure and can be manufactured by repeating the same manufacturing process in the vertical direction, so that manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • the OS transistor since the OS transistor has less variation in electrical characteristics than the Si transistor even in a high temperature environment, the variation in electrical characteristics of the transistor when stacked and integrated is small and a semiconductor device which functions as a highly reliable memory device.
  • a bit line extending from the memory cell array is provided in a vertical direction, whereby the length of the bit line between the memory cell array and the column driver can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced, so that the potential can be read even when the data signal held in the memory cell is multivalued.
  • FIG. 26 shows a schematic diagram of a cross section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10F described with reference to FIGS. 25A and 25B.
  • the memory cells 31_1 to 31_N provided in the element layer 34 and the column driver 22 provided in the silicon substrate 11 are provided in the bit line BL provided in the vertical direction which is the shortest distance. It can be configured to be connected via.
  • the number of bit lines is increased as compared with the configuration in which the bit lines are arranged in the plane direction, the number of memory cells connected to one bit line can be reduced, so that the parasitic capacitance of the bit line can be reduced. .. Therefore, even if the capacitance of the capacitor included in the memory cell is reduced, the potential of the bit line can be changed with the movement of charges.
  • the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N can be reduced in capacity, the capacitors 33_1 to 33_N can be provided in the same layer as the transistors 32_1 to 32_N.
  • the element layers 34_1 to 34_N for each layer can be thinned. Therefore, the semiconductor device 10F can be downsized.
  • the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N may have a structure provided in the same layer as the transistors 32_1 to 32_N, but may have another structure.
  • the capacitor 33A of the memory cell 31 included in the element layers 34_1 to 34_N is provided above the transistor 32 in the vertical direction. With such a structure, the capacity can be increased, so that reliability of data to be read and data retention time can be improved.
  • the electrode of the capacitor 33A whose one electrode is connected to the fixed potential can be arranged above the transistor 32, the influence of noise from the outside can be suppressed.
  • the schematic diagram in FIG. 27B shows a structure in which the capacitor 33B of the memory cell 31 included in the element layers 34_1 to 34_N is provided below the transistor 32 in the vertical direction.
  • the capacity can be increased, so that reliability of data to be read and data retention time can be improved.
  • the electrode of the capacitor 33B whose one electrode is connected to a fixed potential can be arranged between the transistor 32 and the column driver 22, the noise of the column driver 22 is reduced. The influence on the memory cell 31 can be suppressed.
  • FIG. 28 is a circuit illustrating a circuit configuration example of the memory cell array 30 including the element layer 34 described in FIG. 25A and a specific circuit configuration example of the column driver 22 connected to the memory cell. It is a figure.
  • FIG. 28 shows the element layer 34 as the memory cell array 30.
  • the memory cell 31_N_A is provided as a memory cell connected to the bit line BL_A.
  • the memory cell 31_N_A illustrates the transistor 32A and the capacitor 33 whose gates are connected to the word line WL_A.
  • a memory cell 31_N_B is provided as a memory cell connected to the bit line BL_B.
  • the memory cell 31_N_B shows the transistor 32B and the capacitor 33 whose gates are connected to the word line WL_B.
  • the capacitor 33 of each element layer is connected to the wiring VL to which a fixed potential, for example, the ground potential is given.
  • FIG. 28 shows, as circuits included in the column driver 22, a precharge circuit 22_1, a sense amplifier 22_2, a switch circuit 22_3, and a write/read circuit 29 on the silicon substrate side.
  • Si transistors are used as transistors included in the precharge circuit 22_1 and the sense amplifier 22_2.
  • a Si transistor can also be used for the selection switch 22_3.
  • FIG. 29 shows a timing chart for explaining the operation of the circuit diagram shown in FIG.
  • a period T1 corresponds to a period of initialization operation
  • a period T2 corresponds to a write operation
  • a period T3 corresponds to a non-access operation
  • a period T4 corresponds to a read operation.
  • the semiconductor device of one embodiment of the present invention uses an OS transistor with extremely low off-state current as a transistor provided in each element layer.
  • the OS transistor can be provided by being stacked over a silicon substrate provided with a Si transistor. Therefore, the same manufacturing process can be repeated in the vertical direction, and the manufacturing cost can be reduced.
  • transistors included in a memory cell are arranged not in a planar direction but in a vertical direction, so that the memory density can be improved and the device can be downsized.
  • the transistor is illustrated as a top-gate or bottom-gate transistor without a back gate electrode, but the structure of the transistor 32 is not limited to this.
  • the transistor included in the memory cell 31 may be the transistor 32 including the back gate electrode connected to the back gate electrode line BGL.
  • electrical characteristics such as the threshold voltage of the transistor 32 can be easily controlled from the outside.
  • the transistor that constitutes the switching circuit for the element layer 26 described above is illustrated as a top-gate or bottom-gate transistor without a back gate electrode, but the transistor structure is not limited to this.
  • the transistor forming the switching circuit 27 may be a transistor 28 having a back gate electrode connected to the back gate electrode line BGL. With the structure in FIG. 31, electric characteristics such as the threshold voltage of the transistor 28 can be easily controlled from the outside.
  • the transistor is illustrated as a top-gate or bottom-gate transistor without a back gate electrode, but the structure of the transistor 32 is not limited to this.
  • the transistor included in the memory cell 31 may be the transistor 32 including a back gate electrode connected to the back gate electrode line BGL. With the structure in FIG. 32, electric characteristics such as the threshold voltage of the transistor 32 can be easily controlled from the outside.
  • the transistor is illustrated as a transistor having a top gate structure or a bottom gate structure without a back gate electrode, but the structure of the transistor 32 is not limited to this.
  • the transistor included in the memory cell 31 may be the transistor 32 including the back gate electrode connected to the back gate electrode line BGL. With the structure in FIG. 33, electric characteristics such as the threshold voltage of the transistor 32 can be easily controlled from the outside.
  • FIG. 34 illustrates an example of a semiconductor device in which a memory unit 470 (memory units 470_1 to 470_m:m is a natural number of 2 or more) is stacked over the element layer 411 including a circuit provided in the semiconductor substrate 311.
  • a memory unit 470 memory units 470_1 to 470_m:m is a natural number of 2 or more
  • FIG. 34 an element layer 411 and a plurality of memory units 470 are stacked over the element layer 411.
  • the plurality of memory units 470 include a transistor layer 413 (transistor layers 413_1 to 413_m) and transistor layers 413_m, respectively.
  • An example in which a plurality of memory device layers 415 (memory device layers 415_1 to 415_n: n is a natural number of 2 or more) is provided over 413 is illustrated.
  • each memory unit 470 an example in which the memory device layer 415 is provided over the transistor layer 413 is shown; however, the present embodiment is not limited to this.
  • the transistor layer 413 may be provided over the plurality of memory device layers 415, or the memory device layers 415 may be provided above and below the transistor layer 413.
  • the element layer 411 includes the transistor 300 provided over the semiconductor substrate 311 and can function as a circuit of a semiconductor device (sometimes referred to as a peripheral circuit).
  • Examples of circuits include a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, an amplifier circuit, a word line driver circuit, an output circuit, a control logic circuit, and the like.
  • the transistor layer 413 includes the transistor 200T and can function as a circuit which controls each memory unit 470.
  • the memory device layer 415 has a memory device 420.
  • the memory device 420 described in this embodiment includes the transistor 200M and the capacitor 292.
  • m is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less.
  • n is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less.
  • the product of m and n is 4 or more and 256 or less, preferably 4 or more and 128 or less, and more preferably 4 or more and 64 or less.
  • FIG. 34 shows a cross-sectional view in the channel length direction of the transistor 200T and the transistor 200M included in the memory unit.
  • the transistor 300 is provided over the semiconductor substrate 311, and the transistor layer 413 included in the memory unit 470 and the memory device layer 415 are provided over the transistor 300.
  • the transistor layer 413 is provided in one memory unit 470.
  • the transistor 200T included in the memory device layer 415 and the memory device 420 included in the memory device layer 415 are electrically connected to each other by a plurality of conductors 424.
  • the transistor 300 and the transistor 200T included in the transistor layer 413 in each memory unit 470 include the conductor 426. Are electrically connected by.
  • the conductor 426 is preferably electrically connected to the transistor 200T through a conductor 428 which is electrically connected to any one of a source, a drain, and a gate of the transistor 200T.
  • the conductor 424 is preferably provided in each layer of the memory device layer 415.
  • the conductor 426 is preferably provided in each layer of the transistor layer 413 and the memory device layer 415.
  • an insulator on the side surface of the conductor 424 and the side surface of the conductor 426 to suppress impurities such as water or hydrogen and oxygen permeation.
  • an insulator for example, silicon nitride, aluminum oxide, silicon nitride oxide, or the like may be used.
  • the memory device 420 includes the transistor 200M and the capacitor 292, and the transistor 200M can have a structure similar to that of the transistor 200T included in the transistor layer 413.
  • the transistor 200T and the transistor 200M may be collectively referred to as the transistor 200.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is used for a semiconductor including a region where a channel is formed (hereinafter also referred to as a channel formation region). Is preferred.
  • an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium).
  • the oxide semiconductor for example, an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium).
  • neodymium, hafnium, tantalum, tungsten, magnesium, or the like is preferably used.
  • indium oxide, In—Ga oxide, or In—Zn oxide may be used as the oxide semiconductor. Note that the on-state current, field-effect mobility, or the like of the transistor can be increased by using an oxide semiconductor with a high proportion of indium.
  • the transistor 200 including an oxide semiconductor in a channel formation region has an extremely small leakage current in a non-conduction state, so that a semiconductor device with low power consumption can be provided.
  • the oxide semiconductor can be formed by a sputtering method or the like, it can be used for the transistor 200 included in a highly integrated semiconductor device.
  • a transistor including an oxide semiconductor, impurities and oxygen vacancies in the oxide semiconductor by (V O oxygen vacancy also called), its electrical characteristics are varied, a voltage is applied to normally on (gate electrode Even if it does not exist, there is a channel, and the current tends to flow through the transistor).
  • an oxide semiconductor with reduced impurity concentration and defect level density it is preferable to use an oxide semiconductor with reduced impurity concentration and defect level density. Note that in this specification and the like, low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
  • hydrogen as an impurity contained in the oxide semiconductor might cause oxygen vacancies in the oxide semiconductor.
  • defects containing hydrogen to an oxygen vacancy (hereinafter may be referred to as V O H.) May generate electrons serving as carriers.
  • a part of hydrogen may react with oxygen which is bonded to a metal atom to generate an electron serving as a carrier.
  • a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Further, hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field; therefore, when a large amount of hydrogen is contained in the oxide semiconductor, reliability of the transistor might be deteriorated.
  • the oxide semiconductor used for the transistor 200 it is preferable to use a highly purified intrinsic oxide semiconductor in which impurities such as hydrogen and oxygen vacancies are reduced.
  • the transistor 200 may be sealed with a material that suppresses diffusion of impurities (hereinafter also referred to as a barrier material against impurities).
  • the barrier property is a function of suppressing diffusion of a corresponding substance (also referred to as low permeability).
  • the corresponding substance has a function of capturing and fixing (also referred to as gettering).
  • Examples of materials having a function of suppressing diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, it is preferably used as a sealing material.
  • metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.
  • an insulator 211, an insulator 212, and an insulator 214 are preferably provided as a layer having a barrier property.
  • An impurity such as hydrogen or water contained in the semiconductor substrate 311, the transistor 300, or the like is used for at least one of the insulator 211, the insulator 212, and the insulator 214 by using a material which suppresses diffusion or transmission of impurities such as hydrogen. Can be suppressed from diffusing into the transistor 200.
  • a material which suppresses oxygen permeation for at least one of the insulator 211, the insulator 212, and the insulator 214, oxygen contained in the channel of the transistor 200 or the transistor layer 413 diffuses into the element layer 411.
  • a material that suppresses permeation of impurities such as hydrogen and water as the insulator 211 and the insulator 212 and a material that suppresses permeation of oxygen as the insulator 214. Further, it is more preferable to use a material having a property of absorbing and storing hydrogen as the insulator 214.
  • a nitride such as silicon nitride or silicon nitride oxide can be used.
  • a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used. In particular, it is preferable to use aluminum oxide as the insulator 214.
  • the insulator 287 is preferably provided on the side surfaces of the transistor layer 413 and the memory device layer 415, that is, the side surface of the memory unit 470, and the insulator 282 is preferably provided on the upper surface of the memory unit 470.
  • the insulator 282 is preferably in contact with the insulator 287, and the insulator 287 is preferably in contact with at least one of the insulator 211, the insulator 212, and the insulator 214.
  • a material that can be used for the insulator 214 is preferably used.
  • an insulator 283 and an insulator 284 are preferably provided so as to cover the insulator 282 and the insulator 287, and the insulator 283 is at least one of the insulator 211, the insulator 212, and the insulator 214. It is preferable to contact them.
  • the insulator 287 is in contact with the side surface of the insulator 214, the side surface of the insulator 212, and the top surface and side surface of the insulator 211, and the insulator 283 is connected to the top surface and side surface of the insulator 287 and the top surface of the insulator 211.
  • the present embodiment is not limited to this.
  • the insulator 287 may be in contact with the side surface of the insulator 214, the upper surface and the side surface of the insulator 212, and the insulator 283 may be in contact with the upper surface and the side surface of the insulator 287 and the upper surface of the insulator 212.
  • a material that can be used for the insulator 211 and the insulator 212 is preferably used.
  • a material that suppresses oxygen permeation as the insulator 287 and the insulator 282.
  • a material having a property of capturing and fixing hydrogen as the insulator 287 and the insulator 282.
  • hydrogen in the transistor 200 or the memory unit 470 is transferred to the insulator 214, the insulator 287, and the insulator 282.
  • the hydrogen concentration in the transistor 200 can be reduced because of being trapped, captured, and fixed.
  • a material that suppresses permeation of impurities such as hydrogen and water as the insulator 283 and the insulator 284.
  • the memory unit 470 is surrounded by the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. More specifically, the memory unit 470 is surrounded by the insulator 214, the insulator 287, and the insulator 282 (may be referred to as a first structure), and the memory unit 470 and the first structure may be enclosed.
  • a second structure may be referred to as a second structure.
  • a structure in which the memory unit 470 is surrounded by a plurality of structures having two or more layers as described above may be referred to as a nested structure.
  • enclosing the memory unit 470 with a plurality of structures may be referred to as enclosing the memory unit 470 with a plurality of insulators.
  • the second structure seals the transistor 200 through the first structure. Therefore, hydrogen existing outside the second structure is suppressed from being diffused into the inside of the second structure (on the side of the transistor 200) by the second structure. That is, the first structure body can efficiently capture and fix hydrogen existing in the internal structure of the second structure body.
  • a metal oxide such as aluminum oxide can be used for the first structure
  • a nitride such as silicon nitride can be used for the second structure.
  • an aluminum oxide film may be provided between the transistor 200 and the silicon nitride film.
  • the material used for the structure can reduce the hydrogen concentration in the film by appropriately setting the film forming conditions.
  • the film formed using the CVD method has higher coverage than the film formed using the sputtering method.
  • the compound gas used for the CVD method often contains hydrogen, and the film formed by the CVD method has a higher hydrogen content than the film formed by the sputtering method.
  • a film in which the hydrogen concentration in the film is reduced (specifically, a film formed by a sputtering method) may be used as a film close to the transistor 200.
  • a film having a high film-forming property and a relatively high hydrogen concentration in the film (specifically, a film formed by a CVD method) is used as a film for suppressing diffusion of impurities
  • a film having a function of capturing and fixing hydrogen and having a reduced hydrogen concentration may be arranged between the film having a relatively high hydrogen concentration and a high coating property.
  • a film having a relatively low hydrogen concentration in the film as a film arranged in the vicinity of the transistor 200.
  • a film having a relatively high hydrogen concentration in the film may be placed remotely from the transistor 200.
  • the transistor 200 when the transistor 200 is sealed with silicon nitride formed by a CVD method, the transistor 200 is provided between the transistor 200 and the silicon nitride film formed by a CVD method.
  • An aluminum oxide film formed by a sputtering method may be provided. More preferably, a silicon nitride film formed by a sputtering method may be provided between a silicon nitride film formed by a CVD method and an aluminum oxide film formed by a sputtering method.
  • the concentration of hydrogen contained in the formed film is reduced by forming a film using a compound gas which does not contain hydrogen atoms or has a small content of hydrogen atoms. May be.
  • the insulator 282 and the insulator 214 are provided between each transistor layer 413 and the memory device layer 415 or between each memory device layer 415.
  • an insulator 296 is preferably provided between the insulator 282 and the insulator 214.
  • the insulator 296, a material similar to that of the insulator 283 and the insulator 284 can be used. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material may be used.
  • the insulator 282, the insulator 296, and the insulator 214 may be components included in the transistor 200. It is preferable that the insulator 282, the insulator 296, and the insulator 214 also serve as components of the transistor 200 because the number of steps for manufacturing a semiconductor device can be reduced.
  • side surfaces of the insulator 282, the insulator 296, and the insulator 214 provided between the transistor layers 413 and the memory device layers 415 or between the memory device layers 415 are preferably in contact with the insulator 287. ..
  • the transistor layer 413 and the memory device layer 415 are surrounded by the insulator 282, the insulator 296, the insulator 214, the insulator 287, the insulator 283, and the insulator 284, respectively, and are sealed. To be done.
  • the insulator 274 may be provided around the insulator 284. Further, the conductor 430 may be provided so as to be embedded in the insulator 274, the insulator 284, the insulator 283, and the insulator 211. The conductor 430 is electrically connected to the transistor 300, that is, a circuit included in the element layer 411.
  • the height of the memory device 420 can be made approximately the same as that of the transistor 200M, and the height of each memory device layer 415 can be increased. Can be suppressed from becoming excessively large. This makes it possible to increase the number of memory device layers 415 relatively easily.
  • the stack of the transistor layer 413 and the memory device layer 415 may be about 100 layers.
  • Transistor 200 A transistor 200T that can be included in the transistor 200T included in the transistor layer 413 and the transistor 200M included in the memory device 420 will be described with reference to FIG.
  • the transistor 200 includes an insulator 216, a conductor 205 (a conductor 205a and a conductor 205b), an insulator 222, an insulator 224, and an oxide 230 (oxide. 230a, the oxide 230b, and the oxide 230c), the conductor 242 (the conductor 242a, and the conductor 242b), the oxide 243 (the oxide 243a, and the oxide 243b), the insulator 272, and the insulator. 273, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b).
  • the insulator 216 and the conductor 205 are provided on the insulator 214, and the insulator 280 and the insulator 282 are provided on the insulator 273.
  • the insulator 214, the insulator 280, and the insulator 282 can be regarded as forming part of the transistor 200.
  • the semiconductor device of one embodiment of the present invention includes the conductor 240 (the conductor 240a and the conductor 240b) which is electrically connected to the transistor 200 and serves as a plug.
  • the insulator 241 (the insulator 241a and the insulator 241b) may be provided in contact with the side surface of the conductor 240 which functions as a plug.
  • a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and serves as a wiring is provided over the insulator 282 and the conductor 240.
  • a conductive material containing tungsten, copper, or aluminum as a main component for the conductors 240a and 240b.
  • the conductor 240a and the conductor 240b may have a stacked structure.
  • the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen.
  • a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen
  • the conductive material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen may be used as a single layer or a stacked layer.
  • impurities such as water or hydrogen diffused from the insulator 280 or the like can be further reduced from entering the oxide 230 through the conductors 240a and 240b. Further, oxygen added to the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
  • the insulator 241 provided in contact with the side surface of the conductor 240 for example, silicon nitride, aluminum oxide, silicon nitride oxide, or the like may be used. Since the insulator 241 is provided in contact with the insulator 272, the insulator 273, the insulator 280, and the insulator 282, impurities such as water or hydrogen from the insulator 280 are oxidized through the conductor 240a and the conductor 240b. It is possible to prevent the product 230 from being mixed. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.
  • the conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in the opening provided in the insulator.
  • the conductor 260 functions as a first gate of the transistor and the conductor 205 functions as a second gate of the transistor.
  • the conductor 242a and the conductor 242b function as a source electrode or a drain electrode.
  • the oxide 230 functions as a semiconductor having a channel formation region.
  • the insulator 250 functions as a first gate insulator, and the insulator 222 and the insulator 224 function as a second gate insulator.
  • the conductor 260 includes the oxide 230c and the insulator 250 in the openings provided in the insulator 280, the insulator 273, the insulator 272, and the conductor 242. Through, it is formed in a self-aligned manner.
  • the conductor 260 is formed so as to fill the opening provided in the insulator 280 and the like with the oxide 230c and the insulator 250 interposed therebetween, the conductor 260 is formed in a region between the conductor 242a and the conductor 242b. Positioning of 260 is unnecessary.
  • the oxide 230c in the opening provided in the insulator 280 or the like. Therefore, the insulator 250 and the conductor 260 have a region which overlaps with the stacked structure of the oxide 230b and the oxide 230a with the oxide 230c interposed therebetween. With such a structure, the oxide 230c and the insulator 250 can be formed by continuous film formation, so that the interface between the oxide 230 and the insulator 250 can be kept clean. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-state current and high frequency characteristics.
  • the bottom surface and the side surface of the conductor 260 are in contact with the insulator 250. Further, the bottom surface and the side surface of the insulator 250 are in contact with the oxide 230c.
  • the transistor 200 has a structure in which the insulator 282 and the oxide 230c are in direct contact with each other, as shown in FIG. With such a structure, diffusion of oxygen contained in the insulator 280 into the conductor 260 can be suppressed.
  • oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b through the oxide 230c, so that oxygen vacancies in the oxide 230a and the oxide 230b are reduced.
  • the electrical characteristics and reliability of the transistor 200 can be improved.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is used for the oxide 230 including the channel formation region (the oxide 230a, the oxide 230b, and the oxide 230c). preferable.
  • the metal oxide functioning as an oxide semiconductor it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more.
  • an energy gap of 2 eV or more By using a metal oxide having a large energy gap, leakage current (off current) in the non-conduction state of the transistor 200 can be extremely reduced.
  • a low power consumption semiconductor device By using such a transistor, a low power consumption semiconductor device can be provided.
  • an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, A metal oxide such as lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used.
  • the element M is preferably aluminum, gallium, yttrium, or tin.
  • an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used as the oxide 230.
  • the oxide 230 is provided over the oxide 230a over the insulator 224, the oxide 230b over the oxide 230a, and the oxide 230b, and at least a part of the oxide 230b is provided. And an oxide 230c in contact with the upper surface of.
  • the side surface of the oxide 230c is preferably provided in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272, the insulator 273, and the insulator 280.
  • the oxide 230 includes the oxide 230a, the oxide 230b on the oxide 230a, and the oxide 230c on the oxide 230b.
  • the oxide 230a under the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed below the oxide 230a can be suppressed.
  • the oxide 230c over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.
  • the transistor 200 has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in the channel formation region and the vicinity thereof, the present invention is not limited to this. ..
  • a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided.
  • the oxide 230c may have a two-layer structure and a four-layer stacked structure may be provided.
  • the oxide 230 preferably has a laminated structure due to oxides having different atomic ratios of the respective metal atoms.
  • the atomic ratio of the element M in the constituent elements is higher than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. It is preferable.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • the above metal oxide may be used.
  • an In oxide may be used as the oxide 230b.
  • a material that can be used for the oxide 230b may be applied to the oxide 230c and the oxide 230c may be provided as a single layer or a stacked layer.
  • the structure of the OS transistor included in the memory cell array 30 and the structure of the OS transistor included in the element layer 40 described in Embodiment 1 may be different.
  • the oxide 230b and the oxide 230c it is preferable to increase the ratio of indium in the film because the on-state current, the field-effect mobility, or the like of the transistor can be increased. Further, the above-mentioned composition in the vicinity includes a range of ⁇ 30% of a desired atomic number ratio.
  • the oxide 230b may have crystallinity.
  • a CAAC-OS c-axis aligned crystalline oxide semiconductor
  • An oxide having crystallinity such as CAAC-OS has few impurities and defects (such as oxygen vacancies) and has a high crystallinity and a dense structure. Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Further, even if heat treatment is performed, oxygen can be reduced from being extracted from the oxide 230b, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in a manufacturing process.
  • the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260.
  • the conductor 205 is preferably embedded in the insulator 216 and provided.
  • the threshold voltage (Vth of the transistor 200 is changed by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. ) Can be controlled.
  • Vth of the transistor 200 can be further increased and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.
  • the conductor 205 is preferably larger than a region of the oxide 230 which does not overlap with the conductors 242a and 242b as illustrated in FIG.
  • the conductor 205 preferably extends to a region outside the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with the insulator provided outside the side surface of the oxide 230 in the channel width direction.
  • charge-up local charging
  • the conductor 205 may overlap with at least the oxide 230 located between the conductor 242a and the conductor 242b.
  • the height of the bottom surface of the conductor 260 in a region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is lower than the height of the bottom surface of the oxide 230b.
  • the conductor 260 functioning as a gate in the channel width direction has a structure in which the side surface and the upper surface of the oxide 230b in the channel formation region are covered with the oxide 230c and the insulator 250, whereby the conductor 260 is formed.
  • the electric field generated by V.sub.2 becomes easy to act on the entire channel formation region generated in the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • a structure of a transistor that electrically surrounds a channel formation region by an electric field of the conductor 260 and the conductor 205 is referred to as a surrounded channel (S-channel) structure.
  • the conductor 205a is preferably a conductor that suppresses permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen.
  • titanium, titanium nitride, tantalum, or tantalum nitride can be used.
  • the conductor 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component.
  • the conductor 205 is illustrated as having two layers, it may have a multilayer structure of three or more layers.
  • the oxide semiconductor, the insulator or the conductor located in the lower layer of the oxide semiconductor, and the insulator or the conductor located in the upper layer of the oxide semiconductor are formed into different films without being exposed to the atmosphere. It is preferable to continuously form the seeds because an oxide semiconductor film with substantially high purity and intrinsic concentration in which impurities (especially hydrogen and water) are reduced can be formed.
  • At least one of the insulator 222 and the insulator 272 and the insulator 273 functions as a barrier insulating film which suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Is preferred. Therefore, at least one of the insulator 222, the insulator 272, and the insulator 273 has at least one of hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitric oxide molecule (N 2 O, NO, NO 2, etc.), It is preferable to use an insulating material having a function of suppressing diffusion of impurities such as copper atoms (the above impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) (the above oxygen is less likely to permeate).
  • oxygen eg, at least one of oxygen atoms and oxygen molecules
  • silicon nitride or silicon nitride oxide as the insulator 273 and aluminum oxide or hafnium oxide as the insulator 222 and the insulator 272.
  • impurities such as water or hydrogen can be suppressed from diffusing to the transistor 200 side through the insulator 222.
  • oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side through the insulator 222.
  • impurities such as water or hydrogen can be suppressed from diffusing to the transistor 200 side from the insulator 280 and the like which are provided through the insulator 272 and the insulator 273.
  • the transistor 200 is preferably surrounded by the insulator 272 and the insulator 273 which have a function of suppressing diffusion of impurities such as water or hydrogen and oxygen.
  • the insulator 224 in contact with the oxide 230 desorb oxygen by heating.
  • oxygen released by heating may be referred to as excess oxygen.
  • the insulator 224 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate.
  • an oxide material from which part of oxygen is released by heating is preferably used.
  • the oxide that desorbs oxygen by heating means that the desorption amount of oxygen molecules is 1.0 ⁇ 10 18 molecules/cm 3 or more, preferably by thermal desorption gas analysis (TDS (Thermal Desorption Spectroscopy) analysis).
  • TDS Thermal Desorption gas analysis
  • the surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.
  • the insulator 222 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side.
  • the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 222 has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to permeate).
  • the insulator 222 preferably has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 have a function of suppressing diffusion of oxygen and impurities because oxygen in the oxide 230 can be prevented from diffusing below the insulator 222.
  • the conductor 205 can be prevented from reacting with the insulator 224 and oxygen contained in the oxide 230.
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials, may be used.
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and mixture of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator and used.
  • the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3 (BST).
  • An insulator including a so-called high-k material may be used in a single layer or a stacked layer.
  • a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide is sequentially formed, zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed.
  • a four-layer stack formed in order may be used.
  • the insulator 222 may be a compound containing hafnium and zirconium.
  • problems such as leakage current of transistors and capacitors may occur due to thinning of the gate insulator and the dielectric used for the capacitors.
  • a high-k material for a gate insulator and an insulator functioning as a dielectric used for a capacitor reduction in gate potential during operation of a transistor and securing of capacitance of the capacitor while maintaining a physical film thickness can be achieved. It will be possible.
  • the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the oxide 243 (the oxide 243a and the oxide 243b) may be provided between the oxide 230b and the conductor 242 (the conductor 242a and the conductor 242b) which functions as a source electrode or a drain electrode. .. Since the conductor 242 and the oxide 230b are not in contact with each other, the conductor 242 can be prevented from absorbing oxygen in the oxide 230b. That is, by preventing the conductor 242 from being oxidized, it is possible to suppress a decrease in the conductivity of the conductor 242. Therefore, the oxide 243 preferably has a function of suppressing oxidation of the conductor 242.
  • the oxide 243 having a function of suppressing permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, electrical conductivity between the conductor 242 and the oxide 230b can be obtained. It is preferable because the resistance is reduced. With such a structure, electric characteristics of the transistor 200 and reliability of the transistor 200 can be improved.
  • the oxide 243 is selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. You may use the metal oxide which has the element M which consists of 1 type or multiple types. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. The oxide 243 preferably has a higher concentration of the element M than the oxide 230b. Alternatively, gallium oxide may be used as the oxide 243.
  • the oxide 243 a metal oxide such as an In-M-Zn oxide may be used.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less.
  • the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, release of oxygen in the oxide 230 can be preferably suppressed. For example, if the oxide 243 has a hexagonal crystal structure or the like, release of oxygen in the oxide 230 can be suppressed in some cases.
  • the oxide 243 does not necessarily have to be provided. In that case, when the conductor 242 (the conductor 242a and the conductor 242b) is in contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 242 and the conductor 242 may be oxidized. Oxidation of the conductor 242 is likely to reduce the conductivity of the conductor 242. Note that diffusion of oxygen in the oxide 230 to the conductor 242 can be restated as absorption of oxygen in the oxide 230 by the conductor 242.
  • oxygen in the oxide 230 diffuses into the conductor 242 (the conductor 242a and the conductor 242b), so that the conductor 242a and the oxide 230b are separated from each other and the conductor 242b and the oxide 230b are separated from each other.
  • Different layers may be formed between them. Since the different layer contains more oxygen than the conductor 242, it is estimated that the different layer has an insulating property.
  • the three-layer structure of the conductor 242, the different layer, and the oxide 230b can be regarded as a three-layer structure including a metal-insulator-semiconductor and a MIS (Metal-Insulator-Semiconductor) structure. It may be referred to as a diode junction structure mainly including the MIS structure.
  • the different layer is not limited to being formed between the conductor 242 and the oxide 230b.
  • the different layer is formed between the conductor 242 and the oxide 230c, It may be formed between the body 242 and the oxide 230b and between the conductor 242 and the oxide 230c.
  • a conductor 242 (a conductor 242a and a conductor 242b) which functions as a source electrode and a drain electrode is provided over the oxide 243.
  • the film thickness of the conductor 242 may be, for example, 1 nm to 50 nm inclusive, preferably 2 nm to 25 nm inclusive.
  • the conductor 242 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. It is preferable. Further, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when absorbing oxygen is preferable.
  • the insulator 272 is provided in contact with the top surface of the conductor 242 and preferably functions as a barrier layer. With such a structure, absorption of excess oxygen in the insulator 280 by the conductor 242 can be suppressed. Further, by suppressing the oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can have favorable electrical characteristics and reliability.
  • the insulator 272 preferably has a function of suppressing oxygen diffusion.
  • the insulator 272 preferably has a function of suppressing diffusion of oxygen as compared with the insulator 280.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed.
  • an insulator containing aluminum nitride may be used.
  • the insulator 272 is in contact with part of the top surface of the conductor 242b and the side surface of the conductor 242b. Although not shown, the insulator 272 is in contact with part of the upper surface of the conductor 242a and the side surface of the conductor 242a. Further, the insulator 273 is provided over the insulator 272. By doing so, for example, oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 242.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably arranged in contact with the top surface of the oxide 230c.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon-nitrogen-added silicon oxide, or silicon oxide having holes is used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • an insulator from which oxygen is released by heating is provided as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b.
  • the concentration of impurities such as water or hydrogen in the insulator 250 be reduced.
  • the thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 250 and the conductor 260.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260.
  • oxygen diffusion from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed.
  • oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.
  • the metal oxide may have a function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a high-k material with a high relative dielectric constant. When the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure which is stable to heat and has a high relative dielectric constant can be obtained. Therefore, the gate potential applied during the operation of the transistor can be reduced while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator.
  • EOT equivalent oxide film thickness
  • the metal oxide may have a function as a part of the gate.
  • a conductive material containing oxygen may be provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed as a conductor functioning as a gate.
  • a conductive material containing the above metal element and nitrogen may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the conductor 260 is shown as a two-layer structure in FIG. 35A, it may have a single-layer structure or a stacked structure of three or more layers.
  • the conductor 260a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.), and copper atoms. It is preferable to use materials. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.
  • the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductivity of the conductor 260b from being reduced due to the oxygen contained in the insulator 250 from oxidizing the conductor 260b.
  • a conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • the conductor 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used.
  • the conductor 260b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive material.
  • ⁇ metal oxide As the oxide 230, a metal oxide which functions as an oxide semiconductor is preferably used. The metal oxide applicable to the oxide 230 according to the present invention will be described below.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that gallium, yttrium, tin, and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.
  • the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc
  • the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel,
  • the element M is preferably aluminum, gallium, yttrium, or tin.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, the metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • the transistor 300 is described with reference to FIG.
  • the transistor 300 is provided over the semiconductor substrate 311 and functions as a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 which is part of the semiconductor substrate 311, and a source region or a drain region.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor region 313 (a part of the semiconductor substrate 311) in which a channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to cover the conductor 316 with the insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material whose work function is adjusted. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of the semiconductor substrate 311. Note that an insulator which functions as a mask for forming the protrusion may be provided in contact with the top of the protrusion. Further, although the case where a part of the semiconductor substrate 311 is processed to form the convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • transistor 300 illustrated in FIG. 35B is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on a circuit structure or a driving method.
  • the conductor 242a of the transistor 200M functions as one of the electrodes of the capacitor 292, and the insulator 272 and the insulator 273 function as a dielectric.
  • the conductor 290 is provided so as to overlap with the conductor 242a with the insulator 272 and the insulator 273 interposed therebetween, and functions as the other electrode of the capacitor 292.
  • the conductor 290 may be used as the other electrode of the capacitor 292 included in the adjacent memory device 420.
  • the conductor 290 may be electrically connected to the conductor 290 included in the adjacent memory device 420.
  • the conductor 290 is also arranged on the upper surface of the conductor 242a and the side surface of the conductor 242a with the insulator 272 and the insulator 273 sandwiched therebetween. At this time, the capacitor 292 is preferable because a capacitance larger than that obtained by the area where the conductor 242a and the conductor 290 overlap with each other can be obtained.
  • the conductor 424 is electrically connected to the conductor 242b and is also electrically connected to the conductor 424 located in the lower layer via the conductor 205.
  • silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be used. Moreover, these materials can be laminated and used.
  • the dielectric of the capacitor 292 has a stacked-layer structure, a stack of aluminum oxide and silicon nitride or a stack of hafnium oxide and silicon oxide can be used.
  • the top and bottom of the stack are not limited.
  • silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.
  • zirconium oxide having a higher dielectric constant than the above materials may be used as the dielectric of the capacitor 292.
  • zirconium oxide may be used as a single layer or may be used as part of a stack.
  • a stack of zirconium oxide and aluminum oxide can be used.
  • the dielectric of the capacitor 292 may be a stack of three layers, in which zirconium oxide is used for the first layer and the third layer, and the second layer between the first layer and the third layer is used.
  • Aluminum oxide may be used.
  • the area occupied by the capacitor 292 in the memory device 420 can be reduced. Therefore, the area required for the memory device 420 can be reduced, and the bit cost can be improved, which is preferable.
  • the conductor 290 a material which can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, or the like can be used.
  • the example in which the transistor 200M and the capacitor 292 are symmetrically arranged with the conductor 424 provided therebetween is shown.
  • the number of conductors 424 electrically connected to the transistor 200M can be reduced. Therefore, the area required for the memory device 420 can be reduced, and the bit cost can be improved, which is preferable.
  • the conductor 424 is connected to at least part of the upper surface of the conductor 242b.
  • the transistor 200T in the memory unit 470 and the memory device 420 can be electrically connected.
  • the memory device 420A includes a transistor 200M and a capacitor 292A electrically connected to the transistor 200M.
  • the capacitor 292A is provided below the transistor 200M.
  • the conductor 242a is disposed in an opening provided in the oxide 243a, the oxide 230b, the oxide 230a, the insulator 224, and the insulator 222, and is electrically connected to the conductor 205 at the bottom of the opening. Connect to.
  • the conductor 205 is electrically connected to the capacitor 292A.
  • the capacitor 292A has a conductor 294 that functions as one of electrodes, an insulator 295 that functions as a dielectric, and a conductor 297 that functions as the other of the electrodes.
  • the conductor 297 overlaps with the conductor 294 with the insulator 295 provided therebetween.
  • the conductor 297 is electrically connected to the conductor 205.
  • the conductor 294 is provided on the bottom and side surfaces of the opening formed in the insulator 298 provided on the insulator 296, and the insulator 295 is provided so as to cover the insulator 298 and the conductor 294. Further, the conductor 297 is provided so as to be embedded in the recessed portion of the insulator 295.
  • a conductor 299 is provided so as to be embedded in the insulator 296, and the conductor 299 is electrically connected to the conductor 294.
  • the conductor 299 may be electrically connected to the conductor 294 of the adjacent memory device 420A.
  • the conductor 297 is also arranged on the upper surface of the conductor 294 and the side surface of the conductor 294 with the insulator 295 interposed therebetween. At this time, the capacitor 292A is preferable because a capacitance larger than that obtained by the area where the conductor 294 and the conductor 297 are overlapped can be obtained.
  • silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be used. Moreover, these materials can be laminated and used.
  • the insulator 295 has a stacked-layer structure, a stack of aluminum oxide and silicon nitride and a stack of hafnium oxide and silicon oxide can be used.
  • the top and bottom of the stack are not limited.
  • silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.
  • zirconium oxide having a higher dielectric constant than the above materials may be used as the insulator 295.
  • zirconium oxide may be used as a single layer or as part of a stack.
  • a stack of zirconium oxide and aluminum oxide can be used.
  • the insulator 295 may be a stack of three layers, in which zirconium oxide is used for the first layer and the third layer, and aluminum oxide is used for the second layer between the first layer and the third layer. You may use.
  • the area occupied by the capacitor 292A in the memory device 420A can be reduced. Therefore, the area required for the memory device 420A can be reduced, and the bit cost can be improved, which is preferable.
  • a material that can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, or the like can be used.
  • insulator 298 a material that can be used for the insulator 214, the insulator 216, the insulator 224, the insulator 280, and the like can be used.
  • the memory device 420B includes the transistor 200M and the capacitor 292B electrically connected to the transistor 200M.
  • the capacitor 292B is provided above the transistor 200M.
  • the capacitor 292B includes a conductor 276 that functions as one of electrodes, an insulator 277 that functions as a dielectric, and a conductor 278 that functions as the other of the electrodes.
  • the conductor 278 overlaps with the conductor 276 with the insulator 277 interposed therebetween.
  • the insulator 275 is provided on the insulator 282, and the conductor 276 is provided on the bottom and side surfaces of the openings formed in the insulator 275, the insulator 282, the insulator 280, the insulator 273, and the insulator 272.
  • the insulator 277 is provided so as to cover the insulator 282 and the conductor 276.
  • the conductor 278 is provided so as to overlap with the conductor 276 in a concave portion of the insulator 277, and at least part of the conductor 278 is provided over the insulator 275 with the insulator 277 interposed therebetween.
  • the conductor 278 may be used as the other electrode of the capacitor 292B included in the adjacent memory device 420B. Alternatively, the conductor 278 may be electrically connected to the conductor 278 included in the adjacent memory device 420B.
  • the conductor 278 is also arranged on the upper surface of the conductor 276 and the side surface of the conductor 276 with the insulator 277 interposed therebetween. At this time, the capacitor 292B is preferable because a capacitance larger than that obtained by the area where the conductor 276 and the conductor 278 are overlapped is obtained.
  • the insulator 279 may be provided so as to fill the recessed portion of the conductor 278.
  • silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be used. Moreover, these materials can be laminated and used.
  • the insulator 277 has a stacked-layer structure, a stack of aluminum oxide and silicon nitride and a stack of hafnium oxide and silicon oxide can be used.
  • the top and bottom of the stack are not limited.
  • silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.
  • zirconium oxide having a higher dielectric constant than the above materials may be used as the insulator 277.
  • zirconium oxide may be used as a single layer or as part of a stack.
  • a stack of zirconium oxide and aluminum oxide can be used.
  • the insulator 277 may be a stack of three layers, in which zirconium oxide is used for the first layer and the third layer, and aluminum oxide is used for the second layer between the first layer and the third layer. You may use.
  • the area occupied by the capacitor 292B in the memory device 420B can be reduced. Therefore, the area required for the memory device 420B can be reduced, and the bit cost can be improved, which is preferable.
  • the conductor 276 and the conductor 278, a material that can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, or the like can be used.
  • insulator 275 and the insulator 279 a material that can be used for the insulator 214, the insulator 216, the insulator 224, the insulator 280, and the like can be used.
  • FIG. 37 illustrates an example in which the memory device 420 is electrically connected to the conductor 242b functioning as one of a source and a drain of the transistor 200T through the conductor 424, the conductor 205, the conductor 246b, and the conductor 240b. Showing.
  • connection method between the memory device 420 and the transistor 200T can be determined according to the function of the circuit included in the transistor layer 413.
  • FIG. 38 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).
  • Each of the memory device layers 415_1 to 415_4 has a plurality of memory devices 420.
  • the memory device 420 is electrically connected to the memory device 420 included in the different memory device layer 415 and the transistor 200T included in the transistor layer 413 through the conductor 424 and the conductor 205.
  • the memory unit 470 is sealed with the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284.
  • An insulator 274 is provided around the insulator 284.
  • a conductor 430 is provided in the insulator 274, the insulator 284, the insulator 283, and the insulator 211, and is electrically connected to the element layer 411.
  • an insulator 280 is provided inside the sealing structure.
  • the insulator 280 has a function of releasing oxygen by heating.
  • the insulator 280 has an excess oxygen region.
  • the insulator 211, the insulator 283, and the insulator 284 are preferably materials having a function of high blocking property against hydrogen. Further, the insulator 214, the insulator 282, and the insulator 287 are preferably a material having a function of trapping hydrogen or fixing hydrogen.
  • silicon nitride, silicon nitride oxide, or the like can be given as the material having the function of having a high blocking property against hydrogen.
  • silicon nitride, silicon nitride oxide, or the like can be given as the material having the function of having a high blocking property against hydrogen.
  • the material having a function of capturing hydrogen or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • the barrier property is a function of suppressing diffusion of a corresponding substance (also referred to as low permeability).
  • the corresponding substance has a function of capturing and fixing (also referred to as gettering).
  • a crystal structure of a material used for the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284 may be used.
  • an amorphous aluminum oxide film is preferably used as a material having a function of capturing hydrogen or fixing hydrogen.
  • Amorphous aluminum oxide may have a larger amount of trapping and fixing hydrogen than aluminum oxide having high crystallinity.
  • excess oxygen in the insulator 280 can be modeled as follows with respect to diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.
  • Hydrogen existing in the oxide semiconductor diffuses to another structure through the insulator 280 which is in contact with the oxide semiconductor. Excess oxygen in the insulator 280 reacts with oxygen in the oxide semiconductor to form an OH bond, and the hydrogen diffuses in the insulator 280.
  • the hydrogen atom having an OH bond reaches a material having a function of trapping hydrogen or fixing hydrogen (typically, the insulator 282)
  • the hydrogen atom is an atom in the insulator 282 (for example, Reacts with an oxygen atom bonded to a metal atom or the like) and is trapped or fixed in the insulator 282.
  • the oxygen atoms of the excess oxygen that had the OH bond are estimated to remain in the insulator 280 as excess oxygen. That is, it is highly possible that excess oxygen in the insulator 280 plays a bridging role in the diffusion of hydrogen.
  • the semiconductor device manufacturing process is one of the important factors.
  • the insulator 280 having excess oxygen is formed in the oxide semiconductor, and then the insulator 282 is formed.
  • heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher.
  • the heat treatment time is 1 hour or longer, preferably 4 hours or longer, more preferably 8 hours or longer.
  • hydrogen in the oxide semiconductor can diffuse outward through the insulator 280, the insulator 282, and the insulator 287. That is, the absolute amount of hydrogen existing in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.
  • the insulator 283 and the insulator 284 are formed. Since the insulator 283 and the insulator 284 are materials having a function of high blocking property with respect to hydrogen, hydrogen diffused outward or hydrogen existing outside can be stored inside, specifically, in an oxide semiconductor. Alternatively, it is possible to suppress the entry into the insulator 280 side.
  • the above heat treatment has been described as an example of the structure performed after the insulator 282 is formed; however, the present invention is not limited to this.
  • the heat treatment may be performed after each of the transistor layer 413 and the memory device layers 415_1 to 415_3. Further, when hydrogen is diffused outward by the above heat treatment, hydrogen is diffused above or in the lateral direction of the transistor layer 413. Similarly, in the case where heat treatment is performed after formation of the memory device layers 415_1 to 415_3, hydrogen is diffused upward or laterally.
  • the insulator 211 and the insulator 283 are bonded to each other, whereby the above-described sealing structure is formed.
  • a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. Therefore, a highly reliable semiconductor device can be provided. Further, according to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided.
  • FIG. 39A to 39C are diagrams showing an example in which the arrangement of the conductors 424 is different from that in FIG. 39A is a layout diagram when the memory device 420 is viewed from above, and FIG. 39B is a cross-sectional view of a portion indicated by dashed-dotted line A1-A2 in FIG. 39C is a cross-sectional view of a portion indicated by dashed-dotted line B1-B2 in FIG. 39A.
  • the conductor 205 is omitted for easy understanding of the drawing.
  • the conductor 205 has a region overlapping with the conductor 260 and the conductor 424.
  • the opening in which the conductor 424 is provided is not limited to a region overlapping with the oxide 230a and the oxide 230b, but also outside the oxide 230a and the oxide 230b. Is also provided.
  • FIG. 39A illustrates an example in which the conductor 424 is provided so as to extend to the B2 side of the oxide 230a and the oxide 230b, this embodiment is not limited to this.
  • the conductor 424 may be provided so as to extend to the B1 side of the oxide 230a and the oxide 230b, or to be provided so as to extend to both the B1 side and the B2 side.
  • 39B and 39C illustrate an example in which the memory device layer 415_p is stacked over the memory device layer 415_p-1 (p is a natural number of 2 or more and n or less).
  • the memory device 420 included in the memory device layer 415_p-1 is electrically connected to the memory device 420 included in the memory device layer 415_p through the conductor 424 and the conductor 205.
  • FIG. 39B illustrates an example in which the conductor 424 in the memory device layer 415_p-1 is connected to the conductor 242 of the memory device layer 415_p-1 and the conductor 205 of the memory device layer 415_p.
  • the conductor 424 is also connected to the conductor 205 of the memory device layer 415_p-1 outside the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a on the B2 side.
  • the conductor 424 is formed along the side surface of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a on the B2 side, and the insulator 280, the insulator 273, the insulator 272, It can be seen that the conductor 205 is electrically connected to each other through the openings formed in the insulator 224 and the insulator 222.
  • an example in which the conductor 424 is provided along the side surface of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a on the B2 side is illustrated by a dotted line in FIG.
  • An insulator 241 may be formed between the conductor 242, the oxide 243, the oxide 230b, the oxide 230a, the insulator 224, and the side surface of the insulator 222 on the B2 side and the conductor 424. ..
  • the memory device 420 can be electrically connected to the memory devices 420 provided in different memory device layers 415.
  • the memory device 420 can also be electrically connected to the transistor 200T provided in the transistor layer 413.
  • the conductor 424 is a bit line
  • the conductor 424 is also provided in a region which does not overlap with the conductor 242 or the like, whereby the distance between the bit lines of the memory devices 420 adjacent to each other in the B1-B2 direction can be increased. ..
  • the distance between the conductors 424 on the conductor 242 is d1.
  • the distance between the positioned conductors 424 is d2, and d2 is larger than d1.
  • the parasitic capacitance of the conductor 424 can be reduced. It is preferable to reduce the parasitic capacitance of the conductor 424 because the capacitance required for the capacitor 292 can be reduced.
  • the memory device 420 is provided with a conductor 424 that functions as a common bit line for two memory cells.
  • the cell size of each memory cell can be reduced by appropriately adjusting the dielectric constant of the dielectric used for the capacitance and the parasitic capacitance between the bit lines.
  • the estimation of the cell size of the memory cell, the estimation of the bit density, and the estimation of the bit cost when the channel length is set to 30 nm (also referred to as 30 nm node) will be described. Note that in FIGS. 40A to 40D described below, the conductor 205 is not illustrated for easy understanding of the drawings. When the conductor 205 is provided, the conductor 205 has a region overlapping with the conductor 260 and the conductor 424.
  • hafnium oxide having a thickness of 10 nm and silicon oxide having a thickness of 1 nm are sequentially stacked thereover, and a conductor 242 and an oxide 243 of each memory cell included in the memory device 420 are included.
  • the oxide 230a and the oxide 230b are provided with a slit, and the conductor 242 and the conductor 424 functioning as a bit line so as to overlap with the slit are provided.
  • the memory cell 432 thus obtained is called a cell A.
  • the cell size in cell A is 45.25F 2 .
  • 40B shows, as a dielectric of a capacitor, a first zirconium oxide film, an aluminum oxide film over the first zirconium oxide film, and a second zirconium oxide film over the first zirconium oxide film, which are sequentially stacked.
  • An example is shown in which a slit is provided between the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b, and the conductor 242 and the conductor 424 which functions as a bit line so as to overlap with the slit are provided. ..
  • the memory cell 433 thus obtained is called a cell B.
  • the cell B Since the cell B has a higher dielectric constant of the dielectric material used for the capacitance than the cell A, the area of the capacitance element can be reduced. Therefore, in the cell B, the cell size can be reduced as compared with the cell A.
  • the cell size in cell B is 25.53F 2 .
  • the cell A and the cell B correspond to the memory cells included in the memory device 420, the memory device 420A, or the memory device 420B illustrated in FIGS. 34, 36A to 36C, and 37.
  • FIG. 40C illustrates a conductor 242 included in the memory device 420 in which first zirconium oxide, aluminum oxide over the first zirconium oxide, and second zirconium oxide over the first zirconium oxide are stacked as a dielectric of the capacitor.
  • Each of the memory cells shares the object 243, the oxide 230a, and the oxide 230b, and a conductor 424 which functions as a bit line so as to overlap with a part of the conductor 242 and a part of the outside of the conductor 242.
  • the example in which is provided is shown.
  • the memory cell 434 thus obtained is called a cell C.
  • the distance between the conductors 424 in the cell C is wider in a layer below the oxide 230a than in a portion above the conductor 242. Therefore, the parasitic capacitance of the conductor 424 can be reduced and the area of the capacitor can be reduced. Further, no slit is provided in the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b. As described above, in cell C, the cell size can be reduced as compared with cells A and B. The cell size in cell C is 17.20F 2 .
  • FIG. 40D shows an example in which the conductor 205 and the insulator 216 are not provided in the cell C.
  • Such a memory cell 435 is called a cell D.
  • the memory device 420 By omitting the conductor 205 and the insulator 216 in the cell D, the memory device 420 can be thinned. Therefore, the memory device layer 415 including the memory device 420 can be thinned, and the height of the memory unit 470 in which a plurality of memory device layers 415 are stacked can be reduced.
  • the conductor 424 and the conductor 205 are regarded as bit lines, the bit lines can be shortened in the memory unit 470. Since the bit line can be shortened, the parasitic load on the bit line can be reduced, the parasitic capacitance of the conductor 424 can be further reduced, and the area of the capacitor can be reduced.
  • the cell size in the cell D is 15.12F 2 .
  • the cell C and the cell D correspond to the memory cells included in the memory device 420 illustrated in FIGS. 39A to 39C.
  • bit density and the bit cost C b of the cells A to D and the cell E which has been multi-valued in the cell D were estimated.
  • the obtained estimates were compared with the expected values of bit density and bit cost in currently commercially available DRAMs.
  • the bit cost C b in the semiconductor device of one embodiment of the present invention is estimated by using Expression 1.
  • n is the number of stacked memory device layers
  • P c is the number of patterning of the element layer 411 mainly as a common part
  • P s is the number of patterning per layer of the memory device layer 415 and the transistor layer 413
  • D d is DRAM.
  • D 3d is the bit density of one layer of the memory device layer 415
  • P d is the number of times of patterning of the DRAM.
  • P d an increment due to scaling is included.
  • Table 1 shows estimated bit densities of commercially available DRAMs and estimated bit densities of semiconductor devices of one embodiment of the present invention. Note that there are two types of commercially available DRAMs, the process nodes of which are 18 nm and 1 ⁇ nm. Further, the process node of the semiconductor device of one embodiment of the present invention was set to 30 nm, and the bit density was estimated with the number of stacked memory device layers in the cells A to E being 5, 10, and 20 layers.
  • Table 2 shows the result of estimating the relative bit cost of the semiconductor device of one embodiment of the present invention from the bit cost of commercially available DRAM.
  • a DRAM with a process node of 1 ⁇ nm was used for the bit cost comparison.
  • the process node of the semiconductor device of one embodiment of the present invention was set to 30 nm, and the number of stacked memory device layers in the cells A to D was estimated to be 5, 10, and 20 layers.
  • the metal oxide preferably contains at least indium or zinc. It is particularly preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, and the like are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained.
  • FIG. 41A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).
  • IGZO a metal oxide containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous” (amorphous), “Crystalline (crystalline)”, and “Crystal”.
  • Amorphous includes completely amorphous.
  • “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composition).
  • single crystal, poly crystal, and completely amorphous are excluded.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 41(A) is an intermediate state between “Amorphous” and “Crystal” and belongs to a new boundary region (New crystalline phase).
  • the structure That is, the structure can be rephrased as a structure that is completely different from “Amorphous (amorphous)” and “Crystal (crystal)” which are energetically unstable.
  • the crystal structure of the film or substrate can be evaluated by using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • FIG. 41B an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as “Crystalline” is shown in FIG. 41B (the vertical axis represents intensity (Intensity) in arbitrary units (a. u.)).
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 41B is simply referred to as an XRD spectrum.
  • thickness of the CAAC-IGZO film illustrated in FIG. 41B is 500 nm.
  • the crystal structure of the film or the substrate can be evaluated by a diffraction pattern (also referred to as a micro electron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • oxide semiconductors are classified into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single-crystal oxide semiconductor include the above CAAC-OS and nc-OS.
  • the non-single-crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS The CAAC-OS has a plurality of crystal regions, and the plurality of crystal regions is an oxide semiconductor in which the c-axis is aligned in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface where the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film.
  • the crystalline region is a region having a periodic atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also an area where the lattice arrangement is uniform.
  • the CAAC-OS has a region where a plurality of crystal regions is connected in the ab plane direction and the region may have distortion.
  • the strain refers to a portion in which the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in a region where a plurality of crystal regions are connected. That is, the CAAC-OS is an oxide semiconductor which is c-axis aligned and is not clearly aligned in the ab plane direction.
  • each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens nm.
  • the CAAC-OS has indium (In) and oxygen.
  • In layer a layer having an element M, zinc (Zn), and oxygen
  • (M,Zn) layer a layer having an element M, zinc (Zn), and oxygen
  • (M,Zn) layer a layer having an element M, zinc (Zn), and oxygen
  • (M,Zn) layer a layer having an element M, zinc (Zn), and oxygen
  • (M,Zn) layer stacked.
  • the indium and the element M can be replaced with each other. Therefore, the (M,Zn) layer may contain indium.
  • the element M may be contained in the In layer.
  • the In layer may contain Zn.
  • the layered structure is observed as a lattice image in a high resolution TEM image, for example.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal element forming the CAAC-OS.
  • a plurality of bright spots are observed in the electron beam diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at positions of point symmetry with respect to a spot (also referred to as a direct spot) of an incident electron beam that has passed through the sample.
  • the lattice arrangement in the crystal region is basically a hexagonal lattice, but the unit cell is not limited to a regular hexagon and may be a non-regular hexagon.
  • the above distortion may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear crystal grain boundary (grain boundary) cannot be confirmed even in the vicinity of strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate strain due to a non-dense arrangement of oxygen atoms in the ab plane direction, a change in bond distance between atoms due to substitution with a metal atom, or the like. It is thought to be because.
  • the crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal.
  • the crystal grain boundaries serve as recombination centers, and carriers are highly likely to be trapped to cause a decrease in on-current of the transistor and a decrease in field-effect mobility. Therefore, the CAAC-OS in which clear crystal grain boundaries are not confirmed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor.
  • a structure containing Zn is preferable for forming the CAAC-OS.
  • In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress generation of crystal grain boundaries more than In oxide.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries are confirmed. Therefore, it can be said that the CAAC-OS is unlikely to cause a decrease in electron mobility due to a crystal grain boundary.
  • the crystallinity of an oxide semiconductor might be lowered due to entry of impurities, generation of defects, and the like; therefore, it can be said that the CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancy). Therefore, the oxide semiconductor including the CAAC-OS has stable physical properties. Therefore, the oxide semiconductor including the CAAC-OS is highly heat resistant and has high reliability. Further, the CAAC-OS is stable even at a high temperature (so-called thermal budget) in the manufacturing process. Therefore, when the CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be widened.
  • the nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • the nc-OS has minute crystals.
  • the size of the minute crystal is, for example, 1 nm to 10 nm, in particular, 1 nm to 3 nm, and thus the minute crystal is also referred to as a nanocrystal.
  • no regularity is found in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method. For example, when a structural analysis is performed on the nc-OS film using an XRD apparatus, a peak showing crystallinity is not detected in Out-of-plane XRD measurement using a ⁇ /2 ⁇ scan. Further, when electron beam diffraction (also referred to as selected area electron beam diffraction) using an electron beam having a probe diameter (for example, 50 nm or more) larger than that of nanocrystals is performed on the nc-OS film, a diffraction pattern such as a halo pattern is obtained. Is observed.
  • electron beam diffraction also referred to as selected area electron beam diffraction
  • a probe diameter for example, 50 nm or more
  • electron beam diffraction also referred to as nanobeam electron beam diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on the direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the crystallinity of the a-like OS is lower than that of the nc-OS and the CAAC-OS. Further, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
  • the CAC-OS relates to the material composition.
  • CAC-OS is, for example, one structure of a material in which elements forming a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, in the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a mosaic shape due to the material being separated into the first region and the second region, and the first region is distributed in the film (hereinafter, also referred to as cloud-shaped). I say.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic ratios of In, Ga, and Zn with respect to the metal elements forming the CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region containing indium oxide, indium zinc oxide, or the like as a main component.
  • the second region is a region containing gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be restated as a region containing In as a main component. Further, the second region can be restated as a region containing Ga as a main component.
  • EDX Energy Dispersive X-ray spectroscopy
  • EDX mapping obtained using Energy Dispersive X-ray spectroscopy
  • the CAC-OS When the CAC-OS is used for a transistor, a function of switching (a function of turning on/off) by conductive action due to the first region and an insulating property due to the second region complementarily act on each other. Can be added to the CAC-OS. That is, the CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using the CAC-OS for a transistor, a high on-state current (I on ), high field-effect mobility ( ⁇ ), and favorable switching operation can be realized.
  • I on on-state current
  • ⁇ high field-effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. May be.
  • an oxide semiconductor having a low carrier concentration is preferably used for the transistor.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm ⁇ 3 or less, preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . 3 or less, more preferably less than 1 ⁇ 10 10 cm ⁇ 3 , and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
  • the concentration of impurities in the oxide semiconductor film may be lowered and the density of defect states may be lowered.
  • low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • the density of trap states may be low.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density might have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are 2 It is not more than ⁇ 10 18 atoms/cm 3 , preferably not more than 2 ⁇ 10 17 atoms/cm 3 .
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level might be formed and a carrier might be generated. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms/cm 3 , preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less. And more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • the oxide semiconductor reacts with oxygen which is bonded to a metal atom to be water, which might cause oxygen deficiency.
  • oxygen When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. Further, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 1 ⁇ 10 19 atoms/cm 3 , and more preferably 5 ⁇ 10 18 atoms/cm 3. It is less than 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • FIG. 42 is a block diagram showing a configuration example of a semiconductor device that functions as a memory device.
  • the semiconductor device 10E has a peripheral circuit 20 and a memory cell array 30.
  • the peripheral circuit 20 has a row decoder 71, a word line driver circuit 72, a column driver 22, an output circuit 73, and a control logic circuit 74.
  • the row decoder 71 and the word line driver circuit 72 can be applied to the row driver described in the first embodiment and the like.
  • the column driver 22 has a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84.
  • the precharge circuit 82 has a function of precharging the wiring BL and the like.
  • the amplifier circuit 83 has a function of amplifying the data signal read from the wiring BL. The amplified data signal is output to the outside of the semiconductor device 10E as a digital data signal RDATA via the output circuit 73.
  • a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 20, and a high power supply voltage (VIL) for the memory cell array 30 are externally supplied to the semiconductor device 10E as power supply voltages.
  • the control signal (CE, WE, RE), the address signal ADDR, and the data signal WDATA are externally input to the semiconductor device 10E.
  • the address signal ADDR is input to the row decoder 71 and the column decoder 81, and WDATA is input to the write circuit 84.
  • the control logic circuit 74 processes input signals (CE, WE, RE) from the outside and generates control signals for the row decoder 71 and the column decoder 81.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 74 is not limited to this, and another control signal may be input as necessary.
  • a control signal for determining a defective bit may be input and a data signal read from an address of a specific memory cell may be specified as a defective bit.
  • FIG. 43 shows various storage devices layer by layer.
  • a storage device located in the upper layer is required to have a high access speed, and a storage device located in the lower layer is required to have a large storage capacity and a high recording density.
  • a memory, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory that are mixedly mounted as a register in an arithmetic processing unit such as a CPU are shown in order from the top layer.
  • the memory that is embedded as a register in an arithmetic processing unit such as a CPU is used for temporary storage of arithmetic results, and so is frequently accessed by the arithmetic processing unit. Therefore, an operation speed faster than the storage capacity is required.
  • the register also has a function of holding setting information of the arithmetic processing unit.
  • SRAM is used for cache, for example.
  • the cache has a function of copying a part of the information held in the main memory and holding it. By duplicating frequently used data in the cache, the access speed to the data can be increased.
  • the DRAM is used as, for example, a main memory.
  • the main memory has a function of holding programs and data read from the storage.
  • the recording density of DRAM is approximately 0.1 to 0.3 Gbit/mm 2 .
  • the 3D NAND memory is used for storage, for example.
  • the storage has a function of holding data that needs to be stored for a long time, various programs used in the arithmetic processing device, and the like. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density.
  • the storage density of a storage device used for storage is approximately 0.6 to 6.0 Gbit/mm 2 .
  • a semiconductor device that functions as a memory device of one embodiment of the present invention has high operation speed and can hold data for a long time.
  • the semiconductor device of one embodiment of the present invention can be preferably used as a semiconductor device located in the boundary region 901 including both the hierarchy where the cache is located and the hierarchy where the main memory is located. Further, the semiconductor device of one embodiment of the present invention can be favorably used as a semiconductor device located in the boundary region 902 including both the hierarchy where the main memory is located and the hierarchy where the storage is located.
  • 44(A) and 44(B) are diagrams for explaining the power consumption of the DRAM and the DOSRAM.
  • 44A shows the power consumption of the DRAM, DOSRAM1, and DOSRAM2
  • FIG. 44B shows the power consumption of the DRAM, DOSRAM2.
  • FIGS. 44(A) and 44(B) are the results of estimation assuming various usages.
  • a general DRAM and a book assuming that the active mode is 10% (the active mode is assumed to be 10% in one day in the usage state of electronic devices, etc.) and the standby mode is 90%.
  • the result which estimated assuming the electronic device (DOSRAM1, DOSRAM2) of one aspect of invention is shown.
  • the result which estimated assuming the electronic device (DOSRAM2) of 1 aspect of invention is shown.
  • the vertical axis represents power consumption (Power consumption) in arbitrary units (AU).
  • the horizontal axis represents DRAM, DOSRAM1, and DOSRAM2
  • the horizontal axis represents DRAM and DOSRAM2.
  • the lower part of the graph represents the power consumption during Active
  • the middle part represents the power consumption during Standby
  • the upper part represents the power consumption during Refresh.
  • DOSRAM2 is assumed to perform power gating on DOSRAM1 during standby.
  • the electronic devices (DOSRAM1 and DOSRAM2) of one embodiment of the present invention have lower power consumption than a general DRAM.
  • DOSRAM2 is estimated to have a power reduction effect of 75% as compared with a general DRAM.
  • the electronic device (DOSRAM2) of one embodiment of the present invention is estimated to have a power reduction effect of 95% as compared with a general DRAM. ..
  • a semiconductor device or electronic device with reduced power consumption can be provided.
  • FIG. 45A shows a perspective view of the electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 45A has the semiconductor device 10 in which the element layer 34 is laminated on the silicon substrate 11 in the mold 711.
  • FIG. 45A shows the inside of the electronic component 700, and a part of it is not reflected in the drawing.
  • the electronic component 700 has a land 712 outside the mold 711.
  • the land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 10 by the wire 714.
  • the electronic component 700 is mounted on the printed board 702, for example.
  • the mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them to each other on the printed board 702.
  • FIG. 45B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • an interposer 731 is provided on a package board 732 (printed board), and a semiconductor device 735 and a plurality of storage devices 100 are provided on the interposer 731.
  • the electronic component 730 shows an example in which the semiconductor device 10 is used as a wide band memory (HBM: High Bandwidth Memory). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.
  • HBM High Bandwidth Memory
  • the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or a multilayer.
  • the interposer 731 has a function of electrically connecting an integrated circuit provided over the interposer 731 to an electrode provided over the package substrate 732.
  • an interposer may be called a "redistribution board" or an "intermediate board.”
  • a through electrode may be provided in the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode.
  • TSV Three Silicon Via
  • the interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since the silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use the silicon interposer as the interposer for mounting the HBM.
  • a heat sink heat dissipation plate
  • the heights of the integrated circuits provided on the interposer 731 are uniform.
  • the semiconductor device 10 and the semiconductor device 735 have the same height.
  • An electrode 733 may be provided on the bottom of the package substrate 732 to mount the electronic component 730 on another substrate.
  • FIG. 45B an example in which the electrode 733 is formed using a solder ball is shown.
  • BGA All Grid Array
  • the electrode 733 may be formed of a conductive pin.
  • PGA Peripheral Component Interconnect
  • the electronic component 730 can be mounted on another board by using various mounting methods other than BGA and PGA.
  • SPGA Sttaggered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN Quad-on-adhesive method
  • QFN Quad-on-Flade
  • the robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezo sensor, optical sensor, gyro sensor, etc.), and a moving mechanism.
  • the electronic component 730 has a processor and the like and has a function of controlling these peripheral devices.
  • the electronic component 700 has a function of storing data acquired by the sensor.
  • the microphone has the function of detecting acoustic signals such as the user's voice and environmental sounds. Further, the speaker has a function of emitting an audio signal such as a voice and a warning sound.
  • the robot 7100 can analyze an audio signal input via a microphone and emit a necessary audio signal from a speaker. The robot 7100 can communicate with a user using a microphone and a speaker.
  • the camera has a function of capturing an image around the robot 7100. Further, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture an image of the surroundings using a camera, analyze the image, and detect the presence or absence of an obstacle when moving.
  • the flying body 7120 has a propeller, a camera, a battery, and the like, and has a function of autonomously flying.
  • the electronic component 730 has a function of controlling these peripheral devices.
  • image data taken by a camera is stored in the electronic component 700.
  • the electronic component 730 can analyze the image data and detect the presence or absence of an obstacle when moving.
  • the electronic component 730 can estimate the remaining battery level from the change in the storage capacity of the battery.
  • the cleaning robot 7140 has a display arranged on the upper surface, a plurality of cameras arranged on the side surface, brushes, operation buttons, various sensors, and the like. Although not shown, the cleaning robot 7300 is equipped with tires, a suction port, and the like. The cleaning robot 7300 can be self-propelled, detect dust, and suck the dust from the suction port provided on the lower surface.
  • the electronic component 730 can analyze the image captured by the camera and determine the presence or absence of an obstacle such as a wall, furniture, or a step. Further, when the image analysis detects an object such as wiring that is likely to be entangled with the brush, the rotation of the brush can be stopped.
  • the automobile 7160 has an engine, tires, brakes, a steering device, a camera, and the like.
  • the electronic component 730 performs control for optimizing the running state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and brake usage frequency.
  • the image data captured by the camera is stored in the electronic component 700.
  • the electronic component 700 and/or the electronic component 730 can be incorporated in the TV device 7200 (television receiver), smartphone 7210, PC (personal computer) 7220, 7230, game machine 7240, game machine 7260, and the like.
  • the electronic component 730 built in the TV device 7200 can function as an image engine.
  • the electronic component 730 performs image processing such as noise removal and resolution up conversion.
  • the smartphone 7210 is an example of a mobile information terminal.
  • the smartphone 7210 has a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by the electronic component 730.
  • the PC 7220 and PC 7230 are examples of a notebook PC and a stationary PC, respectively.
  • a keyboard 7232 and a monitor device 7233 can be connected to the PC 7230 wirelessly or by wire.
  • the game machine 7240 is an example of a portable game machine.
  • the game machine 7260 is an example of a stationary game machine.
  • a controller 7262 is connected to the game machine 7260 wirelessly or by wire. Electronic component 700 and/or electronic component 730 may also be incorporated into controller 7262.
  • each embodiment can be combined with a structure described in any of the other embodiments or examples as appropriate to be one embodiment of the present invention. Further, in the case where a plurality of configuration examples are shown in one embodiment, the configuration examples can be combined appropriately.
  • contents described in one embodiment are different contents described in the embodiment (may be a part of contents), and/or one or more contents.
  • the contents described in another embodiment can be applied, combined, or replaced.
  • the constituent elements are classified by function and are shown as independent blocks.
  • the blocks in the block diagram are not limited to the components described in the specification, and can be rephrased appropriately according to the situation.
  • the size, the layer thickness, or the region is shown in any size for convenience of description. Therefore, it is not necessarily limited to that scale.
  • the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, it may include a signal, voltage, or current variation due to noise, or a signal, voltage, or current variation due to a timing shift.
  • electrode and “wiring” do not functionally limit these constituent elements.
  • electrode may be used as part of “wiring” and vice versa.
  • electrode and wiring include the case where a plurality of “electrodes” and “wirings” are integrally formed.
  • voltage and potential can be paraphrased as appropriate.
  • the voltage is a potential difference from a reference potential, and for example, when the reference potential is a ground voltage (ground voltage), the voltage can be paraphrased into a potential.
  • the ground potential does not always mean 0V. Note that the potentials are relative, and the potential applied to wiring or the like may be changed depending on the reference potential.
  • a node can be restated as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like, depending on a circuit configuration, a device structure, or the like. Further, terminals, wirings, etc. can be paraphrased as nodes.
  • the phrase “A and B are connected” means that A and B are electrically connected.
  • a and B are electrically connected refers to an object (a device such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) between A and B. ) Is present, it means a connection capable of transmitting an electric signal between A and B.
  • the case where A and B are electrically connected includes the case where A and B are directly connected.
  • “A and B are directly connected” means that an electric signal is transmitted between A and B through a wiring (or an electrode) between A and B without passing through the object.
  • the direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.
  • a switch refers to a switch that is in a conductive state (on state) or in a non-conductive state (off state) and has a function of controlling whether or not to flow current.
  • the switch has a function of selecting and switching a path through which current flows.
  • the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion of a semiconductor in which a current flows) and a gate overlap with each other, or a channel is formed. It is the distance between the source and the drain in the region.
  • the channel width refers to, for example, a source in a region where a semiconductor (or a portion of a semiconductor in which a current flows) and a gate electrode overlap with each other or a region where a channel is formed.
  • BL_1 bit line
  • DA1 data
  • PCL1 precharge line
  • PCL2 precharge line
  • T1 period
  • T2 period
  • T3 period
  • T4 period
  • T11 period
  • T12 period
  • T13 period
  • T14 period
  • Transistor, 24_6 Transistor, 25: Circuit, 25_1: Transistor, 25_2: Transistor, 25_2: Transistor, 25_4: Transistor, 26: Element layer, 27: Circuit, 27_M: Circuit, 27_1: Circuit, 28: Transistor, 28_a: Transistor , 28_b: transistor, 28_n: transistor, 28_1: transistor, 29: circuit, 30: memory cell array, 30_M: unit, 30_1: unit, 31: memory cell, 31_M: memory cell, 31_N: memory cell, 31_N_A: memory cell, 31_N_B: memory cell, 31_1: memory cell, 31_1_A: memory cell, 31_1_B: memory cell, 32: transistor, 32_N: transistor, 32_1: transistor, 32A: transistor, 32B: transistor, 33: capacitor, 33_N: capacitor, 33_1: Capacitor 33A: Capacitor, 33B: Capacitor, 34: Element layer, 34_
  • _B transistor, 44: transistor, 44_a: transistor, 44_b: transistor, 49: circuit, 50: unit, 50_M: unit, 50_1: unit, 51: memory cell, 54: element layer, 55: transistor, 56: transistor, 57: capacitive element, 70A: sealing layer, 70B: sealing layer, 71: row decoder, 72: word line driver circuit, 73: output circuit, 74: control logic circuit, 81: column decoder, 82: precharge circuit , 83: amplifier circuit, 84: circuit, 98: switch circuit, 100: storage device, 200: transistor, 200M: transistor, 200T: transistor, 205: conductor, 205a: conductor, 205b: conductor, 211: insulation Body, 212: insulator, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230b: oxide, 230c: oxide, 240: conductive Body, 240a:

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/IB2019/059906 2019-01-25 2019-11-19 半導体装置および当該半導体装置を有する電気機器 Ceased WO2020152522A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201980089579.4A CN113330552A (zh) 2019-01-25 2019-11-19 半导体装置及包括该半导体装置的电子设备
KR1020217024567A KR20210120003A (ko) 2019-01-25 2019-11-19 반도체 장치 및 상기 반도체 장치를 가지는 전자 기기
US17/422,312 US12426378B2 (en) 2019-01-25 2019-11-19 Semiconductor device and electronic device having stacked element layers on driver-circuit substrate
JP2020567657A JP7462575B2 (ja) 2019-01-25 2019-11-19 半導体装置
JP2024050247A JP2024083377A (ja) 2019-01-25 2024-03-26 半導体装置

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
JP2019011688 2019-01-25
JP2019011691 2019-01-25
JP2019-011688 2019-01-25
JP2019011690 2019-01-25
JP2019011692 2019-01-25
JP2019-011692 2019-01-25
JP2019-011690 2019-01-25
JP2019-011691 2019-01-25
JP2019013505 2019-01-29
JP2019-013505 2019-01-29

Publications (1)

Publication Number Publication Date
WO2020152522A1 true WO2020152522A1 (ja) 2020-07-30

Family

ID=71736829

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2019/059906 Ceased WO2020152522A1 (ja) 2019-01-25 2019-11-19 半導体装置および当該半導体装置を有する電気機器

Country Status (6)

Country Link
US (1) US12426378B2 (enExample)
JP (2) JP7462575B2 (enExample)
KR (1) KR20210120003A (enExample)
CN (1) CN113330552A (enExample)
TW (2) TW202537448A (enExample)
WO (1) WO2020152522A1 (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115274664A (zh) * 2021-04-30 2022-11-01 华为技术有限公司 一种三维存储器、芯片封装结构及电子设备
WO2024052787A1 (ja) * 2022-09-09 2024-03-14 株式会社半導体エネルギー研究所 半導体装置
WO2024089570A1 (ja) * 2022-10-28 2024-05-02 株式会社半導体エネルギー研究所 半導体装置
JP2024527195A (ja) * 2022-06-21 2024-07-23 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体構造及びその製造方法、メモリチップ、電子機器
KR20250023998A (ko) 2022-06-16 2025-02-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR20250088511A (ko) 2022-10-13 2025-06-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2025219839A1 (ja) * 2024-04-19 2025-10-23 株式会社半導体エネルギー研究所 半導体装置及びその駆動方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7330986B2 (ja) * 2018-08-31 2023-08-22 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の動作方法
US12225705B2 (en) 2019-02-22 2025-02-11 Semiconductor Energy Laboratory Co., Ltd. Memory device having error detection function, semiconductor device, and electronic device
KR20220050134A (ko) 2019-08-22 2022-04-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 메모리 셀 및 기억 장치
TWI807494B (zh) * 2021-11-19 2023-07-01 鯨鏈科技股份有限公司 晶圓對晶圓技術之輸入及輸出電路與使用其晶片裝置
US12014796B2 (en) * 2022-02-11 2024-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and method of operating the same
CN115103510A (zh) * 2022-06-20 2022-09-23 山东大学 对称内植压电智能层的复合材料智能结构及其制备方法
US20240032281A1 (en) * 2022-07-20 2024-01-25 Invention And Collaboration Laboratory Pte. Ltd. Memory cell structure
CN116863974B (zh) * 2023-09-05 2023-11-21 北京超弦存储器研究院 半导体器件及电子设备
CN118314936B (zh) * 2024-06-06 2024-09-06 北京超弦存储器研究院 存储器及访问方法、电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000312006A (ja) * 1999-02-26 2000-11-07 Seiko Epson Corp 半導体装置の製造方法及び電気光学装置の製造方法並びに半導体装置及び電気光学装置
JP2013065638A (ja) * 2011-09-15 2013-04-11 Elpida Memory Inc 半導体装置
JP2016192578A (ja) * 2010-11-12 2016-11-10 株式会社半導体エネルギー研究所 半導体装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3603229B2 (ja) 1994-02-09 2004-12-22 富士通株式会社 半導体記憶装置
JP2000312005A (ja) 1999-02-26 2000-11-07 Seiko Epson Corp 半導体装置の製造方法及び電気光学装置の製造方法並びに半導体装置及び電気光学装置
US6687147B2 (en) 2002-04-02 2004-02-03 Hewlett-Packard Development Company, L.P. Cubic memory array with diagonal select lines
US6643159B2 (en) 2002-04-02 2003-11-04 Hewlett-Packard Development Company, L.P. Cubic memory array
WO2012029638A1 (en) 2010-09-03 2012-03-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2012256821A (ja) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
TWI539453B (zh) 2010-09-14 2016-06-21 半導體能源研究所股份有限公司 記憶體裝置和半導體裝置
TWI574259B (zh) 2010-09-29 2017-03-11 半導體能源研究所股份有限公司 半導體記憶體裝置和其驅動方法
US8513773B2 (en) 2011-02-02 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Capacitor and semiconductor device including dielectric and N-type semiconductor
KR102107591B1 (ko) 2012-07-18 2020-05-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 기억 소자 및 프로그래머블 로직 디바이스
JP6347704B2 (ja) 2013-09-18 2018-06-27 株式会社半導体エネルギー研究所 半導体装置
US9653611B2 (en) 2014-03-07 2017-05-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6560508B2 (ja) 2014-03-13 2019-08-14 株式会社半導体エネルギー研究所 半導体装置
TWI767772B (zh) 2014-04-10 2022-06-11 日商半導體能源研究所股份有限公司 記憶體裝置及半導體裝置
WO2015170220A1 (en) 2014-05-09 2015-11-12 Semiconductor Energy Laboratory Co., Ltd. Memory device and electronic device
US9583177B2 (en) 2014-12-10 2017-02-28 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device including memory device
US9589611B2 (en) 2015-04-01 2017-03-07 Semiconductor Energy Laboratory Co., Ltd. Memory device, semiconductor device, and electronic device
US9728243B2 (en) * 2015-05-11 2017-08-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device or electronic component including the same
US9627034B2 (en) 2015-05-15 2017-04-18 Semiconductor Energy Laboratory Co., Ltd. Electronic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000312006A (ja) * 1999-02-26 2000-11-07 Seiko Epson Corp 半導体装置の製造方法及び電気光学装置の製造方法並びに半導体装置及び電気光学装置
JP2016192578A (ja) * 2010-11-12 2016-11-10 株式会社半導体エネルギー研究所 半導体装置
JP2013065638A (ja) * 2011-09-15 2013-04-11 Elpida Memory Inc 半導体装置

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4333062A4 (en) * 2021-04-30 2024-10-30 Huawei Technologies Co., Ltd. Three-dimensional memory, chip packaging structure, and electronic device
WO2022228281A1 (zh) * 2021-04-30 2022-11-03 华为技术有限公司 一种三维存储器、芯片封装结构及电子设备
JP2024517175A (ja) * 2021-04-30 2024-04-19 華為技術有限公司 三次元メモリ、チップパッケージ構造、および電子デバイス
CN115274664A (zh) * 2021-04-30 2022-11-01 华为技术有限公司 一种三维存储器、芯片封装结构及电子设备
CN115274664B (zh) * 2021-04-30 2025-09-16 华为技术有限公司 一种三维存储器、芯片封装结构及电子设备
KR20250023998A (ko) 2022-06-16 2025-02-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2024527195A (ja) * 2022-06-21 2024-07-23 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体構造及びその製造方法、メモリチップ、電子機器
JP7636513B2 (ja) 2022-06-21 2025-02-26 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体構造及びその製造方法、メモリチップ、電子機器
US12426241B2 (en) 2022-06-21 2025-09-23 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof, memory chip and electronic device
WO2024052787A1 (ja) * 2022-09-09 2024-03-14 株式会社半導体エネルギー研究所 半導体装置
KR20250088511A (ko) 2022-10-13 2025-06-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2024089570A1 (ja) * 2022-10-28 2024-05-02 株式会社半導体エネルギー研究所 半導体装置
WO2025219839A1 (ja) * 2024-04-19 2025-10-23 株式会社半導体エネルギー研究所 半導体装置及びその駆動方法

Also Published As

Publication number Publication date
US12426378B2 (en) 2025-09-23
JP2024083377A (ja) 2024-06-21
JP7462575B2 (ja) 2024-04-05
JPWO2020152522A1 (enExample) 2020-07-30
US20220085073A1 (en) 2022-03-17
KR20210120003A (ko) 2021-10-06
TWI863940B (zh) 2024-12-01
CN113330552A (zh) 2021-08-31
TW202105678A (zh) 2021-02-01
TW202537448A (zh) 2025-09-16

Similar Documents

Publication Publication Date Title
JP7462575B2 (ja) 半導体装置
JP7615370B2 (ja) 半導体装置
JP7702530B2 (ja) 半導体装置
JP7639207B2 (ja) 半導体装置
JP7693072B2 (ja) 記憶装置
JP7467430B2 (ja) 記憶装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19911142

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020567657

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19911142

Country of ref document: EP

Kind code of ref document: A1

WWG Wipo information: grant in national office

Ref document number: 17422312

Country of ref document: US