WO2020151740A1 - 置位电压生成单元、置位电压生成方法和显示装置 - Google Patents

置位电压生成单元、置位电压生成方法和显示装置 Download PDF

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Publication number
WO2020151740A1
WO2020151740A1 PCT/CN2020/073754 CN2020073754W WO2020151740A1 WO 2020151740 A1 WO2020151740 A1 WO 2020151740A1 CN 2020073754 W CN2020073754 W CN 2020073754W WO 2020151740 A1 WO2020151740 A1 WO 2020151740A1
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Prior art keywords
voltage
circuit
nth column
mth row
row
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PCT/CN2020/073754
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English (en)
French (fr)
Inventor
何敏
鲍文超
曹春
陈伟
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/957,043 priority Critical patent/US11238800B2/en
Publication of WO2020151740A1 publication Critical patent/WO2020151740A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a setting voltage generating unit, a setting voltage generating method and a display device.
  • the OLED display device In the working process of the OLED display device, it is affected by external factors (mainly temperature) and the instability of its own circuit, which causes the display effect to deteriorate.
  • external factors mainly temperature
  • the present disclosure provides a display device including M rows and N columns of pixel circuits and N setting voltage generating units;
  • the set voltage generating unit includes a voltage generating circuit; the voltage generating circuit is configured to generate a set voltage according to the main gamma voltage, so that the amount of change V01 of the set voltage and the amount of change of the gamma main voltage
  • the ratio between V0 is the voltage coefficient K, and K is a positive number less than or equal to 1;
  • the output port of the nth setting voltage generating unit is connected to the pixel circuit located in the nth column, and is used to provide the setting voltage for the pixel circuit located in the nth column;
  • Both M and N are integers greater than 1, and n is a positive integer less than or equal to N.
  • the display device further includes a display substrate; the pixel circuit is arranged in a display area of the display substrate; the set voltage generating unit is arranged in a peripheral area of the display substrate.
  • the display device further includes a display substrate and a driving integrated circuit; the pixel circuit is arranged in the display area of the display substrate; the set voltage generating unit is arranged in the driving integrated circuit.
  • the display device further includes N columns of detection lines, M rows of gate lines, N columns of data lines, M rows of compensation control lines, and M rows of write control lines; the gate lines are used to output gate drive signals, so The data line is used to output real-time data voltage, the compensation control line is used to input a compensation control signal, and the write control line is used to input a write control signal;
  • the pixel circuit in the m-th row and the n-th column includes a light-emitting element in the m-th row and the n-th column, the m-th row and the n-th column drive circuit, the m-th row and the n-th column display control circuit, the m-th row and the n-th column compensation control circuit, and the m-th row
  • the nth column set voltage is written into the control circuit, where
  • the driving circuit of the mth row and the nth column is used for driving the light emitting element of the mth row and the nth column under the control of its control terminal;
  • the display control circuit of the mth row and the nth column is connected to the control terminal of the driving circuit of the mth row and the nth column, and is used to control the gate drive signal output by the gate line of the mth row according to the data of the nth column.
  • the real-time data voltage on the line performs display driving control on the driving circuit of the mth row and the nth column;
  • the compensation control circuit in the mth row and the nth column is used for controlling the first end of the mth row and the nth column drive circuit and the nth column detection line under the control of the compensation control signal input from the mth row compensation control line Connect between
  • the set voltage write control circuit of the mth row and the nth column is used to control the set voltage write terminal of the mth row and the nth column under the control of the write control signal input from the write control line of the mth row and The nth column of detection lines are connected;
  • the nth set voltage generating circuit is used to write the set voltage of the mth row and the nth column to the mth row and nth column setting voltage write terminal, so as to set the setting voltage in the mth row and nth column
  • the bit voltage writing control circuit controls the communication between the set voltage writing terminal of the mth row and the nth column and the nth column detection line, it controls the writing of the set voltage of the mth row and the nth column to the n columns of detection lines;
  • n is a positive integer less than or equal to M.
  • the mth row and nth column compensation control circuit includes a mth row and nth column compensation control transistor, and the mth row and nth column set voltage write control circuit includes mth row and nth column write control switch;
  • the control electrode of the compensation control transistor in the mth row and the nth column is connected to the mth row compensation control line, and the first electrode of the compensation control transistor in the mth row and the nth column is driven by the mth row and the nth column.
  • the first end of the circuit is connected, and the second electrode of the compensation control transistor in the mth row and nth column is connected to the nth column detection line;
  • the control terminal of the write control switch in the mth row and nth column is connected to the write control line in the mth row, and the first terminal of the write control switch in the mth row and nth column is connected to the mth row and nth column.
  • the setting voltage write terminal is connected, and the second terminal of the write control switch in the mth row and nth column is connected to the nth column detection line.
  • the driving circuit in the mth row and the nth column includes a driving transistor in the mth row and the nth column;
  • the mth row and nth column display control circuit includes a data writing transistor in the mth row and nth column and a data writing transistor in the mth row and nth column.
  • the gate of the driving transistor in the mth row and the nth column is the control terminal of the driving circuit in the mth row and the nth column;
  • the control electrode of the data writing transistor in the mth row and the nth column is connected to the mth row gate line, and the first electrode of the mth row and nth column data writing transistor is connected to the nth column data line ,
  • the second pole of the data writing transistor in the mth row and the nth column is connected to the gate of the driving transistor in the mth row and the nth column;
  • the first electrode of the driving transistor in the mth row and the nth column is connected to the light emitting element in the mth row and the nth column, and the second electrode of the driving transistor in the mth row and the nth column is connected to the power supply voltage terminal;
  • the first end of the storage capacitor in the mth row and nth column is connected to the gate of the driving transistor in the mth row and nth column, and the second end of the storage capacitor in the mth row and nth column is connected to the mth row
  • the first pole of the driving transistor in the nth column is connected.
  • the set voltage generating unit further includes an adjustment circuit
  • the adjustment circuit is used to adjust the voltage coefficient K to (a+1)/B according to the real-time data voltage
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number; a is 0 or a positive integer smaller than B, and B is a positive integer.
  • the voltage generating circuit includes an operational amplifier circuit and a voltage divider circuit
  • the voltage dividing circuit is used to divide the gamma main voltage to obtain a divided voltage, and input the divided voltage to the non-inverting input terminal of the operational amplifier circuit;
  • the inverting input terminal of the operational amplifier circuit is connected to a reference voltage terminal; the operational amplifier circuit is used to generate the set voltage according to the divided voltage and a reference voltage input from the reference voltage terminal.
  • the set voltage generating unit further includes an adjustment circuit
  • the adjusting circuit is configured to provide a voltage dividing adjustment signal to the voltage dividing circuit according to the real-time data voltage, so that the voltage dividing circuit correspondingly controls the variation of the divided voltage and the variation of the gamma main voltage V0
  • the ratio between is b, so that the voltage coefficient K is adjusted accordingly to (a+1)/M;
  • the gray scale corresponding to the real-time data voltage is a, M is the total gray scale number; a is 0 or a positive integer less than M, and M is a positive integer;
  • b is the voltage division coefficient
  • b is equal to K/A
  • A is the amplification coefficient of the operational amplifier circuit.
  • the voltage dividing circuit includes a first voltage dividing resistor and a second voltage dividing resistor
  • the first end of the first voltage dividing resistor is connected to the main gamma voltage, and the second end of the first voltage dividing resistor is connected to the non-inverting input terminal of the operational amplifier circuit;
  • the first end of the second voltage dividing resistor is connected to the positive phase input terminal, and the second end of the second voltage dividing resistor is connected to the first voltage terminal;
  • the resistance value of the first voltage dividing resistor and the resistance value of the second voltage dividing resistor can be adjusted.
  • the voltage dividing adjustment signal includes a resistance value adjustment signal
  • the adjustment circuit is configured to send the resistance value adjustment signal to the first voltage dividing resistor and/or the second voltage dividing resistor according to the real-time data voltage and the gamma main voltage to control and adjust the The resistance value Rz1 of the first voltage dividing resistor and/or the resistance value Rz2 of the second voltage dividing resistor, so as to adjust the voltage coefficient K;
  • Rz2/(Rz1+Rz2) is equal to b.
  • the present disclosure also provides a set voltage generating unit, including a voltage generating circuit
  • the output port of the voltage generating circuit is connected to the pixel circuit; the voltage generating circuit is used to generate a set voltage according to the main gamma voltage, so that the change amount V01 of the set voltage and the change of the main gamma voltage
  • the ratio between the quantities V0 is the voltage coefficient K, which is a positive number less than or equal to 1.
  • the set voltage generating unit further includes an adjustment circuit
  • the adjustment circuit is used to adjust the voltage coefficient K to (a+1)/B according to the real-time data voltage
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number; a is 0 or a positive integer smaller than B, and B is a positive integer.
  • the voltage generating circuit includes an operational amplifier circuit and a voltage divider circuit, wherein,
  • the voltage dividing circuit is used to divide the gamma main voltage to obtain a divided voltage, and input the divided voltage to the non-inverting input terminal of the operational amplifier circuit;
  • the inverting input terminal of the operational amplifier circuit is connected to a reference voltage terminal; the operational amplifier circuit is used to generate the set voltage according to the divided voltage and a reference voltage input from the reference voltage terminal.
  • the set voltage generating unit further includes an adjustment circuit
  • the adjusting circuit is configured to provide a voltage dividing adjustment signal to the voltage dividing circuit according to the real-time data voltage, so that the voltage dividing circuit correspondingly controls the variation of the divided voltage and the variation of the gamma main voltage V0
  • the ratio between is b, so that the voltage coefficient K is adjusted accordingly to (a+1)/M;
  • the gray scale corresponding to the real-time data voltage is a, M is the total gray scale number; a is 0 or a positive integer less than M, and M is a positive integer;
  • b is the voltage division coefficient
  • b is equal to K/A
  • A is the amplification coefficient of the operational amplifier circuit.
  • the voltage dividing circuit includes a first voltage dividing resistor and a second voltage dividing resistor, wherein,
  • the first end of the first voltage dividing resistor is connected to the main gamma voltage, and the second end of the first voltage dividing resistor is connected to the non-inverting input terminal of the operational amplifier circuit;
  • the first end of the second voltage dividing resistor is connected to the positive phase input terminal, and the second end of the second voltage dividing resistor is connected to the first voltage terminal;
  • the resistance value of the first voltage dividing resistor and the resistance value of the second voltage dividing resistor can be adjusted.
  • the voltage dividing adjustment signal includes a resistance value adjustment signal
  • the adjustment circuit is configured to send the resistance value adjustment signal to the first voltage dividing resistor and/or the second voltage dividing resistor according to the real-time data voltage and the gamma main voltage to control and adjust the The resistance value Rz1 of the first voltage dividing resistor and/or the resistance value Rz2 of the second voltage dividing resistor, so as to adjust the voltage coefficient K;
  • Rz2/(Rz1+Rz2) is equal to b.
  • the present disclosure also provides a bit voltage generation method, which is applied to the above-mentioned set voltage generation unit, and the set voltage generation method includes:
  • the voltage generating circuit generates a set voltage according to the gamma main voltage, so that the ratio between the change amount V01 of the set voltage and the change amount V0 of the gamma main voltage is a voltage coefficient K, and K is less than or equal to 1. Positive number.
  • the set voltage generation unit further includes an adjustment circuit; the set voltage generation method further includes:
  • the adjusting circuit adjusts the voltage coefficient K to (a+1)/B according to the real-time data voltage
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number; a is 0 or a positive integer smaller than B, and B is a positive integer.
  • the voltage generating circuit includes an operational amplifier circuit and a voltage divider circuit; the step of generating the set voltage by the voltage generating circuit according to the gamma main voltage includes:
  • the voltage dividing circuit divides the main gamma voltage to obtain a divided voltage, and inputs the divided voltage to the non-inverting input terminal of the operational amplifier circuit;
  • the operational amplifier circuit generates the set voltage according to the divided voltage and the reference voltage input from the reference voltage terminal.
  • the set voltage generation unit further includes an adjustment circuit; the set voltage generation method further includes:
  • the adjustment circuit provides a voltage division adjustment signal to the voltage divider circuit according to the real-time data voltage, so that the voltage divider circuit correspondingly controls the variation of the divided voltage and the variation V0 of the gamma main voltage
  • the ratio of is b, so that the voltage coefficient K is adjusted accordingly to (a+1)/B;
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number; a is 0 or a positive integer less than B, and B is a positive integer;
  • b is the voltage division coefficient
  • b is equal to K/A
  • A is the amplification coefficient of the operational amplifier circuit.
  • the voltage dividing circuit includes a first voltage dividing resistor and a second voltage dividing resistor, and the voltage dividing adjustment signal includes a resistance value adjustment signal;
  • the adjustment circuit provides a voltage division adjustment signal to the voltage divider circuit according to the real-time data voltage, so that the voltage divider circuit correspondingly controls the difference between the variation of the divided voltage and the variation V0 of the gamma main voltage
  • the ratio of is b, so that the corresponding adjustment of the voltage coefficient K to (a+1)/B includes:
  • the adjusting circuit sends the resistance value adjustment signal to the first voltage dividing resistor and/or the second voltage dividing resistor according to the real-time data voltage to control and adjust the resistance value Rz1 of the first voltage dividing resistor And/or the resistance value of the second voltage dividing resistor Rz2, thereby adjusting the voltage coefficient K;
  • Rz2/(Rz1+Rz2) is equal to b.
  • FIG. 1A is a structural diagram of a set voltage generating unit according to an embodiment of the present disclosure
  • Fig. 1B is a structural diagram of a set voltage generating power supply according to another embodiment of the present disclosure.
  • 2A is a circuit diagram of a specific embodiment of a pixel circuit with compensation function
  • Fig. 2B is a schematic diagram of the current flow in the charging phase of the specific embodiment of the pixel circuit with compensation function
  • 2C is a waveform diagram of various voltages after using the set voltage generating unit according to an embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a set voltage generating unit according to another embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of an embodiment of the voltage generating circuit in the set voltage generating unit of the present disclosure
  • FIG. 5 is a circuit diagram of a specific embodiment of the set voltage generating unit according to the present disclosure.
  • FIG. 6 is a flowchart of a method for generating a set voltage according to an embodiment of the present disclosure
  • FIG. 7 is a structural diagram of an embodiment of a pixel circuit in the m-th row and the n-th column in the display device according to the present disclosure
  • FIG. 8 is a circuit diagram of a specific embodiment of the pixel circuit of the mth row and the nth column in the display device according to the present disclosure.
  • the main gamma voltage AVDD will produce a variation V0, which affects the stability of the gamma voltage and causes the output of the data drive circuit
  • the real-time data voltage Vdata will change V01 accordingly.
  • the set voltage V PRESL is a stable voltage value.
  • the gate-source voltage of the driving transistor in the pixel circuit is Vdata+V1-V PRESL , In turn, compensation errors will be caused, resulting in poor compensation display effects.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base electrode, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the set voltage generating unit includes a voltage generating circuit 11;
  • the voltage generating circuit 11 is configured to generate a setting voltage V PRESL according to the main gamma voltage AVDD, so that the ratio between the amount of change V01 of the setting voltage V PRESL and the amount of change V0 of the main gamma voltage AVDD is Is the voltage coefficient K, which is a positive number less than or equal to 1.
  • the setting voltage generating unit includes a voltage generating circuit 11 that generates the setting voltage V PRESL according to the main gamma voltage AVDD, so that the amount of change in the setting voltage V PRESL is equal to the main gamma voltage
  • the variation (that is, the fluctuation value) of AVDD is in a positive proportional relationship, that is, the ratio between the variation V01 of the set voltage V PRESL and the variation V0 of the gamma main voltage AVDD is the voltage coefficient K, so that The change amount of the set voltage V PRESL is equal to the change amount of the real-time data voltage Vdata due to the jitter of the main gamma voltage AVDD, which can eliminate the compensation error caused by the fluctuation of the main gamma voltage AVDD, and ensure a good compensation display effect.
  • the setting voltage generating unit further includes an adjusting circuit 12;
  • the adjusting circuit 12 is connected to the voltage generating circuit 11, and is used for adjusting the voltage coefficient K to (a+1)/B according to the real-time data voltage;
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number; a is 0 or a positive integer smaller than B, and B is a positive integer.
  • the adjusting circuit 12 adjusts the voltage coefficient K to (a+1)/B according to the real-time data voltage Vdata.
  • the data driving circuit outputs a total of 256 gray level voltages, and the gray level corresponding to the real-time data voltage Vdata is a (a is 0 or less than 256 Is a positive integer), K is equal to (a+1)/256.
  • the real-time data voltage is obtained according to the main gamma voltage AVDD, and the amount of change in the real-time data voltage is proportional to the amount of change in the main gamma voltage AVDD, that is, the amount of change V01 of the set voltage V PRESL
  • the ratio with the variation V0 of the gamma main voltage AVDD is the voltage coefficient K.
  • the real-time data voltage can be obtained according to the main gamma voltage AVDD.
  • the data driving circuit outputs 256 gray-scale voltages (the gray-scale voltage is also the data Voltage), the real-time data voltage corresponding to gray level 0 is 0V, and the corresponding voltage coefficient K is equal to 0; the real-time data voltage corresponding to gray level 255 is 8V, and the corresponding voltage coefficient K is equal to 1; the data voltage corresponding to gray level 127 If it is 4V, the corresponding voltage coefficient K is equal to 1/2; the data voltage corresponding to gray scale a is (8 ⁇ (a+1)/256)V, and the corresponding voltage coefficient K is equal to (a+1)/256.
  • a is 0 or a positive integer less than 256.
  • a specific embodiment of a pixel circuit with compensation function includes a driving transistor DT, a data writing transistor T1, a storage capacitor CS, a compensation control transistor T2, a writing control switch SW, and an organic light emitting device.
  • Diode OLED Diode OLED, where,
  • the source of the DT is connected to the anode of the organic light emitting diode OLED, and the drain of the DT is connected to the power supply voltage terminal; the power supply voltage terminal is used to input the power supply voltage ELVDD; the cathode of the OLED is connected to the low voltage ELVSS;
  • the gate of T1 is connected to the gate line Gate, the source of T1 is connected to the data line Data, and the drain of T1 is connected to the gate of DT;
  • the first terminal of CS is connected to the gate of DT, and the second terminal of CS is connected to the source of DT.
  • the gate of T2 is connected to the compensation control line Sc, the source of T2 is connected to the source of DT, and the drain of T2 is connected to the detection line SL;
  • the control end of SW is connected to the write control line, the first end of SW is connected to the set voltage write end, and the second end of SW is connected to the detection line SL; the set voltage write end is used for writing The set voltage V PRESL .
  • DT, T1, and T2 are n-type thin film transistors, but not limited to this.
  • T1 and T2 are turned on, SW controls the connection between the set voltage writing terminal and the detection line SL, and the real-time data voltage Vdata on the data line Data is written into the gate of DT.
  • the gate of DT Source voltage Vgs Vdata-V PRESL ;
  • T1 is closed, T2 is opened, SW controls the disconnection of the connection between the set voltage writing terminal and the detection line SL, DT is opened, and the current flowing through DT is related to Vgs; as shown in Figure 2B, the current passes open DT and T2 charge SL (there is a parasitic capacitance on SL).
  • the voltage on SL is sampled. Different DTs have different mobility. Therefore, the sampled voltage can reflect the mobility of DT. The obtained voltage can determine the corresponding data voltage compensation amount.
  • Vdata fluctuates. If V PRESL is a fixed voltage at this time, the Vgs of DT fluctuates with Vdata. And fluctuations, so that the corresponding current flowing through DT is affected by the fluctuations of Vdata, which in turn affects the accuracy of compensation; therefore, as shown in FIG.
  • the embodiment of the present disclosure controls V PRESL to fluctuate with the fluctuation of Vdata, that is, V PRESL and Vdata have the same fluctuation amplitude, so that the gate-source voltage Vgs of the driving transistor DT has nothing to do with the fluctuation of AVDD, eliminating the compensation error caused by the fluctuation of the gamma main voltage AVDD, and effectively reducing the mura caused by the compensation error (mura is Refers to the phenomenon of uneven display brightness, causing various traces) or noise to ensure a good compensation display effect.
  • the data driving circuit in the display device obtains the real-time data voltage Vdata according to the main gamma voltage AVDD and the low level VSS, and the total number of gray levels is B, that is, the data driving circuit provides a total of B gray levels Voltage (the gray scale voltage is also the data voltage), the real-time data voltage corresponding to gray scale 0 is equal to VSS, the real-time data voltage corresponding to gray scale B-1 is equal to AVDD, and the real-time data voltage corresponding to gray scale a is equal to VSS+ ((AVDD-VSS) ⁇ (a+1)/B), the ratio between the change of the real-time data voltage V01 corresponding to the gray scale a and the change of AVDD V0 is the voltage coefficient K, and the voltage coefficient K It is equal to (a+1)/B, so AVDD fluctuates, and Vdata fluctuates accordingly.
  • VSS can be 0V, common electrode voltage, or other fixed levels, but not limited to this.
  • the voltage generating circuit may include an operational amplifier circuit and a voltage divider circuit, wherein,
  • the voltage dividing circuit is used to divide the gamma main voltage to obtain a divided voltage, and input the divided voltage to the non-inverting input terminal of the operational amplifier circuit;
  • the inverting input terminal of the operational amplifier circuit is connected to a reference voltage terminal; the operational amplifier circuit is used to generate the set voltage according to the divided voltage and a reference voltage input from the reference voltage terminal.
  • the set voltage generating unit described in the embodiment of the present disclosure may further include an adjustment circuit
  • the adjustment circuit is configured to provide a voltage division adjustment signal to the voltage divider circuit according to the real-time data voltage, so that the voltage divider circuit correspondingly controls the variation of the divided voltage and the variation of the gamma main voltage
  • the ratio between the quantities V0 is b, so that the voltage coefficient K is adjusted accordingly to (a+1)/B;
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number, B is a positive integer, and a is 0 or a positive integer less than B.
  • the voltage generating circuit includes a voltage dividing circuit and an operational amplifier circuit, and the adjusting circuit provides a voltage dividing adjustment signal to the voltage dividing circuit to adjust the divided voltage accordingly, thereby adjusting the voltage coefficient K.
  • the reference voltage may be a fixed voltage, for example, it may be 0V or a low voltage, but is not limited to this.
  • the voltage generating circuit 11 includes an operational amplifier circuit Cmp and a voltage divider circuit 110, wherein,
  • the voltage dividing circuit 110 is used to divide the main gamma voltage AVDD to obtain the divided voltage Vf, and input the divided voltage Vf to the non-inverting input terminal of the operational amplifier circuit Cmp;
  • the inverting input terminal of the operational amplifier circuit Cmp is connected to a reference voltage terminal for inputting a reference voltage Vref; the operational amplifier circuit Cmp is used for according to the divided voltage Vf and the reference voltage Vref input from the reference voltage terminal Generating the set voltage;
  • the adjusting circuit 12 is used for the real-time data voltage Vdata and the main gamma voltage AVDD to provide a voltage dividing adjustment signal to the voltage dividing circuit 110, so that the voltage dividing circuit 110 correspondingly controls the voltage of the divided voltage
  • the ratio between the amount of change and the amount of change V0 of the gamma main voltage is b, so that the voltage coefficient K is adjusted accordingly.
  • the voltage generating circuit 11 includes a voltage dividing circuit 110 and an operational amplifier circuit Cmp.
  • the adjusting circuit 12 provides a voltage dividing adjustment signal to the voltage dividing circuit 110,
  • the ratio between the variation of the corresponding control divided voltage Vf and the variation V0 of the gamma main voltage is set to b, thereby adjusting the voltage coefficient K.
  • the set voltage generated by the operational amplifier circuit Cmp is equal to A ⁇ (Vf-Vref), and the ratio between the change in the divided voltage Vf and the change in AVDD is b;
  • K is equal to b ⁇ A
  • A is the amplification factor of the operational amplifier.
  • the voltage dividing circuit may include a first voltage dividing resistor and a second voltage dividing resistor, wherein,
  • the first end of the first voltage dividing resistor is connected to the main gamma voltage, and the second end of the first voltage dividing resistor is connected to the non-inverting input terminal of the operational amplifier circuit;
  • the first end of the second voltage dividing resistor is connected to the positive phase input terminal, and the second end of the second voltage dividing resistor is connected to the first voltage terminal;
  • the resistance value of the first voltage dividing resistor and the resistance value of the second voltage dividing resistor can be adjusted.
  • the first voltage terminal is used to input the first voltage V1; in a specific implementation, the first voltage terminal may be a ground terminal or a low voltage terminal, but is not limited to this.
  • the voltage dividing circuit 110 may include a first voltage dividing resistor R1 and a second voltage dividing resistor R2, wherein,
  • the first terminal of the first voltage dividing resistor R1 is connected to the main gamma voltage AVDD, and the second terminal of the first voltage dividing resistor R2 is connected to the non-inverting input terminal of the operational amplifier circuit Cmp;
  • the first end of the second voltage dividing resistor R2 is connected to the positive input end of the operational amplifier circuit Cmp, and the second end of the second voltage dividing resistor R2 is connected to the ground terminal GND;
  • the resistance value Rz1 of the first voltage dividing resistor R1 and the resistance value Rz2 of the second voltage dividing resistor R2 can be adjusted to be able to adjust the divided voltage Vf.
  • V1 is equal to zero.
  • Vf is equal to AVDD ⁇ Rz2/(Rz1+Rz2)
  • adjusting Rz1 and Rz2 can adjust Vf accordingly
  • the voltage division coefficient b is equal to Rz2/(Rz1 +Rz2)
  • the voltage coefficient K is equal to b ⁇ A
  • A is the amplification factor of the operational amplifier circuit Cmp.
  • the voltage division adjustment signal may include a resistance value adjustment signal
  • the adjustment circuit 12 is configured to send the resistance value adjustment signal to the first voltage dividing resistor R1 and/or the second voltage dividing resistor R2 according to the real-time data voltage Vdata and the main gamma voltage AVDD, Controlling and adjusting the resistance value Rz1 of the first voltage dividing resistor R1 and/or the resistance value Rz2 of the second voltage dividing resistor R2, thereby adjusting the voltage coefficient K;
  • Rz2/(Rz1+Rz2) is equal to b.
  • a specific embodiment of the set voltage generating unit described in the present disclosure includes a voltage generating circuit and a regulating circuit 12;
  • the voltage generating circuit includes an operational amplifier circuit Cmp and a voltage dividing circuit 110, and the voltage dividing circuit 110 includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2;
  • the inverting input terminal of the operational amplifier circuit Cmp is connected to a reference voltage terminal for inputting a reference voltage Vref; the operational amplifier circuit Cmp is configured to generate a preset value according to the divided voltage Vf and the reference voltage Vref input from the reference voltage terminal. Bit voltage V PRESL ;
  • the first terminal of the first voltage dividing resistor R1 is connected to the main gamma voltage AVDD, and the second terminal of the first voltage dividing resistor R1 is connected to the positive input terminal of the operational amplifier circuit Cmp;
  • the first end of the second voltage dividing resistor R2 is connected to the positive input end of the operational amplifier circuit Cmp, and the second end of the second voltage dividing resistor R2 is connected to the ground terminal GND;
  • the voltage division adjustment signal includes a resistance value adjustment signal
  • the adjustment circuit 12 is configured to send the resistance value adjustment signal to the first voltage dividing resistor R1 and/or the second voltage dividing resistor R2 according to the real-time data voltage Vdata and the gamma main voltage AVDD to control
  • the resistance value Rz1 of the first voltage dividing resistor R1 and/or the resistance value Rz2 of the second voltage dividing resistor R2 are adjusted to adjust the divided voltage Vf.
  • V PRESL A ⁇ (Vf-Vref), Vf is equal to AVDD ⁇ Rz2/(Rz1+Rz2), where A is the amplification factor, and A is A positive number; then the variation of V PRESL is equal to A ⁇ Rz2/(Rz1+Rz2) times the variation of AVDD, that is, the voltage coefficient K is equal to A ⁇ Rz2/(Rz1+Rz2).
  • the set voltage generating method according to the embodiment of the present disclosure is applied to the above set voltage generating unit, and the set voltage generating method includes:
  • the voltage generating circuit generates a set voltage according to the gamma main voltage, so that the ratio between the change amount V01 of the set voltage and the change amount V0 of the gamma main voltage is a voltage coefficient K, and K is less than or equal to 1. Positive number.
  • the set voltage generating method described in the embodiment of the present disclosure uses a voltage generating circuit to generate the set voltage according to the gamma main voltage, so that the change of the set voltage is proportional to the change (that is, the fluctuation value) of the gamma main voltage Relationship, that is, the ratio between the change in the set voltage V01 and the change in the gamma main voltage V0 is the voltage coefficient K, so that the change in the set voltage is equal to the real-time data voltage due to the gamma main voltage
  • the amount of change caused by jitter can eliminate the compensation error caused by the fluctuation of the gamma main voltage AVDD, and ensure a good compensation display effect.
  • the set voltage generating unit may further include an adjustment circuit
  • the set voltage generating method As shown in FIG. 6, the set voltage generating method according to the embodiment of the present disclosure is applied to the above set voltage generating unit, and the set voltage generating method includes:
  • the voltage generating circuit generates the set voltage according to the gamma main voltage, so that the ratio between the change amount of the set voltage V01 and the change amount V0 of the gamma main voltage is the voltage coefficient K, and K is less than or A positive number equal to 1;
  • the adjustment circuit adjusts the voltage coefficient K to (a+1)/B according to the real-time data voltage
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number, B is a positive integer, and a is 0 or a positive integer less than B.
  • the set voltage generating unit may further include an adjustment circuit.
  • the adjustment circuit adjusts K to be equal to (a+1)/B, so that the change in the set voltage is equal to the real-time data voltage due to the gamma main voltage jitter. The amount of change brought about.
  • the voltage dividing circuit divides the main gamma voltage to obtain a divided voltage, and inputs the divided voltage to the non-inverting input terminal of the operational amplifier circuit;
  • the operational amplifier circuit generates the set voltage according to the divided voltage and the reference voltage input from the reference voltage terminal.
  • the adjustment circuit provides a voltage division adjustment signal to the voltage divider circuit according to the real-time data voltage, so that the voltage divider circuit correspondingly controls the variation of the divided voltage and the variation V0 of the gamma main voltage
  • the ratio of is b, so that the voltage coefficient K is adjusted accordingly to (a+1)/B;
  • the gray scale corresponding to the real-time data voltage is a, B is the total gray scale number; a is 0 or a positive integer less than B, and B is a positive integer;
  • b is the voltage division coefficient
  • b is equal to K/A
  • A is the amplification coefficient of the operational amplifier circuit.
  • the set voltage generating unit further includes an adjustment circuit that provides a voltage division adjustment signal to the voltage divider circuit to control and adjust the voltage division coefficient b of the voltage divider circuit, thereby reducing the voltage coefficient K Adjust to (a+1)/B.
  • the voltage divider circuit may include a first voltage divider resistor and a second voltage divider resistor, and the voltage divider adjustment signal may include a resistance value adjustment signal;
  • the adjustment circuit provides a voltage division adjustment signal to the voltage divider circuit according to the real-time data voltage, so that the voltage divider circuit correspondingly controls the difference between the variation of the divided voltage and the variation V0 of the gamma main voltage
  • the ratio of is b, so that the corresponding adjustment of the voltage coefficient K to (a+1)/B may include:
  • the adjusting circuit sends the resistance value adjustment signal to the first voltage dividing resistor and/or the second voltage dividing resistor according to the real-time data voltage to control and adjust the resistance value Rz1 of the first voltage dividing resistor And/or the resistance value of the second voltage dividing resistor Rz2, thereby adjusting the voltage coefficient K;
  • Rz2/(Rz1+Rz2) is equal to b.
  • the display device includes M rows and N columns of pixel circuits and N above-mentioned set voltage generating units;
  • the nth set voltage generating unit is connected to the pixel circuit located in the nth column, and is used to provide a set voltage for the pixel circuit located in the nth column;
  • Both M and N are integers greater than 1, and n is a positive integer less than or equal to N.
  • the pixel circuits located in the same column are all connected to a set voltage generating unit, and each row of gate lines and each row of write control lines are turned on row by row, so as to turn on the real-time data on the corresponding column data line.
  • the data voltage is written into the pixel circuits of different rows in a time-sharing manner, and the corresponding column detection line is controlled to time-sharingly access the corresponding column setting voltages in different rows.
  • the display device may further include a display substrate and a driving integrated circuit; the pixel circuit is arranged in the display area of the display substrate;
  • the setting voltage generating unit is arranged in a peripheral area of the display substrate, or the setting voltage generating unit is arranged in the driving integrated circuit.
  • the setting generating unit may be arranged in the peripheral area of the display substrate, or may be arranged in a driver IC (Integrated Circuit, integrated circuit), and a column of pixel circuits share a set voltage generating unit unit.
  • driver IC Integrated Circuit, integrated circuit
  • the display device described in the present disclosure may further include N columns of detection lines, M rows of gate lines, N columns of data lines, M rows of compensation control lines, and M rows of write control lines;
  • the gate lines are used for output A gate drive signal, the data line is used to output a real-time data voltage, the compensation control line is used to input a compensation control signal, and the write control line is used to input a write control signal;
  • the pixel circuit in the m-th row and the n-th column includes a light-emitting element in the m-th row and the n-th column, the m-th row and the n-th column drive circuit, the m-th row and the n-th column display control circuit, the m-th row and the n-th column compensation control circuit, and the m-th row
  • the nth column set voltage is written into the control circuit, where
  • the driving circuit of the mth row and the nth column is used for driving the light emitting element of the mth row and the nth column under the control of its control terminal;
  • the display control circuit of the mth row and the nth column is connected to the control terminal of the driving circuit of the mth row and the nth column, and is used to control the gate drive signal output by the gate line of the mth row according to the data of the nth column.
  • the real-time data voltage on the line performs display driving control on the driving circuit of the mth row and the nth column;
  • the compensation control circuit in the mth row and the nth column is used for controlling the first end of the mth row and the nth column drive circuit and the nth column detection line under the control of the compensation control signal input from the mth row compensation control line Connect between
  • the set voltage write control circuit of the mth row and the nth column is used to control the set voltage write terminal of the mth row and the nth column under the control of the write control signal input from the write control line of the mth row and The nth column of detection lines are connected;
  • the nth set voltage generating unit is used to write the set voltage of the mth row and the nth column to the set voltage write terminal of the mth row and the nth column, so as to set the setting voltage in the mth row and nth column
  • the bit voltage writing control circuit controls the communication between the set voltage writing terminal of the mth row and the nth column and the nth column detection line, it controls the writing of the set voltage of the mth row and the nth column to the n columns of detection lines;
  • n is a positive integer less than or equal to M.
  • the light-emitting element in the m-th row and the n-th column may be an organic light emitting diode, but is not limited to this.
  • an embodiment of the pixel circuit in the mth row and the nth column may include a light emitting element ELmn in the mth row and nth column, a driving circuit 71mn in the mth row and nth column, and a display control circuit 72mn in the mth row and nth column.
  • the compensation control circuit 73mn in the mth row and the nth column and the set voltage writing control circuit 74mn in the mth row and the nth column where,
  • the first end of the driving circuit 71mn in the mth row and nth column is connected to the first electrode of the light emitting element ELmn in the mth row and nth column, and the second end of the driving circuit 71mn in the mth row and nth column is connected to Connected to the power supply voltage terminal of the input power supply voltage ELVDD, the m-th row and n-th column driving circuit 71mn is used to drive the m-th row and n-th column light-emitting element ELmn under the control of its control terminal; the n-th column light-emitting element The second end of ELmn is connected to low voltage ELVSS;
  • the control terminal of the display control circuit 72mn in the mth row and the nth column is connected to the gate line Gatem in the mth row, and the first terminal of the display control circuit 72mn in the mth row and nth column is connected to the data line Datan in the nth column, so
  • the second end of the display control circuit 72mn in the mth row and nth column is connected to the control end of the drive circuit 71mn in the mth row and nth column, and the display control circuit 72mn in the mth row and nth column is used in the mth row Under the control of the gate driving signal output by the gate line Gatem, display driving control of the driving circuit 71mn in the mth row and the nth column according to the real-time data voltage Vdatamn on the data line Datan in the nth column;
  • the control terminal of the compensation control circuit 73mn in the mth row and the nth column is connected to the compensation control line Scm in the mth row, and the first terminal of the compensation control circuit 73mn in the mth row and the nth column is connected to the mth row and the nth column.
  • the first end of the driving circuit 71mn is connected, the second end of the compensation control circuit 73mn of the mth row and the nth column is connected to the detection line SLn of the nth column, and the compensation control circuit 73mn of the mth row and nth column is used for controlling the communication between the first end of the driving circuit 71mn in the m-th row and the n-th column and the detection line SLn in the n-th column under the control of the compensation control signal input from the m-row compensation control line Scm;
  • the control terminal of the mth row and nth column set voltage write control circuit 74mn is connected to the mth row write control line Lwm, and the mth row and nth column set voltage write control circuit 74mn has a first terminal Is connected to the set voltage writing terminal of the mth row and nth column, the second terminal of the mth row and nth column setting voltage writing control circuit 74mn is connected to the nth column detection line SLn, and the mth column Row nth column set voltage write control circuit 74mn is used to control the mth row and nth column set voltage write terminal and the mth row under the control of the write control signal input from the write control line Lwm
  • the n-column detection lines SLn are connected, so that the setting voltage write terminal in the m-th row and the n-th column writes the setting voltage V PRESL-mn in the m-th row and the n-th column to the n-th column detection line
  • the display device includes the nth setting voltage generating unit for writing the setting voltage V PRESL in the mth row and the nth column to the setting voltage writing terminal of the mth row and the nth column.
  • n is a positive integer less than or equal to M.
  • the nth setting voltage generating unit In the setting phase of the mth row and the nth column, the nth setting voltage generating unit writes the setting voltage V PRESL ⁇ in the mth row and nth column to the setting voltage writing terminal of the mth row and nth column.
  • the display control circuit 72mn in the mth row and nth column writes the real-time data voltage Vdatamn on the data line Datan in the nth column into the mth
  • the control terminal of the driving circuit 71mn in the nth row and the nth column, the compensation control circuit 73mn in the mth row and the nth column controls the driving of the mth row and the nth column under the control of the compensation control signal input from the compensation control line Scm in the mth row
  • the first end of the circuit 71mn communicates with the nth column detection line SLn; the mth row and nth column set voltage write control circuit 74mn controls the write control signal input on the mth row write control line Lwm Control the communication between the set voltage write terminal in the mth row and the nth column and the nth column detection line SLn, so that the set voltage write terminal in
  • the mth row and nth column display control circuit 72mn disconnects the nth column data line Datan from the The connection between the control terminals of the driving circuit 71mn in the mth row and the nth column; the control of the write control signal input by the mth row and nth column set voltage write control circuit 74mn on the mth row write control line Lwm Control to disconnect the connection between the set voltage writing terminal of the mth row and the nth column and the nth column detection line SLn; the compensation control circuit 73mn of the mth row and nth column compensates the control line in the mth row Under the control of the compensation control signal input by Scm, the first end of the driving circuit 71mn in the mth row and the nth column is controlled to communicate with the detection line SLn in the nth column; the
  • the circuit 73mn charges the nth column detection line SLn (there is a parasitic capacitance on SLn), and after a predetermined charging time t, samples the voltage on SLn, and compensates the data voltage according to the sampled voltage.
  • the nth setting voltage generating unit transfers to the mth row and the nth column.
  • the column setting voltage writing terminal writes the setting voltage V PRESL -mn in the mth row and the nth column so that the variation of V PRESL -mn is equal to the variation of Vdatanm due to the jitter of the gamma main voltage AVDD, thereby increasing Compensation accuracy.
  • the compensation control circuit for the mth row and the nth column may include a compensation control transistor for the mth row and the nth column, and the mth row and nth column set voltage write control circuit may include the mth row and nth column write Access control switch;
  • the control electrode of the compensation control transistor in the mth row and the nth column is connected to the mth row compensation control line, and the first electrode of the compensation control transistor in the mth row and the nth column is driven by the mth row and the nth column.
  • the first end of the circuit is connected, and the second electrode of the compensation control transistor in the mth row and nth column is connected to the nth column detection line;
  • the control terminal of the write control switch in the mth row and nth column is connected to the write control line in the mth row, and the first terminal of the write control switch in the mth row and nth column is connected to the mth row and nth column.
  • the setting voltage write terminal is connected, and the second terminal of the write control switch in the mth row and nth column is connected to the nth column detection line.
  • the driving circuit in the mth row and the nth column may include a driving transistor in the mth row and the nth column;
  • the mth row and nth column display control circuit includes a data writing transistor in the mth row and nth column and the mth row Storage capacitor in the nth column;
  • the gate of the driving transistor in the mth row and the nth column is the control terminal of the driving circuit in the mth row and the nth column;
  • the control electrode of the data writing transistor in the mth row and the nth column is connected to the mth row gate line, and the first electrode of the mth row and nth column data writing transistor is connected to the nth column data line ,
  • the second pole of the data writing transistor in the mth row and the nth column is connected to the gate of the driving transistor in the mth row and the nth column;
  • the first electrode of the driving transistor in the mth row and the nth column is connected to the light emitting element in the mth row and the nth column, and the second electrode of the driving transistor in the mth row and the nth column is connected to the power supply voltage terminal;
  • the first end of the storage capacitor in the mth row and nth column is connected to the gate of the driving transistor in the mth row and nth column, and the second end of the storage capacitor in the mth row and nth column is connected to the mth row
  • the first pole of the driving transistor in the nth column is connected.
  • the following uses a specific embodiment to illustrate the pixel circuit of the mth row and the nth column included in the display device according to the present disclosure.
  • a specific embodiment of the pixel circuit in the mth row and the nth column includes an organic light emitting diode OLEDmn in the mth row and nth column, a driving circuit 71mn in the mth row and nth column, and a display control circuit in the mth row and nth column.
  • OLEDmn organic light emitting diode
  • a driving circuit 71mn in the mth row and nth column a driving circuit 71mn in the mth row and nth column
  • a display control circuit in the mth row and nth column 72mn, the compensation control circuit 73mn of the mth row and the nth column, and the set voltage write control circuit 74mn of the mth row and the nth column, wherein,
  • the compensation control circuit 73mn in the mth row and nth column includes a compensation control transistor T2mn in the mth row and nth column, and the set voltage write control circuit 74mn in the mth row and nth column includes write control in the mth row and nth column.
  • the m-th row and n-th column display control circuit 72mn includes a m-th row and n-th column data write transistor T1mn and The storage capacitor Csmn in the mth row and the nth column;
  • the gate of the compensation control transistor T2mn in the mth row and nth column is connected to the mth row compensation control line Scm, and the source of the compensation control transistor T2mn in the mth row and nth column is connected to the mth row and nth
  • the source of the column driving transistor is connected, and the drain of the compensation control transistor T2mn in the mth row and the nth column is connected to the nth column detection line SLn;
  • the control end of the write control switch SWmn in the mth row and nth column is connected to the write control line in the mth row, and the first end of the write control switch SWmn in the mth row and nth column is connected to the mth row and nth write control switch SWmn.
  • the set voltage write terminal of the n column is connected, and the second terminal of the write control switch SWmn of the mth row and the nth column is connected to the nth column detection line SLn.
  • the gate of the driving transistor DTmn in the mth row and the nth column is the control terminal of the driving circuit in the mth row and the nth column;
  • the gate of the data writing transistor T1mn of the mth row and the nth column is connected to the gate line Gatem of the mth row, and the source of the data writing transistor T1mn of the mth row and the nth column is connected to the data line Datan of the nth column,
  • the drain of the data writing transistor T1mn in the mth row and nth column is connected to the gate of the driving transistor DTmn in the mth row and nth column;
  • the source of the driving transistor DTmn in the mth row and the nth column is connected to the anode of the organic light emitting diode OLEDmn in the mth row and the nth column, and the drain of the driving transistor DTmn in the mth row and the nth column is connected to the input power source.
  • the power supply voltage terminal of the voltage ELVDD is connected; the cathode of the organic light emitting diode OLEDmn in the mth row and the nth column is connected to the low voltage ELVSS;
  • the first end of the storage capacitor Csmn in the mth row and nth column is connected to the gate of the driving transistor DTmn in the mth row and nth column, and the second end of the storage capacitor Csmn in the mth row and nth column is connected to the The source connection of the driving transistor DTmn in the mth row and the nth column;
  • the display device includes the nth setting voltage generating unit for writing the setting voltage V PRESL in the mth row and the nth column to the setting voltage writing terminal of the mth row and the nth column. mn.
  • all the transistors are n-type thin film transistors, but it is not limited thereto.
  • the nth setting voltage generating unit In the setting phase of the mth row and the nth column, the nth setting voltage generating unit writes the setting voltage V PRESL ⁇ in the mth row and nth column to the setting voltage writing terminal of the mth row and nth column.
  • the data writing transistor T1mn in the mth row and nth column is turned on to write the real-time data voltage Vdatamn on the nth column data line Datan
  • the gate of the driving transistor DTmn in the mth row and the nth column under the control of the compensation control signal input from the mth row compensation control line Scm, the mth row and nth column compensation control transistor T2mn is turned on to control the
  • the source of the driving transistor DTmn in the m row and the n th column is connected with the n th column detection line SLn; under the control of the write control signal input from the m th row write control line, the m th row and the n th column write
  • the control switch SWmn is turned on to control the communication between the set voltage write terminal of the mth row and the nth column and the nth column detection line SLn, so that the set
  • the voltage V PRESL -mn is set in the nth column to the detection line SLn in the nth column, and then V PRESL -mn is written into the source of the driving transistor DTmn in the mth row and nth column; at this time, the mth row
  • the voltage of the gate of the driving transistor DTmn in the nth column is Vdatamn
  • the voltage of the source of the driving transistor DTmn in the mth row and the nth column is V PRESL -mn
  • the gate source of the driving transistor DTmn in the mth row and nth column The voltage Vgs is Vdatamn-V PRESL -mn ;
  • the mth row and nth column data write transistor T1mn is turned off to disconnect the nth column data line Connection between Datan and the gate of the drive transistor DTmn in the mth row and nth column; under the control of the write control signal input from the mth row write control line, the mth row and nth column write control
  • the switch SWmn controls to disconnect the connection between the set voltage write terminal of the mth row and the nth column and the nth column detection line SLn; under the control of the compensation control signal input from the mth row compensation control line Scm, the The compensation control transistor T2mn in the mth row and the nth column is turned on to control the communication between the source of the mth row and nth column drive transistor DTmn and the nth column detection line SLn; the mth row and nth row and nth
  • the n column compensation control transistor T2mn charges the nth column detection line SLn (there is a parasitic capacitance on SLn), after a predetermined charging time t, the voltage on SLn is sampled, and the data voltage is compensated according to the sampled voltage .
  • the nth setting voltage generating unit transfers to the mth row and the nth column.
  • the setting voltage write terminal of the n column writes the setting voltage V PRESL -mn of the mth row and the nth column so that the variation of V PRESL -mn is equal to the variation of Vdatanm due to the jitter of the gamma main voltage AVDD, thus Improve compensation accuracy.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种置位电压生成单元、置位电压生成方法和显示装置。置位电压生成单元包括电压生成电路（11）；电压生成电路（11）用于根据伽马主电压（AVDD）生成置位电压（V PRESL），以使得置位电压（V PRESL）的变化量（V01）与伽马主电压（AVDD）的变化量（V0）之间的比值为电压系数K，K为小于或等于1的正数。

Description

置位电压生成单元、置位电压生成方法和显示装置
相关申请的交叉引用
本申请主张在2019年1月25日在中国提交的中国专利申请号No.201910073659.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种置位电压生成单元、置位电压生成方法和显示装置。
背景技术
在OLED显示设备工作过程中，受到外界因素(主要指温度)以及自身电路不稳定性的影响，导致显示效果变差。
内容
本公开提供了一种显示装置，包括M行N列像素电路和N个置位电压生成单元；
所述置位电压生成单元包括电压生成电路；所述电压生成电路用于根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数；
第n个所述置位电压生成单元的输出端口与位于第n列的像素电路连接，用于为位于第n列的像素电路提供置位电压；
M和N都为大于1的整数，n为小于或等于N的正整数。
实施时，所述显示装置还包括显示基板；所述像素电路设置于所述显示基板的显示区域；所述置位电压生成单元设置于所述显示基板的周边区域。
实施时，所述显示装置还包括显示基板和驱动集成电路；所述像素电路设置于所述显示基板的显示区域；所述置位电压生成单元设置于所述驱动集成电路中。
实施时，所述显示装置还包括N列检测线、M行栅线、N列数据线、M 行补偿控制线和M行写入控制线；所述栅线用于输出栅极驱动信号，所述数据线用于输出实时数据电压，所述补偿控制线用于输入补偿控制信号，所述写入控制线用于输入写入控制信号；
第m行第n列像素电路包括第m行第n列发光元件、第m行第n列驱动电路、第m行第n列显示控制电路、第m行第n列补偿控制电路和第m行第n列置位电压写入控制电路，其中，
所述第m行第n列驱动电路用于在其控制端的控制下驱动所述第m行第n列发光元件；
所述第m行第n列显示控制电路与第m行第n列所述驱动电路的控制端连接，用于在第m行栅线输出的栅极驱动信号的控制下，根据第n列数据线上的实时数据电压对所述第m行第n列驱动电路进行显示驱动控制；
所述第m行第n列补偿控制电路用于在第m行补偿控制线输入的补偿控制信号的控制下，控制所述第m行第n列驱动电路的第一端与第n列检测线之间连通；
所述第m行第n列置位电压写入控制电路用于在第m行写入控制线输入的写入控制信号的控制下，控制第m行第n列置位电压写入端与所述第n列检测线之间连通；
所述第n个置位电压生成电路用于向所述第m行第n列置位电压写入端写入第m行第n列置位电压，以在所述第m行第n列置位电压写入控制电路控制第m行第n列置位电压写入端与所述第n列检测线之间连通时，控制将所述第m行第n列置位电压写入所述第n列检测线；
m为小于或等于M的正整数。
实施时，所述第m行第n列补偿控制电路包括第m行第n列补偿控制晶体管，所述第m行第n列置位电压写入控制电路包括第m行第n列写入控制开关；
所述第m行第n列补偿控制晶体管的控制极与所述第m行补偿控制线连接，所述第m行第n列补偿控制晶体管的第一极与所述第m行第n列驱动电路的第一端连接，所述第m行第n列补偿控制晶体管的第二极与所述第n列检测线连接；
所述第m行第n列写入控制开关的控制端与第m行写入控制线连接，所述第m行第n列写入控制开关的第一端与所述第m行第n列置位电压写入端连接，所述第m行第n列写入控制开关的第二端与所述第n列检测线连接。
实施时，所述第m行第n列驱动电路包括第m行第n列驱动晶体管；所述第m行第n列显示控制电路包括第m行第n列数据写入晶体管和第m行第n列存储电容；
所述第m行第n列驱动晶体管的栅极为所述第m行第n列驱动电路的控制端；
所述第m行第n列数据写入晶体管的控制极与所述第m行栅线连接，所述第m行第n列数据写入晶体管的第一极与所述第n列数据线连接，所述第m行第n列数据写入晶体管的第二极与所述第m行第n列驱动晶体管的栅极连接；
所述第m行第n列驱动晶体管的第一极与所述第m行第n列发光元件连接，所述第m行第n列驱动晶体管的第二极与电源电压端连接；
所述第m行第n列存储电容的第一端与所述第m行第n列驱动晶体管的栅极连接，所述第m行第n列存储电容的第二端与所述第m行第n列驱动晶体管的第一极连接。
实施时，所述置位电压生成单元还包括调节电路；
所述调节电路用于根据实时数据电压调节所述电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数。
实施时，所述电压生成电路包括运算放大电路和分压电路；
所述分压电路用于对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
所述运算放大电路的反相输入端与参考电压端连接；所述运算放大电路用于根据所述分压电压和所述参考电压端输入的参考电压生成所述置位电压。
实施时，所述的置位电压生成单元还包括调节电路；
所述调节电路用于根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变 化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/M；
所述实时数据电压对应的灰阶为a，M为总灰阶数；a为0或小于M的正整数，M为正整数；
b为分压系数，b等于K/A，A为所述运算放大电路的放大系数。
实施时，所述分压电路包括第一分压电阻和第二分压电阻；
所述第一分压电阻的第一端接入所述伽马主电压，所述第一分压电阻的第二端与所述运算放大电路的正相输入端连接；
所述第二分压电阻的第一端与所述正相输入端连接，所述第二分压电阻的第二端与第一电压端连接；
所述第一分压电阻的电阻值和所述第二分压电阻的电阻值能够被调节。
实施时，所述分压调节信号包括电阻值调节信号；
所述调节电路用于根据所述实时数据电压和所述伽马主电压向所述第一分压电阻和/或所述第二分压电阻发送所述电阻值调节信号，以控制调节所述第一分压电阻的电阻值Rz1和/或所述第二分压电阻的电阻值Rz2，从而调节所述电压系数K；
Rz2/(Rz1+Rz2)等于b。
本公开还提供了一种置位电压生成单元，包括电压生成电路；
所述电压生成电路得输出端口与像素电路连接；所述电压生成电路用于根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数。
实施时，所述置位电压生成单元还包括调节电路；
所述调节电路用于根据实时数据电压调节所述电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数。
实施时，所述电压生成电路包括运算放大电路和分压电路，其中，
所述分压电路用于对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
所述运算放大电路的反相输入端与参考电压端连接；所述运算放大电路用于根据所述分压电压和所述参考电压端输入的参考电压生成所述置位电压。
实施时，所述置位电压生成单元还包括调节电路；
所述调节电路用于根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/M；
所述实时数据电压对应的灰阶为a，M为总灰阶数；a为0或小于M的正整数，M为正整数；
b为分压系数，b等于K/A，A为所述运算放大电路的放大系数。
实施时，所述分压电路包括第一分压电阻和第二分压电阻，其中，
所述第一分压电阻的第一端接入所述伽马主电压，所述第一分压电阻的第二端与所述运算放大电路的正相输入端连接；
所述第二分压电阻的第一端与所述正相输入端连接，所述第二分压电阻的第二端与第一电压端连接；
所述第一分压电阻的电阻值和所述第二分压电阻的电阻值能够被调节。
实施时，所述分压调节信号包括电阻值调节信号；
所述调节电路用于根据所述实时数据电压和所述伽马主电压向所述第一分压电阻和/或所述第二分压电阻发送所述电阻值调节信号，以控制调节所述第一分压电阻的电阻值Rz1和/或所述第二分压电阻的电阻值Rz2，从而调节所述电压系数K；
Rz2/(Rz1+Rz2)等于b。
本公开还提供了一种位电压生成方法，应用于上述置位电压生成单元，所述置位电压生成方法包括：
电压生成电路根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数。
实施时，所述置位电压生成单元还包括调节电路；所述置位电压生成方法还包括：
调节电路根据实时数据电压调节所述电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数。
实施时，所述电压生成电路包括运算放大电路和分压电路；所述电压生成电路根据伽马主电压生成置位电压步骤包括：
分压电路对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
所述运算放大电路根据所述分压电压和参考电压端输入的参考电压生成所述置位电压。
实施时，所述置位电压生成单元还包括调节电路；所述置位电压生成方法还包括：
所述调节电路根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数；
b为分压系数，b等于K/A，A为所述运算放大电路的放大系数。
实施时，所述分压电路包括第一分压电阻和第二分压电阻，所述分压调节信号包括电阻值调节信号；
所述调节电路根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/B步骤包括：
所述调节电路根据所述实时数据电压向所述第一分压电阻和/或所述第二分压电阻发送所述电阻值调节信号，以控制调节所述第一分压电阻的电阻值Rz1和/或所述第二分压电阻Rz2的电阻值，从而调节所述电压系数K；
Rz2/(Rz1+Rz2)等于b。
附图说明
图1A是本公开实施例所述的置位电压生成单元的结构图；
图1B是本公开另一实施例所述的置位电压生成电源的结构图；
图2A是具有补偿功能的像素电路的一具体实施例的电路图；
图2B是具有补偿功能的像素电路的该具体实施例在充电阶段的电流流 向示意图；
图2C是采用了本公开实施例所述的置位电压生成单元后的各电压的波形图；
图3是本公开另一实施例所述的置位电压生成单元的结构图；
图4是本公开所述的置位电压生成单元中的电压生成电路的一实施例的电路图；
图5是本公开所述的置位电压生成单元的一具体实施例的电路图；
图6是本公开实施例所述的置位电压生成方法的流程图；
图7是本公开所述的显示装置中的第m行第n列像素电路的一实施例的结构图；
图8是本公开所述的显示装置中的第m行第n列像素电路的一具体实施例的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在OLED显示设备工作过程中，受到外界因素(主要指温度)以及自身电路不稳定性的影响，伽马主电压AVDD会产生变化量V0，从而影响伽马电压的稳定性，造成数据驱动电路输出的实时数据电压Vdata随之产生变化量V01。而在相关技术中的具有补偿功能的像素电路中，置位电压V PRESL为一稳定电压值，在补偿检测的时候，该像素电路中的驱动晶体管的栅源电压为Vdata+V1-V PRESL，进而会造成补偿误差，从而导致补偿显示效果差。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为 基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1A所示，本公开实施例所述的置位电压生成单元包括电压生成电路11；
所述电压生成电路11用于根据伽马主电压AVDD生成置位电压V PRESL，以使得所述置位电压V PRESL的变化量V01与所述伽马主电压AVDD的变化量V0之间的比值为电压系数K，K为小于或等于1的正数。
本公开实施例所述的置位电压生成单元包括电压生成电路11，电压生成电路11根据伽马主电压AVDD生成置位电压V PRESL，以使得置位电压V PRESL的变化量与伽马主电压AVDD的变化量(也即波动值)呈正比例关系，也即所述置位电压V PRESL的变化量V01与所述伽马主电压AVDD的变化量V0之间的比值为电压系数K，从而使得置位电压V PRESL的变化量等于实时数据电压Vdata由于伽马主电压AVDD抖动而带来的变化量，可以消除由于伽马主电压AVDD波动造成的补偿误差，保证良好的补偿显示效果。
如图1B所示，在图1A所示的置位电压生成单元的实施例的基础上，所述置位电压生成单元还包括调节电路12；
所述调节电路12与所述电压生成电路11连接，用于根据实时数据电压调节电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数。
在本公开实施例中，所述调节电路12根据实时数据电压Vdata调节所述电压系数K为(a+1)/B。
在具体实施时，假设总灰阶数为256，也即B等于256，数据驱动电路总共输出256个灰阶电压，并所述实时数据电压Vdata对应的灰阶为a(a为0或小于256的正整数)时，K等于(a+1)/256。
在具体实施时，实时数据电压是根据伽马主电压AVDD得到的，实时数据电压的变化量与伽马主电压AVDD的变化量呈正比例关系，也即所述置位 电压V PRESL的变化量V01与所述伽马主电压AVDD的变化量V0之间的比值为电压系数K。
实际操作时，可以根据伽马主电压AVDD得到实时数据电压，例如，当AVDD为8V，并公共电极电压为0V时，并数据驱动电路输出256个灰阶电压(所述灰阶电压也即数据电压)时，则灰阶0对应的实时数据电压为0V，相应的电压系数K等于0；灰阶255对应的实时数据电压为8V，相应的电压系数K等于1；灰阶127对应的数据电压为4V，相应的电压系数K等于1/2；灰阶a对应的数据电压为(8×(a+1)/256)V，相应的电压系数K等于(a+1)/256。由上可知，数据电压的变化量与伽马主电压AVDD的变化量呈正比例关系。其中，a为0或小于256的正整数。
在具体实施时，如图2A所示，具有补偿功能的像素电路的一具体实施例包括驱动晶体管DT、数据写入晶体管T1、存储电容CS、补偿控制晶体管T2、写入控制开关SW和有机发光二极管OLED，其中，
DT的源极与有机发光二极管OLED的阳极连接，DT的漏极与电源电压端连接；所述电源电压端用于输入电源电压ELVDD；OLED的阴极接入低电压ELVSS；
T1的栅极与栅线Gate连接，T1的源极与数据线Data连接，T1的漏极与DT的栅极连接；
CS的第一端与DT的栅极连接，CS的第二端与DT的源极连接。
T2的栅极与补偿控制线Sc连接，T2的源极与DT的源极连接，T2的漏极与检测线SL连接；
SW的控制端与写入控制线连接，SW的第一端与置位电压写入端连接，SW的第二端与所述检测线SL连接；所述置位电压写入端用于写入所述置位电压V PRESL。
在图2A所示的像素电路的具体实施例中，DT、T1和T2为n型薄膜晶体管，但不以此为限。
如图2A所示的像素电路的具体实施例在工作时，
在置位阶段，T1和T2打开，SW控制导通置位电压写入端与检测线SL之间的连接，数据线Data上的实时数据电压Vdata写入DT的栅极，此时DT 的栅源电压Vgs＝Vdata-V PRESL；
在充电阶段，T1关闭，T2打开，SW控制断开置位电压写入端与检测线SL之间的连接，DT打开，流过DT的电流与Vgs相关；如图2B所示，电流通过打开的DT和T2向SL充电(SL上存在寄生电容)，经过预定充电时间t后，采样SL上的电压，不同的DT的迁移率不同，因此采样得到的电压可以反映DT的迁移率，根据采样得到的电压可以确定相应的数据电压补偿量。
如图2A所示的像素电路的具体实施例在工作时，在置位阶段，由于伽马主电压AVDD波动，Vdata产生波动，如若此时V PRESL为固定电压，则DT的Vgs随着Vdata波动而波动，从而使得相应的流过DT的电流受Vdata的波动影响，进而影响补偿的准确率；因此，如图2C所示，本公开实施例控制V PRESL随着Vdata波动而波动，也即使得V PRESL与Vdata具有相同的波动幅度，从而使得驱动晶体管DT的栅源电压Vgs与AVDD的波动无关，消除伽马主电压AVDD波动造成的补偿误差，可以有效减少由补偿误差产生的mura(mura是指显示器亮度不均匀,造成各种痕迹的现象)或噪点，保证良好的补偿显示效果。
在实际操作时，显示装置中的数据驱动电路根据伽马主电压AVDD和低电平VSS来得到实时数据电压Vdata，总灰阶数为B，也即所述数据驱动电路总共提供B个灰阶电压(所述灰阶电压也即数据电压)，对应于灰阶0的实时数据电压等于VSS，对应于灰阶B-1的实时数据电压等于AVDD，对应于灰阶a的实时数据电压等于VSS+((AVDD-VSS)×(a+1)/B)，则对应于灰阶a的实时数据电压的变化量V01与AVDD的变化量V0之间的比值为电压系数K，所述电压系数K等于(a+1)/B，因此AVDD波动，则Vdata相应产生波动。
在具体实施时，VSS可以为0V、公共电极电压或其他固定电平，但不以此为限。
具体的，所述电压生成电路可以包括运算放大电路和分压电路，其中，
所述分压电路用于对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
所述运算放大电路的反相输入端与参考电压端连接；所述运算放大电路 用于根据所述分压电压和所述参考电压端输入的参考电压生成所述置位电压。
在具体实施时，本公开实施例所述的置位电压生成单元还可以包括调节电路；
所述调节电路用于根据所述实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数，B为正整数，a为0或小于B的正整数。
在本公开实施例中，电压生成电路包括分压电路和运算放大电路，调节电路通过向分压电路提供分压调节信号，以相应调节分压电压，从而调节电压系数K。
在具体实施时，所述参考电压可以为固定电压，例如，可以为0V或低电压，但不以此为限。
如图3所示，在图1所示的置位电压生成单元的实施例的基础上，所述电压生成电路11包括运算放大电路Cmp和分压电路110，其中，
所述分压电路110用于对所述伽马主电压AVDD进行分压，得到分压电压Vf，并将该分压电压Vf输入至所述运算放大电路Cmp的正相输入端；
所述运算放大电路Cmp的反相输入端与用于输入参考电压Vref的参考电压端连接；所述运算放大电路Cmp用于根据所述分压电压Vf和所述参考电压端输入的参考电压Vref生成所述置位电压；
所述调节电路12用于所述实时数据电压Vdata和所述伽马主电压AVDD向所述分压电路110提供分压调节信号，以使得所述分压电路110相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K。
在本公开如图3所示的置位电压生成单元的实施例中，电压生成电路11限定包括分压电路110和运算放大电路Cmp，调节电路12通过向分压电路110提供分压调节信号，以相应控制分压电压Vf的变化量与所述伽马主电压的变化量V0之间的比值为b，从而调节电压系数K。
本公开如图3所示的置位电压生成单元的实施例在工作时，所述分压电 路110对AVDD进行分压，得到分压电压Vf，Vf＝V1+b×(AVDD-V1)，其中，b为分压系数，V1为第一电压，b为0或小于或等于1的正数；
并所述运算放大电路Cmp生成的置位电压等于A×(Vf-Vref)，分压电压Vf的变化量与AVDD的变化量之间的比值为b；
由上可知，K等于b×A，A为所述运算放大器的放大系数。
根据一种具体实施方式，所述分压电路可以包括第一分压电阻和第二分压电阻，其中，
所述第一分压电阻的第一端接入所述伽马主电压，所述第一分压电阻的第二端与所述运算放大电路的正相输入端连接；
所述第二分压电阻的第一端与所述正相输入端连接，所述第二分压电阻的第二端与第一电压端连接；
所述第一分压电阻的电阻值和所述第二分压电阻的电阻值能够被调节。
所述第一电压端用于输入所述第一电压V1；在具体实施时，所述第一电压端可以为地端，也可以为低电压端，但不以此为限。
如图4所示，所述分压电路110可以包括第一分压电阻R1和第二分压电阻R2，其中，
所述第一分压电阻R1的第一端接入所述伽马主电压AVDD，所述第一分压电阻R2的第二端与所述运算放大电路Cmp的正相输入端连接；
所述第二分压电阻R2的第一端与所述运算放大电路Cmp的正相输入端连接，所述第二分压电阻R2的第二端与地端GND连接；
所述第一分压电阻R1的电阻值Rz1和所述第二分压电阻R2的电阻值Rz2能够被调节，以能够调节分压电压Vf。
在图4所示的实施例中，V1等于0。
本公开如图4所示的置位电压生成单元的实施例在工作时，Vf等于AVDD×Rz2/(Rz1+Rz2)，调节Rz1和Rz2能够相应调节Vf，分压系数b等于Rz2/(Rz1+Rz2)，电压系数K等于b×A，A为所述运算放大电路Cmp的放大系数。
在具体实施时，所述分压调节信号可以包括电阻值调节信号；
所述调节电路12用于根据所述实时数据电压Vdata和所述伽马主电压 AVDD向所述第一分压电阻R1和/或所述第二分压电阻R2发送所述电阻值调节信号，以控制调节所述第一分压电阻R1的电阻值Rz1和/或所述第二分压电阻R2的电阻值Rz2，从而调节所述电压系数K；
Rz2/(Rz1+Rz2)等于b。
下面通过一具体实施例来说明本公开所述的置位电压生成单元。
如图5所示，本公开所述的置位电压生成单元的一具体实施例包括电压生成电路和调节电路12；
所述电压生成电路包括运算放大电路Cmp和分压电路110，所述分压电路110包括第一分压电阻R1和第二分压电阻R2；
所述运算放大电路Cmp的反相输入端与用于输入参考电压Vref的参考电压端连接；所述运算放大电路Cmp用于根据分压电压Vf和所述参考电压端输入的参考电压Vref生成置位电压V PRESL；
所述第一分压电阻R1的第一端接入所述伽马主电压AVDD，所述第一分压电阻R1的第二端与所述运算放大电路Cmp的正相输入端连接；
所述第二分压电阻R2的第一端与所述运算放大电路Cmp的正相输入端连接，所述第二分压电阻R2的第二端与地端GND连接；
所述分压调节信号包括电阻值调节信号；
所述调节电路12用于根据实时数据电压Vdata和所述伽马主电压AVDD向所述第一分压电阻R1和/或所述第二分压电阻R2发送所述电阻值调节信号，以控制调节所述第一分压电阻R1的电阻值Rz1和/或所述第二分压电阻R2的电阻值Rz2，从而调节所述分压电压Vf。
本公开所述的置位电压生成单元的该具体实施例在工作时，V PRESL＝A×(Vf-Vref)，Vf等于AVDD×Rz2/(Rz1+Rz2),其中A为放大系数，A为正数；则V PRESL的变化量等于AVDD的变化量的A×Rz2/(Rz1+Rz2)倍，也即，电压系数K等于A×Rz2/(Rz1+Rz2)。
本公开所述的置位电压生成单元的该具体实施例在工作时，当数据驱动电路输出256个灰阶电压(所述灰阶电压也即数据电压)时，并实时数据电压Vdata对应灰阶127时，所述调节电路12控制调节Rz1和/或Rz2，以使得A×Rz2/(Rz1+Rz2)＝1/2，此时电压系数K(也即所述置位电压Vf的变化量V01 与所述伽马主电压AVDD的变化量V0之间的比值)等于1/2；
当数据驱动电路输出256个灰阶电压(所述灰阶电压也即数据电压)时，并实时数据电压Vdata对应灰阶63时，所述调节电路12控制调节Rz1和/或Rz2，以使得A×Rz2/(Rz1+Rz2)＝1/4，此时电压系数K(也即所述置位电压Vf的变化量V01与所述伽马主电压AVDD的变化量V0之间的比值)等于1/4；
当数据驱动电路输出256个灰阶电压(所述灰阶电压也即数据电压)时，并实时数据电压Vdata对应灰阶20时，所述调节电路12控制调节Rz1和/或Rz2，以使得A×Rz2/(Rz1+Rz2)＝21/256，此时电压系数K(也即所述置位电压Vf的变化量V01与所述伽马主电压AVDD的变化量V0之间的比值)等于21/256。
本公开实施例所述的置位电压生成方法应用于上述的置位电压生成单元，所述置位电压生成方法包括：
电压生成电路根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数。
本公开实施例所述的置位电压生成方法采用电压生成电路根据伽马主电压生成置位电压，以使得置位电压的变化量与伽马主电压的变化量(也即波动值)呈正比例关系，也即所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，从而使得置位电压的变化量等于实时数据电压由于伽马主电压抖动而带来的变化量，可以消除由于伽马主电压AVDD波动造成的补偿误差，保证良好的补偿显示效果。
具体的，所述置位电压生成单元还可以包括调节电路；
如图6所示，本公开实施例所述的置位电压生成方法应用于上述的置位电压生成单元，所述置位电压生成方法包括：
S1：电压生成电路根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数；
S2：调节电路根据实时数据电压调节所述电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数，B为正整数，a为0或小于B的正整数。
在具体实施时，所述置位电压生成单元还可以包括调节电路，调节电路调节K等于(a+1)/B，以使得置位电压的变化量等于实时数据电压由于伽马主电压抖动而带来的变化量。
具体的，所述电压生成电路可以包括运算放大电路和分压电路；所述电压生成电路根据伽马主电压生成置位电压步骤可以包括：
分压电路对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
所述运算放大电路根据所述分压电压和参考电压端输入的参考电压生成所述置位电压。
具体的，所述置位电压生成单元还可以包括调节电路；所述置位电压生成方法还可以包括：
所述调节电路根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/B；
所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数；
b为分压系数，b等于K/A，A为所述运算放大电路的放大系数。
在具体实施时，所述置位电压生成单元还包括调节电路，所述调节电路向分压电路提供分压调节信号，以控制调节所述分压电路的分压系数b，从而将电压系数K调节为(a+1)/B。
在具体实施时，所述分压电路可以包括第一分压电阻和第二分压电阻，所述分压调节信号可以包括电阻值调节信号；
所述调节电路根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/B步骤可以包括：
所述调节电路根据所述实时数据电压向所述第一分压电阻和/或所述第 二分压电阻发送所述电阻值调节信号，以控制调节所述第一分压电阻的电阻值Rz1和/或所述第二分压电阻Rz2的电阻值，从而调节所述电压系数K；
Rz2/(Rz1+Rz2)等于b。
本公开实施例所述的显示装置包括M行N列像素电路和N个上述的置位电压生成单元；
第n个所述置位电压生成单元与位于第n列的像素电路连接，用于为位于第n列的像素电路提供置位电压；
M和N都为大于1的整数，n为小于或等于N的正整数。
在本公开实施例所述的显示装置中，位于同一列的像素电路都与一个置位电压生成单元连接，各行栅线和各行写入控制线逐行打开，以将相应列数据线上的实时数据电压分时写入不同行像素电路，并控制相应列检测线分时接入不同行相应列置位电压。
具体的，本公开实施例所述的显示装置还可以包括显示基板和驱动集成电路；所述像素电路设置于所述显示基板的显示区域；
所述置位电压生成单元设置于所述显示基板的周边区域，或者，所述置位电压生成单元设置于所述驱动集成电路中。
在本公开实施例所述的显示装置中，置位生成单元可以设置于显示基板的周边区域，也可以设置于驱动IC(Integrated Circuit，集成电路)中，并一列像素电路共用一个置位电压生成单元。
在具体实施时，本公开所述的显示装置还可以包括N列检测线、M行栅线、N列数据线、M行补偿控制线和M行写入控制线；所述栅线用于输出栅极驱动信号，所述数据线用于输出实时数据电压，所述补偿控制线用于输入补偿控制信号，所述写入控制线用于输入写入控制信号；
第m行第n列像素电路包括第m行第n列发光元件、第m行第n列驱动电路、第m行第n列显示控制电路、第m行第n列补偿控制电路和第m行第n列置位电压写入控制电路，其中，
所述第m行第n列驱动电路用于在其控制端的控制下驱动所述第m行第n列发光元件；
所述第m行第n列显示控制电路与第m行第n列所述驱动电路的控制端 连接，用于在第m行栅线输出的栅极驱动信号的控制下，根据第n列数据线上的实时数据电压对所述第m行第n列驱动电路进行显示驱动控制；
所述第m行第n列补偿控制电路用于在第m行补偿控制线输入的补偿控制信号的控制下，控制所述第m行第n列驱动电路的第一端与第n列检测线之间连通；
所述第m行第n列置位电压写入控制电路用于在第m行写入控制线输入的写入控制信号的控制下，控制第m行第n列置位电压写入端与所述第n列检测线之间连通；
所述第n个置位电压生成单元用于向所述第m行第n列置位电压写入端写入第m行第n列置位电压，以在所述第m行第n列置位电压写入控制电路控制第m行第n列置位电压写入端与所述第n列检测线之间连通时，控制将所述第m行第n列置位电压写入所述第n列检测线；
m为小于或等于M的正整数。
具体的，所述第m行第n列发光元件可以为有机发光二极管，但不以此为限。
如图7所示，第m行第n列像素电路的一实施例可以包括第m行第n列发光元件ELmn、第m行第n列驱动电路71mn、第m行第n列显示控制电路72mn、第m行第n列补偿控制电路73mn和第m行第n列置位电压写入控制电路74mn，其中，
所述第m行第n列驱动电路71mn的第一端与所述第m行第n列发光元件ELmn的第一极连接，所述第m行第n列驱动电路71mn的第二端与用于输入电源电压ELVDD的电源电压端连接，所述第m行第n列驱动电路71mn用于在其控制端的控制下驱动所述第m行第n列发光元件ELmn；所述第n列发光元件ELmn的第二端接入低电压ELVSS；
所述第m行第n列显示控制电路72mn的控制端与第m行栅线Gatem连接，所述第m行第n列显示控制电路72mn的第一端与第n列数据线Datan连接，所述第m行第n列显示控制电路72mn的第二端与所述第m行第n列驱动电路71mn的控制端连接，所述第m行第n列显示控制电路72mn用于在第m行栅线Gatem输出的栅极驱动信号的控制下，根据第n列数据线Datan 上的实时数据电压Vdatamn对所述第m行第n列驱动电路71mn进行显示驱动控制；
所述第m行第n列补偿控制电路73mn的控制端与第m行补偿控制线Scm连接，所述第m行第n列补偿控制电路73mn的第一端与所述第m行第n列驱动电路71mn的第一端连接，所述第m行第n列补偿控制电路73mn的第二端与第n列检测线SLn连接，所述第m行第n列补偿控制电路73mn用于在第m行补偿控制线Scm输入的补偿控制信号的控制下，控制所述第m行第n列驱动电路71mn的第一端与第n列检测线SLn之间连通；
所述第m行第n列置位电压写入控制电路74mn的控制端与第m行写入控制线Lwm连接，所述第m行第n列置位电压写入控制电路74mn的第一端与第m行第n列置位电压写入端连接，所述第m行第n列置位电压写入控制电路74mn的第二端与所述第n列检测线SLn连接，所述第m行第n列置位电压写入控制电路74mn用于在第m行写入控制线Lwm输入的写入控制信号的控制下，控制第m行第n列置位电压写入端与所述第n列检测线SLn之间连通，以使得第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn至第n列检测线SLn；
本公开实施例所述的显示装置包括的第n个置位电压生成单元用于向所述第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn；
m为小于或等于M的正整数。
如图7所示的第m行第n列像素电路的实施例在工作时，
在第m行第n列置位阶段，所述第n个置位电压生成单元向所述第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn；在第m行栅线Gatem输出的栅极驱动信号的控制下，所述第m行第n列显示控制电路72mn将第n列数据线Datan上的实时数据电压Vdatamn写入所述第m行第n列驱动电路71mn的控制端，所述第m行第n列补偿控制电路73mn在第m行补偿控制线Scm输入的补偿控制信号的控制下，控制所述第m行第n列驱动电路71mn的第一端与第n列检测线SLn之间连通；所述第m行第n列置位电压写入控制电路74mn在第m行写入控制线Lwm输入的写入控制信号的控制下，控制第m行第n列置位电压写入端与所述第n列检测线SLn之间连 通，以使得第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn至第n列检测线SLn，进而将V PRESL-mn写入所述第m行第n列驱动电路71mn的第一端；此时，所述第m行第n列驱动电路71mn的控制端的电压为Vdatamn，所述第m行第n列驱动电路71mn的第一端的电压为V PRESL-mn；
在第m行第n列充电阶段，在第m行栅线Gatem输出的栅极驱动信号的控制下，所述第m行第n列显示控制电路72mn断开第n列数据线Datan与所述第m行第n列驱动电路71mn的控制端之间的连接；所述第m行第n列置位电压写入控制电路74mn在第m行写入控制线Lwm输入的写入控制信号的控制下，控制断开第m行第n列置位电压写入端与所述第n列检测线SLn之间的连接；所述第m行第n列补偿控制电路73mn在第m行补偿控制线Scm输入的补偿控制信号的控制下，控制所述第m行第n列驱动电路71mn的第一端与第n列检测线SLn之间连通；所述第m行第n列驱动电路71mn控制导通所述电源电压端与所述第m行第n列补偿控制电路73mn的第一端之间的连接，电流通过所述第m行第n列驱动电路71mn和第m行第n列补偿控制电路73mn向所述第n列检测线SLn(SLn上存在寄生电容)充电，经过预定充电时间t后，对SLn上的电压进行采样，并根据采样得到的电压对数据电压进行补偿。
如图7所示的第m行第n列像素电路的实施例在工作时，在第m行第n列置位阶段，所述第n个置位电压生成单元向所述第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn，以使得V PRESL-mn的变化量等于Vdatanm由于伽马主电压AVDD抖动而带来的变化量，从而提升补偿精度。
具体的，所述第m行第n列补偿控制电路可以包括第m行第n列补偿控制晶体管，所述第m行第n列置位电压写入控制电路可以包括第m行第n列写入控制开关；
所述第m行第n列补偿控制晶体管的控制极与所述第m行补偿控制线连接，所述第m行第n列补偿控制晶体管的第一极与所述第m行第n列驱动电路的第一端连接，所述第m行第n列补偿控制晶体管的第二极与所述第n列检测线连接；
所述第m行第n列写入控制开关的控制端与第m行写入控制线连接，所述第m行第n列写入控制开关的第一端与所述第m行第n列置位电压写入端连接，所述第m行第n列写入控制开关的第二端与所述第n列检测线连接。
具体的，所述第m行第n列驱动电路可以包括第m行第n列驱动晶体管；所述第m行第n列显示控制电路包括第m行第n列数据写入晶体管和第m行第n列存储电容；
所述第m行第n列驱动晶体管的栅极为所述第m行第n列驱动电路的控制端；
所述第m行第n列数据写入晶体管的控制极与所述第m行栅线连接，所述第m行第n列数据写入晶体管的第一极与所述第n列数据线连接，所述第m行第n列数据写入晶体管的第二极与所述第m行第n列驱动晶体管的栅极连接；
所述第m行第n列驱动晶体管的第一极与所述第m行第n列发光元件连接，所述第m行第n列驱动晶体管的第二极与电源电压端连接；
所述第m行第n列存储电容的第一端与所述第m行第n列驱动晶体管的栅极连接，所述第m行第n列存储电容的第二端与所述第m行第n列驱动晶体管的第一极连接。
下面通过一具体实施例来说明本公开所述的显示装置包括的第m行第n列像素电路。
如图8所示，第m行第n列像素电路的一具体实施例包括第m行第n列有机发光二极管OLEDmn、第m行第n列驱动电路71mn、第m行第n列显示控制电路72mn、第m行第n列补偿控制电路73mn和第m行第n列置位电压写入控制电路74mn，其中，
所述第m行第n列补偿控制电路73mn包括第m行第n列补偿控制晶体管T2mn，所述第m行第n列置位电压写入控制电路74mn包括第m行第n列写入控制开关SWmn；所述第m行第n列驱动电路71mn包括第m行第n列驱动晶体管DTmn；所述第m行第n列显示控制电路72mn包括第m行第n列数据写入晶体管T1mn和第m行第n列存储电容Csmn；
所述第m行第n列补偿控制晶体管T2mn的栅极与所述第m行补偿控制 线Scm连接，所述第m行第n列补偿控制晶体管T2mn的源极与所述第m行第n列驱动晶体管的源极连接，所述第m行第n列补偿控制晶体管T2mn的漏极与所述第n列检测线SLn连接；
所述第m行第n列写入控制开关SWmn的控制端与第m行写入控制线连接，所述第m行第n列写入控制开关SWmn的第一端与所述第m行第n列置位电压写入端连接，所述第m行第n列写入控制开关SWmn的第二端与所述第n列检测线SLn连接。
所述第m行第n列驱动晶体管DTmn的栅极为所述第m行第n列驱动电路的控制端；
所述第m行第n列数据写入晶体管T1mn的栅极与第m行栅线Gatem连接，所述第m行第n列数据写入晶体管T1mn的源极与第n列数据线Datan连接，所述第m行第n列数据写入晶体管T1mn的漏极与所述第m行第n列驱动晶体管DTmn的栅极连接；
所述第m行第n列驱动晶体管DTmn的源极与所述第m行第n列有机发光二极管OLEDmn的阳极连接，所述第m行第n列驱动晶体管DTmn的漏极与用于输入电源电压ELVDD的电源电压端连接；所述第m行第n列有机发光二极管OLEDmn的阴极接入低电压ELVSS；
所述第m行第n列存储电容Csmn的第一端与所述第m行第n列驱动晶体管DTmn的栅极连接，所述第m行第n列存储电容Csmn的第二端与所述第m行第n列驱动晶体管DTmn的源极连接；
本公开实施例所述的显示装置包括的第n个置位电压生成单元用于向所述第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn。
图8所示的第m行第n列像素电路的具体实施例中，所有的晶体管均为n型薄膜晶体管，但不以此为限。
图8所示的第m行第n列像素电路的具体实施例在工作时，
在第m行第n列置位阶段，所述第n个置位电压生成单元向所述第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn；在第m行栅线Gatem输出的栅极驱动信号的控制下，所述第m行第n列数据写入晶体管T1mn打开，以将第n列数据线Datan上的实时数据电压Vdatamn写入所述第 m行第n列驱动晶体管DTmn的栅极；在第m行补偿控制线Scm输入的补偿控制信号的控制下，所述第m行第n列补偿控制晶体管T2mn打开，控制所述第m行第n列驱动晶体管DTmn的源极与第n列检测线SLn之间连通；在第m行写入控制线输入的写入控制信号的控制下，所述第m行第n列写入控制开关SWmn打开，以控制第m行第n列置位电压写入端与所述第n列检测线SLn之间连通，以使得第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn至第n列检测线SLn，进而将V PRESL-mn写入所述第m行第n列驱动晶体管DTmn的源极；此时，所述第m行第n列驱动晶体管DTmn的栅极的电压为Vdatamn，所述第m行第n列驱动晶体管DTmn的源极的电压为V PRESL-mn，所述第m行第n列驱动晶体管DTmn的栅源电压Vgs为Vdatamn-V PRESL-mn；
在第m行第n列充电阶段，在第m行栅线Gatem输出的栅极驱动信号的控制下，所述第m行第n列数据写入晶体管T1mn关闭，以断开第n列数据线Datan与所述第m行第n列驱动晶体管DTmn的栅极之间的连接；在第m行写入控制线输入的写入控制信号的控制下，所述第m行第n列写入控制开关SWmn控制断开第m行第n列置位电压写入端与所述第n列检测线SLn之间的连接；在第m行补偿控制线Scm输入的补偿控制信号的控制下，所述第m行第n列补偿控制晶体管T2mn打开，以控制所述第m行第n列驱动晶体管DTmn的源极与第n列检测线SLn之间连通；所述第m行第n列驱动晶体管DTmn打开，以控制导通所述电源电压端与所述第m行第n列补偿控制晶体管T2mn的源极之间的连接，电流通过所述第m行第n列驱动晶体管DTmn和第m行第n列补偿控制晶体管T2mn向所述第n列检测线SLn(SLn上存在寄生电容)充电，经过预定充电时间t后，对SLn上的电压进行采样，并根据采样得到的电压对数据电压进行补偿。
如图8所示的第m行第n列像素电路的具体实施例在工作时，在第m行第n列置位阶段，所述第n个置位电压生成单元向所述第m行第n列置位电压写入端写入第m行第n列置位电压V PRESL-mn，以使得V PRESL-mn的变化量等于Vdatanm由于伽马主电压AVDD抖动而带来的变化量，从而提升补偿精度。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种显示装置，包括M行N列像素电路和N个置位电压生成单元；
    所述置位电压生成单元包括电压生成电路；所述电压生成电路用于根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数；
    第n个所述置位电压生成单元的输出端口与位于第n列的像素电路连接，用于为位于第n列的像素电路提供置位电压；
    M和N都为大于1的整数，n为小于或等于N的正整数。
  2. 如权利要求1所述的显示装置，还包括显示基板；
    所述像素电路设置于所述显示基板的显示区域；
    所述置位电压生成单元设置于所述显示基板的周边区域。
  3. 如权利要求1所述的显示装置，还包括显示基板和驱动集成电路；
    所述像素电路设置于所述显示基板的显示区域；
    所述置位电压生成单元设置于所述驱动集成电路中。
  4. 如权利要求1至3中任一项所述的显示装置，还包括N列检测线、M行栅线、N列数据线、M行补偿控制线和M行写入控制线；所述栅线用于输出栅极驱动信号，所述数据线用于输出实时数据电压，所述补偿控制线用于输入补偿控制信号，所述写入控制线用于输入写入控制信号；
    第m行第n列像素电路包括第m行第n列发光元件、第m行第n列驱动电路、第m行第n列显示控制电路、第m行第n列补偿控制电路和第m行第n列置位电压写入控制电路，其中，
    所述第m行第n列驱动电路用于在其控制端的控制下驱动所述第m行第n列发光元件；
    所述第m行第n列显示控制电路与第m行第n列所述驱动电路的控制端连接，用于在第m行栅线输出的栅极驱动信号的控制下，根据第n列数据线上的实时数据电压对所述第m行第n列驱动电路进行显示驱动控制；
    所述第m行第n列补偿控制电路用于在第m行补偿控制线输入的补偿控制信号的控制下，控制所述第m行第n列驱动电路的第一端与第n列检测线 之间连通；
    所述第m行第n列置位电压写入控制电路用于在第m行写入控制线输入的写入控制信号的控制下，控制第m行第n列置位电压写入端与所述第n列检测线之间连通；
    所述第n个置位电压生成电路用于向所述第m行第n列置位电压写入端写入第m行第n列置位电压，以在所述第m行第n列置位电压写入控制电路控制第m行第n列置位电压写入端与所述第n列检测线之间连通时，控制将所述第m行第n列置位电压写入所述第n列检测线；
    m为小于或等于M的正整数。
  5. 如权利要求4所述的显示装置，其中，所述第m行第n列补偿控制电路包括第m行第n列补偿控制晶体管，所述第m行第n列置位电压写入控制电路包括第m行第n列写入控制开关；
    所述第m行第n列补偿控制晶体管的控制极与所述第m行补偿控制线连接，所述第m行第n列补偿控制晶体管的第一极与所述第m行第n列驱动电路的第一端连接，所述第m行第n列补偿控制晶体管的第二极与所述第n列检测线连接；
    所述第m行第n列写入控制开关的控制端与第m行写入控制线连接，所述第m行第n列写入控制开关的第一端与所述第m行第n列置位电压写入端连接，所述第m行第n列写入控制开关的第二端与所述第n列检测线连接。
  6. 如权利要求4所述的显示装置，其中，所述第m行第n列驱动电路包括第m行第n列驱动晶体管；所述第m行第n列显示控制电路包括第m行第n列数据写入晶体管和第m行第n列存储电容；
    所述第m行第n列驱动晶体管的栅极为所述第m行第n列驱动电路的控制端；
    所述第m行第n列数据写入晶体管的控制极与所述第m行栅线连接，所述第m行第n列数据写入晶体管的第一极与所述第n列数据线连接，所述第m行第n列数据写入晶体管的第二极与所述第m行第n列驱动晶体管的栅极连接；
    所述第m行第n列驱动晶体管的第一极与所述第m行第n列发光元件连 接，所述第m行第n列驱动晶体管的第二极与电源电压端连接；
    所述第m行第n列存储电容的第一端与所述第m行第n列驱动晶体管的栅极连接，所述第m行第n列存储电容的第二端与所述第m行第n列驱动晶体管的第一极连接。
  7. 如权利要求1所述的显示装置，其中，所述置位电压生成单元还包括调节电路；
    所述调节电路用于根据实时数据电压调节所述电压系数K为(a+1)/B；
    所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数。
  8. 如权利要求1所述的显示装置，其中，所述电压生成电路包括运算放大电路和分压电路；
    所述分压电路用于对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
    所述运算放大电路的反相输入端与参考电压端连接；所述运算放大电路用于根据所述分压电压和所述参考电压端输入的参考电压生成所述置位电压。
  9. 如权利要求8所述的显示装置，其中，所述的置位电压生成单元还包括调节电路；
    所述调节电路用于根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/M；
    所述实时数据电压对应的灰阶为a，M为总灰阶数；a为0或小于M的正整数，M为正整数；
    b为分压系数，b等于K/A，A为所述运算放大电路的放大系数。
  10. 如权利要求9所述的显示装置，其中，所述分压电路包括第一分压电阻和第二分压电阻；
    所述第一分压电阻的第一端接入所述伽马主电压，所述第一分压电阻的第二端与所述运算放大电路的正相输入端连接；
    所述第二分压电阻的第一端与所述正相输入端连接，所述第二分压电阻的第二端与第一电压端连接；
    所述第一分压电阻的电阻值和所述第二分压电阻的电阻值能够被调节。
  11. 如权利要求10所述的显示装置，其中，所述分压调节信号包括电阻值调节信号；
    所述调节电路用于根据所述实时数据电压和所述伽马主电压向所述第一分压电阻和/或所述第二分压电阻发送所述电阻值调节信号，以控制调节所述第一分压电阻的电阻值Rz1和/或所述第二分压电阻的电阻值Rz2，从而调节所述电压系数K；
    Rz2/(Rz1+Rz2)等于b。
  12. 一种置位电压生成单元，包括电压生成电路；
    所述电压生成电路得输出端口与像素电路连接；所述电压生成电路用于根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数。
  13. 如权利要求12所述的置位电压生成单元，还包括调节电路；
    所述调节电路用于根据实时数据电压调节所述电压系数K为(a+1)/B；
    所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数。
  14. 如权利要求12所述的置位电压生成单元，其中，所述电压生成电路包括运算放大电路和分压电路，其中，
    所述分压电路用于对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
    所述运算放大电路的反相输入端与参考电压端连接；所述运算放大电路用于根据所述分压电压和所述参考电压端输入的参考电压生成所述置位电压。
  15. 如权利要求14所述的置位电压生成单元，还包括调节电路；
    所述调节电路用于根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/M；
    所述实时数据电压对应的灰阶为a，M为总灰阶数；a为0或小于M的正整数，M为正整数；
    b为分压系数，b等于K/A，A为所述运算放大电路的放大系数。
  16. 如权利要求15所述的置位电压生成单元，其中，所述分压电路包括第一分压电阻和第二分压电阻，其中，
    所述第一分压电阻的第一端接入所述伽马主电压，所述第一分压电阻的第二端与所述运算放大电路的正相输入端连接；
    所述第二分压电阻的第一端与所述正相输入端连接，所述第二分压电阻的第二端与第一电压端连接；
    所述第一分压电阻的电阻值和所述第二分压电阻的电阻值能够被调节。
  17. 如权利要求16所述的置位电压生成单元，其中，所述分压调节信号包括电阻值调节信号；
    所述调节电路用于根据所述实时数据电压和所述伽马主电压向所述第一分压电阻和/或所述第二分压电阻发送所述电阻值调节信号，以控制调节所述第一分压电阻的电阻值Rz1和/或所述第二分压电阻的电阻值Rz2，从而调节所述电压系数K；
    Rz2/(Rz1+Rz2)等于b。
  18. 一种置位电压生成方法，应用于如权利要求11至17中任一权利要求所述的置位电压生成单元，所述置位电压生成方法包括：
    电压生成电路根据伽马主电压生成置位电压，以使得所述置位电压的变化量V01与所述伽马主电压的变化量V0之间的比值为电压系数K，K为小于或等于1的正数。
  19. 如权利要求18所述的置位电压生成方法，其中，所述置位电压生成单元还包括调节电路；所述置位电压生成方法还包括：
    调节电路根据实时数据电压调节所述电压系数K为(a+1)/B；
    所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数。
  20. 如权利要求18所述的置位电压生成方法，其中，所述电压生成电路包括运算放大电路和分压电路；所述电压生成电路根据伽马主电压生成置位电压步骤包括：
    分压电路对所述伽马主电压进行分压，得到分压电压，并将该分压电压输入至所述运算放大电路的正相输入端；
    所述运算放大电路根据所述分压电压和参考电压端输入的参考电压生成所述置位电压。
  21. 如权利要求20所述的置位电压生成方法，其中，所述置位电压生成单元还包括调节电路；所述置位电压生成方法还包括：
    所述调节电路根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/B；
    所述实时数据电压对应的灰阶为a，B为总灰阶数；a为0或小于B的正整数，B为正整数；
    b为分压系数，b等于K/A，A为所述运算放大电路的放大系数。
  22. 如权利要求21所述的置位电压生成方法，其中，所述分压电路包括第一分压电阻和第二分压电阻，所述分压调节信号包括电阻值调节信号；
    所述调节电路根据实时数据电压向所述分压电路提供分压调节信号，以使得所述分压电路相应控制所述分压电压的变化量与所述伽马主电压的变化量V0之间的比值为b，从而相应调节所述电压系数K为(a+1)/B步骤包括：
    所述调节电路根据所述实时数据电压向所述第一分压电阻和/或所述第二分压电阻发送所述电阻值调节信号，以控制调节所述第一分压电阻的电阻值Rz1和/或所述第二分压电阻Rz2的电阻值，从而调节所述电压系数K；
    Rz2/(Rz1+Rz2)等于b。
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