WO2020151227A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2020151227A1
WO2020151227A1 PCT/CN2019/103415 CN2019103415W WO2020151227A1 WO 2020151227 A1 WO2020151227 A1 WO 2020151227A1 CN 2019103415 W CN2019103415 W CN 2019103415W WO 2020151227 A1 WO2020151227 A1 WO 2020151227A1
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Prior art keywords
compensation
signal
falling edge
lines
data line
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PCT/CN2019/103415
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English (en)
French (fr)
Inventor
文超平
黄威
徐竹青
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南京中电熊猫平板显示科技有限公司
南京中电熊猫液晶显示科技有限公司
南京华东电子信息科技股份有限公司
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Publication of WO2020151227A1 publication Critical patent/WO2020151227A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the invention belongs to the field of display technology, and specifically relates to a display device.
  • Demultiplexing circuit (Demux technology) is widely used in display devices. It can convert the data voltage output by the data drive circuit (Source IC) to 1:m (such as 1:2, 1:3, etc., m is an integer greater than 1. , Call 1:m as Mux ratio) in the form of time-sharing transmission to the corresponding m second data lines, the number of first data lines connected to the data driving circuit can be reduced by at least half relative to the number of second data lines connected to the pixel unit. It can reduce the number of ICs, thereby reducing the cost of panel design and saving layout space, reducing the lower frame of the panel, and making the panel meet the requirements of a narrower frame.
  • TFTs thin film transistors
  • oxide semiconductors such as indium gallium zinc oxide, IGZO for short
  • Cgd parasitic capacitance between the gate and drain
  • a scheme of a demultiplexing circuit and its corresponding compensation circuit is shown in Figure 3.
  • the compensation circuit has the same number of compensation lines as the switch control lines, and the compensation lines correspond to the corresponding second data.
  • the overlapping lines form a compensation capacitor.
  • the Mux ratio of the above-mentioned demultiplexing circuit for compensation is 1:m, m compensation lines and m compensation signals are required, which will occupy a large panel space and the overall power consumption of the circuit is large.
  • an embodiment of the present invention provides a display device, which includes:
  • a display panel a data driving circuit connected to n first data lines, a demultiplexing circuit and a compensation circuit; the display panel includes n second data line groups corresponding to the n first data lines, each The second data line group includes m second data lines, where n and m are integers greater than 1;
  • the demultiplexing circuit includes n switch groups corresponding to the n first data lines and the n second data line groups, and the switch group includes m strobe switches, and the control of the m strobe switches The first path ends of the m strobe switches are connected to the corresponding first data line, and the second path ends of the m strobe switches are connected to the corresponding second data line group.
  • the compensation circuit includes a compensation drive circuit and m-1 compensation lines connected to the compensation drive circuit.
  • the compensation drive circuit generates m-1 compensation signals and inputs them to the m-1 compensation lines respectively.
  • Each of the compensation lines forms a compensation capacitor at an overlapping position with m-1 second data lines except the last second data line in each second data line group;
  • the switching signals other than the last switch signal are compensated signals
  • m-1 of the compensation signals correspond to m-1 compensated signals, respectively, in a high-level phase of the scan signal of the display panel
  • any compensation signal has a rising edge.
  • the rising edge of each compensation signal is not earlier than the falling edge of the corresponding compensated signal, and the rising edge of each compensation signal is not later than the falling edge of the high-level phase.
  • the rising edge of the compensation signal and the corresponding falling edge of the compensated signal occur simultaneously.
  • the falling edge of the last switch signal is later than the falling edge of the high level phase in the period of the scan signal, and the falling edges of the m-1 compensation signals are all set at the high level In the low-level phase after the phase.
  • the falling edge of each compensation signal is no earlier than the falling edge of the last switch signal in the period of the scan signal, and the falling edge of each compensation signal is no later than the next period of the scan signal The corresponding falling edge of the compensated signal.
  • the falling edge of the compensation signal and the falling edge of the last switch signal occur simultaneously.
  • the falling edge of the last switch signal is no later than the falling edge of the high-level phase in the period of the scan signal, m-1 falling edges of the compensation signal and the falling edge of the last switch signal The edges occur simultaneously.
  • the compensation voltage difference generated by the pixel voltage of the display panel caused by the m-1 compensation signals is consistent with the gate feedthrough voltage caused by the closing of the last gate switch, and the compensation voltage difference The sum gate feedthrough voltage is compensated by adjusting the common voltage of the display panel.
  • the embodiment of the present invention can compensate the demultiplexing circuit with a Mux ratio of 1:m only by adding m-1 compensation lines, and can solve the color shift caused by the gate parasitic capacitance in the display device. Flicker, horizontal and vertical stripes and other display problems, and save circuit space, reduce the additional power consumption caused by compensation.
  • Figure 1 is a schematic diagram of the parasitic capacitance between the gate and the drain in the thin film transistor structure
  • FIG. 2 is a schematic diagram of the structure of a demultiplexing circuit in the prior art
  • FIG. 3 is a schematic diagram of a structure of a demultiplexing circuit and compensation circuit in the prior art
  • FIG. 4 is a schematic structural diagram of a display device according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram of a partial structure of a display device according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of first waveforms of various signals in a display device according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a second waveform of various signals in a display device according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a third waveform of various signals in a display device according to an embodiment of the present invention.
  • FIG. 9 is a fourth waveform diagram of various signals in a display device according to an embodiment of the invention.
  • the display device of the embodiment of the present invention includes a display panel, a data driving circuit outputting n first data lines, a demultiplexing circuit, and a compensation circuit.
  • the display panel includes a plurality of scan lines and a plurality of second data lines criss-crossed, and a plurality of pixel units defined by the intersection of the scan lines and the second data lines.
  • Each scan line outputs a scan signal to the pixel unit, and the scan signal has a periodic high-level phase and a low-level phase.
  • the data driving circuit respectively outputs the data voltage to the demultiplexing circuit through the n first data lines, and the demultiplexing circuit time-divisionally inputs the data voltage output by one first data line to the display panel corresponding to the first data line M second data lines in the second data line group.
  • the pixel unit includes a thin film transistor and a pixel electrode connected to the thin film transistor.
  • the thin film transistor When the scan signal input to the pixel unit is at a high level, the thin film transistor is turned on, and the corresponding second data line inputs the data signal to the pixel electrode.
  • the display device also includes a common electrode and a liquid crystal layer.
  • the potential of the pixel electrode is called the pixel voltage Vp and the potential of the common electrode is called the common voltage Vcom.
  • the voltage difference between the pixel voltage Vp and the common voltage Vcom in the pixel unit controls the rotation of the liquid crystal layer, and then Control the display of the pixel unit.
  • the demultiplexing circuit includes a switch drive circuit, m switch control lines connected to the switch drive circuit, and n switch groups corresponding to the n first data lines.
  • Each switch group includes m gate switches, the gate switches may be n-type or p-type thin film transistors, and each thin film transistor includes a control terminal, a first channel terminal, and a second channel terminal.
  • the control terminal is the gate
  • one of the channel terminals is the source
  • the other channel terminal is the drain.
  • the m strobe switches in each switch group correspond to m switch control lines and m second data lines; the control terminals of m strobe switches in the same switch group are respectively connected to their corresponding switches Control line, the first path ends of m strobe switches in the same switch group are connected to a first data line, and the second path ends of m strobe switches in the same switch group are respectively connected to the display M second data lines in the second data line group corresponding to the first data lines in the panel.
  • the switch drive circuit generates m switch signals and inputs them to m switch control lines.
  • the m switch signals sequentially generate a rising edge (from low level to high level) during a high level phase of the scanning signal, and the preceding After or at the same time that a switch signal generates a falling edge (falls from a high level to a low level), the latter switch signal generates a rising edge. That is, the m switch control lines respectively control the m gate switches in each switch group to be sequentially turned on during a high-level phase of the scanning signal, and only one gate switch in the switch group is in the open state at the same time.
  • the m strobe switches in the same switch group are turned off sequentially within one cycle of the scan signal.
  • the last strobe switch that is turned on and the last closed is the last strobe switch, and the remaining switches are non-last strobe switches.
  • the switch signal of the last gate switch is the last switch signal, and the second data line connected to the second path end of the last gate switch is the last second data line.
  • the falling edge of the last switch signal may be earlier or later than the falling edge of the high-level phase of the scan signal, and the falling edge of the last switch signal may also coincide with the high-level phase of the scan signal. The falling edges occur simultaneously.
  • the compensation circuit includes a compensation drive circuit and multiple compensation lines connected to the compensation drive circuit.
  • the compensation drive circuit generates m-1 compensation signals and inputs them to m-1 compensation lines, respectively, and m-1 compensation lines are connected to m-1 lines in each second data line group except the last second data line.
  • the second data line forms a compensation capacitor at the overlapping position, and the m-1 compensation capacitors are respectively used to compensate m-1 gate parasitic capacitances formed between the gate and the drain of the non-final gate switch.
  • the switching signals other than the last switching signal are compensated signals, and m-1 compensated signals correspond to m-1 compensated signals one to one.
  • any compensation signal has a rising edge.
  • the parasitic capacitance of the strobe causes the data voltage waveform on the second data line connected to the non-final gating switch to drop; because it is at a high level
  • the scanning signal of the stage controls the thin film transistor in the pixel unit to turn on, and then pulls down the voltage of the pixel electrode connected to the second data line.
  • the compensation signal on the compensation line corresponding to the second data line has a rising edge, and the upward pull of the compensation line on the pixel voltage Vp offsets the downward movement of the pixel voltage Vp caused by the gate switch closure. Pull.
  • the last bit gate switch when the falling edge of the last bit switch signal is later than the falling edge of the high level phase in the cycle of the scan signal, because the last bit gate switch is closed at the same time, the last bit second data line The thin film transistor in the connected pixel unit has been turned off, and the closing of the last gate switch will not affect the pixel voltage Vp in the pixel unit. Therefore, the falling edges of the m-1 compensation signals are all set in the low-level phase after the high-level phase, so that the falling edges of the m-1 compensation signals do not affect the pixel voltage Vp.
  • the thin film transistor in the pixel unit connected to the second data line at the last position is not Turning off, turning off the last gate switch will still affect the pixel voltage Vp in the pixel unit.
  • the falling edge of the m-1 compensation signal and the falling edge of the last switch signal occur simultaneously, and the falling edge of the m-1 compensation signal causes the compensation voltage difference generated by the second data line to decrease and the last gate switch is closed
  • the gate feedthrough voltage (V feedthrough_CK ) generated by the reduction in the potential of the second data line is the same, and the compensation voltage difference and the gate feedthrough voltage can be uniformly compensated by adjusting the common voltage Vcom.
  • the embodiment of the present invention can compensate the demultiplexing circuit with a Mux ratio of 1:m by using m-1 compensation lines, and can solve the problems of poor display such as color shift, flicker, horizontal and vertical stripes caused by the gate parasitic capacitance in the display device , And further save the circuit space, reduce the additional power consumption caused by compensation.
  • FIG. 5 is a schematic diagram of a partial structure of a display device according to an embodiment of the present invention.
  • the Mux ratio of the demultiplexing circuit is 1:3.
  • the switch group includes three strobe switches M1, M2, M3, 3
  • the first path ends of the two strobe switches M1, M2, M3 are connected to and connected to the first data line S1, and the second path ends of the strobe switches M1, M2, M3 are respectively connected to 3 lines in the same second data line group
  • the second data lines D1, D2, D3, the control ends of the strobe switches M1, M2, and M3 are respectively connected to the switch control lines LCK1, LCK2, LCK3, and the control ends of the strobe switches M1, M2, M3 and the second path end respectively Generate gate parasitic capacitance Ckd1, Ckd2, Ckd3.
  • the compensation circuit includes a compensation drive circuit and two compensation lines LCK1' and LCK2'.
  • the compensation line LCK1' overlaps with the second data line D1 at least, and a compensation capacitor C1' is generated at the overlap;
  • the compensation line LCK2' overlaps with the second data line at least The line D2 overlaps, and a compensation capacitor C2' is generated at the overlap.
  • the scan signal Gk is input to the row of pixel units and controls the on and off of the thin film transistors in the pixel units.
  • the second data lines D1, D2, and D3 are respectively connected to the three pixel units p1, p2, and p3.
  • the waveforms of the scanning signals Gk, Gk+1, the switching signals CK1, CK2, CK3, and the compensation signals CK1', CK2' are shown in FIG. 6.
  • the rising edge of the compensation signal CK1' and the corresponding falling edge of the compensated signal (ie, the switching signal CK1) are at the same time.
  • the compensation signal CK1' pulls up the pixel voltage Vp1 and the compensation gate switch M1 turns off the pull down of the pixel voltage Vp1.
  • the rising edge of the compensation signal CK2' and the corresponding falling edge of the compensated signal (ie, the switch signal CK2) are at the same time.
  • the compensation signal CK2' pulls up the pixel voltage Vp2 and the compensation gate switch M2 turns off the pull down of the pixel voltage Vp2.
  • the gate switch M3 Since the gate switch M3 is opened and closed later than the gate switches M1 and M2, the gate switch M3 is the last gate switch.
  • the falling edge of the last switch signal ie, the switch signal CK3
  • the closing of the gate switch M3 only affects the potential V D 3 of the second data line D3. Therefore, the falling edges of the compensation signals CK1' and CK2' are both set in the low-level phase after the high-level phase, without affecting the pixel voltage Vp3.
  • the feedthrough voltage (V feedthrough ) of the pixel voltages Vp1, Vp2, and Vp3 only includes the pixel feedthrough voltage (V feedthrough_Gk ) generated by turning off the thin film transistor in the pixel unit.
  • the rising edge of the compensation signal does not necessarily have to be at the same time as the falling edge of the compensated signal.
  • a slight delay of the compensation signal also has a certain compensation effect.
  • the rising edge of each compensation signal is not earlier than the corresponding falling edge of the compensated signal (switch signal), and the rising edge of each compensation signal is not later than the high level in the period of the scan signal. The falling edge of the phase.
  • the falling edge of the compensation signal does not necessarily have to be at the same time as the falling edge of the last switch signal. As shown in Figure 8, the falling edge of each compensation signal may not be earlier than the scan signal. The falling edge of the last switch signal in the cycle, and the falling edge of each compensation signal is no later than the corresponding falling edge of the compensated signal (switch signal) in the next cycle of the scan signal.
  • the falling edge of the last switch signal (ie, the switch signal CK3) may also be no later than the falling edge of the high-level phase of the scan signal Gk.
  • the closing of the gate switch M3 will not only affect the potential V D 3 of the second data line D3, but also affect the pixel voltage Vp3.
  • the compensation signal The falling edges of CK1' and CK2' occur simultaneously, and the compensation signals CK1' and CK2' cause the compensation voltage difference generated by the pixel voltages Vp1 and Vp2 and the gate feed-through voltage (V) generated by the pixel voltage vp3 due to the closing of the final gate switch.
  • the size of feedthrough_CK ) is the same as the positive and negative.
  • the compensation voltage difference and the gate feedthrough voltage can be uniformly compensated by adjusting the common voltage Vcom.
  • the feedthrough voltage (V feedthrough ) of the pixel voltages Vp1, Vp2, Vp3 of the three pixel units includes not only the pixel feedthrough voltage (V feedthrough_Gk ) generated by the turn-off of the thin film transistor in the pixel unit, but also the gate The gate feedthrough voltage (V feedthrough_CK ) generated when the switch is turned off.
  • the display device of the embodiment of the present invention uses m-1 compensation lines to compensate the gate feedthrough voltage caused by m-1 non-terminal gate switches being turned off, and the gate feedthrough voltage caused by the last gate switch being turned off. According to the situation, choose not to compensate or use the common voltage Vcom to adjust the compensation voltage difference caused by m-1 compensation signals. Only adding m-1 compensation lines can achieve the uniform feedthrough voltage of each column of pixels. The effect can solve the poor display problems such as color shift, flicker, horizontal and vertical stripes caused by the gate switch in the demultiplexing circuit, save the circuit space, and reduce the additional power consumption caused by compensation.

Abstract

一种显示装置，包括补偿驱动电路和连接补偿驱动电路的m-1条补偿线，该补偿驱动电路产生m-1个补偿信号分别输入至m-1条补偿线， m-1条补偿线分别与每一个第二数据线组内除末位第二数据线之外的m-1条第二数据线在相交叠的位置形成补偿电容。通过增设m-1条补偿线即可达到使显示面板的各列像素受到的馈通电压均一的效果，可以解决选通开关关闭导致的显示不良问题，又可节省电路空间，减小补偿带来的额外功耗。

Description

显示装置 技术领域
本发明属于显示技术领域，具体涉及一种显示装置。
背景技术
多路分用电路(Demux技术)广泛应用于显示装置，它可以将数据驱动电路(Source IC)输出的数据电压以1:m(如1:2、1:3等，m为大于1的整数，称1：m为Mux比例)的形式分时传送给对应的m条第二数据线，连接数据驱动电路的第一数据线数量相对于连接像素单元的第二数据线数量至少可减少一半，可减少IC数量，进而减少面板设计成本和节省布局空间，减小面板的下边框，使面板达到更窄边框的要求。
由于采用Demux技术，在第一数据线和对应的多条第二数据线之间需要使用多个薄膜晶体管(TFT)作为选通开关，且需要引入控制选通开关的多条开关控制线。特别是对于使用氧化物半导体(如铟镓锌氧化物，简称IGZO)的TFT而言，因为TFT的特殊性质，在栅极和漏极间会存在一个较大的寄生电容Cgd(如图1)。如图2所示，由于上述寄生电容效应，多路分用电路中选通开关的栅极和漏极间存在较大的选通寄生电容Ckd。由于选通寄生电容Ckd的存在，选通开关的关断会对第二数据线电位带来选通馈通电压(V feedthrough_CK电压)，以及像素单元内薄膜晶体管关断的像素馈通电压(V feedthrough_Gk)。由于不同列像素与多路分用电路的连接关系不同，相邻像素有的会被选通馈通电压影响，有的可能不会被选通馈通电压影响，或者相邻像素受到选通馈通电压影响有差异，导致面板显示会出现色偏、横竖条纹、闪烁等显示不良现象。
为解决上述问题，一种多路分用电路及其相应的补偿电路的方案如图3所示，该方案中补偿电路具有与开关控制线数量相等的补偿线，补偿线与对应的第二数据线交叠形成补偿电容。然而，上述进行补偿的多路分用电路当Mux比例为1：m时，需要m条补偿线和m个补偿信号，会占用较大的面板空间，且电路的整体功耗较大。
发明内容
为解决上述技术问题，本发明实施例提供一种显示装置，该显示装置包括：
显示面板、连接n条第一数据线的数据驱动电路、多路分用电路和补偿电路；所述显示面板包括与所述n条第一数据线对应的n个第二数据线组，每个第二数据线组包括m条第二数据线，其中n、m为大于1的整数；
所述多路分用电路包括与所述n条第一数据线和n个第二数据线组对应的n个开关组，所述开关组包括m个选通开关，m个选通开关的控制端分别输入开关信号，m个选通开关的第一通路端相连接并与对应的一条第一数据线相连，m个选通开关的第二通路端分别连接至对应的第二数据线组的m条第二数据线；
所述补偿电路包括补偿驱动电路和连接所述补偿驱动电路的m-1条补偿线，所述补偿驱动电路产生m-1个补偿信号分别输入至m-1条所述补偿线，m-1条所述补偿线分别与每一个第二数据线组内除末位第二数据线之外的m-1条第二数据线在相交叠的位置形成补偿电容；
其中，除末位开关信号之外的开关信号为被补偿信号，m-1个所述补偿信号分别与m-1个被补偿信号一一对应，在显示面板的扫描信号的一个高电平阶段内，任一补偿信号具有一个上升沿。
在优选的实施方式中，每个补偿信号的上升沿不早于对应的被补偿信号的下降沿，且每个补偿信号的上升沿不晚于所述高电平阶段的下降沿。
在优选的实施方式中，补偿信号的上升沿与对应的被补偿信号的下降沿同时发生。
在优选的实施方式中，末位开关信号的下降沿晚于所处扫描信号的周期内高电平阶段的下降沿，m-1个所述补偿信号的下降沿均设置在所述高电平阶段之后的低电平阶段内。
在优选的实施方式中，每个补偿信号的下降沿不早于所处扫描信号的周期内末位开关信号的下降沿，且每个补偿信号的下降沿不晚于扫描信号的下一周期内对应的被补偿信号的下降沿。
在优选的实施方式中，补偿信号的下降沿和末位开关信号的下降沿同时发生。
在优选的实施方式中，末位开关信号的下降沿不晚于所处扫描信号的周期内高电平阶段的下降沿，m-1个所述补偿信号的下降沿与末位开关信号的下降沿同时发生。
在优选的实施方式中，m-1个所述补偿信号导致的显示面板的像素电压产生的补偿电压差与末位选通开关关闭导致的选通馈通电压的大小一致，所述补偿电压差和选通馈通电压通过对显示面板的公共电压的调整来补偿。
与现有技术相比，本发明实施例仅增设m-1条补偿线即可对Mux比例为1：m的多路分用电路进行补偿，可以解决显示装置中选通寄生电容导致的色偏、闪烁、横竖条纹等显示不良问题，并且节省电路空间，减小补偿带来的额外功耗。
附图说明
下面将以明确易懂的方式，结合附图说明优选实施方式，对本发明予以进一步说明。
图1为薄膜晶体管结构中栅极和漏极间寄生电容的示意图；
图2为现有技术中一种多路分用电路的结构示意图；
图3为现有技术中一种多路分用电路及补偿电路的结构示意图；
图4为根据本发明一实施例的显示装置的结构示意图；
图5为根据本发明一实施例的显示装置的局部结构示意图；
图6为根据本发明一实施例的显示装置中多种信号的第一波形示意图；
图7为根据本发明一实施例的显示装置中多种信号的第二波形示意图；
图8为根据本发明一实施例的显示装置中多种信号的第三波形示意图；
图9为根据本发明一实施例的显示装置中多种信号的第四波形示意图。
具体实施方式
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。
图4为根据本发明一实施例的显示装置的结构示意图。如图4所示，本发明实施例的显示装置包括：显示面板、输出n条第一数据线的数据驱动电路、多路分用电路和补偿电路。
显示面板包括纵横交错的多条扫描线和多条第二数据线、由扫描线和第二数据线交叉限定的多个像素单元。每条扫描线向像素单元输出扫描信号，扫描信号具有周期性的 高电平阶段和低电平阶段。第二数据线分为n个第二数据线组，每个第二数据线组包括m条第二数据线；其中n、m为大于1的整数。图4中仅示意性呈现了m＝3的情形。
数据驱动电路通过n条第一数据线分别输出数据电压至多路分用电路，多路分用电路将一条第一数据线输出的数据电压分时输入至显示面板中与该第一数据线对应的第二数据线组内的m条第二数据线。
像素单元内包括薄膜晶体管和与薄膜晶体管连接的像素电极，当输入像素单元的扫描信号处于高电平阶段时，薄膜晶体管打开，对应的第二数据线将数据信号输入像素电极。显示装置还包括公共电极和液晶层，称像素电极的电位为像素电压Vp、公共电极的电位为公共电压Vcom，像素单元内像素电压Vp和公共电压Vcom间的电压差控制液晶层的旋转，进而控制该像素单元的显示。
多路分用电路包括开关驱动电路、与开关驱动电路连接的m条开关控制线以及与n条第一数据线对应的n个开关组。
每个开关组包括m个选通开关，选通开关可以为n型或p型薄膜晶体管，每个薄膜晶体管均包括控制端、第一通路端和第二通路端。在以下的实施例中，控制端为栅极，其中一个通路端为源极、另一个通路端为漏极。以下以n型薄膜晶体管为例，当给控制端高电平时，源极和漏极通过半导体层电性连接，此时选通开关处于开启状态。每一开关组内的m个选通开关分别与m条开关控制线对应，并与m条第二数据线对应；同一个开关组内的m个选通开关的控制端分别连接其对应的开关控制线，同一个开关组内的m个选通开关的第一通路端相连接并与一条第一数据线相连，同一个开关组内的m个选通开关的第二通路端分别连接至显示面板中与所述第一数据线对应的第二数据线组内的m条第二数据线。
开关驱动电路产生m个开关信号分别输入至m条开关控制线，m个开关信号在扫描信号的一个高电平阶段内依次产生一个上升沿(由低电平上升至高电平)，且在前一个开关信号产生下降沿(由高电平下降至低电平)之后或同时，后一个开关信号产生上升沿。即m条开关控制线分别控制每个开关组中的m个选通开关在扫描信号的一个高电平阶段内依次打开，且同一时间开关组内只有一个选通开关处于打开状态。
同一开关组内的m个选通开关在扫描信号的一个周期内依次关闭，称最后一个打开且最后一个关闭的选通开关为末位选通开关，其余开关为非末位选通开关，控制末位选通开关的开关信号为末位开关信号，末位选通开关的第二通路端所连接的第二数据线为末位第二数据线。在扫描信号的一个周期内，末位开关信号的下降沿可能早于或晚于扫 描信号的高电平阶段的下降沿，末位开关信号的下降沿也可能与扫描信号的高电平阶段的下降沿同时发生。
补偿电路包括补偿驱动电路和连接补偿驱动电路的多条补偿线，对于Mux比例为1：m的显示装置，本发明实施例仅需m-1条补偿线。补偿驱动电路产生m-1个补偿信号分别输入至m-1条补偿线，m-1条补偿线分别与每一个第二数据线组内除末位第二数据线之外的m-1条第二数据线在相交叠的位置形成补偿电容，该m-1个补偿电容分别用于补偿非末位选通开关栅极和漏极间形成的m-1个选通寄生电容。
除末位开关信号之外的开关信号为被补偿信号，m-1个被补偿信号与m-1个补偿信号一一对应。在扫描信号的一个高电平阶段内，任一补偿信号具有一个上升沿。
对于非末位选通开关，当任一个非末位选通开关关闭时，选通寄生电容导致非末位选通开关所连接的第二数据线上的数据电压波形下降；由于处于高电平阶段的扫描信号控制像素单元内的薄膜晶体管打开，进而对第二数据线所连接的像素电极的电压向下拉动。在该高电平阶段内，与上述第二数据线相对应的补偿线上的补偿信号具有一个上升沿，补偿线对像素电压Vp的向上拉动抵消了选通开关关闭对像素电压Vp的向下拉动。
对于末位选通开关，当末位开关信号的下降沿晚于所处扫描信号的周期内高电平阶段的下降沿时，由于末位选通开关关闭的同时，末位第二数据线所连接的像素单元中的薄膜晶体管已经关闭，末位选通开关的关闭不会对该像素单元内的像素电压Vp产生影响。因此，将m-1个补偿信号的下降沿均设置在该高电平阶段之后的低电平阶段内，使m-1个补偿信号的下降沿也均不对像素电压Vp产生影响。
当末位开关信号的下降沿不晚于扫描信号的高电平阶段的下降沿时，由于末位选通开关关闭的同时，末位第二数据线所连接的像素单元中的薄膜晶体管并没有关闭，末位选通开关的关闭仍会对该像素单元内的像素电压Vp产生影响。m-1个补偿信号的下降沿与末位开关信号的下降沿同时发生，且m-1个补偿信号的下降沿导致第二数据线电位降低所产生的补偿电压差与末位选通开关关闭导致该第二数据线电位降低所产生的选通馈通电压(V feedthrough_CK)大小一致，补偿电压差和选通馈通电压可以通过对公共电压Vcom的调整统一进行补偿。
本发明实施例通过m-1条补偿线即可对Mux比例为1：m的多路分用电路进行补偿，可以解决显示装置中选通寄生电容导致的色偏、闪烁、横竖条纹等显示不良问题，且进一步节省电路空间，减小补偿带来的额外功耗。
图5为根据本发明一实施例的显示装置的局部结构示意图。本实施例中多路分用电路的Mux比例为1：3。
如图5所示，以第一数据线S1所连接的开关组及相应的多条第二数据线D1、D2、D3为例，开关组内包括3个选通开关M1、M2、M3，3个选通开关M1、M2、M3的第一通路端相连接并与第一数据线S1相连，选通开关M1、M2、M3的第二通路端分别连接同一第二数据线组内的3条第二数据线D1、D2、D3，选通开关M1、M2、M3的控制端分别连接开关控制线LCK1、LCK2、LCK3，选通开关M1、M2、M3的控制端和第二通路端间分别产生选通寄生电容Ckd1、Ckd2、Ckd3。
补偿电路包括补偿驱动电路和2条补偿线LCK1’、LCK2’，补偿线LCK1’至少与第二数据线D1存在交叠，交叠处产生补偿电容C1’；补偿线LCK2’至少与第二数据线D2存在交叠，交叠处产生补偿电容C2’。
以某一行像素单元为例，扫描信号Gk输入该行像素单元并控制像素单元内薄膜晶体管的打开和关闭，第二数据线D1、D2、D3分别连接该行的三个像素单元p1、p2、p3。
本实施例中，扫描信号Gk、Gk+1、开关信号CK1、CK2、CK3以及补偿信号CK1’、CK2’的波形如图6所示。补偿信号CK1’的上升沿与对应的被补偿信号(即开关信号CK1)的下降沿位于同一时间，补偿信号CK1’对像素电压Vp1的上拉补偿选通开关M1关闭对像素电压Vp1的下拉。补偿信号CK2’的上升沿与对应的被补偿信号(即开关信号CK2)的下降沿位于同一时间，补偿信号CK2’对像素电压Vp2的上拉补偿选通开关M2关闭对像素电压Vp2的下拉。
由于选通开关M3的打开和关闭晚于选通开关M1和M2，选通开关M3为末位选通开关。本实施例中，末位开关信号(即开关信号CK3)的下降沿晚于扫描信号Gk的高电平阶段的下降沿，选通开关M3的关闭仅对第二数据线D3的电位V D3产生影响，而不会对像素电压Vp3产生影响，因此将补偿信号CK1’、CK2’的下降沿均设置在该高电平阶段之后的低电平阶段内。如图6所示，像素电压Vp1、Vp2、Vp3的馈通电压(V feedthrough)仅包括像素单元内薄膜晶体管关闭所产生的像素馈通电压(V feedthrough_Gk)。
在优选的实施方式中，补偿信号的上升沿并不一定要与被补偿信号的下降沿位于同一时间，补偿信号略有延迟也有一定的补偿效果。如图7所示，每个补偿信号的上升沿不早于对应的被补偿信号(开关信号)的下降沿，且每个补偿信号的上升沿不晚于所处扫描信号的周期内高电平阶段的下降沿。
在优选的实施方式中，补偿信号的下降沿并不一定要与末位开关信号的下降沿位于同一时间，如图8所示，每个补偿信号的下降沿还可以不早于所处扫描信号的周期内末位开关信号的下降沿，且每个补偿信号的下降沿不晚于扫描信号的下一周期内对应的被补偿信号(开关信号)的下降沿。
在优选的实施方式中，末位开关信号(即开关信号CK3)的下降沿还可以不晚于扫描信号Gk的高电平阶段的下降沿。如图9所示，由于选通开关M3的关闭不仅会对第二数据线D3的电位V D3产生影响，还会对像素电压Vp3产生影响，在末位选通开关关闭的同时，补偿信号CK1’、CK2’的下降沿同时发生，且补偿信号CK1’、CK2’导致像素电压Vp1、Vp2产生的补偿电压差与末位选通开关关闭导致像素电压vp3产生的选通馈通电压(V feedthrough_CK)大小和正负性一致，补偿电压差和选通馈通电压可以通过对公共电压Vcom的调整统一补偿。
如图9所示，3个像素单元的像素电压Vp1、Vp2、Vp3的馈通电压(V feedthrough)不仅包括像素单元内薄膜晶体管关闭所产生的像素馈通电压(V feedthrough_Gk)，还包括选通开关关闭所产生的选通馈通电压(V feedthrough_CK)。
本发明实施例的显示装置采用m-1条补偿线分别对m-1个非末位选通开关关闭导致的选通馈通电压进行补偿，末位选通开关关闭导致的选通馈通电压根据情况选择不补偿或者与m-1个补偿信号的导致的补偿电压差统一使用公共电压Vcom调整来补偿，仅增设m-1条补偿线即可达到使各列像素受到的馈通电压均一的效果，可以解决多路分用电路中选通开关关闭导致的色偏、闪烁、横竖条纹等显示不良问题，又可节省电路空间，减小补偿带来的额外功耗。
应当说明的是，以上所述仅是本发明的优选实施方式，但是本发明并不限于上述实施方式中的具体细节，应当指出，对于本技术领域的普通技术人员来说，在本发明的技术构思范围内，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，对本发明的技术方案进行多种等同变换，这些改进、润饰和等同变换也应视为本发明的保护范围。

Claims (8)

  1. 一种显示装置，其特征在于，包括：显示面板、连接n条第一数据线的数据驱动电路、多路分用电路和补偿电路；所述显示面板包括与n条所述第一数据线对应的n个第二数据线组，每个第二数据线组包括m条第二数据线，其中n、m为大于1的整数；
    所述多路分用电路包括与n条所述第一数据线和n个第二数据线组对应的n个开关组，所述开关组包括m个选通开关，m个选通开关的控制端分别输入开关信号，m个选通开关的第一通路端相连接并与对应的一条第一数据线相连，m个选通开关的第二通路端分别连接至对应的第二数据线组的m条第二数据线；
    所述补偿电路包括补偿驱动电路和连接所述补偿驱动电路的m-1条补偿线，所述补偿驱动电路产生m-1个补偿信号分别输入至m-1条所述补偿线，m-1条所述补偿线分别与每一个第二数据线组内除末位第二数据线之外的m-1条第二数据线在相交叠的位置形成补偿电容；
    其中，除末位开关信号之外的开关信号为被补偿信号，m-1个所述补偿信号分别与m-1个所述被补偿信号一一对应，在显示面板的扫描信号的一个高电平阶段内，任一补偿信号具有一个上升沿。
  2. 根据权利要求1所述的显示装置，其特征在于，每个补偿信号的上升沿不早于对应的被补偿信号的下降沿，且每个补偿信号的上升沿不晚于所述高电平阶段的下降沿。
  3. 根据权利要求1所述的显示装置，其特征在于，补偿信号的上升沿与对应的被补偿信号的下降沿同时发生。
  4. 根据权利要求1所述的显示装置，其特征在于，末位开关信号的下降沿晚于所处扫描信号的周期内高电平阶段的下降沿，m-1个所述补偿信号的下降沿均设置在所述高电平阶段之后的低电平阶段内。
  5. 根据权利要求4所述的显示装置，其特征在于，每个补偿信号的下降沿不早于所处扫描信号的周期内末位开关信号的下降沿，且每个补偿信号的下降沿不晚于扫描信号的下一周期内对应的被补偿信号的下降沿。
  6. 根据权利要求4所述的显示装置，其特征在于，补偿信号的下降沿和末位开关信号的下降沿同时发生。
  7. 根据权利要求1所述的显示装置，其特征在于，末位开关信号的下降沿不晚于所处扫描信号的周期内高电平阶段的下降沿，m-1个所述补偿信号的下降沿与末位开关信号的下降沿同时发生。
  8. 根据权利要求7所述的显示装置，其特征在于，m-1个所述补偿信号导致的显示面板的像素电压产生的补偿电压差与末位选通开关关闭导致的选通馈通电压的大小一致，所述补偿电压差和选通馈通电压通过对显示面板的公共电压的调整来补偿。
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