WO2020151128A1 - Circuit goa et dispositif d'affichage - Google Patents

Circuit goa et dispositif d'affichage Download PDF

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Publication number
WO2020151128A1
WO2020151128A1 PCT/CN2019/085770 CN2019085770W WO2020151128A1 WO 2020151128 A1 WO2020151128 A1 WO 2020151128A1 CN 2019085770 W CN2019085770 W CN 2019085770W WO 2020151128 A1 WO2020151128 A1 WO 2020151128A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
node
low level
pull
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PCT/CN2019/085770
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English (en)
Chinese (zh)
Inventor
陈帅
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深圳市华星光电技术有限公司
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Publication of WO2020151128A1 publication Critical patent/WO2020151128A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit and a display device.
  • LCD Liquid Crystal Display
  • PDA personal digital assistant
  • LCD TV mobile phone
  • PDA personal digital assistant
  • digital camera computer screen or notebook computer screen, etc.
  • AMLCD Active Matrix Liquid Crystal Display
  • the active matrix liquid crystal display includes multiple pixels. Each pixel is electrically connected to a thin film transistor (TFT).
  • TFT thin film transistor
  • the gate (Gate) is connected to the horizontal scan line
  • the drain (Drain) is connected to the vertical data line
  • the source (Source) is connected to the pixel electrode. Applying enough voltage on the horizontal scan line will turn on all the TFTs that are electrically connected to the horizontal scan line, so that the signal voltage on the data line can be written into the pixel, and the transmittance of different liquid crystals can be controlled to control the color With the effect of brightness.
  • Array substrate line drive (Gate Driver on Array, GOA) technology is to use the existing thin-film transistor liquid crystal display array (Array) process to fabricate the gate row scanning drive circuit on the TFT array substrate to realize the progressive scanning of the gate. Drive mode.
  • GOA technology can reduce external integrated circuit boards (Integrated The bonding process of Circuit (IC) has the opportunity to increase production capacity and reduce product costs, and it can make LCD panels more suitable for manufacturing narrow or borderless display products.
  • the existing GOA circuit generally includes: each level of GOA unit includes: a pull-up control module, a pull-up module, a stage transfer module, a pull-down module, a bootstrap module, and a pull-down maintenance module.
  • the pull-up control module is used in the scanning phase.
  • the pull-up module is controlled to be turned on, the pull-up module is used to output stage transmission signals and scanning signals, the pull-down film is used to control the pull-up module to turn off in the non-scanning phase, and the bootstrap module is used to maintain the
  • the pull-up module is kept open, and the pull-down maintaining module is used to keep the pull-up module closed during the non-scanning phase, wherein the pull-up module uses a clock signal to generate and output a stage transmission signal and a scan signal, and the pull-down module passes
  • the preset low level pulls down the potential of the output terminal of the scan signal so that the pull-up module remains closed.
  • the low level of the clock signal is generally lower than the preset low level adopted by the pull-down module.
  • the purpose of the present invention is to provide a GOA circuit, which can reduce the potential pulling in the GOA circuit and improve the stability of the GOA circuit.
  • the object of the present invention is also to provide a display device that can reduce the potential pulling in the GOA circuit and improve the stability of the GOA circuit.
  • each level of GOA unit includes: pull-up control module, pull-up module, stage transfer module, pull-down module, bootstrap module and pull-down maintenance Module
  • n be a positive integer, in the nth level GOA unit:
  • the pull-up control module is electrically connected to the first node and connected to the level transmission signal of the n-1 level GOA unit and the scanning signal of the n-1 level GOA unit, and is used for the stage of the n-1 level GOA unit Under the control of the transmission signal, output the scan signal of the n-1th level GOA unit to the first node;
  • the pull-up module is electrically connected to the first node and is connected to a clock signal for outputting a scan signal by using the clock signal under the control of the first node;
  • the stage transmission module is electrically connected to the first node and connected to a clock signal, and is used to output stage transmission signals by using the clock signal under the control of the first node;
  • the pull-down module is electrically connected to the first node and connected to the scan signal, the first low level, the second low level, and the scan signal of the n+1 level GOA unit, and is used in the n+1 level GOA unit Pull down the potential of the first node to the first low level under the control of the scan signal of, and pull down the potential of the scan signal to the second low level under the control of the scan signal of the GOA unit of the n+1th stage;
  • the bootstrap module is electrically connected to the first node, and is used to raise the potential of the first node during the scanning signal output period and maintain the raised potential;
  • the pull-down maintaining unit is electrically connected to the first node and connected to the scan signal, the stage transmission signal of the n-1th GOA unit, the first low level and the second low level, and is used during the non-output period of the scan signal , Maintaining the stage transmission signal of the first node and the n-1th stage GOA unit at the first low level, and maintaining the scan signal at the second low level;
  • the low level of the clock signal is equal to the second low level, and the first low level is less than the second low level.
  • the pull-up control module includes a first thin film transistor, the gate of the first thin film transistor is connected to the level transmission signal of the n-1 level GOA unit, and the source is connected to the scan signal of the n-1 level GOA unit, The drain is electrically connected to the first node.
  • the pull-up module includes a second thin film transistor, the gate of the second thin film transistor is electrically connected to the first node, the source is connected to the clock signal, and the drain is outputting the scan signal.
  • the stage transmission module includes: a third thin film transistor, the gate of the third thin film transistor is electrically connected to the first node, the source is connected to the clock signal, and the drain outputs the stage signal.
  • the pull-down module includes a fourth thin film transistor and a fifth thin film transistor
  • the gate of the fourth thin film transistor is connected to the scan signal of the GOA unit of level n+1, the source is electrically connected to the first node, and the drain is connected to the first low level;
  • the gate of the fifth thin film transistor is connected to the scan signal of the n+1th level GOA unit, the source is connected to the scan signal, and the drain is connected to the second low level.
  • the bootstrap module includes a bootstrap capacitor, a first end of the bootstrap capacitor is electrically connected to a first node, and a second end is connected to a scan signal.
  • the pull-down maintenance module includes a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and an inverter;
  • the gate of the sixth thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the scan signal, and the drain is connected to the second low level;
  • the gate of the seventh thin film transistor is electrically connected to the output terminal of the inverter, the source is electrically connected to the first node, and the drain is connected to the first low level;
  • the gate of the eighth thin film transistor is electrically connected to the output terminal of the inverter, the source is connected to the stage transmission signal of the n-1th stage GOA unit, and the drain is connected to the first low level;
  • the input terminal of the inverter is electrically connected to the first node
  • the inverter includes: a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, and a twelfth thin film transistor;
  • the gate and source of the ninth thin film transistor are both connected to an inverted signal, and the drain is electrically connected to the gate of the twelfth thin film transistor;
  • the gate of the tenth thin film transistor is electrically connected to the first node, the source is electrically connected to the gate of the twelfth thin film transistor, and the drain is connected to the first low level;
  • the gate of the eleventh thin film transistor is electrically connected to the first node, the source is electrically connected to the drain of the twelfth thin film transistor, and the drain is connected to the first low level;
  • the source of the twelfth thin film transistor is connected to an inverted signal
  • the drain of the twelfth thin film transistor is the output terminal of the inverter, and the gate of the tenth thin film transistor is the input terminal of the inverter.
  • the start signal is used to replace the scan signal of the n-1 level GOA unit and the level transmission signal of the n-1 level GOA unit is input to the pull-up control unit, in the last level GOA unit , The start signal is used to replace the scan signal of the n+1th level GOA unit and input to the pull-down unit.
  • the phases of the clock signals accessed by the pull-up modules are opposite.
  • the present invention also provides a display device including the GOA circuit described above.
  • the present invention provides a GOA circuit, including multi-level GOA units, each level of GOA unit includes: pull-up control module, pull-up module, stage transfer module, pull-down module, bootstrap module and pull-down module
  • the maintenance module wherein the pull-up module uses a clock signal to output the scan signal under the control of the first node; the pull-down module separates the potentials of the first node and the scan signal under the control of the scan signal of the next-level GOA unit Pull-down to a first low level and a second low level; the pull-down sustaining unit maintains the first node and the level transmission signal of the upper level GOA unit at the first low level during the non-output period of the scan signal, and The scan signal is maintained at the second low level; the low level of the clock signal is equal to the second low level, the first low level is less than the second low level, and the low level of the clock signal is set to the second low level.
  • the two low levels are equal and the level transmission signal of the previous level GOA unit is maintained at the first low level during the non-output period of the scan signal, which can reduce the potential pulling in the GOA circuit and improve the stability of the GOA circuit.
  • the present invention also provides a display device, which can reduce the potential pulling in the GOA circuit and improve the stability of the GOA circuit.
  • FIG. 1 is a circuit diagram of a first level GOA unit of the GOA circuit of the present invention
  • FIG. 2 is a working sequence diagram of the GOA circuit of the present invention.
  • Fig. 3 is a circuit diagram of the first-stage GOA unit of the GOA circuit of the present invention.
  • FIG. 4 is a circuit diagram of the last stage GOA unit of the GOA circuit of the present invention.
  • the present invention provides a GOA circuit including multi-level GOA units.
  • Each level of GOA unit includes: a pull-up control module 100, a pull-up module 200, a stage transfer module 300, a pull-down module 400, and a bootstrap module 500 and pull-down maintenance module 600;
  • n be a positive integer, in the nth level GOA unit:
  • the pull-up control module 100 is electrically connected to the first node Q(n) and is connected to the stage transmission signal ST(n-1) of the n-1 level GOA unit and the scanning signal G( n-1), used to output the scan signal G(n-1) of the n-1th level GOA unit to the first node under the control of the stage transmission signal ST(n-1) of the n-1th level GOA unit Q(n);
  • the pull-up module 200 is electrically connected to the first node Q(n) and connected to the clock signal CK for outputting the scan signal G(n) by using the clock signal CK under the control of the first node Q(n);
  • the stage transmission module 300 is electrically connected to the first node Q(n) and is connected to the clock signal CK for outputting the stage transmission signal ST(n) by using the clock signal CK under the control of the first node Q(n) ;
  • the pull-down module 400 is electrically connected to the first node Q(n) and is connected to the scan signal G(n+1), the first low level VSSQ, the second low level VSSG and
  • the scan signal G(n) is used to pull down the potential of the first node Q(n) to the first low level VSSQ under the control of the scan signal G(n+1) of the GOA unit of the n+1th stage and to Under the control of the scan signal G(n+1) of the +1 level GOA unit, the potential of the scan signal G(n) is pulled down to the second low level VSSG;
  • the bootstrap module 500 is electrically connected to the first node Q(n), and is used to raise the potential of the first node Q(n) during the output period of the scan signal G(n) and maintain the raised potential;
  • the pull-down maintaining unit 600 is electrically connected to the first node Q(n) and connected to the scan signal G(n), the stage transfer signal ST(n-1) of the n-1th GOA unit, and the first low level VSSQ And the second low level VSSG, used to maintain the first node Q(n) and the stage transfer signal ST(n-1) of the n-1th GOA unit during the non-output period of the scan signal G(n)
  • the first low level VSSQ maintains the scan signal G(n) at the second low level VSSG;
  • the low level of the clock signal CK is equal to the second low level VSSG, and the first low level VSSQ is less than the second low level VSSG.
  • the pull-up control module 100 includes a first thin film transistor T1, and the gate of the first thin film transistor T1 is connected to the n-1th GOA
  • the stage transmission signal ST(n-1) of the unit, the source is connected to the scan signal G(n-1) of the n-1th stage GOA unit, and the drain is electrically connected to the first node Q(n).
  • the pull-up module 200 includes: a second thin film transistor T2, and the gate of the second thin film transistor T2 is electrically connected to the first node Q( n), the source is connected to the clock signal CK, and the drain outputs the scan signal G(n).
  • the stage transfer module 300 includes: a third thin film transistor T3, and the gate of the third thin film transistor T3 is electrically connected to the first node Q( n), the source is connected to the clock signal CK, and the drain outputs the stage transmission signal ST(n).
  • the pull-down module 400 includes a fourth thin film transistor T4 and a fifth thin film transistor T5;
  • the gate of the fourth thin film transistor T4 is connected to the scan signal G(n+1) of the n+1th level GOA unit, the source is electrically connected to the first node Q(n), and the drain is connected to the first low voltage Flat VSSQ;
  • the gate of the fifth thin film transistor T5 is connected to the scan signal G(n+1) of the n+1th level GOA unit, the source is connected to the scan signal G(n), and the drain is connected to the second low level VSSG .
  • the bootstrap module 500 includes a bootstrap capacitor C1, and a first end of the bootstrap capacitor C1 is electrically connected to a first node Q(n), The second end receives the scanning signal G(n).
  • the pull-down maintenance module 600 includes a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, and an inverter 601;
  • the gate of the sixth thin film transistor T6 is electrically connected to the output terminal of the inverter 601, the source is connected to the scan signal G(n), and the drain is connected to the second low level VSSG;
  • the gate of the seventh thin film transistor T7 is electrically connected to the output terminal of the inverter 601, the source is electrically connected to the first node Q(n), and the drain is connected to the first low level VSSQ;
  • the gate of the eighth thin film transistor T8 is electrically connected to the output terminal of the inverter 601, the source is connected to the stage transmission signal ST(n-1) of the n-1th GOA unit, and the drain is connected to the first A low level VSSQ;
  • the input terminal of the inverter 601 is electrically connected to the first node Q(n).
  • the inverter 601 is a Darlington structure inverter, and specifically includes: a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, and a twelfth thin film transistor Transistor T12;
  • the gate and source of the ninth thin film transistor T9 are both connected to the inverted signal LC, and the drain is electrically connected to the gate of the twelfth thin film transistor T12;
  • the gate of the tenth thin film transistor T10 is electrically connected to the first node Q(n), the source is electrically connected to the gate of the twelfth thin film transistor T12, and the drain is connected to the first low level VSSQ;
  • the gate of the eleventh thin film transistor T11 is electrically connected to the first node Q(n), the source is electrically connected to the drain of the twelfth thin film transistor T12, and the drain is connected to the first low level VSSQ;
  • the source of the twelfth thin film transistor T12 is connected to an inverted signal LC;
  • the drain of the twelfth thin film transistor T12 is the output terminal of the inverter 601, and the gate of the tenth thin film transistor T10 is the input terminal of the inverter 601.
  • all the thin film transistors described in the GOA circuit of the present invention are metal oxide semiconductor thin film transistors, polysilicon thin film transistors or amorphous silicon thin film transistors, and are all N-type thin film transistors.
  • the phases of the clock signals CK accessed by the pull-up modules 200 are opposite.
  • the high-frequency clock signal CK connected to the n-th GOA unit is one of the first high-frequency clock signal CK1 and the second high-frequency clock signal CK2
  • the high-frequency clock signal CK connected to the n+1-th level GOA unit is the other of the first high-frequency clock signal CK1 and the second high-frequency clock signal CK2, wherein the first high-frequency clock signal CK1 It is opposite to the phase in the second high frequency clock signal CK2.
  • the GOA units of the odd-numbered stages are connected to the first high-frequency clock signal CK1
  • the GOA units of the even-numbered stages are connected to the second high-frequency clock signal CK2.
  • the low level of the clock signal CK and the second low level VSSG are both -5V, and the first low level VSSQ is -10V.
  • the start signal STV is used to replace the stage transmission signal of the n-1th stage GOA unit ST(n-1) and the scanning signal G(n-1) of the GOA unit of the n-1th stage are input to the pull-up control unit 100 to realize the normal operation of the circuit, which corresponds to the preferred embodiment of the present invention, namely
  • the gate and source of the first thin film transistor T1 are both connected to the start signal STV, and the source of the eighth thin film transistor T8 is connected to the start signal STV, as shown in FIG.
  • the start signal STV is used to replace the scan signal G(n+1) of the n+1th-stage GOA unit and input to the pull-down unit 400, which corresponds to the preferred embodiment of the present invention, that is, the last one In the first-level GOA unit, the gates of the fourth thin film transistor T4 and the fifth thin film transistor T5 are connected to the start signal STV.
  • the pulse period of the start signal is equal to one frame duration.
  • Stage 1 Precharge stage: the stage transfer signal ST(n-1) of the n-1th GOA unit is at a high potential, and the scan signal G(n-1) of the n-1th GOA unit is at a high potential.
  • the first thin film transistor T1 is turned on, and the scan signal G(n-1) of the GOA unit of the n-1 level is input to the first node Q(n), so that the first node Q(n) rises to a high potential, and the first high-frequency clock signal CK1 outputs low level;
  • Stage 2 the stage transfer signal ST(n-1) of the n-1th GOA unit is at a low level, and the scan signal G(n-1) of the n-1th GOA unit is at a low level.
  • a thin film transistor T1 is turned off, the bootstrap capacitor C1 makes the first node Q(n) rise higher, the first high-frequency clock signal CK1 outputs a high level, and the second thin film transistor T2 and the third thin film transistor T3 are both turned on , Respectively output the high-level scanning signal G(n) and the level transmission signal ST(n);
  • Stage 3 Pull-down stage: the scan signal G(n+1) of the GOA unit of the n+1 level is at a high potential, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, and the first node Q(n) is pulled down to the first A low level VSSQ pulls down the scan signal G(n) to a second low level VSSG; at this time, the first high frequency clock signal CK1 outputs a low level, and the low level of the first high frequency clock signal CK1 and the second low level
  • the two low levels of VSSG are both -5V, which can avoid potential pulling between the low level of the first high-frequency clock signal CK1 and the second low level VSSG, and ensure the working stability of the GOA circuit.
  • Stage 4 Pull-down sustaining stage: the first node Q(n) is at a low level, the tenth thin film transistor T10 and the eleventh thin film transistor T11 are turned off, the inverted signal LC is at a high level, and the ninth thin film transistor T9 and the twelfth thin film transistor The thin film transistor T12 is turned on, the sixth thin film transistor T6, the seventh thin film transistor T7, and the eighth thin film transistor T8 are turned on, and the first node Q(n) and the stage transfer signal ST(n- 1) Maintain at the first low level VSSQ and maintain the scan signal G(n) at the second low level VSSG.
  • the gate-source voltages of the first thin film transistor T1 and the third thin film transistor T3 are both 0V, and the second The gate-source voltage of the thin film transistor T2 is less than 0V, the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 can all be in a better off state, especially the gate-source voltage of the second thin film transistor T2 is less than 0V , Better than the existing technology closed.
  • the present invention also provides a display device including the GOA circuit described above. .
  • the present invention provides a GOA circuit including multi-level GOA units, each level of GOA unit includes: pull-up control module, pull-up module, stage transfer module, pull-down module, bootstrap module and pull-down maintenance Module, wherein the pull-up module uses a clock signal to output the scan signal under the control of the first node; the pull-down module pulls down the potentials of the first node and the scan signal under the control of the scan signal of the next-stage GOA unit To the first low level and the second low level; during the non-output period of the scan signal, the pull-down maintaining unit maintains the first node and the level transmission signal of the upper level GOA unit at the first low level, and scans The signal is maintained at the second low level; the low level of the clock signal is equal to the second low level, and the first low level is less than the second low level.
  • the present invention also provides a display device, which can reduce the potential pulling in the GOA circuit and improve the stability of the GOA circuit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne un circuit GOA et un dispositif d'affichage. Le circuit GOA comporte de multiples étages d'unités GOA, et chaque étage d'unité GOA comporte: un module (100) de commande de rappel vers le haut, un module (200) de rappel vers le haut, un module (300) de transmission d'étage, un module (400) de rappel vers le bas, un module (500) d'amorçage, et un module (600) de maintien de rappel vers le bas, le module (200) de rappel vers le haut délivrant un signal de balayage (G(n)) en utilisant un signal d'horloge (CK) sous le contrôle d'un premier nœud (Q(n)); le module (400) de rappel vers le bas abaisse respectivement des potentiels du premier nœud Q(n) et du signal de balayage G(n) jusqu'à un premier niveau bas (VSSQ) et un second niveau bas (VSSG) sous le contrôle d'un signal de balayage G(n+1) de l'étage suivant d'unité GOA; le module (600) de maintien de rappel vers le bas maintient des signaux de transmission d'étage ST(N-1) du premier nœud Q(n) et du précédent étage d'unité GOA au premier niveau bas (VSSQ) et maintient le signal de balayage G(n) au second niveau bas (VSSG) dans une période où le signal de balayage G(n) n'est pas délivré; le niveau bas du signal d'horloge (CK) est égal au second niveau bas (VSSG), et le premier niveau bas (VSSQ) est inférieur au second niveau bas (VSSG), de sorte que le rappel de potentiel dans le circuit GOA peut être réduit, et que la stabilité du circuit GOA est améliorée.
PCT/CN2019/085770 2019-01-25 2019-05-07 Circuit goa et dispositif d'affichage WO2020151128A1 (fr)

Applications Claiming Priority (2)

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CN201910075940.X 2019-01-25
CN201910075940.XA CN109509459B (zh) 2019-01-25 2019-01-25 Goa电路及显示装置

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Cited By (1)

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US20230116413A1 (en) * 2020-03-31 2023-04-13 Tcl China Star Optoelectronics Technology Co., Ltd. Goa circuit and display panel

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CN109509459B (zh) * 2019-01-25 2020-09-01 深圳市华星光电技术有限公司 Goa电路及显示装置
CN111402828A (zh) * 2020-04-09 2020-07-10 深圳市华星光电半导体显示技术有限公司 Goa电路和显示面板
CN112967646B (zh) * 2020-11-11 2022-12-16 重庆康佳光电技术研究院有限公司 低电平有效的goa单元和显示屏
CN113889018B (zh) * 2021-10-18 2023-07-04 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN114203112B (zh) * 2021-12-29 2023-07-25 深圳市华星光电半导体显示技术有限公司 Goa电路、显示面板以及显示设备
CN114842786A (zh) * 2022-04-26 2022-08-02 Tcl华星光电技术有限公司 Goa电路及显示面板
CN114758635B (zh) * 2022-04-27 2023-07-25 Tcl华星光电技术有限公司 Goa电路及显示面板
CN115171619B (zh) * 2022-07-20 2023-07-07 长沙惠科光电有限公司 扫描驱动电路、阵列基板和显示面板
CN116343706A (zh) * 2023-03-27 2023-06-27 惠科股份有限公司 扫描驱动电路和显示面板

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