WO2020151087A1 - 一种低反向恢复电荷sj-vdmos器件 - Google Patents

一种低反向恢复电荷sj-vdmos器件 Download PDF

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WO2020151087A1
WO2020151087A1 PCT/CN2019/081815 CN2019081815W WO2020151087A1 WO 2020151087 A1 WO2020151087 A1 WO 2020151087A1 CN 2019081815 W CN2019081815 W CN 2019081815W WO 2020151087 A1 WO2020151087 A1 WO 2020151087A1
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region
epitaxial layer
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low
type epitaxial
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孙伟锋
李阿江
李少红
张龙
祝靖
陆生礼
时龙兴
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Southeast University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate

Definitions

  • the invention relates to a power semiconductor device, in particular to a low reverse recovery charge SJ-VDMOS device.
  • VDMOS Vertical diffusion field effect transistors
  • SJ-VDMOS super junction-vertical diffusion field effect transistor
  • SJ-VDMOS body diode as a freewheeling diode usually has the problem of excessive reverse recovery charge Q rr and excessive reverse recovery current peak value I rrm . Excessive I rrm will cause oscillation during high-speed switching and cause electromagnetic interference. This shortcoming limits the application of super-junction power MOSFETs in hard-switching circuits. Generally, reducing the reverse recovery charge Q rr can effectively reduce the reverse recovery current peak value I rrm . Therefore, reducing the reverse recovery charge of the SJ-VDMOS body diode is an urgent problem in the current engineering field.
  • the present invention proposes a low reverse recovery charge SJ-VDMOS device.
  • This structure can significantly reduce the reverse recovery charge Q of the SJ-VDMOS body diode while maintaining low leakage, high breakdown voltage and low production cost.
  • rr and the reverse recovery current peak value I rrm thereby reducing the power consumption and electromagnetic interference (EMI) of the device during the reverse recovery period, and further improving the reliability of the device.
  • EMI electromagnetic interference
  • a low reverse recovery charge SJ-VDMOS device comprising: an N+ type substrate as a drain region.
  • a first metal drain electrode is provided on the lower surface of the N+ type substrate and used as the drain of the SJ-VDMOS device of the present invention.
  • An N-type epitaxial layer is provided on the bottom, a P-type epitaxial layer is provided on the N-type epitaxial layer, a longitudinal trench gate is provided in the P-type epitaxial layer, and the longitudinal trench gate is located between adjacent P pillars
  • a first metal gate electrode is provided on the surface of the vertical trench gate and used as the gate of the SJ-VDMOS device of the present invention, on the P-type epitaxial layer between adjacent vertical trench gates
  • a first P+ region and a first N+ region are provided, and a first metal source electrode is provided on the surface of the first P+ region and the first N+ region.
  • a SiO2 isolation layer is provided in the P-type epitaxial layer.
  • the SiO2 isolation layer isolates and forms a low-voltage PMOS region in the P-type epitaxial layer.
  • a low-voltage PMOS tube is arranged in the low-voltage PMOS region.
  • the low-voltage PMOS tube includes an N-type region, and a P+ region is provided on one side of the N-type region.
  • the second P+ region and the second N+ region are provided on the other side of the N-type region, and the second metal source electrode is provided above the second P+ region and the second N+ region and serves as the source of the SJ-VDMOS device of the present invention.
  • a second metal drain electrode is provided above the P+ region, and a gate oxide layer and a horizontal polysilicon gate are provided on the surface of the N-type region.
  • the horizontal polysilicon gate is connected to the second metal drain electrode and each first metal source electrode, and is connected to the P-type epitaxy.
  • the layer surface is provided with an interlayer isolation medium.
  • the described low reverse recovery charge SJ-VDMOS device is characterized in that the thickness of the SiO2 isolation layer is
  • the described SJ-VDMOS device with low reverse recovery charge is characterized in that the distance T between the bottom of the SiO2 isolation layer and the surface of the N-type epitaxial layer should be greater than 1 ⁇ m.
  • the described low reverse recovery charge SJ-VDMOS device is characterized in that the horizontal polysilicon gate induces holes on the surface of the N-type region.
  • The absolute value of the threshold voltage of the inversion layer
  • is higher than that of the vertical trench gate
  • the threshold voltage V thN of the electron inversion layer is induced on the surface of the P-type epitaxial layer.
  • the present invention has the following advantages:
  • the structure of the present invention can significantly reduce the reverse recovery charge Q rr and the reverse recovery current peak value I rrm .
  • the half-bridge topology circuit is shown in Figure 4, where M1 and M2 are the upper and lower switch tubes of the bridge arm respectively.
  • M1 and M2 are the upper and lower switch tubes of the bridge arm respectively.
  • the reverse recovery charge Q rr and the reverse recovery current peak value I rrm generated by the switch tubes during the reverse recovery process are relatively large.
  • the SJ-VDMOS device proposed by the present invention is used as the upper and lower switch tubes M1 and M2 of the bridge arm, in the freewheeling stage of the upper tube M1, the freewheeling current flows through the low-voltage PMOS in the low-voltage PMOS region 12 After the tube, part of the electron current flows to the electron channel formed by the vertical trench gate 5 on the surface of the P-type epitaxial layer 4, and the rest flows to the body composed of the P-type epitaxial layer 4, the P pillar 6 and the N-type epitaxial layer 3. diode. At this time, the current freewheeling path of the upper tube M1 is shown in Figure 7, and the current flowing through the body diode during the freewheeling period is significantly reduced.
  • the total amount of minority carriers injected by the P-type epitaxial layer 4 and the P pillar 6 into the N-type epitaxial layer 3 is significantly reduced, and the reverse recovery charge Q rr is significantly reduced, and the reverse recovery current peak value I rrm decreases.
  • the structure of the present invention has good pressure resistance.
  • the present invention isolates the low-voltage PMOS region 12 from other regions of the device through the SiO2 isolation layer 11, which can completely eliminate the adverse effects of the leakage of the low-voltage PMOS region 12 on the withstand voltage of the drift region of the device.
  • the distance T between the bottom of the SiO2 isolation layer 11 and the surface of the N-type epitaxial layer 3 in the structure of the present invention is greater than 1 ⁇ m, which can ensure that the N-type epitaxial layer 3 and the P pillar 6 and the P-type epitaxial layer 4 under the low-voltage PMOS region 12 are sufficient Depletion, thereby ensuring the charge balance of the drift region of the device.
  • the SJ-VDMOS device proposed by the present invention has the same withstand voltage capability as the traditional SJ-VDMOS device.
  • the low-voltage PMOS tube provided in the low-voltage PMOS area in the structure of the present invention has the ability to turn on itself during the freewheeling phase, and no additional gate drive circuit is needed.
  • the horizontal polysilicon gate 20 of the low-voltage PMOS transistor is short-circuited with the second metal drain electrode 18, and the N-type region 13 is short-circuited with the second metal source electrode 17.
  • the freewheeling state is in charge, the M2 tube is turned off, and the source potential of the M1 tube rises rapidly and generates an overshoot voltage higher than V BUS , that is, the potential of the second metal source electrode 17 rises rapidly and generates a voltage higher than V
  • the overshoot voltage of the BUS and the overshoot voltage of the second metal source electrode 17 make the potential of the N-type region 13 higher than the horizontal polysilicon gate 20.
  • the threshold of the low-voltage PMOS transistor When the voltage is applied, the low-voltage PMOS tube forms a hole channel, and the low-voltage PMOS tube turns on by itself.
  • Figure 1 shows a schematic diagram of the traditional SJ-VDMOS device structure.
  • FIG. 2 is a schematic diagram of the structure of the SJ-VDMOS device proposed by the present invention.
  • Figure 3(a) is a schematic diagram of the equivalent circuit of the SJ-VDMOS device proposed by the present invention.
  • Fig. 3(b) shows an equivalent circuit diagram of the forward conduction phase of the SJ-VDMOS device proposed by the present invention.
  • Figure 4 shows a schematic diagram of a half-bridge topology circuit
  • Figure 5 shows the equivalent circuit of the half-bridge topology using the SJ-VDMOS device proposed by the present invention as a switch tube.
  • Figure 6 shows the gate drive signals of the switches M1 and M2 in the half-bridge circuit.
  • FIG. 7 shows the equivalent circuit diagram and the schematic diagram of the freewheeling current path during the freewheeling period of the upper tube M1.
  • FIG. 8 is a comparison diagram of reverse recovery characteristic curves between the structure proposed by the present invention and the traditional structure.
  • Fig. 9 is a comparison diagram of the withstand voltage characteristics of the structure proposed by the present invention and the traditional structure.
  • a low reverse recovery charge SJ-VDMOS device includes: an N+ type substrate 1 as a drain region. The lower surface of the N+ type substrate 1 is provided with a first metal drain electrode 2 and serves as the drain of the SJ-VDMOS device of the present invention.
  • An N-type epitaxial layer 3 is provided on the N+ type substrate 1
  • a P-type epitaxial layer 4 is provided on the N-type epitaxial layer 3
  • a vertical trench gate 5 is provided in the P-type epitaxial layer 4
  • the vertical The trench gate 5 is located above the N-type epitaxial layer 3 between adjacent P pillars 6, and a first metal gate electrode 7 is provided on the surface of the vertical trench gate 5 and serves as the gate of the SJ-VDMOS device of the present invention.
  • a first P+ region 8 and a first N+ region 9 are provided on the P-type epitaxial layer 4 between adjacent vertical trench gates 5, and a first metal source is provided on the surface of the first P+ region 8 and the first N+ region 9
  • the electrode 10 is characterized in that a SiO2 isolation layer 11 is provided in the P-type epitaxial layer 4, and the SiO2 isolation layer 11 isolates and forms a low-voltage PMOS region 12 in the P-type epitaxial layer.
  • a low-voltage PMOS tube is provided in 12, the low-voltage PMOS tube includes an N-type region 13, a P+ region 14 is provided on one side of the N-type region 13, and a second P+ region 15 and a second N+ are provided on the other side of the N-type region 13
  • a second metal source electrode 17 is provided above the second P+ region 15 and the second N+ region 16 and serves as the source of the SJ-VDMOS device of the present invention.
  • a second metal drain electrode 18 is provided above the P+ region 14.
  • the surface of the N-type region 13 is provided with a gate oxide layer 19 and a horizontal polysilicon gate 20.
  • the horizontal polysilicon gate 20 is connected to the second metal drain electrode 18 and each first metal source electrode 10, and a layer is provided on the surface of the P-type epitaxial layer 4. Between the isolation medium 21.
  • the first metal gate electrode 7 is connected to a positive voltage
  • the first metal drain electrode 2 is connected to a positive voltage
  • the second metal source electrode 17 is grounded.
  • the vertical trench gate 5 forms an electron channel on the surface of the P-type epitaxial layer 4.
  • the first metal drain electrode 2 and the first metal source electrode 10 are connected through the electron channel. At this time, the potential of the first metal source electrode 10 will follow The potential of the first metal drain electrode 2 rises.
  • the second metal source electrode 17 of the low-voltage PMOS tube is grounded, and the horizontal polysilicon gate 20 of the low-voltage PMOS tube is shorted to the second metal drain electrode 18 and each first metal source electrode 10, so the potential of the horizontal polysilicon gate 20 is higher than that of the second metal
  • the potential of the source electrode 17, at this time the channel of the low-voltage PMOS is closed, and the low-voltage PMOS transistor is in the off state.
  • the P+ region 14, the N-type region 13, and the second N+ region 16 in the low-voltage PMOS region constitute the body diode of the low-voltage PMOS transistor.
  • the N+ type substrate 1, the N type epitaxial layer 3, the P pillar 6, the P type epitaxial layer 4, the longitudinal trench gate 5, and the first P+ region 8 and the first N+ region 9 of the present invention can constitute a traditional SJ-VDMOS tube.
  • the SJ-VDMOS device proposed by the present invention can be equivalently regarded as a series connection of a traditional SJ-VDMOS tube and a low-voltage PMOS tube.
  • FIG. 3 The corresponding equivalent circuit diagram is shown in Figure 3(a), where Figure 3(a) The gate G of the traditional SJ-VDMOS tube corresponds to the first metal gate electrode 7 in Figure 2; the drain D of the traditional SJ-VDMOS tube in Figure 3(a) corresponds to the first metal drain electrode 2 in Figure 2; Figure 3( a) traditional source SJ-VDMOS transistor is a source S of the first metal electrode 10 corresponds to FIG. 2; FIG. 3 the drain D P (a) low-voltage PMOS transistor in FIG. 2 corresponding to the second metal 18 drain electrode; Figure 3 (a), the gate G P corresponding to the low voltage PMOS transistor of FIG.
  • FIG. 3b the current path of the forward conduction of the SJ-VDMOS device proposed by the present invention in the forward conduction phase is shown in FIG. 3b.
  • the half-bridge topology circuit is shown in Figure 4, where M1 and M2 are the upper and lower switch tubes of the bridge arm respectively.
  • M1 and M2 are the upper and lower switch tubes of the bridge arm respectively.
  • the SJ-VDMOS proposed in the present invention is used as the upper and lower switch tubes M1 and M2 of the bridge arm
  • the SJ-VDMOS device proposed in the present invention is regarded as a string of a traditional SJ-VDMOS tube and a low-voltage PMOS tube Connection form
  • the equivalent circuit of the half-bridge topology is shown in Figure 5.
  • the gate drive signals of the M1 and M2 tubes during the period t 0 to t 5 are shown in Figure 6.
  • time t 1 the tube is in forward conduction M2 operating state, the inductor current through M2 tube.
  • the overshoot voltage makes the potential of the second metal source electrode 17 higher than the potential of the horizontal polysilicon gate 20 and the second metal drain electrode 18, that is, a negative voltage is generated between the second metal source electrode 17 of the low-voltage PMOS tube and the horizontal polysilicon gate 20.
  • the potential difference ⁇ V GS1 The first metal gate electrode 7 is short-circuited with the second metal source electrode 17, and the first metal source electrode 10 is short-circuited with the second metal drain electrode 18. There is a gap between the first metal gate electrode 7 and the first metal source electrode 10.
  • the horizontal polysilicon gate 20 induces the absolute value of the threshold voltage of the hole inversion layer on the surface of the N-type region 13
  • the threshold voltage is V thN , so the vertical trench gate 5 forms an electron channel in the P-type epitaxial layer 4, and the first metal drain electrode 2 and the first metal source electrode 10 are connected through the electron channel, that is, the traditional SJ -VDMOS tube is turned on.
  • the structure of the present invention has significantly improved reverse recovery current peak value I rrm and reverse recovery charge Q rr .

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Abstract

一种低反向恢复电荷SJ-VDMOS器件，包括N+型衬底，在其下表面设有第一金属漏电极，N+型衬底上方设有N型外延层、P型外延层和P柱，P型外延层内设有纵向沟槽栅，P型外延层表面设有第一P+区域及第一N+区域并且设有第一金属源电极和第一金属栅电极，其特征在于，P型外延层内设有SiO2隔离层以隔离形成低压PMOS区并在其内置有低压PMOS管，低压PMOS管包括N型区域，N型区域一侧设有P+区域及第二金属漏电极，另一侧设有第二P+区域、第二N+区域及第二金属源电极，N型区域表面设有栅氧及横向多晶硅栅，横向多晶硅栅与第二金属漏电极及各第一金属源电极连接，P型外延层表面设有层间隔离介质。本发明通过引入电子沟道续流机制，显著降低反向恢复电荷Qrr。

Description

一种低反向恢复电荷SJ-VDMOS器件 技术领域
本发明涉及一种功率半导体器件，特别是涉及一种低反向恢复电荷SJ-VDMOS器件。
背景技术
垂直扩散场效应晶体管(VDMOS)具有开关速度快、输入阻抗高、频率特性好等优点被越来越多的应用于三相桥式电路、逆变器、智能功率模块和电子镇流器等领域当中。其中超结-垂直扩散场效应晶体管(SJ-VDMOS)因为漂移区采用P柱和N柱交替设置的结构，从而突破了传统的“硅极限”，使得器件同时具备极高的反向击穿电压和极低的正向导通电阻。
采用SJ-VDMOS的体二极管作为续流二极管通常存在反向恢复电荷Q rr过大以及反向恢复电流峰值I rrm过高的问题，过高的I rrm在高速开关过程中会引起振荡，产生电磁干扰。这一缺点限制了超结功率MOSFET在硬开关电路中的应用。通常降低反向恢复电荷Q rr可以有效减小反向恢复电流峰值I rrm。所以降低SJ-VDMOS体二极管的反向恢复电荷是当前工程领域急需解决的难题。
一些降低SJ-VDMOS体二极管反向恢复电荷的技术方案相继被提出，比如采用寿命控制技术，通过采用电子辐照或者重金属掺杂等手段，减小存储载流子的寿命，从而减小反向恢复电荷Q rr。但是这种方案成本较高，并且也会带来漏电增大、击穿电压降低等不利影响。另外一种方案是使用SiC代替SJ-VDMOS的体二极管作为续流二极管。SiC二极管具有单极性导电的特点，所以可实现反向恢复电荷Q rr≈0。但是这种方法成本较高，实际工程中没有较多实用价值。
发明内容
本发明针对上述问题，提出一种低反向恢复电荷SJ-VDMOS器件，该结构在保持低漏电、高击穿电压和低生产成本的同时，显著减小SJ-VDMOS体二极管反向恢复电荷Q rr及反向恢复电流峰值I rrm，从而减小了器件在反向恢复期间的功耗以及电磁干扰(EMI)，进一步提高了器件的可靠性。
本发明的技术方案如下：
一种低反向恢复电荷SJ-VDMOS器件，包括：作为漏区的N+型衬底，N+型衬底下表面设有第一金属漏电极并作为本发明SJ-VDMOS器件漏极，在N+型衬底上设有N型外延层，在N型外延层上设有P型外延层，在所述P型外延层内设有纵向沟槽栅且所 述纵向沟槽栅位于相邻P柱之间的N型外延层上方，在所述纵向沟槽栅的表面设有第一金属栅电极并作为本发明SJ-VDMOS器件的栅极，在相邻纵向沟槽栅之间的P型外延层上设有第一P+区域及第一N+区域，在第一P+区域和第一N+区域表面设有第一金属源电极，其特征在于，在所述P型外延层内设有SiO2隔离层，由所述SiO2隔离层在P型外延层内隔离并形成低压PMOS区，在所述低压PMOS区内设置低压PMOS管，所述低压PMOS管包括N型区域，在N型区域一侧设有P+区域，在N型区域另一侧设有第二P+区域及第二N+区域，在第二P+区域及第二N+区域上方设有第二金属源电极并作为本发明SJ-VDMOS器件源极，在P+区域上方设有第二金属漏电极，在N型区域表面设有栅氧化层及横向多晶硅栅，所述横向多晶硅栅与第二金属漏电极及各第一金属源电极连接，在P型外延层表面设有层间隔离介质。
所述的一种低反向恢复电荷SJ-VDMOS器件，其特征在于，SiO2隔离层的厚度为
Figure PCTCN2019081815-appb-000001
所述的一种低反向恢复电荷SJ-VDMOS器件，其特征在于，SiO2隔离层底部与N型外延层表面之间距离T应大于1μm。
所述的一种低反向恢复电荷SJ-VDMOS器件，其特征在于，横向多晶硅栅在N型区域表面感应出空穴反型层的阈值电压的绝对值|V thP|高于纵向沟槽栅在P型外延层表面感应出电子反型层的阈值电压V thN。
与现有技术相比，本发明具有如下优点：
(1)本发明结构可以显著降低反向恢复电荷Q rr以及反向恢复电流峰值I rrm。半桥拓扑电路如图4所示，其中M1和M2分别是桥臂的上、下两个开关管。当采用传统SJ-VDMOS作为桥臂的开关管M1和M2时，开关管在经历反向恢复过程中产生的反向恢复电荷Q rr以及反向恢复电流峰值I rrm较大。当采用本发明所提出的SJ-VDMOS器件作为桥臂的上、下两个开关管M1和M2时，在上管M1管续流阶段，续流电流在流过低压PMOS区12中的低压PMOS管之后，一部分以电子电流的形式流向纵向沟槽栅5在P型外延层4表面形成的电子沟道，其余部分流向由P型外延层4以及P柱6与N型外延层3构成的体二极管。此时上管M1的电流续流路径如图7所示，续流期间流经体二极管的电流明显减小。所以续流期间，P型外延层4以及P柱6向N型外延层3中注入的少数载流子总量明显减少，进而反向恢复电荷Q rr明显减少，并且使得反向恢复电流峰值I rrm减小。
(2)本发明结构具备良好的耐压性能。本发明通过SiO2隔离层11将低压PMOS区12与器件其他区域隔离开来，可以完全消除低压PMOS区12的漏电对器件漂移区耐 压产生的不良影响。此外本发明结构中SiO2隔离层11底部与N型外延层3表面之间的距离T大于1μm，这样可以保证低压PMOS区12下方的N型外延层3与P柱6及P型外延层4充分耗尽，从而保证了器件漂移区的电荷平衡。如图9所示，本发明所提出的SJ-VDMOS器件与传统SJ-VDMOS器件具备相同的耐压能力。
(3)本发明结构中低压PMOS区设置的低压PMOS管在续流阶段具有自开启的能力，无需额外的栅极驱动电路。低压PMOS管的横向多晶硅栅20与第二金属漏电极18短接，N型区域13与第二金属源电极17短接。在半桥驱动电路上管续流状态，M2管关闭，M1管的源极电位迅速抬升并产生高于V BUS的过冲电压，即第二金属源电极17的电位迅速抬升并产生高于V BUS的过冲电压，第二金属源电极17的过冲电压使得N型区域13的电位高于横向多晶硅栅20，当横向多晶硅栅20与N型区域13之间的电压差达到低压PMOS管阈值电压时，低压PMOS管形成空穴沟道，低压PMOS管自行导通。
附图说明
图1所示为传统SJ-VDMOS器件结构示意图。
图2所示为本发明所提出的SJ-VDMOS器件结构示意图。
图3(a)所示为本发明所提出的SJ-VDMOS器件的等效电路示意图。
图3(b)所示为本发明所提出的SJ-VDMOS器件正向导通阶段等效电路图。
图4所示为半桥拓扑电路示意图
图5所示为采用本发明所提出的SJ-VDMOS器件作为开关管的半桥拓扑结构的等效电路。
图6所示为半桥电路中开关管M1及M2的栅极驱动信号。
图7所示为上管M1管续流期间的等效电路图及续流电流路径示意图。
图8所示为本发明所提出的结构与传统结构反向恢复特性曲线对比图。
图9所示为本发明所提出的结构与传统结构耐压特性对比图。
具体实施方式
下面结合附图，详细描述本发明的技术方案：
一种低反向恢复电荷SJ-VDMOS器件，包括：作为漏区的N+型衬底1，N+型衬底1下表面设有第一金属漏电极2并作为本发明SJ-VDMOS器件漏极，在N+型衬底1上设有N型外延层3，在N型外延层3上设有P型外延层4，在所述P型外延层4内设有纵向沟槽栅5且所述纵向沟槽栅5位于相邻P柱6之间的N型外延层3上方，在所述纵 向沟槽栅5的表面设有第一金属栅电极7并作为本发明SJ-VDMOS器件的栅极，在相邻纵向沟槽栅5之间的P型外延层4上设有第一P+区域8及第一N+区域9，在第一P+区域8和第一N+区域9表面设有第一金属源电极10，其特征在于，在所述P型外延层4内设有SiO2隔离层11，由所述SiO2隔离层11在P型外延层内隔离并形成低压PMOS区12，在所述低压PMOS区12内设置低压PMOS管，所述低压PMOS管包括N型区域13，在N型区域13一侧设有P+区域14，在N型区域13另一侧设有第二P+区域15及第二N+区域16，在第二P+区域15及第二N+区域16上方设有第二金属源电极17并作为本发明SJ-VDMOS器件源极，在P+区域14上方设有第二金属漏电极18，在N型区域13表面设有栅氧化层19及横向多晶硅栅20，所述横向多晶硅栅20与第二金属漏电极18及各第一金属源电极10连接，在P型外延层4表面设有层间隔离介质21。
下面结合附图对本发明进行进一步说明。
本发明的工作原理：
当本发明所提出的SJ-VDMOS器件处于正向导通工作状态，第一金属栅电极7接正压，第一金属漏电极2接正压，第二金属源电极17接地。纵向沟槽栅5在P型外延层4表面形成电子沟道，第一金属漏电极2与第一金属源电极10通过电子沟道接通，此时第一金属源电极10的电位会随着第一金属漏电极2电位的抬升而抬升。低压PMOS管的第二金属源电极17接地，低压PMOS管的横向多晶硅栅20与第二金属漏电极18以及各第一金属源电极10短接，所以横向多晶硅栅20的电位高于第二金属源电极17的电位，此时低压PMOS的沟道关闭，低压PMOS管处于关闭状态。低压PMOS区中的P+区域14、N型区域13以及第二N+区域16构成低压PMOS管的体二极管。因低压PMOS管的第二金属源电极17接地，当低压PMOS管的第二金属漏电极18的电位跟随第一金属源电极10的电位抬升至0.7V以上时，低压PMOS管的体二极管导通，进而本发明器件进入正向导通工作状态。本发明的N+型衬底1、N型外延层3、P柱6、P型外延层4、纵向沟槽栅5以及第一P+区域8和第一N+区域9可构成传统SJ-VDMOS管，并且本发明器件在P型外延层4内通过SiO2隔离层11隔离出一个低压PMOS区12,该低压PMOS区12内设有一个低压PMOS管。所以本发明所提出的SJ-VDMOS器件可等效视为传统SJ-VDMOS管与低压PMOS管的串联形式，对应的等效电路示意图如图3(a)所示，其中图3(a)中传统SJ-VDMOS管的栅极G对应图2中的第一金属栅电极7；图3(a)中传统SJ-VDMOS管的漏极D对应图2中第一金属漏电极2；图3(a)中传统SJ-VDMOS管的源极S对应图2中的第一金属源电极10；图3(a)中低压PMOS管的漏极D P对应图2中的第二金属漏电极18；图3(a)中低压PMOS管的栅 极G P对应图2中的横向多晶硅栅20；图3(a)中低压PMOS管的源极S P及衬底电极B P对应图2(b)中的第二金属源电极17。因此本发明所提出的SJ-VDMOS器件处于正向导通阶段正向导通的电流路径如图3b所示。
半桥拓扑电路如图4所示，其中M1和M2分别是桥臂的上、下两个开关管。当采用本发明所提出的SJ-VDMOS作为桥臂的上、下两个开关管M1和M2时，若将本发明所提出的SJ-VDMOS器件视为传统SJ-VDMOS管与低压PMOS管的串接形式，此时半桥拓扑结构的等效电路如图5所示。假设M1和M2管在t 0～t 5阶段的栅极驱动信号如图6所示。t 1时刻，M2管处于正向导通工作状态，电感电流经过M2管。t 2时刻M2管关闭，M1管的第二金属源电极17的电位迅速抬升并在电感作用下产生高于V BUS的过冲电压。该过冲电压使得第二金属源电极17的电位高于横向多晶硅栅20及第二金属漏电极18的电位，即在低压PMOS管第二金属源电极17与横向多晶硅栅20之间产生一个负的电势差ΔV GS1。第一金属栅电极7与第二金属源电极17短接，并且第一金属源电极10与第二金属漏电极18短接，第一金属栅电极7与第一金属源电极10之间存在一个正的电势差ΔV GS2，并且ΔV GS2＝–ΔV GS1。当横向多晶硅栅20与第二金属源电极17之间电位差ΔV GS1达到低压PMOS管的阈值电压，即满足条件|ΔV GS1|>|V thP|时，低压PMOS管导通。又因为横向多晶硅栅20在N型区域13表面感应出空穴反型层的阈值电压的绝对值|V thP|高于纵向沟槽栅5在P型外延层4表面感应出电子反型层的阈值电压V thN，，故此时纵向沟槽栅5在P型外延层4中形成电子沟道，第一金属漏电极2与第一金属源电极10通过电子沟道接通，即此时传统SJ-VDMOS管导通。所以续流电流在经过低压PMOS管之后，一部分以电子电流的形式流向纵向沟槽栅5在P型外延层4表面形成的电子沟道，进而流向第一金属漏电极2，其余的续流电流流向由P型外延层4以及P柱6和N型外延层3构成的体二极管。此时上管M1的电流续流路径如图7所示，续流期间流经体二极管的电流明显减小。所以在上管M1管续流期间，P型外延层4以及P柱6向N型外延层3中的少数载流子总量明显减少，进而反向恢复电荷Q rr明显减少，反向恢复电流峰值I rrm减小。如图8所示，本发明所提结构相比于传统SJ-VDMOS结构，其反向恢复电流峰值I rrm与反向恢复电荷Q rr均得到明显改善。

Claims (4)

  1. 一种低反向恢复电荷SJ-VDMOS器件，包括：作为漏区的N+型衬底(1)，N+型衬底(1)下表面设有第一金属漏电极(2)并作为本发明SJ-VDMOS器件漏极，在N+型衬底(1)上设有N型外延层(3)，在N型外延层(3)上设有P型外延层(4)，在所述P型外延层(4)内设有纵向沟槽栅(5)且所述纵向沟槽栅(5)位于相邻P柱(6)之间的N型外延层(3)上方，在所述纵向沟槽栅(5)的表面设有第一金属栅电极(7)并作为本发明SJ-VDMOS器件的栅极，在相邻纵向沟槽栅(5)之间的P型外延层(4)上设有第一P+区域(8)及第一N+区域(9)，在第一P+区域(8)和第一N+区域(9)表面设有第一金属源电极(10)，其特征在于，在所述P型外延层(4)内设有SiO2隔离层(11)，由所述SiO2隔离层(11)在P型外延层内隔离并形成低压PMOS区(12)，在所述低压PMOS区(12)内设置低压PMOS管，所述低压PMOS管包括N型区域(13)，在N型区域(13)一侧设有P+区域(14)，在N型区域(13)另一侧设有第二P+区域(15)及第二N+区域(16)，在第二P+区域(15)及第二N+区域(16)上方设有第二金属源电极(17)并作为本发明SJ-VDMOS器件源极，在P+区域(14)上方设有第二金属漏电极(18)，在N型区域(13)表面设有栅氧化层(19)及横向多晶硅栅(20)，所述横向多晶硅栅(20)与第二金属漏电极(18)及各第一金属源电极(10)连接，在P型外延层(4)表面设有层间隔离介质(21)。
  2. 根据权利要求1所述的一种低反向恢复电荷SJ-VDMOS器件，其特征在于，SiO2隔离层(11)的厚度为
    Figure PCTCN2019081815-appb-100001
  3. 根据权利要求1所述的一种低反向恢复电荷SJ-VDMOS器件，其特征在于，SiO2隔离层(11)底部与N型外延层(3)表面之间的距离T应大于1μm。
  4. 根据权利要求1所述的一种低反向恢复电荷SJ-VDMOS器件，其特征在于，横向多晶硅栅(20)在N型区域(13)表面感应出空穴反型层的阈值电压的绝对值|V thP|高于纵向沟槽栅(5)在P型外延层(4)表面感应出电子反型层的阈值电压V thN。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115939215A (zh) * 2022-12-16 2023-04-07 广微集成技术（深圳）有限公司 一种vdmos器件
CN116153929A (zh) * 2022-12-13 2023-05-23 无锡中微晶园电子有限公司 一种嵌入三维堆叠Trench MOS的功率集成器件

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611749B (zh) * 2021-08-16 2025-02-21 上海道之科技有限公司 一种改善反向恢复特性的超结mosfet器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050040490A1 (en) * 2003-08-19 2005-02-24 Park Nam Kyu Transistor in semiconductor device and method of manufacturing the same
CN103441148A (zh) * 2013-08-13 2013-12-11 电子科技大学 一种集成肖特基二极管的槽栅vdmos器件
CN103560151A (zh) * 2013-10-18 2014-02-05 西安龙腾新能源科技发展有限公司 优化体二极管反向恢复特性的超结vdmos及制备方法
CN108091683A (zh) * 2017-12-11 2018-05-29 深圳迈辽技术转移中心有限公司 半导体功率器件的超结结构及其制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5650561B2 (ja) * 2011-02-24 2015-01-07 株式会社豊田中央研究所 半導体装置
WO2017130374A1 (ja) * 2016-01-29 2017-08-03 新電元工業株式会社 パワー半導体装置及びパワー半導体装置の製造方法
CN107359190A (zh) * 2017-07-12 2017-11-17 长沙方星腾电子科技有限公司 一种低压工艺中的高压pmos晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050040490A1 (en) * 2003-08-19 2005-02-24 Park Nam Kyu Transistor in semiconductor device and method of manufacturing the same
CN103441148A (zh) * 2013-08-13 2013-12-11 电子科技大学 一种集成肖特基二极管的槽栅vdmos器件
CN103560151A (zh) * 2013-10-18 2014-02-05 西安龙腾新能源科技发展有限公司 优化体二极管反向恢复特性的超结vdmos及制备方法
CN108091683A (zh) * 2017-12-11 2018-05-29 深圳迈辽技术转移中心有限公司 半导体功率器件的超结结构及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116153929A (zh) * 2022-12-13 2023-05-23 无锡中微晶园电子有限公司 一种嵌入三维堆叠Trench MOS的功率集成器件
CN115939215A (zh) * 2022-12-16 2023-04-07 广微集成技术（深圳）有限公司 一种vdmos器件

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