WO2020151056A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2020151056A1
WO2020151056A1 PCT/CN2019/077346 CN2019077346W WO2020151056A1 WO 2020151056 A1 WO2020151056 A1 WO 2020151056A1 CN 2019077346 W CN2019077346 W CN 2019077346W WO 2020151056 A1 WO2020151056 A1 WO 2020151056A1
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Prior art keywords
layer
via hole
aperture
film transistor
color resist
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French (fr)
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朱峰
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof.
  • the moisture introduced by the Q-time (waiting time) and cleaning after the color resist process will cause the water vapor in the color resist material to reach a saturated state, which will cause the electrical degradation of the device.
  • a passivation layer is also formed on the color resist due to the COA process to prevent the subsequent dry etching process from damaging the surface of the color resist. Therefore, the passivation layer hinders the discharge of water vapor in the color resist, resulting in severe degradation of the performance of the TFT device.
  • the moisture introduced by the Q-time (waiting time) and cleaning after the color resist process will cause the water vapor in the color resist material to reach a saturated state, which will cause the electrical degradation of the device.
  • a passivation layer is also formed on the color resist due to the COA process to prevent the subsequent dry etching process from damaging the surface of the color resist. Therefore, the passivation layer hinders the discharge of water vapor in the color resist, resulting in severe degradation of the performance of the TFT device.
  • the object of the present invention is to provide an array substrate and a manufacturing method thereof, which realize the via holes on the passivation layer by controlling the thickness of the photoresist or adjusting the etching process parameters, and ensure that the water vapor in the color resist layer can be removed from the color resist layer during the subsequent baking process. Via discharge, effectively reducing the problem of display device performance degradation.
  • the present invention provides an array substrate including a substrate, a thin film transistor device, a color resist layer, a passivation layer and a pixel electrode layer.
  • Thin film transistor devices are provided on the substrate.
  • the color resistance layer covers the thin film transistor device, and the color resistance layer is provided with grooves.
  • the passivation layer covers the color resist layer and covers the surface of the groove.
  • the pixel electrode layer is disposed on the passivation layer, wherein the passivation layer is provided with a first via hole and at least one second via hole, and the pixel electrode layer passes through the first via hole and the thin film transistor
  • the metal electrode of the device is electrically connected, the at least one second via hole exposes the color resist layer, wherein the at least one second via hole is located on the groove, and the groove includes a first aperture and a second aperture. Aperture, the first aperture is smaller than the second aperture.
  • the number of the second via holes is one or more.
  • it further includes a flat layer disposed between the thin film transistor device and the color resist layer.
  • the invention also provides an array substrate including a substrate, a thin film transistor device, a color resist layer, a passivation layer and a pixel electrode layer.
  • Thin film transistor devices are provided on the substrate.
  • the color resistance layer covers the thin film transistor device, and the color resistance layer is provided with grooves.
  • the passivation layer covers the color resist layer and covers the surface of the groove.
  • the pixel electrode layer is disposed on the passivation layer, wherein the passivation layer is provided with a first via hole and at least one second via hole, and the pixel electrode layer passes through the first via hole and the thin film transistor
  • the metal electrodes of the device are electrically connected, the at least one second via hole exposes the color resist layer, and the at least one second via hole is located on the groove.
  • the groove includes a first aperture and a second aperture, and the first aperture is smaller than the second aperture.
  • the number of the second via holes is one or more.
  • it further includes a flat layer disposed between the thin film transistor device and the color resist layer.
  • the present invention also provides a manufacturing method of an array substrate, including the following steps:
  • the pixel electrode layer is electrically connected to the metal electrode of the thin film transistor device through the first via hole, and the at least one second via hole exposes the color resist layer.
  • step S40 a photoresist is coated on the passivation layer and etched after exposure and development, wherein the etching process is dry etching (Dry Etching) process to form the first via hole and the second via hole.
  • the etching process is dry etching (Dry Etching) process to form the first via hole and the second via hole.
  • the photoresist in the groove is exposed and developed to form an opening, and then the photoresist is dried by the dry etching.
  • the first via hole is formed on the passivation layer.
  • part of the photoresist when the photoresist is coated on the passivation layer, part of the photoresist will flow down and become thinner along the two sidewalls of the groove, and then the dry etching , Thereby forming the at least one second via hole on the passivation layer.
  • the thickness of the photoresist coating is controlled to be between 1.5 and 2 microns (um), and the thickness of the color resist layer is between 0.5 and 3.5 microns (um).
  • the groove is formed in a trapezoidal shape, the groove includes a first aperture and a second aperture, the first aperture is smaller than the second aperture, and the first aperture is smaller than the second aperture.
  • the second aperture is farther away from the thin film transistor device than the first aperture.
  • the present invention can simply realize the via hole on the passivation layer without increasing the cost of the process equipment and other additional processes.
  • the process of the present invention such as photoresist thickness control, etching process parameter adjustment, etc.
  • via holes on the passivation layer are realized, thereby ensuring that the water vapor in the color resist layer can be discharged during the subsequent baking process, effectively reducing
  • the performance of the array substrate/display device is degraded to improve the performance and quality of the display device.
  • Figure 1 is a cross-sectional view of the array substrate of the present invention provided with a thin film transistor device on the base;
  • FIG. 2 is a cross-sectional view of the array substrate of the present invention having a color resist layer, a passivation layer and a coated photoresist on a thin film transistor device;
  • FIG. 3 is a cross-sectional view of the array substrate of the present invention etched with photoresist to form via holes on the passivation layer;
  • FIG. 4 is a cross-sectional view of the array substrate of the present invention provided with a pixel electrode layer on the passivation layer;
  • FIG. 5 is a diagram of an embodiment of implementing via holes on the passivation layer of the present invention.
  • Fig. 6 is a flow chart of the manufacturing method of the array substrate of the present invention.
  • the present invention provides an array substrate including a substrate 1, a thin film transistor device 2, a color resist layer 3, a passivation layer 4, and a pixel electrode layer 5.
  • the thin film transistor device 2 shown in FIG. 1 to FIG. 4 is preferably a Back Channel Etching (BCE) TFT structure.
  • the thin film transistor device 2 may also be an etch stop layer (Etch Stop Layer, ESL), a top gate coplanar type (Top Gate type) and other TFT structures are not limited. Since the above-mentioned TFT structure is a prior art, it will not be repeated here.
  • the thin film transistor device 2 is arranged on the substrate 1.
  • the color resist layer 3 covers the thin film transistor device 2, and the color resist layer 3 is provided with a groove 31 adjacent to the thin film transistor device 2.
  • the passivation layer 4 covers the color resist layer 3 and covers the surface of the groove 31.
  • the pixel electrode layer 5 is disposed on the passivation layer 4.
  • the passivation layer 4 is provided with a first via 41 and at least one second via 42.
  • the pixel electrode layer 5 is electrically connected to the metal electrode 21 of the thin film transistor device 2 through the first via 41, and the at least one second via 42 exposes the color resist layer 42, wherein the at least A second via 42 is located in the groove 31.
  • a via hole is formed on the passivation layer 4 to ensure that the water vapor in the color resist layer 3 can be discharged from the via hole 42, which effectively reduces the performance degradation of the display device, thereby improving the performance and quality of the display device, as shown in FIG.
  • the groove 31 includes a first aperture 311 and a second aperture 312.
  • the first aperture 311 is smaller than the second aperture 312, and the second aperture 312 is farther away from the thin film transistor device 2 than the first aperture 311.
  • the groove 31 shown in the figure is trapezoidal, cup-shaped or ring-shaped.
  • the number of the second via holes 42 is preferably one or more, and each of the second via holes 42 is symmetrical and disposed adjacent to the second aperture 312.
  • the number of the second via holes 42 may be one or more, and they are formed on the sidewall of the groove 31.
  • it further includes a flat layer 7 arranged between the thin film transistor device 2 and the color resist layer 3.
  • the material of the flat layer 7 is, for example, a polysilicon material.
  • the present invention also provides a manufacturing method of an array substrate, including the following steps: S10, providing a base 1; S20, preparing a thin film transistor device 2 on the base 1; S30, in the thin film transistor device 2 is coated with a color resist layer 3, the color resist layer 3 is adjacent to the thin film transistor device 2 to form a groove 31; and S40, a passivation layer 4 is deposited on the color resist layer 3, and along the groove The surface of the groove 31 is deposited, a photoresist 6 is coated on the passivation layer 4 and etched after exposure and development to form a first via 41 and at least one second via 42 in the passivation layer 4; And S50, depositing and patterning a pixel electrode layer 5 on the passivation layer 4; wherein the pixel electrode layer 5 is electrically connected to the metal electrode 21 of the thin film transistor device 2 through the first via 41, The at least one second via 42 exposes the color resist layer 3.
  • the groove 31 is formed to have a trapezoidal shape.
  • the groove 31 includes a first aperture 311 and a second aperture 312, the first aperture 311 is smaller than the second aperture 312, and the second aperture 312 is farther away from the thin film transistor device 2 than the first aperture 311 .
  • a photoresist 6 is coated on the passivation layer 4 and etched after exposure and development, wherein the etching process is dry etching (Dry Etching) process to form the first via 41 and the second via 42.
  • the coating thickness of the photoresist 6 can be controlled to be between 1.5 and 2 microns (um), preferably 1.8 microns (um).
  • the thickness of the color resist layer 3 is 0.5-3.5 micrometers (um).
  • the preferred etching process parameter adjustment for example, using CF4+O2 process gas, using reactive ion etching (RIE), dry etching for 150 seconds, etc., so that the thickness of the photoresist 6 above the groove 31 ( It is thinner) and loses the function of protecting the passivation layer 4, resulting in the passivation layer 4 being also etched away to form a second via hole 42, as shown in FIG.
  • RIE reactive ion etching
  • the photoresist 6 in the groove 31 is patterned by exposure and development.
  • a photoresist 6 opening is formed in the region of the groove 31, and then the first via 41 is formed on the passivation layer 4 by the dry etching.
  • the photoresist 6 since the photoresist 6 has a certain viscosity and fluidity, the photoresist 6 is coated on the passivation layer 4 on both sides of the groove 31, and the photoresist 6 is not completely leveled to the groove 31. Etching is carried out in the middle, thereby forming the first via 41 on the passivation layer 4.
  • part of the photoresist 6 will flow down and become thinner along the two side walls of the groove 31, resulting in The thickness of the photoresist 6 is different, and the dry etching is used to form the at least one second via 42 on the passivation layer 4.
  • the thickness of the color resist layer 3 described here needs to be greater than 0.5 ⁇ m, preferably 3 ⁇ m, in order to realize the step structure of the groove.
  • the passivation layer 4 is preferably a laminated structure of SiOx or SiNx, and its thickness is 300 or 100 microns.
  • the passivation layer 4 is preferably a plasma-assisted chemical vapor deposition coating (Plasma Enhanced CVD, PECVD) method for film formation, and then dry etching process for etching process.
  • the passivation layer 4 is an insulating material such as SiOx, SiNx, HfO2, Al2O3, or a laminated structure composed of the foregoing materials.
  • the thickness of the passivation layer 4 can be 1000A-10000A, and it is formed into a film by a chemical vapor deposition (CVD) method.
  • the gate insulating layer in the thin film transistor device is preferably a SiNx or SiOx laminated structure with a thickness of 100/300 nm, and is formed by a PECVD method.
  • the gate insulating layer can also be an optional laminated structure among insulating dielectric materials such as SiOx, SiNx, HfO2, Al2O3.
  • the thickness of the gate insulating layer can be 100A-10000A, and can be formed by a CVD method, which is not limited.
  • the active layer in the thin film transistor device 2 is preferably (Indium Gallium Zinc Oxide, IGZO) indium gallium zinc oxide.
  • the active layer can also be made of various semiconductor materials, including Si-based semiconductors, AZO, IZO, IGTO, ZTO, and other metal oxide semiconductor materials.
  • the present invention can simply realize the via hole on the passivation layer without increasing the cost of the process equipment and other additional processes.
  • the manufacturing process of the present invention such as photoresist thickness control, etching process parameter adjustment, etc.
  • via holes on the passivation layer can be realized to ensure that the water vapor in the color resist layer can be discharged during the subsequent baking process, which is effective Reduce the performance degradation of the array substrate/display device, thereby improving the performance and quality of the display device.

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制作方法，其中阵列基板包括基板、薄膜晶体管器件、色阻层、钝化层及像素电极层。薄膜晶体管器件设置在所述基板上。色阻层覆盖在所述薄膜晶体管器件上，所述色阻层设有凹槽。钝化层覆盖在所述色阻层上，并沿着所述凹槽的表面覆盖。像素电极层设置在所述钝化层上。所述钝化层开设有第一过孔和第二过孔，所述像素电极层通过所述第一过孔与所述薄膜晶体管器件电性连接，所述第二过孔曝露所述色阻层，其中所述至少一第二过孔位于所述凹槽上。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤指一种阵列基板及其制作方法。
 背景技术
随着社会进步与人们需求的提升，显示器也向着大尺寸、高分辨率(High Definition)的方向发展。为满足高分辨率和大尺寸的需求，在薄膜晶体管（Thin-Film Transistor，TFT）阵列基板涂布色阻(COA，color filter on array)的工艺技术已被广泛应用。COA工艺一方面可以实现面板开口率(aperture ratio)的提升。另一方面，色阻材料由于其吸水特性，尤其是采用金属氧化物有源层，如氧化铟镓锌(IGZO，Indium Gallium Zinc Oxide)等，能够阻隔外界水汽对TFT器件性能有显着的提升效果。
然而，在COA工艺研发中，由于Q-time(等待时间)以及色阻制程后清洗等制程引入的水分会导致色阻材料中水汽达到饱和状态，从而使导致器件电性劣化。虽然色阻中水汽可以通过后续烘烤制程加以去除，但是由于COA工艺在色阻上还会制备钝化层，以防止后续干刻工艺对色阻表面的损害。因此钝化层阻碍了色阻中的水汽排出，导致TFT器件性能严重劣化。
 技术问题
在COA工艺研发中，由于Q-time(等待时间)以及色阻制程后清洗等制程引入的水分会导致色阻材料中水汽达到饱和状态，从而使导致器件电性劣化。虽然色阻中水汽可以通过后续烘烤制程加以去除，但是由于COA工艺在色阻上还会制备钝化层，以防止后续干刻工艺对色阻表面的损害。因此钝化层阻碍了色阻中的水汽排出，导致TFT器件性能严重劣化。
 技术解决方案
本发明的目的，在于提供一种阵列基板及其制作方法，通过控制光阻厚度或蚀刻工艺参数调整实现钝化层上的过孔，保证色阻层中的水汽可在后续烘烤制程中从过孔排出，有效减少显示器件性能劣化的问题。
为达成本发明的前述目的，本发明提供一种阵列基板，包括基底、薄膜晶体管器件、色阻层、钝化层及像素电极层。薄膜晶体管器件设置在所述基底上。色阻层覆盖在所述薄膜晶体管器件上，所述色阻层设有凹槽。钝化层覆盖在所述色阻层上，并沿着所述凹槽的表面覆盖。像素电极层设置在所述钝化层上，其中，所述钝化层开设有第一过孔和至少一第二过孔，所述像素电极层通过所述第一过孔与所述薄膜晶体管器件的金属电极电性连接，所述至少一第二过孔曝露所述色阻层，其中所述至少一第二过孔位于所述凹槽上，所述凹槽包括第一孔径和第二孔径，所述第一孔径小于所述第二孔径。
在本发明的一实施例中，所述第二过孔数量为1个或多个。
在本发明的一实施例中，还包括设置在所述薄膜晶体管器件和所述色阻层之间的平坦层。
本发明提供还提供一种阵列基板，包括基底、薄膜晶体管器件、色阻层、钝化层及像素电极层。薄膜晶体管器件设置在所述基底上。色阻层覆盖在所述薄膜晶体管器件上，所述色阻层设有凹槽。钝化层覆盖在所述色阻层上，并沿着所述凹槽的表面覆盖。像素电极层设置在所述钝化层上，其中，所述钝化层开设有第一过孔和至少一第二过孔，所述像素电极层通过所述第一过孔与所述薄膜晶体管器件的金属电极电性连接，所述至少一第二过孔曝露所述色阻层，其中所述至少一第二过孔位于所述凹槽上。
在本发明的一实施例中，所述凹槽包括第一孔径和第二孔径，所述第一孔径小于所述第二孔径。
在本发明的一实施例中，所述第二过孔数量为1或多个。
在本发明的一实施例中，还包括设置在所述薄膜晶体管器件和所述色阻层之间的平坦层。
再者，本发明另提供一种阵列基板的制作方法，包括以下步骤：
S10、提供基底；
S20、在所述基底上制备薄膜晶体管器件；
S30、在所述薄膜晶体管器件上涂布色阻层，所述色阻层邻近所述薄膜晶体管器件形成凹槽；及
S40、在所述色阻层上沉积钝化层，并沿着所述凹槽的表面沉积，在所述钝化层上涂布光阻并经曝光显影后刻蚀，以在所述钝化层形成第一过孔和至少一第二过孔；及
S50、在所述钝化层上沉积并图形化像素电极层；
其中所述像素电极层通过所述第一过孔与所述薄膜晶体管器件的金属电极电性连接，所述至少一第二过孔曝露所述色阻层。
在本发明的一实施例中，在步骤S40中，在所述钝化层上涂布光阻并经曝光显影后刻蚀，其中所述蚀刻工艺是以干法蚀刻(Dry Etching)工艺形成所述第一过孔和所述第二过孔。
在本发明的一实施例中，当涂布所述光阻在所述钝化层的表面时，所述凹槽内的光阻通过曝光显影形成开孔，然后通过所述干法蚀刻在所述钝化层上形成所述第一过孔。
在本发明的一实施例中，当涂布所述光阻在所述钝化层时，部分的所述光阻会沿所述凹槽二侧壁流下变薄，再通过所述干法蚀刻，从而在所述钝化层上形成所述至少一第二过孔。
在本发明的一实施例中，在步骤S40中，控制所述光阻涂布厚度介于1.5至2微米（um），所述色阻层的厚度介于0.5-3.5微米（um）。
在本发明的一实施例中，在步骤S30中，形成所述凹槽为梯形，所述凹槽包括第一孔径和第二孔径，所述第一孔径小于所述第二孔径，所述第二孔径相对所述第一孔径远离所述薄膜晶体管器件。
 有益效果
与现有技术相比较，本发明能够在不增加制程设备成本和其他额外制程基础上，简单的实现了在钝化层上的过孔。通过本发明制程工艺的改进，例如光阻厚度控制、刻蚀工艺参数调整等，实现在钝化层上的过孔，从而保证色阻层内的水汽可在后续烘烤制程中排出，有效减少阵列基板／显示器件性能劣化，达到提升显示器件的性能与品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明阵列基板在基底上设置薄膜晶体管器件的横截面图；
图2是本发明阵列基板在薄膜晶体管器件上设置色阻层、钝化层及涂布光阻的横截面图；
图3是本发明阵列基板将光阻蚀刻以在钝化层上形成过孔的横截面图；
图4是本发明阵列基板在钝化层上设置像素电极层的横截面图；
图5是本发明在钝化层上实现过孔的实施例图；及
图6是本发明阵列基板的制作方法的流程图。
 本发明的最佳实施方式
在具体实施方式中提及“实施例”意指结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的不同位置出现的相同用语并非必然被限制为相同的实施方式，而应当理解为与其它实施例互为独立的或备选的实施方式。在本发明提供的实施例所公开的技术方案启示下，本领域的普通技术人员应理解本发明所描述的实施例可具有其他符合本发明构思的技术方案结合或变化。
请参照图1至图4所示，本发明提供一种阵列基板，包括基底1、薄膜晶体管器件2、色阻层3、钝化层4及像素电极层5。如图1至图4所示的薄膜晶体管器件2优选为背沟道刻蚀型（Back Channel Etching, BCE）的TFT结构。在其它不同的实施例中，薄膜晶体管器件2也可以是刻蚀阻挡层型(Etch Stop Layer, ESL)、顶栅共面型（Top Gate type）等TFT结构，并不限定。由于上述TFT结构为现有技术，在此不多加赘述。
薄膜晶体管器件2设置在所述基底1上。色阻层3覆盖在所述薄膜晶体管器件2上，所述色阻层3邻近所述薄膜晶体管器件2设有凹槽31。钝化层4覆盖在所述色阻层3上，并沿着所述凹槽31的表面覆盖。像素电极层5设置在所述钝化层4上。所述钝化层4开设有第一过孔41和至少一第二过孔42。所述像素电极层5通过所述第一过孔41与所述薄膜晶体管器件2的金属电极21电性连接，所述至少一第二过孔42曝露所述色阻层42，其中所述至少一第二过孔42位于所述凹槽31。借此，实现钝化层4上开设过孔，保证色阻层3中的水汽可从过孔42排出，有效减少显示器件性能劣化，进而提升显示器件的性能与品质，如图5所示。
如图2所示，所述凹槽31包括第一孔径311和第二孔径312。所述第一孔径311小于所述第二孔径312，且所述第二孔径312相对所述第一孔径311远离所述薄膜晶体管器件2。如图所示的凹槽31为梯形、杯形或环形。请一并参照图3及图4所示，所述第二过孔42数量优选为1或多个，每一所述第二过孔42对称且邻近所述第二孔径312设置。然而在其他次选的实施例中，所述第二过孔42数量可为1或多个，且形成于所述凹槽31的侧壁上。
如图1至图4所示的实施例中，还包括设置在所述薄膜晶体管器件2和所述色阻层3之间的平坦层7。所述平坦层7材料例如为多晶硅材料。
请同样参照图6所示，本发明另提供阵列基板的制作方法，包括以下步骤：S10、提供基底1；S20、在所述基底1上制备薄膜晶体管器件2；S30、在所述薄膜晶体管器件2上涂布色阻层3，所述色阻层3邻近所述薄膜晶体管器件2形成凹槽31；及S40、在所述色阻层3上沉积钝化层4，并沿着所述凹槽31的表面沉积，在所述钝化层4上涂布光阻6并经曝光显影后刻蚀，以在所述钝化层4形成第一过孔41和至少一第二过孔42；及S50、在所述钝化层4上沉积并图形化像素电极层5；其中所述像素电极层5通过所述第一过孔41与所述薄膜晶体管器件2的金属电极21电性连接，所述至少一第二过孔42曝露所述色阻层3。
在步骤S30中，形成所述凹槽31为梯形。所述凹槽31包括第一孔径311和第二孔径312，所述第一孔径311小于所述第二孔径312，所述第二孔径312相对所述第一孔径311远离所述薄膜晶体管器件2。
在步骤S40中，在所述钝化层4上涂布光阻6并经曝光显影后刻蚀，其中所述蚀刻工艺是以干法蚀刻(Dry Etching)工艺形成所述第一过孔41和所述第二过孔42。控制所述光阻6涂布厚度可介于1.5至2微米（um），优选为1.8微米（um）。所述色阻层3的厚度则介于0.5-3.5微米（um）。优选的蚀刻工艺参数调整，例如采用CF4+O2的制程气体、使用反应性离子蚀刻(Reactive Ion Etching；RIE)，进行干法刻蚀150秒等，因此使得凹槽31上方光阻6的厚度(较薄)而失去保护钝化层4的作用，导致所述钝化层4也被蚀刻掉而形成第二过孔42，如图5所示。
在如图2及图3所示的实施例中，当涂布所述光阻6在所述钝化层4的表面时，所述凹槽31内的光阻6通过曝光显影完成图形化，并在所述凹槽31区域内形成光阻6开孔，然后通过所述干法蚀刻在所述钝化层4上形成所述第一过孔41。具体而言，由于所述光阻6具有一定的粘度和流动性，通过在凹槽31二侧的钝化层4上涂布光阻6，并在光阻6尚未完全流平到凹槽31中间即进行蚀刻，从而在钝化层4上形成所述第一过孔41。此外，当涂布所述光阻6在所述钝化层4时，部分的所述光阻6会沿所述凹槽31的二侧壁流下变薄，造成在凹槽31二侧上方的光阻6厚度差异，再通过所述干法蚀刻，从而在所述钝化层4上形成所述至少一第二过孔42。
在此所述的色阻层3厚度需大于0.5微米，优选为3微米，以实现凹槽的台阶结构。所述钝化层4优选为SiOx或SiNx的叠层结构，其厚度为300或100微米。所述钝化层4优选为以电浆辅助化学气相沈积镀膜（Plasma Enhanced CVD, PECVD）方法成膜，再通过干法蚀刻工艺进行蚀刻制程。然而在其他可选的实施例中，所述钝化层4为SiOx、SiNx、HfO2、Al2O3 等绝缘材料，或上述材料所构成的叠层结构。所述钝化层4的厚度可为1000A-10000A，并通过化学气相沉积法(Chemical Vapor Deposition，CVD)方法成膜。
需说明的是，薄膜晶体管器件中的栅极绝缘层优选为SiNx或SiOx叠层结构，厚度为100/300nm，并由PECVD方法成膜。然而在其他不同实施例中，栅极绝缘层也可为SiOx、SiNx、HfO2、Al2O3 等绝缘介电材料中任选的叠层结构。栅极绝缘层的厚度可为100A-10000A，并可通过CVD方法成膜，并不限定。薄膜晶体管器件2中的有源层优选为(Indium Gallium Zinc Oxide，IGZO)氧化铟镓锌。然而在可选的实施例中，有源层也可为各种半导体材料，包括Si基半导体、AZO、IZO、IGTO、ZTO等金属氧化物半导体材料。
因此，本发明能够在不增加制程设备成本和其他额外制程基础上，简单的实现了在钝化层上的过孔。通过本发明制程工艺的改进，例如光阻厚度控制、刻蚀工艺参数调整等，即能够实现在钝化层上的过孔，保证色阻层内的水汽可在后续烘烤制程中排出，有效减少阵列基板／显示器件性能的劣化，进而提升显示器件的性能与品质。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种阵列基板，包括:
    基底；
    薄膜晶体管器件，设置在所述基底上；
    色阻层，覆盖在所述薄膜晶体管器件上，所述色阻层设有凹槽；
    钝化层，覆盖在所述色阻层上，并沿着所述凹槽的表面覆盖；及
    像素电极层，设置在所述钝化层上；
    其中，所述钝化层开设有第一过孔和至少一第二过孔，所述像素电极层通过所述第一过孔与所述薄膜晶体管器件的金属电极电性连接，所述至少一第二过孔曝露所述色阻层，其中所述至少一第二过孔位于所述凹槽上，所述凹槽包括第一孔径和第二孔径，所述第一孔径小于所述第二孔径。
  2. 如权利要求1所述的阵列基板，其中所述第二过孔数量为1个或多个。
  3. 如权利要求1所述的阵列基板，其中还包括设置在所述薄膜晶体管器件和所述色阻层之间的平坦层。
  4. 一种阵列基板，包括：
    基底；
    薄膜晶体管器件，设置在所述基底上；
    色阻层，覆盖在所述薄膜晶体管器件上，所述色阻层设有凹槽；
    钝化层，覆盖在所述色阻层上，并沿着所述凹槽的表面覆盖；及
    像素电极层，设置在所述钝化层上；
    其中，所述钝化层开设有第一过孔和至少一第二过孔，所述像素电极层通过所述第一过孔与所述薄膜晶体管器件的金属电极电性连接，所述至少一第二过孔曝露所述色阻层，其中所述至少一第二过孔位于所述凹槽上。
  5. 如权利要求4所述的阵列基板，其中所述凹槽包括第一孔径和第二孔径，所述第一孔径小于所述第二孔径。
  6. 如权利要求4所述的阵列基板，其中所述第二过孔数量为1个或多个。
  7. 如权利要求4所述的阵列基板，其中还包括设置在所述薄膜晶体管器件和所述色阻层之间的平坦层。
  8. 一种阵列基板的制作方法，包括以下步骤：
    S10、提供基底；
    S20、在所述基底上制备薄膜晶体管器件；
    S30、在所述薄膜晶体管器件上涂布色阻层，所述色阻层邻近所述薄膜晶体管器件形成凹槽；及
    S40、在所述色阻层上沉积钝化层，并沿着所述凹槽的表面沉积，在所述钝化层上涂布光阻并经曝光显影后刻蚀，以在所述钝化层形成第一过孔和至少一第二过孔；及
    S50、在所述钝化层上沉积并图形化像素电极层；
    其中所述像素电极层通过所述第一过孔与所述薄膜晶体管器件的金属电极电性连接，所述至少一第二过孔曝露所述色阻层。
  9. 如权利要求8所述的阵列基板的制作方法，其中在步骤S40中，在所述钝化层上涂布光阻并经曝光显影后刻蚀，其中所述蚀刻工艺是以干法蚀刻(Dry Etching)工艺形成所述第一过孔和所述第二过孔。
  10. 如权利要求9所述的阵列基板的制作方法，其中当涂布所述光阻在所述钝化层的表面时，所述凹槽内的光阻通过曝光显影形成开孔，然后通过所述干法蚀刻在所述钝化层上形成所述第一过孔。
  11. 如权利要求9所述的阵列基板的制作方法，其中当涂布所述光阻在所述钝化层时，部分的所述光阻会沿所述凹槽的二侧壁流下变薄，再通过所述干法蚀刻，从而在所述钝化层上形成所述至少一第二过孔。
  12. 如权利要求8所述的阵列基板的制作方法，其中在步骤S40中，控制所述光阻涂布厚度介于1.5至2微米（um）为1.8微米（um），所述色阻层的厚度介于0.5-3.5微米（um）。
  13. 如权利要求8所述的阵列基板的制作方法，其中在步骤S30中，形成所述凹槽为梯形，所述凹槽包括第一孔径和第二孔径，所述第一孔径小于所述第二孔径，所述第二孔径相对所述第一孔径远离所述薄膜晶体管器件。
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