WO2020143437A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2020143437A1
WO2020143437A1 PCT/CN2019/127345 CN2019127345W WO2020143437A1 WO 2020143437 A1 WO2020143437 A1 WO 2020143437A1 CN 2019127345 W CN2019127345 W CN 2019127345W WO 2020143437 A1 WO2020143437 A1 WO 2020143437A1
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WIPO (PCT)
Prior art keywords
conductive portion
array substrate
electrode
electrode pad
substrate according
Prior art date
Application number
PCT/CN2019/127345
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English (en)
French (fr)
Inventor
张震
刘庭良
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19908209.0A priority Critical patent/EP3910678A4/en
Priority to JP2020560908A priority patent/JP2022515578A/ja
Priority to US16/768,194 priority patent/US11462572B2/en
Publication of WO2020143437A1 publication Critical patent/WO2020143437A1/zh
Priority to US17/891,173 priority patent/US20220406821A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • the display panel needs to be packaged well to maintain the stability of the internal materials. For example, for an OLED (organic light emitting diode) display panel, if the package fails, external water, oxygen, etc. will invade the display area of the display panel, resulting in the failure of the organic light emitting material and reducing the display quality of the OLED.
  • OLED organic light emitting diode
  • the display panel is prone to package failure problems on the pad side, for example, the package layer is prone to fall off at the electrode lead, and the gap between the electrode lead and the dropped package layer will form a path for water and oxygen erosion, resulting in water and oxygen intrusion into the display Area, causing package failure.
  • the purpose of the present disclosure is to provide an array substrate and a display device that can reduce the risk of peeling of the packaging layer at this location and improve the yield of the array substrate packaging.
  • an array substrate including a display area and a peripheral area, wherein the display area is provided with a common electrode, and the peripheral area is provided with an electrode bus near the display area; the array substrate also includes:
  • the first electrode pad is provided on a side of the peripheral area away from the display area;
  • the second electrode pad is provided on the side of the peripheral area away from the display area;
  • the second conductive portion is connected to the second electrode pad and extends in a direction away from the first conductive portion to be connected to the electrode bus.
  • the second conductive portion extends from the second electrode pad in a direction away from the first conductive portion along a bending trajectory.
  • the second conductive portion includes a first connection segment, a second connection segment, and a third connection segment that are sequentially connected, wherein the first connection segment and the second Electrode pad connection, the third connection section is connected to the electrode bus;
  • the second connection segment extends along a linear trajectory from a connection position with the first connection segment away from the first conductive portion.
  • the first connection segment extends along a linear trajectory from the second electrode pad in a direction away from the first conductive portion.
  • the extending direction of the second connection segment is parallel to the extending direction of the electrode bus.
  • the extending direction of the third connection segment is perpendicular to the extending direction of the electrode bus.
  • a chamfer is provided at the connection position of the first connection section and the second connection section.
  • the array substrate further includes:
  • the isolation bar is provided between the second electrode pad and the electrode bus;
  • the second electrode pad, the second conductive portion, the electrode bus, and the isolation bar are disposed on the same side of the base substrate, and the isolation bar covers at least a portion of the second conductive portion.
  • the number of the isolation bars is multiple and arranged at intervals.
  • a display device including the above array substrate.
  • the second conductive portion extends away from the first conductive portion to be connected to the electrode bus, so the distance between the first conductive portion and the second conductive portion is relatively large, which facilitates the first conductive Heat dissipation on the second conductive portion.
  • the distance between the two current converging positions such as the connection between the first conductive portion and the common electrode, and the connection between the second conductive portion and the electrode bus, is relatively large, which facilitates the temperature dissipation of the two current collecting positions.
  • the array substrate has good heat dissipation performance at the location of the first conductive portion and the second conductive portion, can reduce the degree of heat accumulation, and is not prone to high temperature, so the risk of peeling of the packaging layer at this location can be reduced and the array can be improved The yield of substrate packaging.
  • FIG. 1 is a partial schematic diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a partial schematic view of an array substrate according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the drawings.
  • the example embodiments can be implemented in various forms and should not be construed as being limited to the examples set forth herein; on the contrary, providing these embodiments makes the present disclosure more comprehensive and complete, and fully conveys the idea of the example embodiments For those skilled in the art.
  • the described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to give a full understanding of the embodiments of the present disclosure.
  • a structure When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” arranged on the other structure, or that the structure is arranged “indirectly” through another structure.
  • Other structures The terms “a”, “a”, “said” are used to indicate the presence of one or more elements/components/etc.; the terms “include” and “have” are used to mean an open-ended inclusion and refer to In addition to the listed elements/components/etc. there may be additional elements/components/etc.
  • the terms “first” and “second” are only used as marks, not to limit the number of objects.
  • the display panel is prone to package failure on the pad side, and is particularly prone to defects that the electrode lead and the package layer peel off from each other.
  • the applicant has analyzed the structure of the defective location of the package, analyzed the temperature of various parts of the display panel during operation, and other tests, and found that the peeling of the packaging layer is related to the high temperature of the peeling area.
  • the peripheral area of the display panel is provided with adjacent anode pads and cathode pads on the pad side.
  • the cathode pad is connected to the common electrode through the cathode conductive portion
  • the anode pad is connected to the electrode bus through the anode conductive portion.
  • the cathode conductive portion and the anode conductive portion extend side by side in the direction of the display area, which not only causes the distance between the two current converging points to be closer, but also the distance between the cathode conductive portion and the anode conductive portion. Therefore, the heat at the place where the two currents converge is difficult to dissipate efficiently, and the heat at the cathode conductive part and the anode conductive part is also difficult to dissipate efficiently, which results in a high temperature at the position of the cathode conductive part and the anode conductive part, and the encapsulation layer is easily exposed to high temperature Peel off.
  • an embodiment of the present disclosure provides an array substrate.
  • the array substrate includes a display area B and a peripheral area A.
  • the display area B is provided with a common electrode
  • the peripheral area A is provided with an electrode bus 7 near the display area B.
  • the array substrate further includes An electrode pad 1, a first conductive part 3, a second electrode pad 2 and a second conductive part 4; wherein, the first electrode pad 1 and the first conductive part 3 are connected to the power supply negative electrode VSS, the second electrode pad, for example 2 and the second conductive portion 4 are connected to the positive power supply VDD.
  • the first electrode pad 1 is provided on the side of the peripheral area A away from the display area B; the first conductive portion 3 connects the first electrode pad 1 and the common electrode; the second electrode pad 2 is provided on the peripheral area A away from the display area B The second conductive portion 4 is connected to the second electrode pad 2 and extends away from the first conductive portion 3 to connect to the electrode bus 7.
  • the second conductive portion 4 extends in a direction away from the first conductive portion 3 to be connected to the electrode bus 7, so the distance between the first conductive portion 3 and the second conductive portion 4 is relatively large, which is convenient for the first Heat dissipation on the one conductive part 3 and the second conductive part 4.
  • the distance between two current converging locations, such as the connection between the first conductive portion 3 and the common electrode, the connection between the second conductive portion 4 and the electrode bus 7, is also relatively large, which is convenient for the temperature of the two current collecting locations Dissipation.
  • the array substrate has good heat dissipation performance at the location of the first conductive portion 3 and the second conductive portion 4, can reduce the degree of heat accumulation, and is not prone to high temperature, so the risk of peeling of the packaging layer at this location can be reduced, Improve the yield of array substrate packaging.
  • One of the first electrode pad 1 and the second electrode pad 2 may be an anode pad and the other is a cathode pad; the first electrode pad 1 and the second electrode pad 2 may be arranged adjacent to each other Connection of external power supply.
  • the first electrode pad 1 is connected to the negative electrode VSS of the external power supply
  • the second electrode pad 2 is connected to the positive electrode VDD of the external power supply.
  • the first electrode pad 1 may be a cathode pad, and correspondingly, the common electrode is a common cathode.
  • the second electrode pad 2 may be an anode pad.
  • the electrode bus 7 is connected to the second electrode pad 2 as an anode bus; the display area B is also provided with electrode leads 8 (as shown in FIG. 1), each electrode The lead 8 is connected to the electrode bus 7, wherein the electrode lead 8 is used to connect each display unit.
  • the first conductive portion 3 flows to the first electrode pad 1.
  • first electrode pads 1 and second electrode pads 2 may be provided on the array substrate, or multiple sets of first electrode pads 1 and second electrode pads 2 may be provided at intervals (as shown in FIG. 2), this disclosure makes no special limitation on this.
  • the material of the first electrode pad 1 may be metal, alloy, conductive metal oxide, or other conductive materials.
  • the material of the first electrode pad 1 may be a metal such as copper, tungsten, titanium, or an alloy containing any of the above metals.
  • the shape of the first electrode pad 1 may be a rectangle, a circle, or other geometric shapes, which is not limited in this disclosure.
  • the material and shape of the second electrode pad 2 may be the same as or different from that of the first electrode pad 1, subject to being able to meet design requirements.
  • the second conductive portion 4 is connected to the second electrode pad 2 and extends in a direction away from the first conductive portion 3 to be connected to the electrode bus 7. Therefore, the first conductive portion 3 and the second conductive portion 4 as a whole are flared toward the display area B.
  • the first conductive portion 3 and the second conductive portion 4 may each extend in a straight line or a smooth curve, and form a flared shape.
  • the distance between the first conductive portion 3 and the second conductive portion 4 may not change for at least one segment, but abruptly occur at at least one point.
  • the first conductive portion 3 may extend linearly to be connected to the common electrode, or may be connected to the common electrode through a broken-line trajectory. In an embodiment, the first conductive portion 3 may first extend from the first electrode pad 1 in a direction oblique to the common electrode toward a side away from the second electrode pad 2, and then in a direction perpendicular to the common electrode The common electrode extends to connect with the common electrode.
  • the material of the first conductive portion 3 may be a metal, a conductive metal oxide, or other conductive materials, such as aluminum, copper, tungsten, molybdenum, silver, or other metals or alloys including any of the above metals, or may be ITO (indium oxide Tin) and other transparent conductive materials.
  • the first conductive portion 3 may be composed of a layer of conductive material, or may be composed of multiple layers of different conductive layer materials.
  • the first conductive portion 3 may be ITO.
  • the second conductive portion 4 may extend from the second electrode pad 2 in a direction away from the first conductive portion 3 along a bending locus.
  • the bending trajectory may be a curved trajectory or a polyline trajectory.
  • the second conductive portion 4 may include a first connection segment 41, a second connection segment 42, and a third connection segment 43 that are connected in sequence, wherein the first connection segment 41 is connected to the second electrode pad 2, the third The connection section 43 is connected to the electrode bus 7; the second connection section 42 extends along a linear trajectory from the connection position with the first connection section 41 in a direction away from the first conductive portion 3.
  • the arrangement of the second connection section 42 ensures that the third connection section 43 is away from the first conductive portion 3, and in particular that the connection position of the third connection section 43 and the electrode bus 7 is away from the first conductive portion 3, so that the second conductive portion
  • the heat dissipation of 4 is reduced by the influence of the first conductive portion 3, ensuring the improvement of the heat dissipation efficiency of the second conductive portion 4.
  • the first connection segment 41 extends from the second electrode pad 2 in a direction away from the first conductive portion 3 along a linear trajectory. In this way, the distance between the first conductive portion 3 and the second conductive portion 4 can be increased as much as possible while keeping the positions of the first electrode pad 1 and the second electrode pad 2 unchanged, and the heat accumulation can be reduced possibility.
  • the first connection segment 41 may also extend from the second electrode pad 2 to the display area B in a direction perpendicular to the electrode bus 7.
  • the extending direction of the second connection section 42 is parallel to the extending direction of the electrode bus 7. This not only facilitates increasing the degree that the second conductive portion 4 is far from the first conductive portion 3, but also facilitates reducing the difficulty of preparing the mask of the second conductive portion 4.
  • connection position of the first connection section 41 and the second connection section 42 may be provided with a chamfer, so that the tip discharge at the connection position can be suppressed.
  • the chamfer can also be rounded to further eliminate the tip and improve the effect of suppressing discharge of the tip.
  • the extending direction of the third connection section 43 may be perpendicular to the extending direction of the electrode bus 7. In this way, the uniformity of the collection of the current on the electrode bus 7 by the third connection section 43 can be improved, and the difference in the connection angle between the electrode bus 7 and the third section can be reduced, resulting in the difference in the current distribution on the third connection section 43 Skin effect and cutting-edge effect.
  • the material and the number of layers of the second conductive part 4 may be the same as or different from those of the first conductive part 3.
  • the first conductive portion 3 may be a three-layer composite material of a molybdenum layer/aluminum layer/molybdenum layer.
  • all or part of the edges of the first conductive portion 3 and the second conductive portion 4 may also be provided with irregular shapes, as shown by the zigzag concave and convex lines in FIG. 1 in order to increase water
  • the length of the oxygen invasion path reduces the amount of water and oxygen invading the display area B, and reduces the risk of black spots and other adverse effects caused by the water and oxygen intrusion into the display area B.
  • the array substrate can also be provided with isolation bars 5 to increase the isolation of water and oxygen.
  • the array substrate may include a base substrate 6 and an isolation bar 5, the isolation bar 5 is provided between the second electrode pad 2 and the electrode bus 7; the second electrode pad 2, the second conductive portion 4, The electrode bus 7 and the isolation bar 5 are disposed on the same side of the base substrate 6, and the isolation bar 5 covers at least part of the second conductive portion 4, that is, the isolation bar 5 is disposed on a side of the second conductive portion 4 away from the base substrate 6.
  • An encapsulation layer is provided on the side of the second electrode pad 2, the second conductive portion 4 and the electrode bus 7 which is away from the base substrate 6.
  • the isolation strip 5 can block water and oxygen from intruding into the display area B along the gap between the second conductive portion 4 and the encapsulation layer, reducing the black spots of the display area B caused by poor packaging of the display area B risk.
  • the material of the isolation bar 5 may be an organic insulating material, an inorganic insulating material, or other insulating materials, or a combination of multiple layers of different insulating materials.
  • the material of the spacer 5 may be resin.
  • the isolation bar 5 may also extend between the first electrode pad 1 and the common electrode, covering at least part of the first conductive portion 3. In another embodiment, the isolation bar 5 extends in a direction parallel to the electrode bus 7 and covers the first conductive portion 3 and the second conductive portion 4 in the extending direction thereof.
  • the number of the isolation bars 5 is multiple and arranged at intervals.
  • the number of the isolation bars 5 is two, including a first isolation bar 51 and a second isolation bar 52 that are parallel to each other, wherein the first isolation bar 51 is provided between the electrode bus 7 and the second electrode pad 2, The second isolation bar 52 is provided between the electrode bus 7 and the first isolation bar 51.
  • the first isolation bar 51 covers at least part of the second connection section 42, and the second isolation bar 52 covers at least part of the third connection section 43.
  • the first conductive portion 3, the second conductive portion 4 and the electrode bus 7 are covered with an organic layer, and the first isolation bar 51 and the second isolation bar 52 are two open grooves on the organic layer A part of the organic layer is retained between the two open grooves, and the structure is used to block water and oxygen.
  • the number of the opening grooves may be more than two.
  • the material of the organic layer may be an organic insulating material, an inorganic insulating material or other insulating materials, or a combination of multiple layers of different insulating materials. In one embodiment, the material of the organic layer may be resin.
  • the encapsulation layer of the array substrate may be an organic insulating material or an inorganic insulating material, so as to achieve encapsulation protection of the first conductive portion 3 and the second conductive portion 4.
  • the encapsulation layer may be a layer of encapsulation material or multiple layers of different encapsulation materials.
  • the material of the encapsulation layer may be an insulating material such as silicon nitride formed by CVD (Chemical Vapor Deposition), and the encapsulation layer covers the first conductive portion 3, the second conductive portion 4, and the isolation strip 5 , The first isolation strip 51 and the second isolation strip 52, etc.
  • the present disclosure also provides a display device including any of the array substrates described in the above-mentioned array substrate embodiments.
  • the display device may be an AMOLED (Active Matrix Organic Light Emitting Diode) display panel, a PMOLED (Passive Matrix Organic Electrically Excited Photodiode) display panel, or other types of display panels, which are not specifically limited in this disclosure.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • PMOLED Passive Matrix Organic Electrically Excited Photodiode
  • the array substrate used in the display device of the embodiment of the present disclosure is the same as the array substrate in the above embodiment of the array substrate, and therefore, has the same beneficial effects, which will not be repeated here.

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Abstract

一种阵列基板和显示装置，属于显示技术领域。该阵列基板包括显示区（B）和外围区（A），所述显示区（B）设置有公共电极，所述外围区（A）靠近所述显示区（B）设置有电极总线（7）；所述阵列基板还包括第一电极焊盘（1）、第一导电部（3）、第二电极焊盘（2）和第二导电部（4）；其中，第一电极焊盘（1）设于所述外围区（A）远离所述显示区（B）的一侧；第一导电部（3）连接所述第一电极焊盘（1）和所述公共电极；第二电极焊盘（2）设于所述外围区（A）远离所述显示区（B）的一侧；第二导电部（4）连接于所述第二电极焊盘（2），并沿远离所述第一导电部（3）的方向延伸至与所述电极总线（7）连接。所述阵列基板和显示装置能够降低该位置封装层剥离的风险，提高阵列基板封装的良率。

Description

阵列基板和显示装置
相关申请的交叉引用
本公开要求于2019年1月8日提交的中国申请号为201910016329.X，标题为“阵列基板和显示装置”的中国申请的优先权，其全部内容通过引用结合在本文中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板和显示装置。
背景技术
显示面板需要通过良好的封装，以保持内部材料的稳定性。举例而言，对于OLED(有机发光二极管)显示面板，若封装失效，外界的水氧等将会侵入显示面板的显示区，导致有机发光材料失效，降低OLED的显示质量。
显示面板在焊盘(pad)侧容易出现封装失效问题，例如在电极引线处容易发生封装层脱落，电极引线与脱落的封装层之间的隙将形成水氧侵蚀的通路，导致水氧侵入显示区，造成封装失效。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种阵列基板和显示装置，能够降低该位置封装层剥离的风险，提高阵列基板封装的良率。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种阵列基板，包括显示区和外围区，其中所述显示区设置有公共电极，所述外围区靠近所述显示区设置有电极总线；所述阵列基板还包括：
第一电极焊盘，设于所述外围区远离所述显示区的一侧；
第一导电部，连接所述第一电极焊盘和所述公共电极；
第二电极焊盘，设于所述外围区远离所述显示区的一侧；
第二导电部，连接于所述第二电极焊盘，并沿远离所述第一导电部的方向延伸至与所述电极总线连接。
在本公开的一种示例性实施例中，所述第二导电部从所述第二电极焊盘向远离所述第一导电部的方向沿弯折轨迹延伸。
在本公开的一种示例性实施例中，所述第二导电部包括依次连接的第一连接段、第二连接段和第三连接段，其中，所述第一连接段与所述第二电极焊盘连接，所述第三连接段与所述电极总线连接；
所述第二连接段从与所述第一连接段的连接位置向远离所述第一导电部的方向沿直线轨迹延伸。
在本公开的一种示例性实施例中，所述第一连接段从所述第二电极焊盘向远离所述第一导电部的方向沿直线轨迹延伸。
在本公开的一种示例性实施例中，所述第二连接段的延伸方向平行于所述电极总线的延伸方向。
在本公开的一种示例性实施例中，所述第三连接段的延伸方向垂直于所述电极总线的延伸方向。
在本公开的一种示例性实施例中，在所述第一连接段与所述第二连接段的连接位置设置有倒角。
在本公开的一种示例性实施例中，所述阵列基板还包括：
衬底基板；
隔离条，设于所述第二电极焊盘和所述电极总线之间；
所述第二电极焊盘、所述第二导电部、所述电极总线与所述隔离条设于所述衬底基板的同一侧面，且所述隔离条覆盖至少部分所述第二导电部。
在本公开的一种示例性实施例中，所述隔离条的数量为多个且间隔设置。
根据本公开的第一个方面，提供一种显示装置，包括上述的阵列基板。
本公开提供的阵列基板和显示装置，第二导电部沿远离第一导电部的方向延伸至与电极总线连接，因此第一导电部和第二导电部之间的距离比较大，便于第一导电部和第二导电部上热量的散逸。不仅如此，第一导电部与公共电极之间的连接处、第二导电部与电极总线的连接处等两处电流汇聚位置的距离也比较大，便于两处电流汇聚位置的温度的散逸。因此，该阵列基板在第一导电部和第二导电部所在位置具有良好的散热性能，能够降低热量积累的程度，不容易出现高温的情形，因此可以降低该位置封装层剥离的风险，提高阵列基板封装的良率。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开一实施方式的阵列基板的局部结构示意图。
图2是本公开一实施方式的阵列基板的局部结构示意图。
图中主要元件附图标记说明如下：
1、第一电极焊盘；2、第二电极焊盘；3、第一导电部；4、第二导电部；41、第一连接段；42、第二连接段；43、第三连接段；5、隔离条；51、第一隔离条；52、第二隔离条；6、衬底基板；7、电极总线；8、电极引线；A、外围区；B、显示区。
具体实施例
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结 构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
显示面板在焊盘侧容易发生封装失效，尤其是容易高发电极引线与封装层相互剥离的不良。申请人通过对封装不良位置的结构进行解析、分析显示面板工作时各个部位的温度以及其他试验，发现该封装层剥离与剥离区域的高温有关。
相关技术中，显示面板的外围区在焊盘侧设置有相邻的阳极焊盘和阴极焊盘，阴极焊盘通过阴极导电部连接公共电极，阳极焊盘通过阳极导电部连接电极总线，电极总线连接显示区的各个电极引线。其中，阴极导电部与公共电极连接处会有阴极电流的汇聚而产生大量热量，阳极导电部与电极总线的连接处会有阳极电流的汇聚而产生大量热量。相关技术中，阴极导电部和阳极导电部并排向显示区方向延伸，这不仅导致两个电流汇聚之处之间的距离比较近，而且阴极导电部和阳极导电部之间的距离也比较近。因此，两个电流汇聚之处的热量难以高效散逸，阴极导电部和阳极导电部上的热量也难以高效散逸，这导致阴极导电部和阳极导电部位置处的温度高，封装层容易在高温下剥离。
基于此，本公开实施方式中提供一种阵列基板。如图1(未显示公共电极)所示，该阵列基板包括显示区B和外围区A，显示区B设置有公共电极，外围区A靠近显示区B设置有电极总线7；阵列基板还包括第一电极焊盘1、第一导电部3、第二电极焊盘2和第二导电部4；其中，第一电极焊盘1和第一导电部3例如连接电源负极VSS，第二电极焊盘2和第二导电部4连接电源正极VDD。
第一电极焊盘1设于外围区A远离显示区B的一侧；第一导电部3连接第一电极焊盘1和公共电极；第二电极焊盘2设于外围区A远离显示区B的一侧；第二导电部4连接于第二电极焊盘2，并沿远离第一导电部3的方向延伸至与电极总线7连接。
本公开提供的阵列基板，第二导电部4沿远离第一导电部3的方向延伸至与电极总线7连接，因此第一导电部3和第二导电部4之间的距离比较大，便于第一导电部3和第二导电部4上热量的散逸。不仅如此，第一导电部3与公共电极之间的连接处、第二导电部4与电极总线7的连接处等两处电流汇聚位置的距离也比较大，便于两处电流汇聚位置的温度的散逸。因此，该阵列基板在第一导电部3和第二导电部4所在位置具有良好的散热性能，能够降低热量积累的程度，不容易出现高温的情形，因此可以降低该位置封装层剥离的风险，提高阵列基板封装的良率。
下面结合附图进一步对本公开实施方式提供的阵列基板的各部件进行详细说明：
第一电极焊盘1和第二电极焊盘2中的一个可以为阳极焊盘，另一个为阴极焊盘；第一电极焊盘1和第二电极焊盘2可以相邻设置，用于与外部电源的连接。例如，第一电极焊盘1连接外部电源的负极VSS，第二电极焊盘2连接外部电源的正极VDD。
举例而言，在本公开的实施方式中，如图1和2(未显示公共电极)所示，例如，第一电极焊盘1可以为阴极焊盘，对应的，公共电极为公共阴极。第二电极焊盘2可以为阳极焊盘，对应的，电极总线7作为阳极总线与第二电极焊盘2连接；显示区B还设置有电极引线8(如图1中所示)，各电极引线8连接电极总线7，其中电极引线8用于连接各显示单元。如此，在工作时，如图2中箭头所示，电流从第二电极焊盘2流经第二导电部4、电极总线7至各电极引线8，经过显示单元后流入公共电极，从公共电极通过第一导电部3流向第一电极焊盘1。
可以理解的是，阵列基板上可以设置一组第一电极焊盘1和第二电极焊盘2，也可以设置多组间隔设置的第一电极焊盘1和第二电极焊盘2(如图2所示)，本公开对此不做特殊的限定。
第一电极焊盘1的材料可以为金属、合金、导电金属氧化物或者其他导电材料。举例而言，第一电极焊盘1的材料可以为铜、钨、钛等金属或者包含上述任一金属的合金。第一电极焊盘1的形状可以为矩形、圆形或者其他几何形状，本公开对此不做限定。
第二电极焊盘2的材料和形状可以与第一电极焊盘1相同或者不同，以能够满足设计要求为准。
第二导电部4连接于第二电极焊盘2并沿远离第一导电部3的方向延伸至与电极总线7连接。因此，第一导电部3和第二导电部4在整体上呈朝向显示区B的扩口状。在一实施方式中，第一导电部3和第二导电部4可以均呈直线或平滑曲线延伸，并形成扩口状。在另一实施方式中，在朝向显示区B的方向上，第一导电部3和第二导电部4之间的距离可以在至少一段上不变化，而在至少一个点上出现突变。
第一导电部3可以呈直线延伸至与公共电极连接，也可以通过折线轨迹与公共电极连接。在一实施方式中，第一导电部3可以先从第一电极焊盘1以与公共电极倾斜的方向向远离第二电极焊盘2的一侧延伸，然后再以垂直于公共电极的方向向公共电极延伸，至与公共电极连接。
第一导电部3的材料可以为金属、导电金属氧化物或者其他导电材料，例如可以为铝、铜、钨、钼、银等金属或者包括上述任一金属的合金，或者可以为ITO(氧化铟锡)等透明导电材料。第一导电部3可以由一层导电材料组成，也可以由多层不同的导电层材料组成。举例而言，在一实施方式中，第一导电部3的可以为ITO。
第二导电部4可以从第二电极焊盘2向远离第一导电部3的方向沿弯折轨迹延伸。该弯折轨迹可以为曲线轨迹，也可以为折线轨迹。举例而言，第二导电部4可以包括依次连接的第一连接段41、第二连接段42和第三连接段43，其中，第一连接段41与第二电极焊盘2连接，第三连接段43与电极总线7连接；第二连接段42从与第一连接段41的连接位置向远离第一导电部3的方向沿直线轨迹延伸。第二连接段42的设置，确保了第三连接段43远离第一导电部3，尤其是确保了第三连接段43与电极总线7的连接位置远离第一导电部3，使得第二导电部4的散热受到第一导电部3的影响减小，确保了第二导电部4散热效率的提高。
在一实施方式中，第一连接段41从第二电极焊盘2向远离第一导电部3的方向沿直线轨迹延伸。如此，可以在保持第一电极焊盘1和第二电极焊盘2位置不变的条件下，尽可能增大第一导电部3和第二导电部4之间的距离，减小热量积聚的可能性。当然的，在另一实施方式中，第 一连接段41也可以从第二电极焊盘2以垂直于电极总线7的方向，向显示区B延伸。
在一实施方式中，第二连接段42的延伸方向平行于电极总线7的延伸方向。这不仅便于提高第二导电部4远离第一导电部3的程度，也便于降低制备第二导电部4的掩膜板的难度。
在一实施方式中，在第一连接段41与第二连接段42的连接位置可以设置有倒角，如此，可以抑制该连接位置处的尖端放电。该倒角还可以为圆角，以便进一步消除尖端，提高抑制尖端放电的效果。
在一实施方式中，第三连接段43的延伸方向可以垂直于电极总线7的延伸方向。如此，可以提高第三连接段43对电极总线7上的电流的汇集的均匀性，减小电极总线7两侧与第三段连接角度的不同导致第三连接段43上电流分布的差异，降低集肤效应和尖端效应的影响。
第二导电部4的材料和层数可以与第一导电部3相同或者不同。举例而言，在一实施方式中，第一导电部3的可以为钼层/铝层/钼层的三层复合材料。
为了尽可能降低封装不良的可能性，第一导电部3和第二导电部4的全部或者部分边缘还可以被设置成凹凸状，如图1中的锯齿状的凹凸线所示，以便增加水氧入侵路径的长度，降低侵入显示区B的水氧的量，减小水氧入侵显示区B引起黑斑等不良的风险。
该阵列基板还可以通过设置隔离条5来增加对水氧的隔离。举例而言，该阵列基板可以包括有衬底基板6和隔离条5，隔离条5设于第二电极焊盘2和电极总线7之间；第二电极焊盘2、第二导电部4、电极总线7与隔离条5设于衬底基板6的同一侧面，且隔离条5覆盖至少部分第二导电部4，即隔离条5设置于第二导电部4远离衬底基板6的一侧面。在第二电极焊盘2、第二导电部4和电极总线7远离衬底基板6的一侧面，设置有封装层。如果封装层从第二导电部4剥离，隔离条5可以阻挡水氧沿第二导电部4与封装层之间的间隙侵入显示区B，降低显示区B封装不良引起的显示区B黑斑的风险。
隔离条5的材料可以为有机绝缘材料、无机绝缘材料或者其他绝缘材料，还可以为多层不同绝缘材料的组合。在一实施方式中，隔离条5 的材料可以为树脂。
在一实施方式中，该隔离条5还可以延伸至第一电极焊盘1和公共电极之间，覆盖至少部分第一导电部3。在另一实施方式中，隔离条5沿平行于电极总线7方向延伸，在其延伸方向上覆盖第一导电部3和第二导电部4。
在一实施方式中，隔离条5的数量为多个且间隔设置。举例而言，隔离条5数量为两个，包括相互平行的第一隔离条51和第二隔离条52，其中，第一隔离条51设于电极总线7与第二电极焊盘2之间，第二隔离条52设于电极总线7与第一隔离条51之间。其中，第一隔离条51覆盖至少部分第二连接段42，第二隔离条52覆盖至少部分第三连接段43。如此，可以通过多个隔离条5实现对水氧的多重阻隔，避免水氧入侵显示区B，避免封装不良导致的显示区B黑斑等不良。
在一实施方式中，第一导电部3、第二导电部4和电极总线7上面覆盖有一层有机层，上述第一隔离条51和第二隔离条52是该有机层上的两个开口槽，该两个开口槽之间保留有该有机层的一部分，以此结构来实现对水氧的阻隔。所述开口槽的数量可以多于两个。该有机层的材料可以为有机绝缘材料、无机绝缘材料或者其他绝缘材料，还可以为多层不同绝缘材料的组合。在一实施方式中，该有机层的材料可以为树脂。
在一实施方式中，该阵列基板的封装层可以为有机绝缘材料或者无机绝缘材料，以实现对第一导电部3和第二导电部4的封装保护。可以理解的是，该封装层可以为一层封装材料，也可以为多层不同的封装材料。举例而言，在一实施方式中，封装层的材料可以为通过CVD(化学气相沉积)形成的氮化硅等绝缘材料，封装层覆盖第一导电部3、第二导电部4、隔离条5、第一隔离条51和第二隔离条52等。
本公开还提供一种显示装置，该显示装置包括上述的阵列基板实施方式所描述的任一阵列基板。该显示装置可以为AMOLED(主动矩阵有机发光二极体)显示面板、PMOLED(被动矩阵有机电激发光二极管)显示面板或者其他类型的显示面板，本公开对此不做特殊的限定。
本公开实施方式的显示装置采用的阵列基板与上述阵列基板的实施方式中的阵列基板相同，因此，具有相同的有益效果，在此不再赘述。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (15)

  1. 一种阵列基板，包括显示区和外围区，其中所述显示区设置有公共电极，所述外围区靠近所述显示区设置有电极总线；其特征在于，所述阵列基板还包括：
    第一电极焊盘，设于所述外围区远离所述显示区的一侧；
    第一导电部，连接所述第一电极焊盘和所述公共电极；
    第二电极焊盘，设于所述外围区远离所述显示区的一侧；
    第二导电部，连接于所述第二电极焊盘，并沿远离所述第一导电部的方向延伸至与所述电极总线连接，
    其中所述第二导电部从所述第二电极焊盘向远离所述第一导电部的方向沿弯折轨迹延伸。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述第二导电部包括依次连接的第一连接段、第二连接段和第三连接段，其中，所述第一连接段与所述第二电极焊盘连接，所述第三连接段与所述电极总线连接；
    所述第二连接段从与所述第一连接段的连接位置向远离所述第一导电部的方向沿直线轨迹延伸。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述第一连接段从所述第二电极焊盘向远离所述第一导电部的方向沿直线轨迹延伸。
  4. 根据权利要求2所述的阵列基板，其特征在于，所述第二连接段的延伸方向平行于所述电极总线的延伸方向。
  5. 根据权利要求2所述的阵列基板，其特征在于，所述第三连接段的延伸方向垂直于所述电极总线的延伸方向。
  6. 根据权利要求2所述的阵列基板，其特征在于，在所述第一连接段与所述第二连接段的连接位置设置有倒角。
  7. 根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括：
    衬底基板；
    隔离条，设于所述第二电极焊盘和所述电极总线之间；
    所述第二电极焊盘、所述第二导电部、所述电极总线与所述隔离条设于所述衬底基板的同一侧面，且所述隔离条覆盖至少部分所述第二导电部。
  8. 根据权利要求7所述的阵列基板，其特征在于，所述隔离条的数量为多个且间隔设置。
  9. 根据权利要求7或8所述的阵列基板，其特征在于，所述隔离条的材料为有机绝缘材料、无机绝缘材料、或多层不同绝缘材料的组合。
  10. 根据权利要求7或8所述的阵列基板，其特征在于，该有机层的材料为树脂。
  11. 根据权利要求8所述的阵列基板，其特征在于，所述第一导电部、所述第二导电部和所述电极总线上面覆盖有一层有机层，所述多个隔离条是该有机层上的开口槽，所述开口槽之间保留有该有机层的一部分。
  12. 根据权利要求11所述的阵列基板，其特征在于，该有机层的材料为有机绝缘材料、无机绝缘材料、或多层不同绝缘材料的组合。
  13. 根据权利要求11所述的阵列基板，其特征在于，该有机层的材料为树脂。
  14. 根据权利要求1-13所述的阵列基板，其特征在于，所述第一导电部和所述第二导电部的全部或者部分边缘还被设置成凹凸状。
  15. 一种显示装置，其特征在于，包括权利要求1～14任一项所述的阵列基板。
PCT/CN2019/127345 2019-01-08 2019-12-23 阵列基板和显示装置 WO2020143437A1 (zh)

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