WO2020140688A1 - 阵列基板及显示装置 - Google Patents
阵列基板及显示装置 Download PDFInfo
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- WO2020140688A1 WO2020140688A1 PCT/CN2019/123401 CN2019123401W WO2020140688A1 WO 2020140688 A1 WO2020140688 A1 WO 2020140688A1 CN 2019123401 W CN2019123401 W CN 2019123401W WO 2020140688 A1 WO2020140688 A1 WO 2020140688A1
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- Prior art keywords
- peripheral
- shielding layer
- array substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 160
- 230000002093 peripheral effect Effects 0.000 claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 56
- 238000002161 passivation Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 4
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000007788 liquid Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Definitions
- the invention relates to the field of display technology, in particular to an array substrate and a display device.
- an alignment layer needs to be made so that the liquid crystal can have an initial deflection angle, for example, polyimide is used as the material of the alignment layer, because polyimide has fluidity before being cured Yes, so some design is needed to control the boundary of the polyimide liquid coating.
- a substrate, the substrate is divided into a display area and a peripheral wiring area located outside the display area of the substrate;
- the peripheral wiring is located in the peripheral wiring area
- An insulating layer located on a side of the peripheral trace facing away from the substrate, the insulating layer has a plurality of grooves surrounding the display area, and the insulating layer and the groove between the grooves form a retaining wall structure , The extending direction of the groove crosses the peripheral wiring, and there is an overlapping area between the groove and the peripheral wiring;
- a conductive shielding layer is located on a side of the insulating layer facing away from the substrate, and an overlapping area of the peripheral trace and the groove is covered by an orthographic projection of the conductive shielding layer on the substrate.
- the conductive shielding layer includes a plurality of strip-shaped shield electrodes corresponding one-to-one with the peripheral traces, and one of the strips
- the orthographic projection of the shield electrode on the substrate covers the corresponding orthographic projection of the corresponding one of the peripheral traces passing through the retaining wall structure on the substrate.
- the conductive shield electrode includes at least one block shield electrode, and an orthographic projection of the block shield electrode on the substrate An orthographic projection on the substrate of a portion covering multiple peripheral traces passing through the retaining wall structure.
- the peripheral traces include data line leads.
- the peripheral wiring includes a common electrode lead; each of the common electrode leads includes a plurality of parallel sub-leads, and the parallel positions of the sub-leads and the retaining wall structure The orthographic projections on the substrate do not overlap each other.
- the conductive shielding layer includes a plurality of sub-strip shield electrodes corresponding to the sub-leads, and one of the sub-strip shield electrodes is on the substrate
- the orthographic projection covers the orthographic projection of the corresponding one of the sub-leads on the substrate.
- the array substrate provided by the present invention further includes: a metal shielding layer between the substrate and the peripheral wiring, the metal shielding layer and the peripheral wiring are insulated from each other, and the The overlapping area of the peripheral trace and the groove is covered by the orthographic projection of the metal shielding layer on the substrate.
- the metal shielding layer and the conductive shielding layer are electrically connected through a via, and the via is provided in an insulating layer outside the groove.
- the metal shielding layer includes a plurality of strip-shaped metal electrodes corresponding one-to-one with the peripheral traces, and one of the strips
- the orthographic projection of the metal electrode on the substrate covers a corresponding orthographic projection of the portion of the peripheral trace passing through the retaining wall structure on the substrate.
- the metal shield electrode includes at least one bulk metal electrode, and an orthographic projection of the bulk metal electrode on the substrate An orthographic projection on the substrate of a portion covering multiple peripheral traces passing through the retaining wall structure.
- the patterns of the conductive shielding layer and the metal shielding layer are only provided in the area where the peripheral wiring passes through the retaining wall structure, or the metal shielding
- the layer has a pattern that blocks the fan-out area of the peripheral traces.
- the insulating layer includes:
- a flattening layer on a side of the passivation layer facing away from the peripheral wiring, and the blocking wall structure is formed only on the flattening layer.
- the material of the conductive shielding layer is indium tin oxide, and the conductive shielding layer is located on the side of the planarization layer facing away from the substrate.
- the array substrate provided by the present invention further includes a pixel electrode located in the display area, and the conductive shielding layer is prepared in the same layer as the pixel electrode.
- the material of the conductive shielding layer is metal, and the conductive shielding layer is located between the planarization layer and the passivation layer.
- the array substrate provided by the present invention further includes touch electrode leads, and the conductive shielding layer is prepared in the same layer as the touch electrode leads.
- the array substrate provided by the present invention further includes a metal pixel electrode, and the conductive shielding layer is prepared in the same layer as the metal pixel electrode.
- the invention also provides a display device comprising the above array substrate provided by the invention.
- FIG. 1 is a plan view of an array substrate provided by an embodiment of the present invention.
- FIG. 2 is a cross-sectional view of a pixel thin film transistor in an array substrate provided by an embodiment of the present invention
- FIG. 3 is a cross-sectional view along the aa direction in FIG. 1;
- FIG. 4 is a cross-sectional view along the bb direction in FIG. 1;
- FIG. 5 is a cross-sectional view along the cc direction in FIG. 1;
- FIG. 6 is a plan view of another array substrate provided by an embodiment of the present invention.
- FIG. 7 is a plan view of another array substrate provided by an embodiment of the present invention.
- FIG. 8 is a cross-sectional view along the dd direction in FIG. 7;
- FIG. 9 is a plan view of another array substrate provided by an embodiment of the present invention.
- FIG. 10 is a plan view of another array substrate provided by an embodiment of the present invention.
- FIG. 11 is a plan view of another array substrate provided by an embodiment of the present invention.
- FIG. 12 is a cross-sectional view along the ee direction in FIG. 11;
- FIG. 13 is a cross-sectional view along the ff direction in FIG. 11;
- FIG. 14 is a plan view of another array substrate provided by an embodiment of the present invention.
- FIG. 15 is a cross-sectional view of another pixel thin film transistor in an array substrate provided by an embodiment of the present invention.
- FIG. 16 is a cross-sectional view along the gg direction in FIG. 14;
- 17 is a top view of an array substrate provided by an embodiment of the present invention.
- the retaining wall structure On the array substrate of the liquid crystal display, the retaining wall structure is arranged on the four sides within the frame sealant of the non-display area, and the retaining wall structure is composed of a slotted planarization layer.
- the polyimide liquid of the alignment film flows into the groove of the retaining wall structure.
- the retaining wall structure of the alignment film has a wavy design, and the flow of the polyimide liquid toward the retaining wall structure will follow the convex and concave portions The arc-shaped edges between them flow to buffer the force acting between the polyimide liquid and the retaining wall structure, so that the polyimide liquid cannot cross the retaining wall structure, thereby realizing the control of the boundary coated by the polyimide liquid.
- the source-drain metal layer traces that is, the passivation layer around the periphery traces are only protected by about 0.2 microns, and the following two problems are prone to occur: (1) In the orientation process Friction electrostatic damage is more likely to occur here; (2) Peripheral traces here are more likely to absorb impurity ions of the liquid crystal layer, resulting in uneven local brightness of the display and causing various traces.
- an array substrate provided by the present invention includes:
- the substrate 10 is provided with a display area A and a peripheral wiring area B provided outside the display area A of the substrate 10.
- FIG. 1 only shows the peripheral wiring area B;
- Peripheral trace 81 located in the peripheral trace area B;
- the insulating layer 100 on the side of the peripheral trace 81 facing away from the substrate 10 has a plurality of grooves 101 surrounding the display area.
- the insulating layer 100 and the groove 101 between the grooves 101 form a retaining wall structure 102.
- the extending direction of 101 intersects with the peripheral wiring 81, and there is an overlapping area between the groove 101 and the peripheral wiring 81; in FIG. 1, the extending direction of the groove 101 is the horizontal direction, and the extending direction of the peripheral wiring 81 is the vertical direction Take an example for explanation;
- the array substrate includes a substrate 10, the substrate 10 is provided with a display area and a peripheral wiring area, and a peripheral wiring 81 is provided in the peripheral wiring area, and the array substrate further includes a peripheral wiring disposed away from the substrate 10
- the insulating layer 100 has a plurality of grooves 101 corresponding to the area of the peripheral trace 81 to form a barrier wall structure 102, and the portion of the peripheral trace 81 and the groove 101 directly facing the substrate 10 is on the substrate 10 Is located in the orthographic projection of the conductive shielding layer 130 on the substrate 10.
- the conductive shielding layer 130 is formed on one side of the insulating layer 100, and the conductive shielding layer 130 shields the outside from damaging the surrounding traces 81 corresponding to the grooves 101 of the insulating layer 100.
- the conductive shielding The layer 130 further forms a further protection for the peripheral wiring 81 at the retaining wall structure 102.
- the conductive shielding layer 130 can shield external electric fields and static electricity, effectively solving the technical problems such as electrostatic discharge.
- the above-mentioned array substrate facilitates the formation of auxiliary protection for the peripheral wiring 81 at the retaining wall structure 102, avoids the problem of electrostatic damage that is easily generated here during the alignment process, and avoids the peripheral wiring here 81 Absorption of impurity ions in the liquid crystal layer causes local brightness unevenness of the display and causes various traces.
- the insulating layer 100 may specifically include:
- planarization layer 1002 disposed on the side of the passivation layer 1001 facing away from the peripheral trace 81 only forms the retaining wall structure 102 on the planarization layer 1002.
- the display area of the array substrate provided by the present invention may further include a transparent pixel electrode 110, wherein: the conductive shielding layer 130 may be connected to the transparent pixel electrode 110 same layer preparation.
- the preparation of the conductive shielding layer 130 and the transparent pixel electrode 110 in the same layer can reduce the thickness of the array substrate and simplify the production steps.
- the preparation material of the conductive shielding layer 130 is indium tin oxide semiconductor as an example for specific description, and the display area of the array substrate provided by the present invention, as shown in FIG. 2, may also be included in
- the substrate 10 is arranged along the substrate 10 toward the planarization layer 1002 in the order of the gate 20, the gate insulating layer 30, the active layer 40, the source and drain (the source 50 and the drain 60 are arranged in the same layer), and the etch stop layer 70,
- the peripheral traces 81 and the data lines 80 are located in the same layer on the side of the etch stop layer 70 facing away from the substrate 10, the passivation layer 1001 is on the side of the data line 80 facing away from the substrate 10, and the planarization layer 1002 is on the passivation layer 1001
- the transparent pixel electrode 110 is located on the side facing away from the substrate 10 of the planarization layer 1002.
- the conductive shielding layer 130 includes a plurality of strip-shaped shield electrodes corresponding to the peripheral traces 81, and the orthographic projection of one strip-shaped shield electrode on the substrate 10 covers the corresponding one of the peripheral traces 81 The orthographic projection of the portion passing through the retaining wall structure 102 on the substrate 10.
- a plurality of strip-shaped shield electrodes of the conductive shield layer 130 may correspond to the peripheral traces 81 one by one, that is, each strip-shaped shield electrode corresponds to a peripheral trace 81, And the orthographic projection of the strip-shaped shielding electrode on the substrate 10 covers the orthographic projection of the peripheral wiring 81 corresponding to it one-to-one on the portion of the retaining wall structure 102.
- each strip-shaped shield electrode forms a shield to the peripheral trace 81 corresponding to it one by one, so as to shield the peripheral trace 81 from external electric fields and static electricity, and effectively solve the technical problem of electrostatic discharge.
- each strip-shaped shield electrode may be generally a strip shape, and the edge thereof may be a straight line or a wavy line, which will not be repeated here.
- the peripheral wiring 81 includes data line leads, and the data line leads lead the data lines in the display area to corresponding connection terminals.
- the peripheral wiring 81 may further include a common electrode lead.
- the common electrode lead is used to lead the common electrode of the display area to the corresponding connection terminal. Since the common electrode lead is wider, as shown in FIG. 6, a wider common
- the electrode lead is divided into a plurality of parallel sub-leads 811, and the parallel positions of the sub-leads 811 and the retaining wall structure 102 do not overlap each other.
- Each common electrode lead with a larger width is designed to be composed of multiple sub-leads 811 with a smaller width in parallel, which reduces the width of the common electrode lead. Therefore, the coverage area of the common electrode lead can be reduced to facilitate shielding of external electric fields And static electricity, effectively solve the technical problems of electrostatic discharge.
- each strip-shaped shield electrode includes a plurality of sub-strip shield electrodes, and an orthographic projection of one sub-strip shield electrode on the substrate 10 covers one The orthographic projection of the sub-lead 811 on the substrate 10.
- each sub-strip shield electrode can correspond to the sub-lead 811 (as shown in FIG. 6), and each sub-strip shield electrode
- the one-to-one corresponding sub-leads 811 are shielded, or several sub-strip shield electrodes shield the same first sub-lead 811, or one sub-strip shield electrode shields multiple first sub-leads 811, which is not limited herein .
- the array substrate provided by the present invention may further include a metal shielding layer 21 formed between the substrate 10 and the peripheral trace 81, the metal shielding layer 21
- the peripheral trace 81 is insulated from each other, and the overlapping area of the peripheral trace 81 and the groove 101 is covered by the orthographic projection of the metal shield layer 21 on the substrate 10.
- the metal shielding layer 21 can be prepared in the same layer as the gate electrode 20.
- the metal shielding layer 21 can also be electrically connected to the conductive shielding layer 130 through a via 150, and the via 150 can be provided in the insulating layer 100 outside the groove structure 101, as shown in FIG. 7 and As shown in Figure 8.
- the metal shield layer 21 includes a plurality of strip-shaped metal electrodes corresponding one-to-one with the peripheral traces 81, and one strip-shaped metal electrode is formed on the substrate 10
- the orthographic projection covers the orthographic projection of the corresponding one of the peripheral traces 81 passing through the retaining wall structure 102 on the substrate 10.
- the strip metal electrode and the strip shield electrode corresponding to one peripheral trace 81 can be electrically connected through the via 150, and generally, the strip shield electrode will cover the strip metal electrode, that is, the area of the strip shield electrode is larger than The area of the strip metal electrode.
- the metal shield electrode 21 may include at least one bulk metal electrode.
- the orthographic projection of the bulk metal electrode on the substrate 10 covers multiple peripheral traces 81 passing through the retaining wall structure 102 Orthographic projection of part on the substrate 10.
- the plurality of strip-shaped shield electrodes corresponding to the plurality of peripheral traces 81 may be electrically connected to one bulk metal electrode through the vias 150, respectively.
- the patterns of the conductive shielding layer 130 and the metal shielding layer 21 may be provided only in the area where the peripheral wiring 81 passes through the retaining wall structure 102, ie The patterns of the conductive shielding layer 130 and the metal shielding layer 21 are not provided at the position of the peripheral lead 81 outside the retaining wall structure 102, which can reduce the thickness of the array substrate.
- the metal shielding layer 21 has a pattern that blocks the fan-out area of the peripheral trace 81, that is, the pattern of the metal shielding layer 21 is always provided under the peripheral trace 81, and in the fan-out area, The vertical projection of the metal shielding layer 21 on the substrate 10 is located in the vertical projection of the peripheral trace 81 on the substrate 10.
- the conductive shielding layer 130 may include at least one bulk shield electrode, and the orthographic projection of the bulk shield electrode on the substrate 10 covers multiple peripheral traces 81 through The orthographic projection of the portion passing through the barrier wall structure 102 on the substrate 10.
- the provision of the conductive shielding layer 130 includes block-shaped shielding electrodes, which can simplify the manufacturing process and improve the production efficiency.
- the preparation material of the conductive shielding layer 130 is metal
- the conductive shielding layer 130 may be disposed between the planarization layer 1002 and the passivation layer 1001, and the above embodiments are not described here. A detailed structural description will be made by using the material of the conductive shielding layer 130 as a metal.
- the conductive shielding layer 130 may be prepared in the same layer as the touch electrode lead 120, please refer to FIGS. 14 to 16.
- the display device using the above array substrate has a structure of in-cell touch (touch panel function embedded in liquid crystal pixels).
- the conductive shielding layer 130 can also be prepared in the same layer as the metal pixel electrode, which will not be described in detail here.
- an embodiment of the present invention further provides a display device, including the array substrate of the foregoing embodiment.
- the display device may be any product or component with a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Since the principle of the display device to solve the problem is similar to that of the aforementioned array substrate, the implementation of the display device can refer to the implementation of the aforementioned array substrate, and the repetition is not repeated here.
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Abstract
Description
Claims (18)
- 一种阵列基板,其中,包括:基板,所述基板分为显示区域和位于所述基板显示区域外侧的周边走线区域;周边走线,位于所述周边走线区域;绝缘层,位于所述周边走线背离所述基板一侧,所述绝缘层具有环绕所述显示区域的多个凹槽,所述凹槽之间的绝缘层和所述凹槽构成挡墙结构,所述凹槽的延伸方向与所述周边走线交叉,且所述凹槽与所述周边走线存在交叠区域;导电屏蔽层,位于所述绝缘层背离所述基板一侧,所述周边走线与凹槽的交叠区域被所述导电屏蔽层在所述基板上的正投影所覆盖。
- 根据权利要求1所述的阵列基板,其中,所述周边走线为多条,所述导电屏蔽层包括与所述周边走线一一对应的多个条状屏蔽电极,且一个所述条状屏蔽电极在所述基板上的正投影覆盖对应的一条所述周边走线穿过所述挡墙结构的部分在所述基板上的正投影。
- 根据权利要求1所述的阵列基板,其中,所述周边走线为多条,所述导电屏蔽电极包括至少一个块状屏蔽电极,一个所述块状屏蔽电极在所述基板上的正投影覆盖多条所述周边走线穿过所述挡墙结构的部分在所述基板上的正投影。
- 根据权利要求1所述的阵列基板,其中,所述周边走线包括数据线引线。
- 根据权利要求1所述的阵列基板,其中,所述周边走线包括公共电极引线;每个所述公共电极引线包括多条并联的子引线,所述子引线并联位置与所述挡墙结构在所述基板上的正投影互不交叠。
- 根据权利要求5所述的阵列基板,其中,所述导电屏蔽层包括与所述子引线一一对应的多个子条状屏蔽电极,且一个所述子条状屏蔽电极在所述 基板上的正投影覆盖对应的一条所述子引线在所述基板上的正投影。
- 根据权利要求1所述的阵列基板,其中,还包括:位于所述基板与所述周边走线之间的金属遮蔽层,所述金属屏蔽层与所述周边走线相互绝缘,且所述周边走线与凹槽的交叠区域被所述金属屏蔽层在所述基板上的正投影所覆盖。
- 根据权利要求7所述的阵列基板,其中,所述金属遮蔽层与所述导电屏蔽层之间通过过孔电连接,且所述过孔设于所述凹槽之外的绝缘层。
- 根据权利要求7所述的阵列基板,其中,所述周边走线为多条,所述金属屏蔽层包括与所述周边走线一一对应的多个条状金属电极,且一个所述条状金属电极在所述基板上的正投影覆盖对应的一条所述周边走线穿过所述挡墙结构的部分在所述基板上的正投影。
- 根据权利要求7所述的阵列基板,其中,所述周边走线为多条,所述金属屏蔽电极包括至少一个块状金属电极,一个所述块状金属电极在所述基板上的正投影覆盖多条所述周边走线穿过所述挡墙结构的部分在所述基板上的正投影。
- 根据权利要求7所述的阵列基板,其中,所述导电屏蔽层和所述金属屏蔽层的图案仅设置在所述周边走线穿过所述挡墙结构的区域,或,所述金属屏蔽层具有遮挡所述周边走线的扇出区域的图案。
- 根据权利要求1-11任一项所述的阵列基板,其中,所述绝缘层包括:位于所述周边走线背离所述基板一侧的钝化层;位于所述钝化层背离所述周边走线一侧的平坦化层,仅在所述平坦化层形成所述挡墙结构。
- 根据权利要求12所述的阵列基板,其中,所述导电屏蔽层的材料为氧化铟锡,所述导电屏蔽层位于所述平坦化层背离所述基板的一侧。
- 根据权利要求13所述的阵列基板,其中,还包括位于所述显示区域的像素电极,所述导电屏蔽层与所述像素电极同层制备。
- 根据权利要求12所述的阵列基板,其中,所述导电屏蔽层的材料为 金属,所述导电屏蔽层位于所述平坦化层与所述钝化层之间。
- 根据权利要求15所述的阵列基板,其中,还包括触摸电极引线,所述导电屏蔽层与所述触摸电极引线同层制备。
- 根据权利要求15所述的阵列基板,其中,还包括金属像素电极,所述导电屏蔽层与所述金属像素电极同层制备。
- 一种显示装置,其中,包括根据权利要求1-17任一项所述的阵列基板。
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US20080137022A1 (en) * | 2006-12-06 | 2008-06-12 | Hitachi Displays, Ltd. | Liquid crystal display device |
CN102792219A (zh) * | 2010-04-16 | 2012-11-21 | 夏普株式会社 | 显示装置 |
CN102998820A (zh) * | 2011-09-12 | 2013-03-27 | 株式会社日本显示器东 | 显示装置 |
CN105304642A (zh) * | 2015-09-24 | 2016-02-03 | 南京中电熊猫液晶显示科技有限公司 | 一种阵列基板及其制造方法 |
CN209070278U (zh) * | 2019-01-02 | 2019-07-05 | 京东方科技集团股份有限公司 | 一种阵列基板 |
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US20080137022A1 (en) * | 2006-12-06 | 2008-06-12 | Hitachi Displays, Ltd. | Liquid crystal display device |
CN102792219A (zh) * | 2010-04-16 | 2012-11-21 | 夏普株式会社 | 显示装置 |
CN102998820A (zh) * | 2011-09-12 | 2013-03-27 | 株式会社日本显示器东 | 显示装置 |
CN105304642A (zh) * | 2015-09-24 | 2016-02-03 | 南京中电熊猫液晶显示科技有限公司 | 一种阵列基板及其制造方法 |
CN209070278U (zh) * | 2019-01-02 | 2019-07-05 | 京东方科技集团股份有限公司 | 一种阵列基板 |
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