CN209070278U - 一种阵列基板 - Google Patents
一种阵列基板 Download PDFInfo
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- CN209070278U CN209070278U CN201920005949.9U CN201920005949U CN209070278U CN 209070278 U CN209070278 U CN 209070278U CN 201920005949 U CN201920005949 U CN 201920005949U CN 209070278 U CN209070278 U CN 209070278U
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- 239000000758 substrate Substances 0.000 title claims abstract description 146
- 238000009413 insulation Methods 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000000873 masking effect Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 22
- 239000007788 liquid Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 231100000241 scar Toxicity 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
本实用新型涉及显示技术领域,公开了一种阵列基板,该阵列基板包括基板,基板设有显示区域和设于基板显示区域外侧的周边走线区域;设置于周边走线区域的周边走线;设置于周边走线背离基板一侧的绝缘薄膜,绝缘薄膜中与周边走线区域对应位置具有多个凹槽以形成挡墙结构;设置于绝缘薄膜一侧的保护屏蔽层,且周边走线与凹槽正对的部位在基板上的垂直投影位于保护屏蔽层在基板上的垂直投影内。本实用新型提供的阵列基板内保护屏蔽层形成于绝缘薄膜的一侧,保护屏蔽层遮蔽绝缘薄膜上凹槽对应部位的周边走线,明显的,保护屏蔽层进一步形成对挡墙结构处周边走线的进一步保护,该结构可以屏蔽外部电场和静电,有效解决静电释放的技术问题。
Description
技术领域
本实用新型涉及显示技术领域,特别涉及一种阵列基板。
背景技术
在液晶显示器的阵列基板上,挡墙布置在非显示区封框胶以内的四边,挡墙由平坦化层开槽构成。取向膜的聚酰亚胺液流入挡墙的凹槽内,在此,取向膜挡墙为波浪状的设计,聚酰亚胺液朝取向膜挡墙的流动会顺着凸部和凹部间的弧状边缘来流动,缓冲聚酰亚胺液和取向膜挡墙间作用的力量,使聚酰亚胺液不能越过取向膜挡墙,从而实现控制所述聚酰亚胺液涂覆的边界。
但是,由于挡墙处的平坦化层被挖空,使得源漏金属层走线上方仅有0.2微米左右的钝化层保护,容易发生以下两个问题:(1)取向工艺中在此处更容易发生摩擦静电损伤;(2)此处的电极线更容易吸附液晶层的杂质离子导致显示器局部亮度不均匀,造成各种痕迹的现象。
实用新型内容
本实用新型提供了一种阵列基板,上述阵列基板通过改变基板内的结构,便于对挡墙处的周边走线形成辅助保护,避免产生取向工艺中此处易产生的静电损伤问题,以及避免此处周边走线吸附液晶层的杂质离子导致显示器局部亮度不均匀、造成各种痕迹的现象。
为达到上述目的,本实用新型提供以下技术方案:
一种阵列基板,包括:
基板,所述基板设有显示区域和设于所述基板显示区域外侧的周边走线区域;
设置于所述周边走线区域的周边走线;
设置于所述周边走线背离所述基板一侧的绝缘薄膜,所述绝缘薄膜中与所述周边走线区域对应位置具有多个凹槽以形成挡墙结构;
设置于所述绝缘薄膜一侧的保护屏蔽层,且所述周边走线与凹槽正对的部位在所述基板上的垂直投影位于所述保护屏蔽层在所述基板上的垂直投影内。
上述阵列基板中,阵列基板包括基板,基板设有显示区域和周边走线区域,周边走线区域内设有周边走线,且该阵列基板还包括设于周边走线背离基板一侧的绝缘薄膜以及设于绝缘薄膜一侧的保护屏蔽层。具体的,上述阵列基板中,绝缘薄膜中与周边走线区域对应位置具有多个凹槽以形成挡墙结构,而周边走线与凹槽正对的部位在基板上的垂直投影位于保护屏蔽层在所述基板上的垂直投影内。
本实用新型提供的阵列基板内保护屏蔽层形成于绝缘薄膜的一侧,保护屏蔽层遮蔽绝缘薄膜上凹槽对应部位的周边走线,明显的,保护屏蔽层进一步形成对挡墙结构处周边走线的进一步保护,该结构可以屏蔽外部电场和静电,有效解决静电释放的技术问题。
因此,上述阵列基板通过改变基板内的结构,便于对挡墙处的周边走线形成辅助保护,避免产生取向工艺中此处易产生的静电损伤问题,以及避免此处周边走线吸附液晶层的杂质离子导致显示器局部亮度不均匀、造成各种痕迹的现象。
优选地,所述周边走线包括多条第一数据线引线,所述保护屏蔽层包括多个遮蔽块,且多个所述遮蔽块在所述基板上的垂直投影覆盖多条所述第一数据线引线在所述基板上的垂直投影。
优选地,每个所述第一数据线引线包括多条第一子数据线引线,且多条所述第一子数据线引线之间并联。
优选地,每个所述遮蔽块包括多个子遮蔽块,且多个所述子遮蔽块在所述基板上的垂直投影覆盖多条所述第一子数据线引线在所述基板上的垂直投影。
优选地,还包括形成于所述基板与所述第一数据线引线之间的金属遮蔽层。
优选地,所述金属遮蔽层与所述保护屏蔽层之间通过过孔电连接,且所述过孔设于所述挡墙结构。
优选地,所述基板还设有用于连接所述显示区域和所述周边走线区域的扇出区,所述扇出区设有与所述第一数据线引线一一对应的第二数据线引线,且每条所述第二数据线引线与与其一一对应的所述第二数据线引线电连接。
优选地,所述第二数据线引线对应部位设置有所述金属遮蔽层,所述金属遮蔽层在所述基板上的垂直投影位于所述第二数据线引线在所述基板上的垂直投影内。
优选地,所述周边走线包括多条第一数据线引线,所述保护屏蔽层包括一个遮蔽块,且所述遮蔽块在所述基板上的垂直投影覆盖各所述第一数据线引线在所述基板上的垂直投影。
优选地,所述绝缘薄膜包括:
设置于所述周边走线背离所述基板一侧的钝化层;
设置于所述钝化层背离所述周边走线一侧的平坦化层,所述平坦化层形成所述挡墙结构。
优选地,所述保护屏蔽层的制备材料为铟锡氧化物半导体,所述保护屏蔽层设于所述平坦化层背离所述基板的一侧。
优选地,还包括像素电极,所述保护屏蔽层与所述像素电极同层制备。
优选地,所述保护屏蔽层的制备材料为金属,所述保护屏蔽层设于所述平坦化层朝向所述基板的一侧。
优选地,还包括触摸电极引线,所述保护屏蔽层与所述触摸电极引线同层制备。
优选地,还包括金属像素电极,所述保护屏蔽层与所述金属像素电极同层制备。
附图说明
图1为本实用新型实施例提供的阵列基板的平面图;
图2为图1中阵列基板的像素薄膜晶体管截面图;
图3为图1中阵列基板的纵向截面图;
图4为图1中阵列基板的横向截面图;
图5为图1中阵列基板的又一横向截面图;
图6为本实用新型实施例提供的又一阵列基板的平面图;
图7为本实用新型实施例提供的又一阵列基板的平面图;
图8为图7中阵列基板的像素薄膜晶体管截面图;
图9为图7中阵列基板的纵向截面图;
图10为图7中阵列基板的横向截面图;
图11为图7中阵列基板的又一横向截面图;
图12为本实用新型实施例提供的又一阵列基板的平面图;
图13为本实用新型实施例提供的又一阵列基板的平面图;
图14为本实用新型实施例提供的又一阵列基板的平面图;
图15为图14中阵列基板的像素薄膜晶体管截面图;
图16为图14中阵列基板的纵向截面图;
图17为图14中阵列基板的横向截面图;
图18为图14中阵列基板的又一横向截面图;
图19为本实用新型实施例提供的又一阵列基板的平面图;
图20为图19中阵列基板的像素薄膜晶体管截面图;
图21为图19中阵列基板的纵向截面图。
图标:10-基板;20-栅极;30-栅极绝缘层;40-有源层;50-源极;60-漏极;70-刻蚀阻挡层;80-数据线引线;81-第一数据线引线;811-第一子数据线引线;82-第二数据线引线;90-钝化层;100-平坦化层;101-凹槽;110-像素电极;120-触摸电极引线;130-保护屏蔽层;140-金属遮蔽层;150-过孔。
具体实施方式
下面将结合本实用新型实施例中的附图,对本实用新型实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本实用新型一部分实施例,而不是全部的实施例。基于本实用新型中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本实用新型保护的范围。
请参考图1,本实用新型提供一种阵列基板,包括:
基板10,基板10设有显示区域和设于基板10显示区域外侧的周边走线区域;
设置于周边走线区域的周边走线;
设置于周边走线背离基板10一侧的绝缘薄膜,绝缘薄膜中与周边走线区域对应位置具有多个凹槽101以形成挡墙结构;
设置于绝缘薄膜一侧的保护屏蔽层130,且周边走线与凹槽101正对的部位在基板10上的垂直投影位于保护屏蔽层130在基板10上的垂直投影内。
上述阵列基板中,阵列基板包括基板10,基板10设有显示区域和周边走线区域,周边走线区域内设有周边走线,且该阵列基板还包括设于周边走线背离基板10一侧的绝缘薄膜以及设于绝缘薄膜一侧的保护屏蔽层130。具体的,上述阵列基板中,绝缘薄膜中与周边走线区域对应位置具有多个凹槽101以形成挡墙结构,而周边走线与凹槽101正对的部位在基板10上的垂直投影位于保护屏蔽层130在基板10上的垂直投影内。
本实用新型提供的阵列基板内保护屏蔽层130形成于绝缘薄膜的一侧,保护屏蔽层130遮蔽绝缘薄膜上凹槽101对应部位的周边走线,明显的,保护屏蔽层130进一步形成对挡墙结构处周边走线的进一步保护,该结构可以屏蔽外部电场和静电,有效解决静电释放的技术问题。
因此,上述阵列基板通过改变基板10内的结构,便于对挡墙处的周边走线形成辅助保护,避免产生取向工艺中此处易产生的静电损伤问题,以及避免此处周边走线吸附液晶层的杂质离子导致显示器局部亮度不均匀、造成各种痕迹的现象。
具体的,绝缘薄膜包括:
设置于周边走线背离基板10一侧的钝化层90;
设置于钝化层90背离周边走线一侧的平坦化层100,平坦化层100形成挡墙结构。
值得注意的是,屏蔽保护层的制备材料存在多种可能:
当保护屏蔽层130的制备材料为铟锡氧化物半导体时,本实用新型提供的阵列基板还包括像素电极110,其中:保护屏蔽层130与像素电极110同层制备。
需要说明的是,保护屏蔽层130与像素电极110同层制备可以减小阵列基板的厚度,且简化生产步骤。
值得注意的是,以下技术方案中,以保护屏蔽层130的制备材料为铟锡氧化物半导体为例进行具体说明,且本实用新型提供的阵列基板上还包括在基板10朝向平坦化层100一侧、沿基板10指向平坦化层100依次排列的栅极20、栅极绝缘层30、有源层40、源漏极(源极50和漏极60同层设置)以及刻蚀阻挡层70,其中,周边走线即数据线引线80位于刻蚀阻挡层70背离基板10的一侧,钝化层90位于数据线引线80背离基板10的一侧,平坦化层100位于钝化层90背离基板10的一侧,像素电极110位于平坦化层100背离基板10的一侧。
在上述技术方案的基础上,周边走线与保护遮蔽层之间的遮蔽关系存在多种可能,具体至少为以下几种结构中的一种:
结构一:
周边走线包括多条第一数据线引线81,保护屏蔽层130包括多个遮蔽块,且多个遮蔽块在基板10上的垂直投影覆盖多条第一数据线引线81在基板10上的垂直投影。
具体的,请参考图1、图2至图5,保护屏蔽层130的多个遮蔽块可以与周边走线内的多条第一数据线引线81一一对应,即,每个遮蔽块对应一条第一数据线引线81,且该遮蔽块在基板10上的垂直投影覆盖与其一一对应的第一数据线引线81在基板10上的垂直投影。
由上述分析可知,每个遮蔽块形成对与其一一对应的第一数据线引线81的遮蔽,以针对该条第一数据线引线81屏蔽外部电场和静电,有效解决静电释放的技术问题。
需要说明的是,每个遮蔽块的形状可以为条形,或者其他形状,在此不再进行赘述。
当然,除遮蔽块与第一数据线引线81一一对应的结构外,还存在若干遮蔽块遮蔽同一条第一数据线引线81,或者,一个遮蔽块遮蔽多条第一数据线引线81,以及上述各种结构共同存在的结构,值得注意的是,遮蔽块与第一数据线引线81的设置形式可根据实际生产设计需求进行变化。
在上述技术方案的基础上,作为一种优选实施方式,设置每个第一数据线引线81包括多条第一子数据线引线811,且多条第一子数据线引线811之间并联。
需要说明的是,将每条宽度较大的第一数据线引线81设计成由多条宽度较小的第一子数据线引线811并联组成,减小了周边走线的宽度,因而,可以减小周边走线的覆盖面积,便于屏蔽外部电场和静电,有效解决静电释放的技术问题。
对应上述技术方案中的多条第一子数据线引线811,可设置:每个遮蔽块包括多个子遮蔽块,且多个子遮蔽块在基板10上的垂直投影覆盖多条第一子数据线引线811在基板10上的垂直投影。
需要说明的是,参照遮蔽块与第一数据引线之间的对应关系,每个子遮蔽块可以与第一子数据线引线811一一对应(如图6所示),且每个子遮蔽块对与其一一对应的第一子数据线引线811进行遮蔽,或者,若干子遮蔽块遮蔽同一条第一子数据线引线811,或者,一个子遮蔽块遮蔽多条第一子数据线引线811。
此外,还存在上述各种结构共同存在的结构,值得注意的是,子遮蔽块与第一子数据线引线811的设置形式可根据实际生产设计需求进行变化。
在上述技术方案的基础上,作为一种实施方式:本实用新型提供的阵列基板还包括形成于基板10与第一子数据线引线811之间的金属遮蔽层(金属遮蔽层与栅极20同层制备)。
在上述技术方案的基础上行,金属遮蔽层与保护屏蔽层130之间通过过孔150电连接,且过孔150设于挡墙结构,如图7、图8至图11所示。
作为另一种实施方式:基板10还设有用于连接显示区域和周边走线区域的扇出区,扇出区设有与第一数据线引线81一一对应的第二数据线引线82,且每条第二数据线引线82与与其一一对应的第二数据线引线82电连接。
具体的,请参考图12,第二数据线引线82对应部位设置未设有金属遮蔽层140。
或者,请参考图13,第二数据线引线82对应部位设置有金属遮蔽层140,金属遮蔽层140在基板10上的垂直投影位于第二数据线引线82在基板10上的垂直投影内。
结构二:
请参考图14、图15至图18,周边走线包括多条第一数据线引线81,保护屏蔽层130包括一个遮蔽块,且遮蔽块在基板10上的垂直投影覆盖各第一数据线引线81在基板10上的垂直投影。
需要说明的是,设置保护屏蔽层130仅包括一个遮蔽块,可简化制备工艺,提高生产效率。
此外,当保护屏蔽层130的制备材料为金属时,保护屏蔽层130设于平坦化层100朝向基板10的一侧,在此不再对上述各实施方式以保护屏蔽层130的制备材料为金属进行详细结构描述。
当然,当本实用新型提供的阵列基板还包括触摸电极引线120时,保护屏蔽层130与触摸电极引线120同层制备,请参考图19以及图20和图21。
需要说明的是,应用上述阵列基板的显示装置,为in cell touch(触摸面板功能嵌入到液晶像素中)的结构。
此外,当本实用新型提供的阵列基板还包括金属像素电极110时,保护屏蔽层130与金属像素电极110同层制备。
显然,本领域的技术人员可以对本实用新型实施例进行各种改动和变型而不脱离本实用新型的精神和范围。这样,倘若本实用新型的这些修改和变型属于本实用新型权利要求及其等同技术的范围之内,则本实用新型也意图包含这些改动和变型在内。
Claims (15)
1.一种阵列基板,其特征在于,包括:
基板,所述基板设有显示区域和设于所述基板显示区域外侧的周边走线区域;
设置于所述周边走线区域的周边走线;
设置于所述周边走线背离所述基板一侧的绝缘薄膜,所述绝缘薄膜中与所述周边走线区域对应位置具有多个凹槽以形成挡墙结构;
设置于所述绝缘薄膜一侧的保护屏蔽层,且所述周边走线与凹槽正对的部位在所述基板上的垂直投影位于所述保护屏蔽层在所述基板上的垂直投影内。
2.根据权利要求1所述的阵列基板,其特征在于,所述周边走线包括多条第一数据线引线,所述保护屏蔽层包括多个遮蔽块,且多个所述遮蔽块在所述基板上的垂直投影覆盖多条所述第一数据线引线在所述基板上的垂直投影。
3.根据权利要求2所述的阵列基板,其特征在于,每个所述第一数据线引线包括多条第一子数据线引线,且多条所述第一子数据线引线之间并联。
4.根据权利要求3所述的阵列基板,其特征在于,每个所述遮蔽块包括多个子遮蔽块,且多个所述子遮蔽块在所述基板上的垂直投影覆盖多条所述第一子数据线引线在所述基板上的垂直投影。
5.根据权利要求4所述的阵列基板,其特征在于,还包括形成于所述基板与所述第一数据线引线之间的金属遮蔽层。
6.根据权利要求5所述的阵列基板,其特征在于,所述金属遮蔽层与所述保护屏蔽层之间通过过孔电连接,且所述过孔设于所述挡墙结构。
7.根据权利要求5所述的阵列基板,其特征在于,所述基板还设有用于连接所述显示区域和所述周边走线区域的扇出区,所述扇出区设有与所述第一数据线引线一一对应的第二数据线引线,且每条所述第二数据线引线与与其一一对应的所述第二数据线引线电连接。
8.根据权利要求7所述的阵列基板,其特征在于,所述第二数据线引线对应部位设置有所述金属遮蔽层,所述金属遮蔽层在所述基板上的垂直投影位于所述第二数据线引线在所述基板上的垂直投影内。
9.根据权利要求1所述的阵列基板,其特征在于,所述周边走线包括多条第一数据线引线,所述保护屏蔽层包括一个遮蔽块,且所述遮蔽块在所述基板上的垂直投影覆盖各所述第一数据线引线在所述基板上的垂直投影。
10.根据权利要求1-9任一项所述的阵列基板,其特征在于,所述绝缘薄膜包括:
设置于所述周边走线背离所述基板一侧的钝化层;
设置于所述钝化层背离所述周边走线一侧的平坦化层,所述平坦化层形成所述挡墙结构。
11.根据权利要求10所述的阵列基板,其特征在于,所述保护屏蔽层的制备材料为铟锡氧化物半导体,所述保护屏蔽层设于所述平坦化层背离所述基板的一侧。
12.根据权利要求11所述的阵列基板,其特征在于,还包括像素电极,所述保护屏蔽层与所述像素电极同层制备。
13.根据权利要求10所述的阵列基板,其特征在于,所述保护屏蔽层的制备材料为金属,所述保护屏蔽层设于所述平坦化层朝向所述基板的一侧。
14.根据权利要求13所述的阵列基板,其特征在于,还包括触摸电极引线,所述保护屏蔽层与所述触摸电极引线同层制备。
15.根据权利要求13所述的阵列基板,其特征在于,还包括金属像素电极,所述保护屏蔽层与所述金属像素电极同层制备。
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CN110993670A (zh) * | 2019-12-16 | 2020-04-10 | 武汉华星光电半导体显示技术有限公司 | Oled显示面板 |
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