WO2020134572A1 - 一种存储器内建自测试电路和对存储器的测试方法 - Google Patents

一种存储器内建自测试电路和对存储器的测试方法 Download PDF

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Publication number
WO2020134572A1
WO2020134572A1 PCT/CN2019/115239 CN2019115239W WO2020134572A1 WO 2020134572 A1 WO2020134572 A1 WO 2020134572A1 CN 2019115239 W CN2019115239 W CN 2019115239W WO 2020134572 A1 WO2020134572 A1 WO 2020134572A1
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test
memory
algorithm
test element
instruction
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PCT/CN2019/115239
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English (en)
French (fr)
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张先富
王正波
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华为技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

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  • the present application relates to the field of memory technology, and in particular, to a built-in self-test circuit in a memory and a method for testing the memory.
  • the MBIST circuit targets the memory, automatically generates a test circuit for the memory, and detects the memory by executing a specific test algorithm Certain defects exist in different test algorithms to obtain different memory test coverage.
  • An algorithm module corresponds to a test algorithm.
  • the MBIST circuit receives a test instruction, it can be generated according to the background data specified in the test instruction and the pre-stored algorithm module Corresponding test algorithm to execute the test algorithm on the memory to detect defects in the memory.
  • the embodiments of the present application provide a built-in self-test circuit in a memory and a test method for the memory, which are used to reduce the development cost of modifying the test algorithm supported by the MBIST circuit.
  • an embodiment of the present application provides a built-in self-test circuit in a memory, including: an algorithm generation module, which is used according to a target test instruction according to background data, a pre-stored test element module, and a target test algorithm The construction rule of each test element constructs each of the test elements in sequence; the algorithm execution module is used to sequentially execute each of the test elements on the memory.
  • the built-in self-test MBIST circuit of the memory provided by this application constructs the test elements of the test algorithm by pre-storing the test element module, and then executes the test elements of the test algorithm on the memory to complete the test.
  • the construction rule includes a construction parameter
  • the construction parameter includes a combination of memory operations included in the corresponding test element, and an operand of each memory operation
  • the construction rule includes a combination of memory operations included in the corresponding test element, and an operand of each memory operation
  • the target test algorithm includes N test elements
  • the target test instruction includes N sub-test instructions, i is a positive integer not greater than N, and the i-th sub-test instruction is used to instruct the MBIST circuit to perform the i-th test of the target test algorithm on the memory Element, when the algorithm generating module is used to construct the i-th test element, specifically used to construct the i-th test element according to the i-th sub-test instruction.
  • the built-in self-test circuit in the memory further includes a recycling module, and the recycling module is used in the algorithm After executing the i-th test element on the memory, the execution module sends the recycling information of the i-th instruction ID of the sub-test instruction to the processing circuit, and the processing circuit is used to manage the idle instruction identifier and The instruction mark generates test instructions.
  • the recycling information of the instruction identifier of the test instruction corresponding to the test element after the execution of the test element is completed it is beneficial to increase the idle instruction identifier of the processor, help to ensure the continuation of the test, and reduce the test running time.
  • an embodiment of the present application provides a method for testing a memory, including: a built-in self-test MBIST circuit in the memory according to a target test instruction according to background data, pre-stored test element modules, and construction rules of each test element of the target test algorithm , Construct each test element in sequence; the MBIST circuit sequentially executes each test element to the memory.
  • the construction rule includes a construction parameter
  • the construction parameter includes a combination of memory operations included in the corresponding test element, and an operand of each memory operation At least one of the correspondence with the background data, the data length of the operand of each memory operation, and the address sequence of each memory operation.
  • the construction rule further includes a module identifier of a test element module that matches the corresponding test element;
  • the MBIST circuit constructing the test element includes: the MBIST circuit acquiring a target test element module from a plurality of pre-stored test element modules according to the module identification in the test element construction rule; the MBIST circuit according to the background data, The target test element module and the construction parameters of the test element construct the test element.
  • the target test algorithm includes N test elements
  • the test instruction includes N sub-test instructions, i is a positive integer not greater than N, and the i-th sub-test instruction is used to instruct the MBIST circuit to perform the i-th test element of the target test algorithm on the memory
  • the MBIST circuit constructs the i-th test element includes: the MBIST circuit constructs the i-th test element according to the i-th sub-test instruction.
  • the method further includes: after executing the i-th test element on the memory, the The MBIST circuit sends the recycling information of the instruction identifier of the i-th sub-test instruction to the processing circuit.
  • the processing circuit is used to manage the idle instruction identifier and generate a test instruction according to the idle instruction identifier.
  • Figure 1 is a schematic diagram of the MBIST test system
  • FIG. 2 is a schematic diagram of an embodiment of the MBIST circuit of this application.
  • FIG. 3 is a schematic diagram of an embodiment of the MBIST test system of this application.
  • FIG. 4 is a schematic diagram of the memory testing process of the MBIST test system of this application.
  • FIG. 5 is another schematic diagram of the memory test process of the MBIST test system of this application.
  • FIG. 6 is another schematic diagram of the memory testing process of the MBIST test system of this application.
  • FIG. 7 is a schematic diagram of an embodiment of a test method for a memory of this application.
  • step 801 is a schematic diagram of a possible detailed step of step 701 in the embodiment corresponding to FIG. 7;
  • FIG. 9 is a schematic diagram of an embodiment of a method for performing an ith test element on a memory in this application.
  • the embodiments of the present application provide a built-in self-test circuit for a memory and a method for testing the memory.
  • At least one item (a) in a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be a single or multiple .
  • Modern integrated circuits increasingly need to embed memory on the semiconductor chip itself.
  • the traditional test method for memory is restricted by the test difficulty and test cost, which is no longer accepted by chip design manufacturers.
  • the most commonly used test method for memory is to achieve it through the memory built-in self-test (MBIST) method, which automatically generates a test circuit for the memory, reads and writes the memory address according to the corresponding test algorithm, and completes Memory testing.
  • MBIST memory built-in self-test
  • this test method will add some control logic to the circuit to increase the area of the chip, for large-scale test circuits, this method can achieve test automation, reduce test duration, improve test coverage, and greatly save test cost.
  • the MBIST method is a test method that uses a specific test algorithm to detect certain defects in the memory by implementing a specific test algorithm. Different test algorithms can obtain different memory test coverage.
  • FIG. 1 it is a schematic structural diagram of an MBIST test system.
  • the MBIST test system includes a processing circuit 1, an MBIST circuit 2, a memory controller 3, and a memory 4.
  • the processing circuit 1 such as a processor or a certain module in the processor, can Enter a test command into the MBIST circuit 2.
  • the test command is used to specify the test algorithm.
  • you can also specify the background data.
  • the MBIST circuit 2 is used to generate the corresponding test algorithm according to the received test command and execute the test algorithm.
  • the background data can also be pre-configured in the MBIST circuit 2.
  • test algorithm used by MBIST is a limited sequence of test elements.
  • the test elements include a series of specified memory operations, the operands of each memory operation, and the address sequence of memory operations.
  • the following are the algorithm primitives of the March C-algorithm:
  • the March C-algorithm contains 6 test elements, which are with Take the second test element
  • the memory operations included are read operation and write operation in sequence
  • the background data is A
  • the operand of the read operation is the background data
  • the operand of the write operation is the background data
  • the address sequence of the memory operation is ascending, that is The memory operations specified in the test element are sequentially performed on each storage unit in the memory 4 in ascending order.
  • the MBIST circuit 2 executes the second test element on the memory 4 means performing the following memory operations on each memory cell in the memory 4 in ascending order: first read the data in the current memory cell and compare it with A, if they are the same, then Write to current storage unit If they are not the same, an error will be reported.
  • An algorithm module corresponds to a test algorithm.
  • MBIST circuit 2 receives the test instruction sent by processing circuit 1, it can The specified background data and the pre-stored algorithm module generate corresponding test algorithms. If you need to modify the test algorithm, you need to modify the entire pre-written algorithm module. If you need to add a new test algorithm, you need to rewrite the entire algorithm module corresponding to the new test algorithm. Test algorithm development high cost.
  • the MBIST circuit 2 includes: an algorithm generation module 21 and an algorithm execution module 22, wherein the algorithm generation module 21 is used to Test instructions, according to the background data, the pre-stored test element module and the construction rules of each test element of the target test algorithm, construct each test element of the target test algorithm; the algorithm execution module 22 is used to execute each test of the target test algorithm for the memory to be tested element.
  • the test instruction is used to specify the test algorithm.
  • the background data can also be specified, or the background data can be pre-configured in the MBIST circuit 2 without being specified by the test instruction.
  • the same test element module can be used to construct multiple test elements. Specifically, multiple test elements that can be constructed by the same test element module can belong to the same test algorithm or different test algorithms. Specific restrictions.
  • MBIST circuit 2 can also The storage module 23 is included, and the storage module 23 can be used to store the test element module and the construction rules of each test element of multiple test algorithms. Developers can compare multiple algorithm elements of the test algorithm, write test element modules based on the similarities between different algorithm elements, and write construction rules for each test element based on the differences between different algorithm elements.
  • the operation objects of the memory operations in each test element of the March algorithm are the current memory unit.
  • the differences between the test elements are mainly reflected in: 1.
  • the address sequence of the memory operation may be different: ascending or descending; 2
  • the combination of included memory operations may be different: the included combination may be one operation, such as a write operation or a read operation, the included combination may be two operations, a combination of a read operation and a write operation, or a write operation and a read operation
  • the combination of operations, including the combination may be three or more operations, no longer specific examples; 3.
  • Correspondence between the operands of memory operations and background data may be different: the operands of memory operations may be background data, or, It may be the inverse of the background data; 4.
  • the data length of the operands of the memory operation may be different; and so on.
  • the construction rule of the test element may include a construction parameter
  • the construction parameter of the test element includes a combination of memory operations included in the corresponding test element, the number of operations of each memory operation in the corresponding test element, and At least one of the correspondence between the background data, the data length of the operand of each memory operation, and the address sequence of the memory operation. Developers can write at least one test element module for the March class algorithm, and use the above differences as configurable parameters to write the construction parameters of each test element.
  • the algorithm generation module 21 can be based on background data
  • the test element module of the test algorithm and the construction parameters of the test elements of the test algorithm construct the test elements of the test algorithm respectively, thereby obtaining the test algorithm. It can be seen that developers only need to write at least one test element module, and the algorithm generation module 21 can construct all March-type algorithms.
  • test elements used by MBIST in addition to the mainstream March algorithm, there are some other types of algorithms, such as Butterfly algorithm, Surrounding algorithm, 3-step algorithm and PRBS algorithm, etc., developers may need to write corresponding non-March algorithms Test element module.
  • Each test element of the non-March algorithm can be generated using the test element module corresponding to the algorithm, or some test elements in the non-March algorithm can be generated by reusing the test element module corresponding to the March algorithm, and other test elements can use this
  • the test element module corresponding to the algorithm is generated.
  • the algorithm primitives are as follows:
  • the algorithm contains 4 test elements, the first test element And the third test element
  • the operation objects in the memory operation are the current memory unit, and these two test elements can be constructed by reusing the test element module of the March-like algorithm.
  • the second test element in the algorithm And the fourth test element The operation object of some memory operations in is not the current memory unit, for example, The operation object is the memory unit on the east side of the current memory unit.
  • These two test elements cannot be constructed by reusing the test element module of the March class algorithm, so it is necessary to add the second test element of the Butterfly algorithm to the fourth test element.
  • Test element module. Only the read and write operands differ between M1 and M3.
  • the read and write operands of M3 are the inverse of the read and write operands of M1.
  • test elements and the fourth test element can be shared.
  • test element modules of other algorithms such as Surrounding algorithm, 3-step algorithm, and PRBS algorithm, etc.
  • test elements of non-March algorithms can be reused as much as possible.
  • test element modules of March algorithms can be used for tests that cannot reuse existing test element modules. Element write the corresponding test element module.
  • the MBIST test system may store multiple test element modules in advance, such as the March algorithm , Butterfly algorithm, Surrounding algorithm, 3-step algorithm and PRBS algorithm corresponding test element modules, different test element modules have different identifiers.
  • the construction rule of the test element also includes the module identification of the test element module corresponding to the test element.
  • the algorithm generation module 21 is based on the background data, the pre-stored test element module and the i-th test element in the target test algorithm.
  • test element When constructing the test element (where i is a positive integer and not greater than the number of test elements included in the target test algorithm), it is specifically used to identify multiple tests from pre-stored according to the module identification in the construction rule of the i-th test element Get the target test element module in the element module.
  • the target test element module is the test element module corresponding to the i-th test element of the target test algorithm. Then, based on the background data, the obtained target test element module and the i-th test element Construction parameters, construct the i-th test element of the target test algorithm.
  • the MBIST test system includes a processing circuit 1, an MBIST circuit 2, a storage controller 3, and a memory 4.
  • the MBIST circuit 2 includes: an algorithm generation module 21, an algorithm execution module 22, and a storage module 23, and each of the modules in the MBIST circuit 2 The function can be described in the embodiment corresponding to FIG. 2 and will not be repeated here.
  • the processing circuit 1 may input a test instruction to the MBIST circuit 2, the test instruction is used to indicate the background data and the target test algorithm selected for the test memory 4, and for ease of description, the test instruction corresponding to the complete target test algorithm is called the target test instruction.
  • the algorithm generation module 21 may construct each test element of the target test algorithm according to the received target test instruction, and the algorithm execution module 22 may execute each test element to execute the target test algorithm on the memory 4 to detect the memory 4 through the memory controller 3 Existing defects.
  • the MBIST test system sequentially tests the memory algorithm 4 and the test algorithm 1 and the test algorithm 2 in various ways.
  • the processing circuit 1 may first generate a test instruction 1, and the test instruction 1 may be used to instruct the MBIST circuit 2 to execute all test elements of the test algorithm 1, and at this time, the algorithm generation module 21 may be constructed according to the test instruction 1 To test all the test elements corresponding to the algorithm 1, the algorithm execution module 22 may execute each test element in sequence after the algorithm generation module 21 generates all the test elements of the test algorithm 1.
  • the processing circuit 1 may generate a test instruction 2 and continue to input the test instruction 2 to the MBIST circuit 2, the test instruction 2 is used to instruct the MBIST circuit 2 to execute all test elements of the test algorithm 2,
  • the algorithm execution module 22 may execute each test element in sequence after the algorithm generation module 21 generates all test elements of the test algorithm 2. Assuming that test algorithm 1 contains 5 test elements and test algorithm 2 contains 4 test elements, at this time, the process of MBIST test system testing memory 4 according to test algorithm 1 and test algorithm 2 can be embodied in a timeline manner, as shown in the figure 4 is shown.
  • the test operation duration of the MBIST test system generally includes two parts: the processing circuit 1 configures the target test instruction duration Ta and the MBIST circuit 2 executes the test duration Tb according to the target test instruction.
  • Ta is mainly limited by the operating frequency of the configuration processing circuit 1, etc., and occupies a relatively large proportion in the test running time;
  • Tb is mainly limited by factors such as the access timing parameters and access flow of the memory 4, which is generally fixed .
  • Ta1 and Ta2 in FIG. 4 represent the duration of the processing circuit 1 configuring the test command 1 and the test command 2, respectively, and Tb1 and Tb2 represent the duration of the MBIST circuit 2 performing the test according to the test command 1 and the test command 2, respectively. It can be seen that the test run duration of the MBIST test system corresponding to Example 1 is: Ta1+Tb1+Ta2+Tb2.
  • the algorithm execution module 22 may also execute the test element after the algorithm generation module 21 generates part of the test element (such as the first test element) of the test algorithm 1, as in Example 1. Compared, it is beneficial to reduce the duration Tb of the MBIST circuit 2 performing the test according to the target test instruction, thereby reducing the test running duration of the MBIST test system.
  • the target test instruction may include N sub-test instructions, and the i-th sub-test instruction is used to instruct the MBIST circuit 2 to perform the target test
  • the i-th test element of the algorithm, i is a positive integer not greater than N, that is to say, the process of the processing circuit 1 generating the target test instruction may specifically refer to the process of sequentially configuring N sub-test instructions, and the processing circuit 1 may configure the The sub-test instructions are sequentially input into the MBIST circuit 2, and thereafter, the MBIST circuit 2 may sequentially execute N sub-test instructions.
  • the process of the MBIST circuit 2 executing the i-th sub-test instruction may include: the algorithm generating module 21 constructs the i-th test element, After the generating module 21 constructs the i-th test element, the algorithm execution module 22 may execute the i-th test element. Therefore, the MBIST test system can test the test algorithm 1 and the test algorithm 2 on the memory 4 in sequence as in Example 3:
  • the processing circuit 1 can first configure the five sub-test instructions corresponding to the test algorithm 1, and sequentially generate the test instruction 1_1, the test Instruction 1_2, test instruction 1_3, test instruction 1_4 and test instruction 1_5, and sequentially input each generated test instruction to MBIST circuit 2.
  • the test command 1_1 can be used to instruct the MBIST circuit 2 to execute the first test element of the test algorithm 1
  • the test command 1_2 can be used to instruct the MBIST circuit 2 to execute the second test element of the test algorithm 1 and so on
  • the test command 1_5 It can be used to instruct the MBIST circuit 2 to execute the fifth test element of the test algorithm 1.
  • the test instruction 1_1 can be input into the algorithm generation module 21, the algorithm generation module 21 can construct the first test element of the test algorithm 1 according to the test instruction 1_1, and the algorithm execution module 22 can be in the algorithm generation module 21 Execute the test element after generating the first test element of test algorithm 1.
  • the MBIST circuit 2 can sequentially execute the test instruction 1_2, the test instruction 1_3, the test instruction 1_4, and the test instruction 1_5.
  • the processing circuit 1 may generate four sub-test instructions corresponding to the test algorithm 2, and sequentially generate a test instruction 2_1, a test instruction 2_2, a test instruction 2_3, and a test instruction 2_4, and Input each generated test instruction to MBIST circuit 2 in sequence, where test instruction 2_1 can be used to instruct MBIST circuit 2 to execute the first test element of test algorithm 2, and test instruction 2_2 can be used to instruct MBIST circuit 2 to execute test algorithm 2
  • test instruction 2_4 can be used to instruct the MBIST circuit 2 to execute the fourth test element of the test algorithm 2.
  • the process of the MBIST circuit 2 executing each sub-test instruction of the test algorithm 2 can refer to the process of executing the sub-test instructions of the test algorithm 1 described above. Therefore, the process of testing the memory 4 according to the test algorithm 1 and the test algorithm 2 in the MBIST test system in Example 3 can be embodied in a timeline manner, as shown in FIG. 5.
  • Ta1_m and Ta2_n in FIG. 5 represent the duration of the processing circuit 1 configuring the test command 1_m and the test command 2_n
  • test run duration of the MBIST test system corresponding to Example 3 is: Ta1_1+(Tb1_1+Tb1_2+Tb1_3+Tb1_4+Tb1_5)+Ta2_1+(Tb2_1+Tb2_2+Tb2_3+Tb2_4), where Tb1_1+Tb1_2+Tb1_3+Tb1_3+Tb1_3+Tb1_3+Tb1_3+Tb1_3 It is equivalent to Tb1 in Example 1, and Tb2_1+Tb2_2+Tb2_3+Tb2_4 is equivalent to Tb2 in Example 1.
  • Example 3 By comparing the test run time of the MBIST test system corresponding to Example 3 and Example 1, it is easy to see that the test run time of the MBIST test system of Example 3 is much shorter than that of Example 1. It can be seen that by splitting the test instructions corresponding to the target test algorithm according to the test elements of the target test algorithm into multiple sub-test instructions, the MBIST circuit 2 implements the test of the sub-tests in sequence to test the memory 4 according to the target test algorithm, which is beneficial to Reduce the test run time of the MBIST test system.
  • the MBIST test system In the actual operation of the MBIST test system, the MBIST test system usually includes an instruction cache 5, such as first-in first-out (First Input First Output, FIFO) memory, and the processing circuit 1 can input the generated test instruction into the instruction cache 5, and then the MBIST The circuit 2 reads the test instruction from the instruction cache 5.
  • the processing circuit 1 can also be used to manage idle instruction identifiers, and the idle instruction identifiers need to be used to generate tests instruction.
  • Example 1 since the test command configured by the processing circuit 1 is the target test command, which corresponds to a complete test algorithm, the content of the target test command is more. At this time, the processing circuit 1 usually sets only one command identifier. Therefore, only After the MBIST circuit 2 executes the completion of the test instruction 1, the processing circuit 1 can regain the idle instruction identifier, and then, the processing circuit 1 can start to configure the test instruction 2.
  • the test command configured by the processing circuit 1 corresponds to a sub-test command, and each sub-test command corresponds to a test element. Therefore, the content of the sub-test command is less.
  • the processing circuit 1 may be provided with multiple command identifiers, such as 5 instruction identifiers, the processing circuit 1 can sequentially generate 5 sub-test instructions corresponding to the test algorithm 1 (ie test instruction 1_1, test instruction 1_2, test instruction 1_3, test instruction 1_4 and test instruction 1_5), each sub-test instruction corresponds to one The instruction identifier, the processing circuit 1 can input each generated sub-test instruction into the instruction cache 5. After the processing circuit 1 generates the five sub-test instructions corresponding to the test algorithm 1, there is no idle instruction identifier in the processing circuit 1. At this time, the processing circuit 1 cannot continue to configure the sub-test instructions corresponding to the test algorithm 2. After the MBIST circuit 2 executes the 5 sub-test instructions corresponding to the test algorithm 1, the processing circuit 1 can regain the 5 idle instruction identifiers. At this time, the processing circuit 1 can start to configure the 4 sub-test instructions corresponding to the test algorithm 2.
  • 5 instruction identifiers such as 5 instruction identifiers
  • the MBIST circuit 2 may further include a recovery module 24.
  • the recovery module 24 may send the processing circuit 1 Send the recycling information of the instruction identifier of the i-th sub-test instruction.
  • the processing circuit 1 can use the instruction identifier of the i-th sub-test instruction as an idle instruction identifier, and generate a test instruction according to the idle instruction identifier.
  • the generated test instruction is a certain
  • the test instruction corresponding to the test element is the sub-test instruction referred to above.
  • the test instruction to be generated may be a sub-test instruction of the target test algorithm, or may be a test algorithm to be executed other than the target test algorithm.
  • a sub-test instruction In this way, based on Example 3, assuming that the processing circuit 1 can be provided with five instruction identifiers, after the MBIST circuit 2 executes the test instruction 1_1, it can send the recycling information of the instruction identifier corresponding to the test instruction 1_1 to the processing circuit 1, so that the processing circuit 1 Reacquire the idle instruction identifier, at this time, the processing circuit 1 can use the idle instruction identifier to configure the test instruction to be generated, in this example, the subtest instruction 2_1 corresponding to the first test element of the configuration test algorithm 2 is configured , Conducive to the continuation of the test.
  • the process of testing the memory 4 according to the test algorithm 1 and the test algorithm 2 in the MBIST test system in Example 3 can be embodied in a timeline manner, as shown in FIG. 6, the configuration process of the sub-test instruction 2_1 and the test algorithm 1 The execution process is carried out in parallel. Therefore, the test run time of the MBIST test system corresponding to Example 3 can reduce the configuration time Ta2_1 of the sub-test instruction 2_1, specifically: Ta1_1+(Tb1_1+Tb1_2+Tb1_3+Tb1_4+Tb1_5)+(Tb2_1+Tb2_2+ Tb2_3+Tb2_4).
  • an embodiment of the method for testing the memory of the present application includes the following steps:
  • the pre-stored test element modules and the construction rules of the test elements of the target test algorithm construct each test element in turn;
  • the built-in self-test MBIST circuit in the memory can construct each test element in turn according to the target test instruction according to the background data, the pre-stored test element module and the construction rules of each test element of the target test algorithm.
  • the target test instruction is used to instruct the MBIST circuit to execute the target test algorithm for the memory to be tested, which corresponds to the entire target test algorithm.
  • the MBIST circuit executes each test element in sequence for the memory to be tested
  • the construction rules include construction parameters
  • the construction parameters include a combination of memory operations included in the corresponding test element, the correspondence between the operands of each memory operation and the background data, and the operations of each memory operation At least one of the data length of the number and the address sequence of each memory operation.
  • Step 701 may be performed by the algorithm generation module 21 in the above device embodiment, and step 702 may be performed by the algorithm execution module 22 in the above device embodiment.
  • the construction rule further includes a module identifier of a test element module that matches the corresponding test element.
  • the process of constructing a single test element by the MBIST circuit in step 701 may specifically include:
  • test elements based on background data, target test element modules, and test element construction parameters.
  • the target test instruction may include N sub-test instructions, i is a positive integer not greater than N, and the i-th sub-test instruction is used to indicate MBIST
  • the circuit executes the i-th test element of the target test algorithm for the memory to be tested.
  • the process of the MBIST circuit constructing the i-th test element may include:
  • the MBIST circuit may send the recycling information of the instruction identifier of the i-th sub-test instruction to the processing circuit, and the processing circuit is used to manage idle Instruction ID, and generate test instructions according to the idle instruction ID.
  • the steps of the MBIST circuit performing the i-th test element of the target test algorithm on the memory to be tested may include:
  • the i-th test element module corresponds to the i-th test element.

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Abstract

本申请实施例公开了一种存储器内建自测试电路和对存储器的测试方法，用于降低修改MBIST电路支持的测试算法的开发成本。本申请存储器内建自测试MBIST电路可以包括：算法生成模块，用于按照目标测试指令根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，依次构造各个测试元素；算法执行模块，用于对待测的存储器依次执行各个测试元素。

Description

一种存储器内建自测试电路和对存储器的测试方法
本申请要求于2018年12月29日提交中国专利局、申请号为201811645058.6、发明名称为“一种存储器内建自测试电路和对存储器的测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储器技术领域，尤其涉及一种存储器内建自测试电路和对存储器的测试方法。
背景技术
目前存储器最常用的测试方法是存储器内建自测试(Memory Build-in Self-test，MBIST)方法，MBIST电路以存储器为目标，自动生成存储器的测试电路，通过执行特定的测试算法，来检测存储器中存在的某些缺陷，不同的测试算法可以得到不同的存储器测试覆盖率。
现有技术中开发人员通常需要在MBIST电路中预先编写算法模块，一个算法模块对应于一个测试算法，MBIST电路在接收到测试指令时，可以根据测试指令中指定的背景数据和预存的算法模块生成对应的测试算法，以对存储器执行该测试算法，检测存储器中存在的缺陷。
但是，当需要对测试算法进行修改时，需要开发人员对预先编写的整个算法模块进行修改，测试算法的开发成本高。
发明内容
本申请实施例提供了一种存储器内建自测试电路和对存储器的测试方法，用于降低修改MBIST电路支持的测试算法的开发成本。
为解决上述技术问题，第一方面，本申请实施例提供一种存储器内建自测试电路，包括：算法生成模块，用于按照目标测试指令根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，依次构造各个所述测试元素；算法执行模块，用于对存储器依次执行各个所述测试元素。本申请提供的存储器内建自测试MBIST电路通过预存测试元素模块来构造测试算法的各个测试元素，进而对存储器执行测试算法的各个测试元素，完成测试，当需要对测试算法进行修改时，开发人员只需对预存的测试元素模块进行修改即可，有利于降低修改算法的开发成本。
基于第一方面，在第一方面的第一种可能的实现方式中，所述构造规则包括构造参数，所述构造参数包括对应的测试元素中包括的内存操作的组合、各内存操作的操作数与背景数据的对应关系、各内存操作的操作数的数据长度和各内存操作的地址序列中的至少一种，通过细化构造规则，增加了本申请实施例的可操作性。
基于第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述构造规则还包括与对应的测试元素相匹配的测试元素模块的模块标识；所述算法生成模块用于构造所述测试元素时，具体用于根据所述测试元素的构造规则中的模块标识从预存的多个测试元素模块中获取目标测试元素模块；之后根据所述背景数据、所述目标测试元素模块和 所述测试元素的构造参数，构造所述测试元素。通过预存多个测试元素模块，有利于丰富MBIST电路可构造的测试算法的类型。
基于第一方面至第一方面的第二种可能的实现方式中任意一种可能的实现方式，在第一方面的第三种可能的实现方式中，所述目标测试算法包括N个测试元素，所述目标测试指令包括N个子测试指令，i为不大于N的正整数，第i个所述子测试指令用于指示所述MBIST电路对所述存储器执行所述目标测试算法的第i个测试元素，所述算法生成模块用于构造第i个所述测试元素时，具体用于按照第i个所述子测试指令构造第i个所述测试元素。通过按照每个测试元素对应的测试指令对存储器进行测试，有利于减少测试等待时长。
基于第一方面的第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述存储器内建自测试电路还包括回收模块，所述回收模块用于在所述算法执行模块对所述存储器执行第i个所述测试元素之后，向处理电路发送第i个所述子测试指令的指令标识的回收信息，所述处理电路用于管理空闲的指令标识，并根据空闲的指令标识生成测试指令。通过在执行完成测试元素后，发送该测试元素对应的测试指令的指令标识的回收信息，有利于增加处理器的空闲指令标识，有利于保证测试的接续进行，减少测试运行时长。
第二方面，本申请实施例提供一种对存储器的测试方法，包括：存储器内建自测试MBIST电路按照目标测试指令根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，依次构造各个所述测试元素；所述MBIST电路对存储器依次执行各个所述测试元素。
基于第二方面，在第二方面的第一种可能的实现方式中，所述构造规则包括构造参数，所述构造参数包括对应的测试元素中包括的内存操作的组合、各内存操作的操作数与背景数据的对应关系、各内存操作的操作数的数据长度和各内存操作的地址序列中的至少一种。
基于第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述构造规则还包括与对应的测试元素相匹配的测试元素模块的模块标识；所述MBIST电路构造所述测试元素包括：所述MBIST电路根据所述测试元素的构造规则中的模块标识从预存的多个测试元素模块中获取目标测试元素模块；所述MBIST电路根据所述背景数据、所述目标测试元素模块和所述测试元素的构造参数，构造所述测试元素。
基于第二方面至第二方面的第二种可能的实现方式中任意一种可能的实现方式，在第二方面的第三种可能的实现方式中，所述目标测试算法包括N个测试元素，所述测试指令包括N个子测试指令，i为不大于N的正整数，第i个所述子测试指令用于指示所述MBIST电路对所述存储器执行所述目标测试算法的第i个测试元素，所述MBIST电路构造第i个所述测试元素包括：所述MBIST电路按照第i个所述子测试指令构造第i个所述测试元素。
基于第二方面的第三种可能的实现方式，在第二方面的第四种可能的实现方式中，所述方法还包括：在对所述存储器执行第i个所述测试元素之后，所述MBIST电路向处理电路发送第i个所述子测试指令的指令标识的回收信息，所述处理电路用于管理空闲的指令标识，并根据空闲的指令标识生成测试指令。
附图说明
图1是MBIST测试系统的一个结构示意图；
图2是本申请MBIST电路的一个实施例示意图；
图3是本申请MBIST测试系统的一个实施例示意图；
图4是本申请MBIST测试系统对存储器的测试过程的一个示意图；
图5是本申请MBIST测试系统对存储器的测试过程的另一个示意图；
图6是本申请MBIST测试系统对存储器的测试过程的另一个示意图；
图7是本申请对存储器的测试方法的一个实施例示意图；
图8是图7对应的实施例中步骤701的一种可能的细化步骤示意图；
图9是本申请对存储器执行第i个测试元素的方法的一个实施例示意图。
具体实施方式
本申请实施例提供了一种存储器内建自测试电路和对存储器的测试方法。
下面结合附图，对本申请的实施例进行描述。
本申请中出现的术语“和/或”，可以是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。另外，本申请中字符“/”，一般表示前后关联对象是一种“或”的关系。本申请中，“至少一个”是指一个或多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，以便包含一系列单元的过程、方法、系统、产品或设备不必限于那些单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它单元。
现代集成电路日益需要在半导体芯片本身上嵌入存储器，对存储器的传统的测试方法受测试难度和测试成本所制约，已不为芯片设计厂商所接受。目前存储器最常用的测试方法是通过存储器内建自测试(Memory Build-in Self-test，MBIST)方法来实现，自动生成存储器的测试电路，根据相应的测试算法对存储器地址进行读写操作，完成存储器的测试。这种测试方法虽然会在电路中加入一些控制逻辑，从而增加芯片的面积，但是对于大规模测试电路，这种方法能够实现测试自动化，减少测试时长，提高测试覆盖率，很大程度上节约测试成本。
MBIST方法是以存储器为目标，通过执行特定的测试算法，来检测存储器中存在的某些缺陷的一种测试方法，不同的测试算法可以得到不同的存储器测试覆盖率。参考图1，为MBIST测试系统的一个结构示意图，MBIST测试系统包括处理电路1、MBIST电路2、存储控制器3和存储器4，处理电路1，比如处理器或处理器中的某个模块，可以向MBIST电路2输入测试指令，测试指令用于指定测试算法，可选的，还可以指定背景数据，MBIST电路2用于按照接收到的测试指令，生成相应的测试算法，并执行该测试算法，以通过存储控制器3 检测存储器4中存在的缺陷。在实际应用中，背景数据也可以在MBIST电路2中预先配置。
MBIST采用的测试算法是测试元素的有限序列，测试元素包括一系列指定的内存操作、各内存操作的操作数和内存操作的地址序列。下面是March C-算法的算法原语：
Figure PCTCN2019115239-appb-000001
March C-算法包含6个测试元素，分别为
Figure PCTCN2019115239-appb-000002
Figure PCTCN2019115239-appb-000003
和
Figure PCTCN2019115239-appb-000004
以第2个测试元素
Figure PCTCN2019115239-appb-000005
为例，其包括的内存操作依次为读操作和写操作，背景数据为A，读操作的操作数为背景数据，写操作的操作数为背景数据取反，内存操作的地址序列为升序，即按照升序来依次对存储器4中的各个存储单元进行测试元素中规定的内存操作。MBIST电路2对存储器4执行第2个测试元素是指，按照升序依次对存储器4中的各个存储单元进行如下内存操作：首先读取当前存储单元中的数据，和A进行比较，若相同，则向当前存储单元写入
Figure PCTCN2019115239-appb-000006
若不相同，则报错。
为了灵活调整对存储器4的测试策略，需要丰富MBIST电路可选用的测试算法，从中选择一个或多个测试算法，来对存储器4进行测试。为此，现有技术中开发人员通常需要在MBIST电路2中预先编写算法模块，一个算法模块对应于一个测试算法，MBIST电路2在接收到处理电路1发送的测试指令时，可以根据测试指令中指定的背景数据和预存的算法模块生成对应的测试算法。若需要对测试算法进行修改，则需要开发人员对预先编写的整个算法模块进行修改，若需要新增测试算法，则需要开发人员重新编写新增的测试算法对应的整个算法模块，测试算法的开发成本高。
为了解决上述问题，本申请提供一种MBIST电路2，请参阅图2，MBIST电路2包括：算法生成模块21和算法执行模块22，其中，算法生成模块21用于在接收到测试指令后，按照测试指令，根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，构造目标测试算法的各个测试元素；算法执行模块22用于对待测的存储器执行目标测试算法的各个测试元素。其中，测试指令用于指定测试算法，可选的，还可以指定背景数据，或者，背景数据也可以无需由测试指令指定，而是在MBIST电路2中进行预先配置。为了尽量减少开发成本，同一测试元素模块可以用于构造多个测试元素，具体的，同一测试元素模块可以构造的多个测试元素可以属于同一测试算法，也可以属于不同测试算法，此处不做具体限定。
开发人员可以预先编写测试元素模块和测试算法的各个测试元素的构造规则，并将其存储在MBIST测试系统中，在本申请一种可能的实现方式中，继续参考图2，MBIST电路2还可以包括存储模块23，存储模块23可以用于存储测试元素模块和多个测试算法的各个测试元素的构造规则。开发人员可以通过对测试算法的多个算法元素进行对比，根据不同算法元素之间的相同点来编写测试元素模块，根据不同算法元素之间的区别点来编写各个测试元素的构造规则。示例性的，通过对比March类算法的不同测试元素(包括同一算法的不同测试元素和不同算法的测试元素)，以March C-算法和March Y算法为例，其中March C-算法的算法原语为：
Figure PCTCN2019115239-appb-000007
March Y算法的算法原语为：
Figure PCTCN2019115239-appb-000008
可以发现March类算法的各个测试元素中的内存操作的操作对象均是当前内存单元，各个测试元素之间的差异主要体现在：1、内存操作的地址序列可能不同：为升序或为降序；2、包括的内存操作的组合可能不同：包括的组合可能为一个操作，比如写操作或者读操作，包括的组合可能为两个操作，可能为读操作和写操作的组合，或者为写操作和读操作的组合，包括的组合可能为三个或三个以上操作，具体不再举例；3、内存操作的操作数与背景数据的对应关系可能不同：内存操作的操作数可能为背景数据，或者，可能为背景数据的取反；4、内存操作的操作数的数据长度可能不同；等等。在本申请一种可能的实现方式中，测试元素的构造规则可以包括构造参数，测试元素的构造参数包括对应的测试元素包括的内存操作的组合、对应的测试元素中各内存操作的操作数与背景数据的对应关系、各内存操作的操作数的数据长度和内存操作的地址序列中的至少一种。开发人员可以为March类算法编写至少一个测试元素模块，并将上述差异作为可配置的参数，编写各个测试元素的构造参数，当需要生成某个March类算法时，算法生成模块21可以根据背景数据、该测试算法的测试元素模块和该测试算法的各个测试元素的构造参数，分别构造该测试算法的各个测试元素，从而得到该测试算法。可见，开发人员最少只需编写一个测试元素模块，算法生成模块21便可以构造出所有的March类算法。
MBIST采用的测试算法，除了主流的March类算法，还有一些其他类型的算法，比如Butterfly算法、Surrounding算法、3-step算法和PRBS算法等，开发人员可能需要为这些非March类算法编写相应的测试元素模块。非March类算法的各个测试元素可以均利用该算法对应的测试元素模块生成，或者，非March类算法中的部分测试元素可以复用March类算法对应的测试元素模块生成，其他测试元素可以利用该算法对应的测试元素模块生成。以Butterfly算法为例，其算法原语如下：
Figure PCTCN2019115239-appb-000009
Figure PCTCN2019115239-appb-000010
该算法包含4个测试元素，第一个测试元素
Figure PCTCN2019115239-appb-000011
和第三个测试元素
Figure PCTCN2019115239-appb-000012
中内存操作的操作对象均是当前内存单元，这两个测试元素可以通过复用March类算法的测试元素模块构造出来。而该算法中的第二个测试元素
Figure PCTCN2019115239-appb-000013
和第四个测试元素
Figure PCTCN2019115239-appb-000014
中的部分内存操作的操作对象不是当前内存单元，比如，
Figure PCTCN2019115239-appb-000015
的操作对象是当前内存单元东侧的内存单元，这两个测试元素无法通过复用March类算法的测试元素模块构造出来，所以需要增加Butterfly算法的第二个测试元素和第四个测试元素对应的测试元素模块。M1和M3之间只有读写操作数有区别，M3的读写操作数是M1的读写操作数取反，为了减少对测试元素模块的开发成本，因此最少只要构造一个测试元素模块，由第二个测试元素和第四个测试元素共用即可。通过类似的方法，我们可以扩展其他算法(比如Surrounding算法、3-step算法和PRBS算法等)的测试元素模块。为了减少对测试元素模块的开发成本，非March类算法的测试元素可以尽量复用已编写好的测试元素模块，比如March类算法的测试元素模块，可以为无法复用已有测试元素模块的测试元素编写相应的测试元素模块。
可见，为了使得本申请提供的MBIST电路2能够采用多种测试算法对存储器进行测试， 在本申请的一种可能的实现方式中，MBIST测试系统可以预先存储多个测试元素模块，比如March类算法、Butterfly算法、Surrounding算法、3-step算法和PRBS算法对应的测试元素模块，不同测试元素模块的标识不同。测试元素的构造规则还包括与该测试元素相对应的测试元素模块的模块标识，此时，算法生成模块21在根据背景数据、预存的测试元素模块和目标测试算法中的第i个测试元素的构造规则构造该测试元素时(其中i为正整数，且不大于目标测试算法包括的测试元素的数目)，具体用于根据第i个测试元素的构造规则中的模块标识从预存的多个测试元素模块中获取目标测试元素模块，目标测试元素模块为与目标测试算法的第i个测试元素相对应的测试元素模块，之后，根据背景数据、获取到的目标测试元素模块和第i个测试元素的构造参数，构造目标测试算法的第i个测试元素。
下面对MBIST测试系统对待测试的存储器执行目标测试算法的一种可能的实施过程进行说明。参考图3，MBIST测试系统包括处理电路1、MBIST电路2、存储控制器3和存储器4，MBIST电路2包括：算法生成模块21、算法执行模块22和存储模块23，MBIST电路2中各个模块的功能可以图2对应的实施例的描述，此处不再赘述。处理电路1可以向MBIST电路2输入测试指令，该测试指令用于指示测试存储器4所选用的背景数据和目标测试算法，为了便于描述，将对应于完整的目标测试算法的测试指令称作目标测试指令。算法生成模块21可以按照接收到的目标测试指令构造目标测试算法的各个测试元素，算法执行模块22可以执行各个测试元素，以对存储器4执行目标测试算法，从而通过存储控制器3检测存储器4中存在的缺陷。
MBIST测试系统对存储器4依次进行测试算法1和测试算法2的测试的过程可以有多种具体的实现方式。示例性的，例1中，处理电路1可以首先生成测试指令1，测试指令1可以用于指示MBIST电路2执行测试算法1的全部测试元素，此时，算法生成模块21可以根据测试指令1构造测试算法1对应的全部测试元素，算法执行模块22可以在算法生成模块21生成测试算法1的全部测试元素后再依次执行各个测试元素。在算法执行模块22执行完各个测试元素之后，处理电路1可以生成测试指令2，向MBIST电路2继续输入测试指令2，该测试指令2用于指示MBIST电路2执行测试算法2的全部测试元素，算法执行模块22可以在算法生成模块21生成测试算法2的全部测试元素后再依次执行各个测试元素。假设测试算法1包含5个测试元素，测试算法2包含4个测试元素，此时，MBIST测试系统对存储器4按照测试算法1和测试算法2进行测试的过程可以以时间轴的方式体现，如图4所示。MBIST测试系统的测试运行时长一般主要包括两部分：处理电路1配置目标测试指令的时长Ta和MBIST电路2按照目标测试指令执行测试的时长Tb。其中，Ta主要受限于配置处理电路1的运行频率等，在测试运行时长里占用的比重也比较大；Tb主要受限于存储器4自身的访问时序参数和访问流量等因数限制，一般比较固定。图4中的Ta1和Ta2分别代表处理电路1配置测试指令1和测试指令2的时长，Tb1和Tb2分别代表MBIST电路2按照测试指令1和测试指令2执行测试的时长。可见，例1对应的MBIST测试系统的测试运行时长为：Ta1+Tb1+Ta2+Tb2。
例2中，在例1的基础上，算法执行模块22也可以在算法生成模块21生成测试算法1的部分测试元素(比如第一个测试元素)后，便执行该测试元素，和例1相比，有利于减少MBIST电路2按照目标测试指令执行测试的时长Tb，进而减少MBIST测试系统的测试运行时 长。
若目标测试算法包括N个测试元素，N为正整数，在本申请一种可能的实现方式中，目标测试指令可以包括N个子测试指令，第i个子测试指令用于指示MBIST电路2执行目标测试算法的第i个测试元素，i为不大于N的正整数，也就是说，处理电路1生成目标测试指令的过程可以具体指依次配置N个子测试指令的过程，处理电路1可以将配置好的子测试指令依次输入MBIST电路2中，之后，MBIST电路2可以依次执行N个子测试指令，MBIST电路2执行第i个子测试指令的过程可以包括：算法生成模块21构造第i个测试元素，在算法生成模块21构造得到第i测试元素之后，算法执行模块22可以执行第i个测试元素。因此，MBIST测试系统对存储器4依次进行测试算法1和测试算法2的测试的过程也可以如例3：处理电路1可以首先配置测试算法1对应的5个子测试指令，依次生成测试指令1_1、测试指令1_2、测试指令1_3、测试指令1_4和测试指令1_5，并依次将生成的各个测试指令输入MBIST电路2。其中，测试指令1_1可以用于指示MBIST电路2执行测试算法1的第一个测试元素，测试指令1_2可以用于指示MBIST电路2执行测试算法1的第二个测试元素，依次类推，测试指令1_5可以用于指示MBIST电路2执行测试算法1的第五个测试元素。在处理电路1生成测试指令1_1之后，可以将测试指令1_1输入算法生成模块21，算法生成模块21可以根据测试指令1_1构造测试算法1的第一个测试元素，算法执行模块22可以在算法生成模块21生成测试算法1的第一个测试元素后执行该测试元素。之后，MBIST电路2可以依次执行测试指令1_2、测试指令1_3、测试指令1_4和测试指令1_5。在算法执行模块22执行完测试算法1对应的各个指令后，处理电路1可以生成测试算法2对应的四个子测试指令，依次生成测试指令2_1、测试指令2_2、测试指令2_3和测试指令2_4，并依次将生成的各个测试指令输入MBIST电路2，其中，测试指令2_1可以用于指示MBIST电路2执行测试算法2的第一个测试元素，测试指令2_2可以用于指示MBIST电路2执行测试算法2的第二个测试元素，依次类推，测试指令2_4可以用于指示MBIST电路2执行测试算法2的第四个测试元素。MBIST电路2执行测试算法2的各个子测试指令的过程可以参考上述执行测试算法1的各个子测试指令的过程。因此，例3中MBIST测试系统对存储器4按照测试算法1和测试算法2进行测试的过程可以以时间轴的方式体现，如图5所示。图5中的Ta1_m和Ta2_n分别代表处理电路1配置测试指令1_m和测试指令2_n的时长，Tb1_m和Tb2_n分别代表MBIST电路2按照测试指令1_m和测试指令2_n执行测试的时长，其中m＝1，2，3，4，5，n＝1，2，3，4。可见，例3对应的MBIST测试系统的测试运行时长为：Ta1_1+(Tb1_1+Tb1_2+Tb1_3+Tb1_4+Tb1_5)+Ta2_1+(Tb2_1+Tb2_2+Tb2_3+Tb2_4),其中，Tb1_1+Tb1_2+Tb1_3+Tb1_4+Tb1_5相当于例1中的Tb1，Tb2_1+Tb2_2+Tb2_3+Tb2_4相当于例1中的Tb2。通过比较例3和例1对应的MBIST测试系统的测试运行时长，容易看出，例3的MBIST测试系统的测试运行时长远小于例1。可见，通过将目标测试算法对应测试指令按照目标测试算法的各个测试元素拆分为多个子测试指令，MBIST电路2通过依次执行各个子测试指令来实现对存储器4按照目标测试算法进行测试，有利于缩短MBIST测试系统的测试运行时长。
在MBIST测试系统的实际运行中，MBIST测试系统通常包括指令缓存5，比如先入先出(First Input First Output，FIFO)存储器，处理电路1可以将生成的测试指令输入指令缓存5中，再由MBIST电路2从指令缓存5中读取测试指令。受到指令缓存5的存储空间的限 制，并且为了保证MBIST测试系统有序正确的执行测试指令，参考图3，处理电路1还可以用于管理空闲的指令标识，并且需要利用空闲的指令标识生成测试指令。
例1中，由于处理电路1配置的测试指令为目标测试指令，对应于一个完整的测试算法，因此目标测试指令的内容较多，此时，处理电路1通常只设置一个指令标识，因此，只有在MBIST电路2执行完成测试指令1之后，处理电路1才能重新获得空闲的指令标识，之后，处理电路1才能开始配置测试指令2。而例3中，处理电路1配置的测试指令对应于一个子测试指令，每个子测试指令对应于一个测试元素，因此子测试指令的内容较少，处理电路1可以设置有多个指令标识，比如5个指令标识，处理电路1可以依次生成测试算法1对应的5个子测试指令(即测试指令1_1、测试指令1_2、测试指令1_3、测试指令1_4和测试指令1_5)，每个子测试指令分别对应一个指令标识，处理电路1可以将生成的各个子测试指令输入指令缓存5中。处理电路1生成测试算法1对应的5个子测试指令之后，处理电路1中便没有空闲的指令标识，此时，处理电路1无法继续配置测试算法2对应的子测试指令。MBIST电路2在执行完成测试算法1对应的5个子测试指令后，处理电路1可以重新获得空闲的5个指令标识，此时，处理电路1可以开始配置测试算法2对应的4个子测试指令。
为了进一步缩短MBIST测试系统的测试运行时长，参考图3，MBIST电路2还可以包括回收模块24，算法执行模块22在执行完目标测试算法的第i个子测试指令时，回收模块24可以向处理电路1发送第i个子测试指令的指令标识的回收信息，处理电路1可以将第i个子测试指令的指令标识作为空闲的指令标识，并根据空闲的指令标识生成测试指令，生成的测试指令为某个测试元素对应的测试指令，即上文所称的子测试指令，比如，待生成的测试指令可以是目标测试算法的某个子测试指令，也可以是目标测试算法以外的其他待执行的测试算法的某个子测试指令。这样，基于例3，假设处理电路1可以设置有5个指令标识，MBIST电路2在执行完测试指令1_1之后，便可以向处理电路1发送测试指令1_1对应的指令标识的回收信息，使得处理电路1重新获得空闲的指令标识，此时，处理电路1便可以利用空闲的指令标识配置待生成的测试指令，在本示例中，即配置测试算法2的第一个测试元素对应的子测试指令2_1，有利于测试的接续进行。此时，例3中MBIST测试系统对存储器4按照测试算法1和测试算法2进行测试的过程可以以时间轴的方式体现，如图6所示，子测试指令2_1的配置过程与测试算法1的执行过程并行进行，因此，例3对应的MBIST测试系统的测试运行时长可以减少子测试指令2_1的配置时长Ta2_1，具体为：Ta1_1+(Tb1_1+Tb1_2+Tb1_3+Tb1_4+Tb1_5)+(Tb2_1+Tb2_2+Tb2_3+Tb2_4)。
上面对本申请的装置实施例进行了描述，与上述MBIST电路相应的，本申请实施例还提供一种对存储器的测试方法，参考图7，本申请对存储器的测试方法一个实施例包括如下步骤：
701、按照目标测试指令根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，依次构造各个测试元素；
存储器内建自测试MBIST电路可以按照目标测试指令根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，依次构造各个测试元素。目标测试指令用于指示MBIST电路对待测的存储器执行目标测试算法，对应于整个目标测试算法。
702、对存储器依次执行各个测试元素。
MBIST电路对待测的存储器依次执行各个测试元素
在本申请一种可能的实现方式中，构造规则包括构造参数，构造参数包括对应的测试元素中包括的内存操作的组合、各内存操作的操作数与背景数据的对应关系、各内存操作的操作数的数据长度和各内存操作的地址序列中的至少一种。
步骤701可以由上述装置实施例中的算法生成模块21执行，步骤702可以由上述装置实施例中的算法执行模块22执行。
在本申请一种可能的实现方式中，构造规则还包括与对应的测试元素相匹配的测试元素模块的模块标识。参考图8，步骤701中MBIST电路构造单个测试元素的过程，具体可以包括：
7011、根据测试元素的构造规则中的模块标识从预存的多个测试元素模块中获取目标测试元素模块；
7012、根据背景数据、目标测试元素模块和测试元素的构造参数，构造测试元素。
在本申请一种可能的实现方式中，若目标测试算法包括N个测试元素，那么目标测试指令可以包括N个子测试指令，i为不大于N的正整数，第i个子测试指令用于指示MBIST电路对待测的存储器执行目标测试算法的第i个测试元素，步骤S100中，MBIST电路构造第i个测试元素的过程，可以包括：
按照第i个子测试指令构造第i个测试元素。构造第i个测试元素的具体过程可以参考图8对应的细化步骤。
在本申请一种可能的实现方式中，在对待测的存储器执行第i个测试元素之后，MBIST电路可以向处理电路发送第i个子测试指令的指令标识的回收信息，处理电路用于管理空闲的指令标识，并根据空闲的指令标识生成测试指令。参考图9，MBIST电路对待测的存储器执行目标测试算法的过程中，MBIST电路对待测的存储器执行目标测试算法的第i个测试元素的步骤可以包括：
901、按照第i个子测试指令，根据测试元素的构造规则中的模块标识从预存的多个测试元素模块中获取目标测试元素模块；
第i个测试元素模块与第i个测试元素相对应。
902、根据背景数据、目标测试元素模块和第i个测试元素的构造参数，构造第i个测试元素；
903、对存储器执行第i个测试元素；
904、向处理电路发送第i个子测试指令的指令标识的回收信息。
需要说明的是，前述关于MBIST电路2的各个实施例均适用于本申请方法的实施例，且方法实施例和相应的装置实施例可以达到相同的技术效果，此处不再赘述。
本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请的各实施例中，为了方面理解，进行了多种举例说明。然而，这些例子仅仅是 一些举例，并不意味着是实现本申请的最佳实现方式。
上述实施例，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现，当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
以上对本申请所提供的技术方案进行了详细介绍，本申请中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种存储器内建自测试电路，其特征在于，包括：
    算法生成模块，用于按照目标测试指令根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，依次构造各个所述测试元素；
    算法执行模块，用于对存储器依次执行各个所述测试元素。
  2. 根据权利要求1所述的存储器内建自测试电路，其特征在于，所述构造规则包括构造参数，所述构造参数包括对应的测试元素中包括的内存操作的组合、各内存操作的操作数与背景数据的对应关系、各内存操作的操作数的数据长度和各内存操作的地址序列中的至少一种。
  3. 根据权利要求2所述的存储器内建自测试电路，其特征在于，所述构造规则还包括与对应的测试元素相匹配的测试元素模块的模块标识；
    所述算法生成模块用于构造所述测试元素时，具体用于：
    根据所述测试元素的构造规则中的模块标识从预存的多个测试元素模块中获取目标测试元素模块；
    根据所述背景数据、所述目标测试元素模块和所述测试元素的构造参数，构造所述测试元素。
  4. 根据权利要求1至3中任一项所述的存储器内建自测试电路，其特征在于，所述目标测试算法包括N个测试元素，所述目标测试指令包括N个子测试指令，i为不大于N的正整数，第i个所述子测试指令用于指示所述MBIST电路对所述存储器执行所述目标测试算法的第i个测试元素，所述算法生成模块用于构造第i个所述测试元素时，具体用于：
    按照第i个所述子测试指令构造第i个所述测试元素。
  5. 根据权利要求4所述的存储器内建自测试电路，其特征在于，所述存储器内建自测试电路还包括回收模块，所述回收模块用于：
    在所述算法执行模块对所述存储器执行第i个所述测试元素之后，向处理电路发送第i个所述子测试指令的指令标识的回收信息，所述处理电路用于管理空闲的指令标识，并根据空闲的指令标识生成测试指令。
  6. 一种对存储器的测试方法，其特征在于，包括：
    存储器内建自测试MBIST电路按照目标测试指令根据背景数据、预存的测试元素模块和目标测试算法的各个测试元素的构造规则，依次构造各个所述测试元素；
    所述MBIST电路对存储器依次执行各个所述测试元素。
  7. 根据权利要求6所述的对存储器的测试方法，其特征在于，所述构造规则包括构造参数，所述构造参数包括对应的测试元素中包括的内存操作的组合、各内存操作的操作数与背景数据的对应关系、各内存操作的操作数的数据长度和各内存操作的地址序列中的至少一种。
  8. 根据权利要求7所述的对存储器的测试方法，其特征在于，所述构造规则还包括与对应的测试元素相匹配的测试元素模块的模块标识；
    所述MBIST电路构造所述测试元素包括：
    所述MBIST电路根据所述测试元素的构造规则中的模块标识从预存的多个测试元素模块中获取目标测试元素模块；
    所述MBIST电路根据所述背景数据、所述目标测试元素模块和所述测试元素的构造参数，构造所述测试元素。
  9. 根据权利要求6至8中任一项所述的对存储器的测试方法，其特征在于，所述目标测试算法包括N个测试元素，所述目标测试指令包括N个子测试指令，i为不大于N的正整数，第i个所述子测试指令用于指示所述MBIST电路对所述存储器执行所述目标测试算法的第i个测试元素，所述MBIST电路构造第i个所述测试元素包括：
    所述MBIST电路按照第i个所述子测试指令构造第i个所述测试元素。
  10. 根据权利要求9所述的对存储器的测试方法，其特征在于，所述方法还包括：
    在对所述存储器执行第i个所述测试元素之后，所述MBIST电路向处理电路发送第i个所述子测试指令的指令标识的回收信息，所述处理电路用于管理空闲的指令标识，并根据空闲的指令标识生成测试指令。
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