WO2020134018A1 - 薄膜晶体管的栅极制作方法 - Google Patents

薄膜晶体管的栅极制作方法 Download PDF

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WO2020134018A1
WO2020134018A1 PCT/CN2019/095016 CN2019095016W WO2020134018A1 WO 2020134018 A1 WO2020134018 A1 WO 2020134018A1 CN 2019095016 W CN2019095016 W CN 2019095016W WO 2020134018 A1 WO2020134018 A1 WO 2020134018A1
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gate
metal layer
substrate
manufacturing
film transistor
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PCT/CN2019/095016
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English (en)
French (fr)
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王文龙
徐向阳
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020134018A1 publication Critical patent/WO2020134018A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al

Definitions

  • the invention relates to a method for manufacturing a gate electrode of a thin film transistor, in particular to a method for manufacturing a gate electrode for controlling the slope angle of the gate electrode.
  • the main object of the present invention is to provide a method for manufacturing a gate electrode of a thin film transistor, a metal wire halftone mask, and under the condition of ensuring line resistance, the slope angle of the metal layer becomes smaller through the metal wire halftone mask process.
  • the present invention provides a method for manufacturing a gate of a thin film transistor, which includes the following steps:
  • a gate metal layer is formed on the substrate, and a photoresist layer is formed on the gate metal layer;
  • the photoresist layer is removed, leaving the trapezoidal gate metal layer on the substrate.
  • the halftone mask includes a substrate, a metal wire cadmium film and a semi-transparent film, the metal wire cadmium film and the semi-transparent film are provided on the substrate, the semi-transparent Films are provided on both ends of the metal wire cadmium film.
  • the substrate is a glass substrate.
  • the gate metal layer is a metal layer including one or more of copper/aluminum/molybdenum.
  • the present invention also provides a method for manufacturing a gate of a thin film transistor, which includes the following steps:
  • a gate metal layer is formed on the substrate, and a photoresist layer is formed on the gate metal layer;
  • the photoresist layer is removed, leaving the trapezoidal gate metal layer on the substrate.
  • the exposure and development step is performed by a half-tone mask.
  • the halftone mask includes a substrate, a metal wire cadmium film and a semi-transparent film, the metal wire cadmium film and the semi-transparent film are provided on the substrate, the semi-transparent Films are provided on both ends of the metal wire cadmium film.
  • the exposure and development step is performed using an ultraviolet light.
  • the substrate is a glass substrate.
  • the gate metal layer is a metal layer including one or more of copper/aluminum/molybdenum.
  • the gate metal layer has problems such as excessive slope angle or poor undercut after etching.
  • the present invention provides a metal wire half-tone mask under the condition of ensuring wire resistance . Through the halftone mask process of the metal wire, the slope angle of the metal layer becomes smaller, reducing over-cutting and electrostatic discharge (Electro Static Discharge; ESD) incidence rate, so as to achieve the purpose of improving the operation window (Window) in the process.
  • ESD Electro Static Discharge
  • Figure 1 Schematic diagram of the first step of a method for manufacturing a gate of a thin film transistor of the present invention.
  • FIG. 2 is a schematic diagram of the second step of the method for manufacturing the gate of the thin film transistor of the present invention.
  • FIG. 3 is a schematic diagram of the third step of a method for manufacturing a gate of a thin film transistor of the present invention.
  • FIG. 4 is a schematic diagram of the fourth step of a method for manufacturing a gate of a thin film transistor of the present invention.
  • FIG. 5 is a schematic diagram of the fifth step of a method for manufacturing a gate of a thin film transistor of the present invention.
  • FIG. 6 is a schematic diagram of the sixth step of a method for manufacturing a gate of a thin film transistor of the present invention.
  • FIG. 7 is a flowchart of a method for manufacturing a gate of a thin film transistor of the present invention.
  • FIG. 1 to FIG. 2 is a schematic diagram of the first step to the sixth step of a method of manufacturing a thin film transistor gate of the present invention
  • FIG. 7 is a gate of a thin film transistor of the present invention Flow chart of the extreme production method.
  • the invention provides a method for manufacturing a gate of a thin film transistor, which includes the following steps:
  • Step S1 providing a substrate 10 on which a gate metal layer 20 is formed, and a photoresist layer 30 is formed on the gate metal layer.
  • the substrate 10 is, for example, a glass substrate
  • the gate metal layer 20 is, for example, one or more metals such as copper/aluminum/molybdenum (Cu/Al/Mo), etc. Floor.
  • Step S2 performing an exposure and development step, forming the photoresist layer 30 on a preset position of the gate electrode to form a stepped shape with a thick side cross section.
  • the exposure and development step is through a halftone mask (Halftone Mask), the half-tone mask includes a substrate 40, a metal wire cadmium film 41 and a semi-transparent film 42, the metal wire cadmium film 41 and the semi-transparent film 42 are provided on the substrate 40, the The semi-permeable membrane 42 is provided at both ends of the metal wire cadmium membrane 41.
  • Halftone Mask Halftone Mask
  • the exposure and development step is performed by using ultraviolet light (UV).
  • UV ultraviolet light
  • the photoresist layer 30 forms a step-like shape with a thicker center and thinner ends.
  • Step S3 performing a first wet etching step to remove the gate metal layer 20 other than the photoresist layer 30, and form over-etching on both ends of the photoresist layer 30.
  • Step S4 performing a photoresist burning step to shorten both ends of the photoresist layer 30 to form a shorter shape than the gate metal layer 20.
  • Step S5 performing a second wet etching step to form the gate metal layer 20 into a trapezoidal shape on one side.
  • the second wet etching is used to modify the slope angle (Taper) of the gate metal layer 20.
  • Step S6 The photoresist layer 30 is removed, leaving the trapezoidal gate metal layer 20 on the substrate 10.
  • the remaining photoresist layer 30 is finally removed by a photoresist stripping process to complete the manufacturing process of the gate metal layer 20.
  • the longitudinal and lateral etching speeds can be adjusted by the concentration of the chemical components in the etching solution twice, so that the slope angle of the gate metal layer 20 can be better controlled.
  • the gate metal layer has the problems of excessively large slope angle or poor undercut after etching.
  • the present invention provides a metal wire half-tone mask to ensure Under the condition of line resistance, the half-tone mask process of the metal wire makes the slope angle of the metal layer smaller, reducing over-cutting and electrostatic discharge (Electro Static Discharge; ESD) incidence rate, so as to achieve the purpose of improving the operation window (Window) in the process.
  • ESD Electro Static Discharge

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种薄膜晶体管的栅极制作方法，其包含步骤：一曝光显影步骤、一第一湿蚀刻步骤、一烧光阻步骤、一第二湿蚀刻步骤及一移除光刻胶层(30)步骤，以在一基板(10)上制作一梯形的栅极金属层(20)，所述栅极金属层(20)坡度角较小，可降低过切和静电放电的发生率，从而达到提升制程中的操作窗的目的。

Description

薄膜晶体管的栅极制作方法 技术领域
本发明涉及一种薄膜晶体管的栅极制作方法，特别是涉及一种控制栅极坡度角的栅极制作方法。
 背景技术
随着平板显示技术的发展，大尺寸、高分辨率、高对比度、高刷新速率、窄边框、薄型化等已成为平板显示发展趋势，但大尺寸、高分辨率显示面板，例如一75吋(inch) 8K 120Hz显示面板，其行扫描时间仅有不到2微秒(µs：10 -6秒)，而由于充电时间要小于扫描时间减去信号的线路延迟，因此只有通过增加金属走线的膜厚来降低线路延迟。
然而，这对于蚀刻后金属走线的坡度角(taper)角较难控制，一般会大于80°，甚至会出现过切(undercut)情形，现有技术中只能通过蚀刻参数及溶液金属离子浓度来控制，但其制程的操作窗(window)较小，因此容易形成断线及静电放电(electro static discharge；ESD)的良率损失。
因此，有必要提供一种改良的薄膜晶体管的栅极制作方法，以解决上述技术问题。
 技术问题
本发明的主要目的是提供一种薄膜晶体管的栅极制作方法一种金属线半色调光罩，在保证线电阻的条件下，通过金属线的半色调光罩工艺使得金属层坡度角变小。
 技术解决方案
为达上述目的，本发明提供一种薄膜晶体管的栅极制作方法，其包含以下步骤：
提供一基板，所述基板上形成一栅极金属层，所述栅极金属层上形成一光刻胶层；
进行一曝光显影步骤，采用一紫外光，通过一半色调光罩，在一栅极预设位置上将所述光刻胶层形成一侧剖视为中间较厚的阶梯形状；
进行一第一湿蚀刻步骤，将所述光刻胶层以外的所述栅极金属层除去，并且对所述光刻胶层的两端形成过蚀刻；
进行一烧光阻步骤，将所述光刻胶层的两端缩短，形成相较于所述栅极金属层为较短的形状；
进行一第二湿蚀刻步骤，将所述栅极金属层形成一侧剖视为梯形的形状；及
移除所述光刻胶层，在所述基板上留下所述梯形的栅极金属层。
在本发明的一实施例中，所述半色调光罩包含基板、金属线镉膜及半透膜，所述金属线镉膜及所述半透膜设于所述基板上，所述半透膜设于所述金属线镉膜的两端。
在本发明的一实施例中，所述基板是一玻璃基板。
在本发明的一实施例中，所述栅极金属层是包含铜/铝/钼之中一种或多种的金属层。
为达上述目的，本发明另提供一种薄膜晶体管的栅极制作方法，其包含以下步骤：
提供一基板，所述基板上形成一栅极金属层，所述栅极金属层上形成一光刻胶层；
进行一曝光显影步骤，在一栅极预设位置上将所述光刻胶层形成一侧剖视为中间较厚的阶梯形状；
进行一第一湿蚀刻步骤，将所述光刻胶层以外的所述栅极金属层除去，并且对所述光刻胶层的两端形成过蚀刻；
进行一烧光阻步骤，将所述光刻胶层的两端缩短，形成相较于所述栅极金属层为较短的形状；
进行一第二湿蚀刻步骤，将所述栅极金属层形成一侧剖视为梯形的形状；及
移除所述光刻胶层，在所述基板上留下所述梯形的栅极金属层。
在本发明的一实施例中，所述进行一曝光显影步骤中，是通过一半色调光罩进行。
在本发明的一实施例中，所述半色调光罩包含基板、金属线镉膜及半透膜，所述金属线镉膜及所述半透膜设于所述基板上，所述半透膜设于所述金属线镉膜的两端。
在本发明的一实施例中，所述曝光显影步骤是采用一紫外光进行。
在本发明的一实施例中，所述基板是一玻璃基板。
在本发明的一实施例中，所述栅极金属层是包含铜/铝/钼之中一种或多种的金属层。
 有益效果
相较于在现有技术中，栅极金属层在蚀刻后具有坡度角过大或过切(undercut)不良等问题，本发明提供一种金属线半色调光罩，在保证线电阻的条件下，通过金属线的半色调光罩工艺使得金属层坡度角变小，降低了过切和静电放电(Electro Static Discharge；ESD)的发生率，从而达到提升制程中的操作窗(Window)的目的。
 附图说明
图1：本发明的一种薄膜晶体管的栅极制作方法的第一步骤的示意图。
图2：本发明的一种薄膜晶体管的栅极制作方法的第二步骤的示意图。
图3：本发明的一种薄膜晶体管的栅极制作方法的第三步骤的示意图。
图4：本发明的一种薄膜晶体管的栅极制作方法的第四步骤的示意图。
图5：本发明的一种薄膜晶体管的栅极制作方法的第五步骤的示意图。
图6：本发明的一种薄膜晶体管的栅极制作方法的第六步骤的示意图。
图7：本发明的一种薄膜晶体管的栅极制作方法的流程图。
 本发明的实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参照附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
参照图1至图7所示，图1至图2是本发明的一种薄膜晶体管的栅极制作方法的第一步骤至第六步骤的示意图，图7是本发明的一种薄膜晶体管的栅极制作方法的流程图。
本发明提供一种薄膜晶体管的栅极制作方法，其包含以下步骤：
S1步骤：提供一基板10，所述基板上形成一栅极金属层20，所述栅极金属层上形成一光刻胶层30。
如图1所示，在本步骤中，所述基板10例如是一玻璃基板，所述栅极金属层20例如是铜/铝/钼(Cu/Al/Mo)等一种或多种的金属层。
S2步骤：进行一曝光显影步骤，在一栅极预设位置上将所述光刻胶层30形成一侧剖视为中间较厚的阶梯形状。
如图2所示，所述曝光显影步骤是通过一半色调光罩(Halftone Mask)来进行，所述半色调光罩包含基板40、金属线镉膜41及半透膜42，所述金属线镉膜41及所述半透膜设42于所述基板40上，所述半透膜42设于所述金属线镉膜41的两端。
在本步骤中，所述曝光显影步骤是采用一紫外光(UV)进行。
在本步骤中，所述栅金属层20曝光显影之后，所述光刻胶层30形成了一个中间较厚两端较薄的类似阶梯的形状。
S3步骤：进行一第一湿蚀刻步骤，将所述光刻胶层30以外的所述栅极金属层20除去，并且对所述光刻胶层30的两端形成过蚀刻。
S4步骤：进行一烧光阻步骤，将所述光刻胶层30的两端缩短，形成相较于所述栅极金属层20为较短的形状。
如图4所示，在本步骤中，通过烧光阻工艺，将所述栅极金属层20上的所述光刻胶层30的较薄的边缘(阶梯状)烧去，并曝漏出所述栅极金属层20的两端。
S5步骤：进行一第二湿蚀刻步骤，将所述栅极金属层20形成一侧剖视为梯形的形状。
如图5所示，在本步骤中，通过第二次湿蚀刻来修饰所述栅极金属层20的坡度角(Taper)。
S6步骤：移除所述光刻胶层30，在所述基板10上留下所述梯形的栅极金属层20。
如图6所示，在本步骤中，最后通过光阻剥离工艺去除剩余的所述光刻胶层30，以完成所述栅极金属层20的制作流程。
优选地，本发明可以通过两次蚀刻液中的药液成分浓度来调节纵向与横向蚀刻速度，使所述栅极金属层20的坡度角得到更好的控制。
综上所述，相较于在现有技术中，栅极金属层在蚀刻后具有坡度角过大或过切(undercut)不良等问题，本发明提供一种金属线半色调光罩，在保证线电阻的条件下，通过金属线的半色调光罩工艺使得金属层坡度角变小，降低了过切和静电放电(Electro Static Discharge；ESD)的发生率，从而达到提升制程中的操作窗(Window)的目的。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (10)

  1. 一种薄膜晶体管的栅极制作方法，其包含以下步骤：
    提供一基板，所述基板上形成一栅极金属层，所述栅极金属层上形成一光刻胶层；
    进行一曝光显影步骤，采用一紫外光，通过一半色调光罩，在一栅极预设位置上将所述光刻胶层形成一侧剖视为中间较厚的阶梯形状；
    进行一第一湿蚀刻步骤，将所述光刻胶层以外的所述栅极金属层除去，并且对所述光刻胶层的两端形成过蚀刻；
    进行一烧光阻步骤，将所述光刻胶层的两端缩短，形成相较于所述栅极金属层为较短的形状；
    进行一第二湿蚀刻步骤，将所述栅极金属层形成一侧剖视为梯形的形状；及
    移除所述光刻胶层，在所述基板上留下所述梯形的栅极金属层。
  2. 如权利要求1所述的薄膜晶体管的栅极制作方法，其中所述半色调光罩包含基板、金属线镉膜及半透膜，所述金属线镉膜及所述半透膜设于所述基板上，所述半透膜设于所述金属线镉膜的两端。
  3. 如权利要求1所述的薄膜晶体管的栅极制作方法，其中所述基板是一玻璃基板。
  4. 如权利要求1所述的薄膜晶体管的栅极制作方法，其中所述栅极金属层是包含铜/铝/钼之中一种或多种的金属层。
  5. 一种薄膜晶体管的栅极制作方法，其包含以下步骤：
    提供一基板，所述基板上形成一栅极金属层，所述栅极金属层上形成一光刻胶层；
    进行一曝光显影步骤，在一栅极预设位置上将所述光刻胶层形成一侧剖视为中间较厚的阶梯形状；
    进行一第一湿蚀刻步骤，将所述光刻胶层以外的所述栅极金属层除去，并且对所述光刻胶层的两端形成过蚀刻；
    进行一烧光阻步骤，将所述光刻胶层的两端缩短，形成相较于所述栅极金属层为较短的形状；
    进行一第二湿蚀刻步骤，将所述栅极金属层形成一侧剖视为梯形的形状；及
    移除所述光刻胶层，在所述基板上留下所述梯形的栅极金属层。
  6. 如权利要求5所述的薄膜晶体管的栅极制作方法，其中所述进行一曝光显影步骤中，是通过一半色调光罩进行。
  7. 如权利要求6所述的薄膜晶体管的栅极制作方法，其中所述半色调光罩包含基板、金属线镉膜及半透膜，所述金属线镉膜及所述半透膜设于所述基板上，所述半透膜设于所述金属线镉膜的两端。
  8. 如权利要求5所述的薄膜晶体管的栅极制作方法，其中所述曝光显影步骤是采用一紫外光进行。
  9. 如权利要求5所述的薄膜晶体管的栅极制作方法，其中所述基板是一玻璃基板。
  10. 如权利要求5所述的薄膜晶体管的栅极制作方法，其中所述栅极金属层是包含铜/铝/钼之中一种或多种的金属层。
PCT/CN2019/095016 2018-12-26 2019-07-08 薄膜晶体管的栅极制作方法 WO2020134018A1 (zh)

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CN102651337A (zh) * 2011-05-13 2012-08-29 京东方科技集团股份有限公司 一种多晶硅tft阵列基板的制造方法
CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法
CN109686662A (zh) * 2018-12-26 2019-04-26 深圳市华星光电半导体显示技术有限公司 薄膜晶体管的栅极制作方法

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CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法
CN109686662A (zh) * 2018-12-26 2019-04-26 深圳市华星光电半导体显示技术有限公司 薄膜晶体管的栅极制作方法

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