WO2020133832A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2020133832A1
WO2020133832A1 PCT/CN2019/083591 CN2019083591W WO2020133832A1 WO 2020133832 A1 WO2020133832 A1 WO 2020133832A1 CN 2019083591 W CN2019083591 W CN 2019083591W WO 2020133832 A1 WO2020133832 A1 WO 2020133832A1
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Prior art keywords
thin film
goa circuit
film transistor
type thin
signal line
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PCT/CN2019/083591
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English (en)
French (fr)
Inventor
宋乔乔
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a GOA circuit.
  • GOA Gate Drive On Array
  • TFT Thin Film Transistor
  • the gate scanning driving circuit is made on the thin film transistor array substrate, so as to realize the progressive scanning driving method, such a design, it can not only save the cost of the gate integrated circuit, but also Reducing the width of the panel border is very beneficial to the ultra-narrow border design now, and is an important technology for panel design in the future.
  • the GOA circuit it has two basic functions, one is to output the scan drive signal, and the second is the displacement register function. When the Nth scan drive signal is output, the N+1th through the clock control and passed in turn Go on.
  • the present disclosure provides a GOA circuit to solve the problems in the prior art that there are a large number of circuits in the GOA circuit, the circuit design layout occupies a large space, and the cost is high.
  • a GOA circuit includes:
  • the Nth stage GOA circuit unit is connected to the Nth stage GOA circuit output signal line Sn, the Nth stage GOA circuit output signal line Sn is connected to the Nth stage selection circuit unit, and the Nth stage selection circuit unit is connected to the
  • the N-stage gate output signal line Gn is connected to the N+2th stage gate output signal line Gn+2, and N is a positive integer;
  • the selection circuit unit further includes: a first data signal line, a second data signal line, and multiple sets of N-type and P-type thin film transistors connected;
  • each of the GOA circuit units realizes the output of two gate signals
  • the GOA circuit further includes a clock control signal line, and the clock control signal line includes a first clock signal CK1 and a second clock signal CK2, wherein the plurality of cascaded GOA circuit units alternate with the first The clock signal CK1 and the second clock signal CK2 are connected.
  • the selection circuit unit further includes: wherein the selection circuit unit further includes: a first N-type thin film transistor, a first P-type thin film transistor, a second N-type thin film transistor, a second P-type thin film transistor, the drain of the first N-type thin film transistor is connected to the second data signal line, and the gate of the first N-type thin film transistor is connected to and connected to the gate of the first P-type thin film transistor
  • the N-th stage GOA circuit outputs a signal Sn
  • the source of the first N-type thin film transistor is connected to the drain of the first P-type thin film transistor and is connected to the N-th gate output signal line Gn
  • the source of the first P-type thin film transistor is connected to the drain of the second N-type thin film transistor and the first data signal line
  • the gate of the second N-type thin film transistor is connected to the second P-type thin film
  • the gate of the transistor is connected to the output signal Sn of the Nth stage GOA circuit, and the source of the second N-type thin film
  • the first data signal line is a DC signal with a voltage of -6V.
  • the second data signal line is a DC signal with a voltage of 28V.
  • the layout of the GOA circuit occupies a width of 500um-1000um.
  • a GOA circuit including: a plurality of cascaded GOA circuit units, GOA circuit output signal lines, selection circuit units, and gate output signal lines;
  • the Nth stage GOA circuit unit is connected to the Nth stage GOA circuit output signal line Sn, the Nth stage GOA circuit output signal line Sn is connected to the Nth stage selection circuit unit, and the Nth stage selection circuit unit is connected to the
  • the N-stage gate output signal line Gn is connected to the N+2th stage gate output signal line Gn+2, and N is a positive integer;
  • the selection circuit unit further includes: a first data signal line, a second data signal line, and multiple sets of N-type and P-type thin film transistors connected.
  • the selection circuit unit further includes: a first N-type thin film transistor, a first P-type thin film transistor, a second N-type thin film transistor, a second P-type thin film transistor, the first The drain of the N-type thin film transistor is connected to the second data signal line, and the gate of the first N-type thin film transistor is connected to the gate of the first P-type thin film transistor and connected to the output signal of the N-th stage GOA circuit Sn, the source of the first N-type thin film transistor is connected to the drain of the first P-type thin film transistor and connected to the N-th gate output signal line Gn, and the source of the first P-type thin film transistor Connected to the drain of the second N-type thin film transistor and connected to the first data signal line, and the gate of the second N-type thin film transistor is connected to the gate of the second P-type thin film transistor and connected to the first The N-level GOA circuit outputs a signal Sn.
  • the source of the second N-type thin film transistor is connected
  • the GOA circuit further includes a clock control signal line, the clock control signal line includes a first clock signal CK1, a second clock signal CK2, wherein the cascaded multiple GOAs The circuit unit is alternately connected to the first clock signal CK1 and the second clock signal CK2.
  • each of the GOA circuit units realizes the output of two gate signals.
  • the first data signal line is a DC signal with a voltage of -6V.
  • the second data signal line is a DC signal with a voltage of 28V.
  • the layout of the GOA circuit occupies a width of 500um-1000um.
  • the line row can be reduced without changing the number of gate signal output stages
  • the layout reduces the number of GOA circuits, thereby saving layout design area, realizing the design of ultra-narrow bezel panels, and reducing product production costs.
  • FIG. 1 is a schematic diagram of panel gate output in the disclosed embodiment
  • FIG. 2 is an internal circuit diagram of a selection circuit unit in the GOA circuit of the present disclosure
  • FIG. 3 is a timing diagram of the operation of the selection circuit unit in the GOA circuit of the present disclosure.
  • FIG. 1 is a schematic diagram of panel gate output in the disclosed embodiment.
  • the circuit of FIG. 1 includes clock control signal line (CK1) 1, clock control signal line (CK2) 2, low frequency inversion AC signal line (LC1) 3, low frequency inversion AC signal line (LC2) 4, VSS
  • the DC signal line 5 a multi-level GOA circuit, output signals S1, S2... connected to the GOA circuit and outputting a plurality of thin film transistor units, and an output N-th gate output signal line Gn.
  • the GOA circuit Gn is similar to the function of a shift register.
  • the clock signal is transmitted to the GOA circuit Gn through the clock control signal line 1, the clock control signal line 2, the low frequency inversion AC signal line 3, and the low frequency inversion AC signal line 4.
  • the gate signal Sn is transmitted for the first time.
  • the output gate signal is not directly input into the pixel, but also needs to pass through a plurality of circuit units and pass through each selection circuit unit.
  • each circuit unit After conversion, each circuit unit outputs two gate output signals Gn, Gn+2 again.
  • the gate signal S1 passes through the action of the circuit unit, and then outputs the gate signal G1 and the gate signal G3, respectively.
  • the GOA circuit of each stage can output two gate output signals with different signal timings. Therefore, the number of stages of the GOA circuit is reduced, which can effectively reduce the number of circuits and make the space of the circuit layout larger. , More conducive to the design of ultra-narrow bezel circuits.
  • FIG. 2 is an internal circuit diagram of the circuit unit in the GOA circuit in FIG. 1 of the present disclosure.
  • the GOA circuit at each level includes a GOA circuit unit, a first data signal line 1, a second data signal line 2, and a selection circuit unit 3.
  • the selection circuit unit 3 further specifically includes: a first N-type thin film transistor T1, a first A P-type thin film transistor T2, a second N-type thin film transistor T3, and a second P-type thin film transistor T4 have a gate output signal S1, a gate output signal G1, and a gate output signal G3.
  • the selection circuit unit 3 is formed by connecting a plurality of N-type and P-type thin film transistors in parallel or in series, thereby integrating a plurality of thin film transistors together.
  • the drain of the first N-type thin film transistor T1 is connected to the second data signal line 2
  • the gate of the first N-type thin film transistor T1 is connected to the gate of the first P-type thin film transistor T2
  • the source of the first N-type thin film transistor T1 is connected to the drain of the first P-type thin film transistor T2 and connected to the first-stage gate output signal line G1
  • the first P-type thin film transistor T2 Is connected to the drain of the second N-type thin film transistor T3 and connected to the first data signal line 1
  • the gate of the second N-type thin film transistor T3 is connected to the second P-type thin film transistor T4
  • the gate is connected to the output signal S1 of the first-stage GOA circuit
  • each stage of the GOA circuit realizes the output of two sets of gate signals.
  • FIG. 3 is a working timing diagram of the selection circuit unit in the present disclosure.
  • the output gate signals S1 and S1 are DC signals.
  • the signal S1 is low, the first P-type thin film transistor T2 is turned on and the first thin film transistor T1 is turned off.
  • the gate signal G1 output in the first-stage GOA circuit is the signal of the first data signal line 1; when the signal S1 is high, the first N-type thin film transistor T1 is turned on, and the first P-type thin film transistor T2 is turned off, At this time, the gate signal G1 output in the first-stage GOA circuit is the signal of the second data signal line 2. In this way, the circuit completes the output of the gate signal G1.
  • the gate signal G3 output from the circuit is the second The signal of the data signal line 2; when the signal S1 is high, the second N-type thin film transistor T3 is turned on, and the second P-type thin film transistor T4 is turned off. At this time, the gate signal G3 output from the circuit is the first data signal Line 1 signal. In this way, the circuit completes the output of the gate signal G3.
  • the high potential voltage is set to 33V
  • the high potential voltage output by the gate is 28V
  • the first data The signal line 1 is a DC signal of -6V
  • the second data signal line 2 is a DC signal of 28V.
  • the GOA circuit of the present disclosure can be used in various high-definition, ultra-high-definition, 8K and other display products.
  • S1 outputs a two-level gate signal, that is, the function of a single-level GOA circuit to output a two-level gate signal is realized.
  • this The number of GOA circuits in the disclosure is reduced by half, and only a 384-level GOA circuit can be realized.
  • the width of the GOA circuit of the existing panel is 1000um-2000um
  • the GOA circuit of the present disclosure saves half of the GOA circuit, so the circuit layout width is reduced to 500um-1000um. Therefore, this peripheral circuit design will be more advantageous for ultra-narrow bezel products.
  • a GOA circuit disclosed in this design adds a plurality of N-type and P-type thin film transistors to a plurality of cascaded GOA circuits, thereby achieving the same number of gate signal output stages Under the circumstances, reduce the arrangement of lines, reduce the number of GOA circuits, thereby saving the layout design width, achieving the design of ultra-narrow bezel panels, and reducing the production cost of the product.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路，包括级联的多个GOA电路单元、第一数据信号线（1）、第二数据信号线（2）、第N级GOA电路输出信号（Sn）、第N级栅极输出信号线(Gn)、第N+2级栅极输出信号线(Gn+2)及多组N型与P型连接的薄膜晶体管(T1, T2, T3, T4)，通过在GOA电路中增加N型和P型的薄膜晶体管(T1, T2, T3, T4)，减少线路的排布，减少GOA电路数目，实现超窄边框面板，降低生产成本。

Description

GOA电路 技术领域
本揭示涉及显示技术领域，尤其涉及一种GOA电路。
 背景技术
GOA（Gate Drive On Array）技术即阵列基板行驱动技术，是利用薄膜晶体管（Thin Film Transistor，TFT）液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板之上，从而实现逐行扫描的驱动的方式，这样的设计，它既可以节省栅极集成电路的成本，也能够缩减面板边框的宽度，对现在超窄边框设计非常有利，是未来面板设计的一个重要技术。在GOA电路中，它具有两项基本的功能，一是输出扫描驱动信号，第二是位移寄存功能，当第N个扫描驱动信号输出完成后，通过时钟控制进行第N+1个并依次传递下去。
然而，现有GOA产品在实现栅极信号输出时需要多组时钟信号（Clock cycle，CK ）和低频信号（Low Complexity ，LC）和GOA电路（18个TFT和一个电容）的共同作用，并且，现有产品对GOA电路充电和续传能力的要求也不断提高，对器件的频率、分辨率等性能参数的要求也越来越高，同时伴随着器件数量的增加，TFT的尺寸和时钟信号的数目加大，使得电路的布局变得复杂，放置电路的面板的面积也相应增大，导致现有电路面板的栅极边框变大。
 技术问题
现有的GOA电路中，电路数目较多并且电路的设计版图面积较大，不利于面板超窄边框的设计，并且成本较高的问题，需要提出进一步的完善和改进方案。
 技术解决方案
本揭示提供一种GOA电路，以解决现有技术水平中GOA电路中电路数目较多，电路的设计版图占据空间较大，并且成本较高的问题。
为解决上述技术问题，本揭示提供的技术方案如下：
根据本揭示实施例的第一方面，提供了一种GOA电路，所述的GOA电路包括：
级联的多个GOA电路单元、GOA电路输出信号线、选择电路单元以及栅极输出信号线；
其中，第N级GOA电路单元与第N级GOA电路输出信号线Sn连接，所述第N级GOA电路输出信号线Sn与第N级选择电路单元连接，所述第N级选择电路单元与第N级栅极输出信号线Gn和第N+2级栅极输出信号线Gn+2连接，N为正整数；
其中，选择电路单元中还包括：第一数据信号线、第二数据信号线、多组N型与P型连接的薄膜晶体管；
其中，每一个所述GOA电路单元实现两个栅极信号的输出；
所述的GOA电路还包括时钟控制信号线，所述时钟控制信号线包括第一时钟信号CK1、第二时钟信号CK2，其中，所述级联的多个GOA电路单元交替的与所述第一时钟信号CK1和第二时钟信号CK2相连接。
根据本揭示的一实施例，所述选择电路单元中还包括：其中所述选择电路单元中还包括：第一N型薄膜晶体管、第一P型薄膜晶体管、第二N型薄膜晶体管、第二P型薄膜晶体管，所述第一N型薄膜晶体管的漏极连接所述第二数据信号线，所述第一N型薄膜晶体管的栅极连接所述第一P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第一N型薄膜晶体管的源极连接所述第一P型薄膜晶体管的漏极并连接所述第N级栅极输出信号线Gn，所述第一P型薄膜晶体管的源极连接所述第二N型薄膜晶体管的漏极并连接所述第一数据信号线，所述第二N型薄膜晶体管的栅极连接所述第二P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第二N型薄膜晶体管的源极连接所述第二P型薄膜晶体管的漏极并连接所述第N+2级栅极输出信号线Gn+2，所述第二P型薄膜晶体管的源极连接所述第二数据信号线。
根据本揭示的一实施例，其中所述GOA电路单元中有两个直流信号。
根据本揭示的一实施例，其中所述第一数据信号线为电压-6V的直流信号。
根据本揭示的一实施例，其中所述第二数据信号线为电压28V的直流信号。
根据本揭示的一实施例，其中所述GOA电路的版图占据的宽度为500um—1000um。
根据本揭示的第二方面，还提供了一种GOA电路，包括：级联的多个GOA电路单元、GOA电路输出信号线、选择电路单元以及栅极输出信号线；
其中，第N级GOA电路单元与第N级GOA电路输出信号线Sn连接，所述第N级GOA电路输出信号线Sn与第N级选择电路单元连接，所述第N级选择电路单元与第N级栅极输出信号线Gn和第N+2级栅极输出信号线Gn+2连接，N为正整数；
其中，选择电路单元中还包括：第一数据信号线、第二数据信号线、多组N型与P型连接的薄膜晶体管。
根据本揭示的一实施例，其中所述选择电路单元中还包括：第一N型薄膜晶体管、第一P型薄膜晶体管、第二N型薄膜晶体管、第二P型薄膜晶体管，所述第一N型薄膜晶体管的漏极连接所述第二数据信号线，所述第一N型薄膜晶体管的栅极连接所述第一P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第一N型薄膜晶体管的源极连接所述第一P型薄膜晶体管的漏极并连接所述第N级栅极输出信号线Gn，所述第一P型薄膜晶体管的源极连接所述第二N型薄膜晶体管的漏极并连接所述第一数据信号线，所述第二N型薄膜晶体管的栅极连接所述第二P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第二N型薄膜晶体管的源极连接所述第二P型薄膜晶体管的漏极并连接所述第N+2级栅极输出信号线Gn+2，所述第二P型薄膜晶体管的源极连接所述第二数据信号线。
根据本揭示的一实施例，其中所述的GOA电路还包括时钟控制信号线，所述时钟控制信号线包括第一时钟信号CK1、第二时钟信号CK2，其中，所述级联的多个GOA电路单元交替的与所述第一时钟信号CK1和第二时钟信号CK2相连接。
根据本揭示的一实施例，其中每一个所述GOA电路单元实现两个栅极信号的输出。
根据本揭示的一实施例，其中所述GOA电路单元中有两个直流信号。
根据本揭示的一实施例，其中所述第一数据信号线为电压-6V的直流信号。
根据本揭示的一实施例，其中所述第二数据信号线为电压28V的直流信号。
根据本揭示的一实施例，其中所述GOA电路的版图占据的宽度为500um—1000um。
 有益效果
本揭示的有益效果为：
通过对现有的电路进行改进，通过在级联的多个GOA电路中增加多个N型和P型的薄膜晶体管，从而实现在栅极信号输出级数不变的情况下，减少线的排布，减少GOA电路的数目，从而节省版图设计面积，实现超窄边框面板的设计，并且降低产品的生产成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示实施例中的面板栅极输出示意图；
图2为本揭示GOA电路中选择电路单元的内部电路图；
图3为本揭示GOA电路中选择电路单元的工作时序图。
本揭示的最佳实施方式
下面将结合本揭示实施例中的附图，对本揭示实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本揭示一部分实施例，而不是全部的实施例。基于本揭示中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本揭示保护的范围。
在本揭示的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、 “厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本揭示和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本揭示的限制。在本揭示的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本实施例中，如图1所示，图1为本揭示实施例中的面板栅极输出示意图。在图1的电路中，包括，时钟控制信号线（CK1）1，时钟控制信号线（CK2）2，低频反转交流信号线（LC1）3，低频反转交流信号线（LC2）4，VSS直流信号线5，多级GOA电路，与GOA电路连接并输出的输出信号S1、S2……多个薄膜晶体管单元，以及输出的第N级栅极输出信号线Gn。GOA电路Gn类似于一个移位寄存器的功能，时钟信号通过时钟控制信号线1、时钟控制信号线2、低频反转交流信号线3以及低频反转交流信号线4，传输到GOA电路Gn内，然后第一次传输出栅极信号Sn，此时，在本揭示中，输出的栅极信号并没有直接输入到像素内，而是还需要经过多个电路单元，经过每一个选择电路单元内部的转换后，每一个电路单元都重新输出两个栅极输出信号Gn、Gn+2。具体的，当GOA电路1中输出栅极信号S1后，栅极信号S1经过电路单元的作用，再分别输出栅极信号G1、栅极信号G3。
这样，以不同的信号时序使每一级的GOA电路能够分别输出两个栅极输出信号，因此，GOA电路的级数降低，能够有效的减少电路的数目，使得电路版图的空间变得更大，更有利于超窄边框电路的设计。
如图2所示，图2为本揭示图1中GOA电路中电路单元的内部电路图。每一级所述GOA电路包括GOA电路单元、第一数据信号线1、第二数据信号线2、选择电路单元3，在选择电路单元3内部具体还包括：第一N型薄膜晶体管T1、第一P型薄膜晶体管T2、第二N型薄膜晶体管T3以及第二P型薄膜晶体管T4，栅极输出信号S1，栅极输出信号G1、栅极输出信号G3。
选择电路单元3内由多个N型和P型薄膜晶体管之间的并联或者是串联而形成，从而将多个薄膜晶体管集成在一起。其中，第一N型薄膜晶体管T1的漏极连接第二数据信号线2，所述第一N型薄膜晶体管T1的栅极连接第一P型薄膜晶体管T2的栅极并连接第1级GOA电路输出信号S1，第一N型薄膜晶体管T1的源极连接所述第一P型薄膜晶体管T2的漏极并连接所述第1级栅极输出信号线G1，所述第一P型薄膜晶体管T2的源极连接所述第二N型薄膜晶体管T3的漏极并连接所述第一数据信号线1，所述第二N型薄膜晶体管T3的栅极连接所述第二P型薄膜晶体管T4的栅极并连接所述第1级GOA电路输出信号S1，所述第二N型薄膜晶体管T3的源极连接所述第二P型薄膜晶体管T4的漏极并连接所述第3级栅极输出信号线G3，所述第二P型薄膜晶体管T4的源极连接所述第二数据信号线2。
经过选择电路单元3的处理，每一级GOA电路，实现了两组栅极信号的输出。如图3所示，图3为本揭示中选择电路单元的工作时序图。具体的，在第一级GOA电路中，输出的栅极信号S1，S1为直流信号，当信号S1为低电平时，第一P型薄膜晶体管T2打开，第一薄膜晶体管T1则关闭，此时，第一级GOA电路中输出的栅极信号G1为第一数据信号线1的信号；当信号S1为高电平时，第一N型薄膜晶体管T1打开，第一P型薄膜晶体管T2则关闭，此时，第一级GOA电路中输出的栅极信号G1为第二数据信号线2的信号。这样，电路就完成了栅极信号G1的输出情况。
同理，当第一级GOA电路中，信号S1为低电平时，第二P型薄膜晶体管T4打开，第二N型薄膜晶体管T3关闭，此时，电路中输出的栅极信号G3为第二数据信号线2的信号；当信号S1为高电平时，第二N型薄膜晶体管T3打开，第二P型薄膜晶体管T4则关闭，此时，电路中输出的栅极信号G3为第一数据信号线1的信号。这样，电路就完成栅极信号G3的输出情况。
在本揭示中，考虑到各个薄膜晶体管的阀值电压，以及时钟时信号和低频反转信号等的影响因素，高电位的电压设置为33V，栅极输出的高电位电压为28V，第一数据信号线1上为-6V的直流信号，第二数据信号线2上为28V的直流信号，同时，本揭示的GOA电路可以使用在各种高清、超高清、8K等显示器产品上。
通过选择电路单元3的作用，S1输出了两级栅极信号，即实现了单一级的GOA电路输出两级栅极信号的功能，在显示器产品中，相比现有的768级GOA电路，本揭示中的GOA电路数目减少一半，只需要384级的GOA电路就能够实现。进一步说明，如果在现有面板的GOA电路中，所占据的宽度为1000um—2000um，本揭示的GOA电路，由于节省了一半的GOA电路，故电路版图宽度降为500um—1000um。因此，这种外围的电路设计，对超窄边框产品来说，会更加的有利。
从上述实施例可以看出，本设计揭示的一种GOA电路，通过在级联的多个GOA电路中增加多个N型和P型的薄膜晶体管，从而实现在栅极信号输出级数不变的情况下，减少线的排布，减少GOA电路的数目，从而节省版图设计宽度，实现超窄边框面板的设计，并且降低产品的生产成本。
以上对本揭示实施例所提供的一种GOA电路进行了详细介绍，本文中应用了具体个例对本揭示的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本揭示的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本揭示各实施例的技术方案的范围。

Claims (14)

  1. 一种GOA电路，包括，
    级联的多个GOA电路单元、GOA电路输出信号线、选择电路单元以及栅极输出信号线；
    其中，第N级GOA电路单元与第N级GOA电路输出信号线Sn连接，所述第N级GOA电路输出信号线Sn与第N级选择电路单元连接，所述第N级选择电路单元与第N级栅极输出信号线Gn和第N+2级栅极输出信号线Gn+2连接，N为正整数；
    其中，选择电路单元还包括：第一数据信号线、第二数据信号线以及多组N型与P型连接的薄膜晶体管；
    其中，每一个所述GOA电路单元实现两个栅极信号的输出；
    其中，所述的GOA电路还包括时钟控制信号线，所述时钟控制信号线包括第一时钟信号CK1、第二时钟信号CK2，其中，所述级联的多个GOA电路单元交替的与所述第一时钟信号CK1和第二时钟信号CK2相连接。
  2. 根据权利要求1所述的GOA电路，其中所述选择电路单元中还包括：第一N型薄膜晶体管、第一P型薄膜晶体管、第二N型薄膜晶体管、第二P型薄膜晶体管，所述第一N型薄膜晶体管的漏极连接所述第二数据信号线，所述第一N型薄膜晶体管的栅极连接所述第一P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第一N型薄膜晶体管的源极连接所述第一P型薄膜晶体管的漏极并连接所述第N级栅极输出信号线Gn，所述第一P型薄膜晶体管的源极连接所述第二N型薄膜晶体管的漏极并连接所述第一数据信号线，所述第二N型薄膜晶体管的栅极连接所述第二P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第二N型薄膜晶体管的源极连接所述第二P型薄膜晶体管的漏极并连接所述第N+2级栅极输出信号线Gn+2，所述第二P型薄膜晶体管的源极连接所述第二数据信号线。
  3. 根据权利要求2所述的GOA电路，其中所述GOA电路单元中有两个直流信号。
  4. 根据权利要求1所述的GOA电路，其中所述第一数据信号线为电压-6V的直流信号。
  5. 根据权利要求1所述的GOA电路，其中所述第二数据信号线为电压28V的直流信号。
  6. 根据权利要求1所述的GOA电路，其中所述GOA电路的版图占据的宽度为500um—1000um。
  7. 一种GOA电路，包括，
    级联的多个GOA电路单元、GOA电路输出信号线、选择电路单元以及栅极输出信号线；
    其中，第N级GOA电路单元与第N级GOA电路输出信号线Sn连接，所述第N级GOA电路输出信号线Sn与第N级选择电路单元连接，所述第N级选择电路单元与第N级栅极输出信号线Gn和第N+2级栅极输出信号线Gn+2连接，N为正整数；
    其中，选择电路单元中还包括：第一数据信号线、第二数据信号线、多组N型与P型连接的薄膜晶体管。
  8. 根据权利要求7所述的GOA电路，其中所述选择电路单元中还包括：第一N型薄膜晶体管、第一P型薄膜晶体管、第二N型薄膜晶体管、第二P型薄膜晶体管，所述第一N型薄膜晶体管的漏极连接所述第二数据信号线，所述第一N型薄膜晶体管的栅极连接所述第一P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第一N型薄膜晶体管的源极连接所述第一P型薄膜晶体管的漏极并连接所述第N级栅极输出信号线Gn，所述第一P型薄膜晶体管的源极连接所述第二N型薄膜晶体管的漏极并连接所述第一数据信号线，所述第二N型薄膜晶体管的栅极连接所述第二P型薄膜晶体管的栅极并连接所述第N级GOA电路输出信号Sn，所述第二N型薄膜晶体管的源极连接所述第二P型薄膜晶体管的漏极并连接所述第N+2级栅极输出信号线Gn+2，所述第二P型薄膜晶体管的源极连接所述第二数据信号线。
  9. 根据权利要求7所述的GOA电路，其中所述的GOA电路还包括时钟控制信号线，所述时钟控制信号线包括第一时钟信号CK1、第二时钟信号CK2，其中，所述级联的多个GOA电路单元交替的与所述第一时钟信号CK1和第二时钟信号CK2相连接。
  10. 根据权利要求7所述的GOA电路，其中每一个所述GOA电路单元实现两个栅极信号的输出。
  11. 根据权利要求10所述的GOA电路，其中所述GOA电路单元中有两个直流信号。
  12. 根据权利要求7所述的GOA电路，其中所述第一数据信号线为电压-6V的直流信号。
  13. 根据权利要求7所述的GOA电路，其中所述第二数据信号线为电压28V的直流信号。
  14. 根据权利要求7所述的GOA电路，其中所述GOA电路的版图占据的宽度为500um—1000um。
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