WO2020125308A1 - 一种体声波谐振器及其制备方法 - Google Patents

一种体声波谐振器及其制备方法 Download PDF

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Publication number
WO2020125308A1
WO2020125308A1 PCT/CN2019/119746 CN2019119746W WO2020125308A1 WO 2020125308 A1 WO2020125308 A1 WO 2020125308A1 CN 2019119746 W CN2019119746 W CN 2019119746W WO 2020125308 A1 WO2020125308 A1 WO 2020125308A1
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Prior art keywords
electrode
interdigitated
metal layer
bulk acoustic
acoustic wave
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PCT/CN2019/119746
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English (en)
French (fr)
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吕萍
李刚
胡维
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苏州敏芯微电子技术股份有限公司
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Publication of WO2020125308A1 publication Critical patent/WO2020125308A1/zh
Priority to US17/351,594 priority Critical patent/US20210313946A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02228—Guided bulk acoustic wave devices or Lamb wave devices having interdigital transducers situated in parallel planes on either side of a piezoelectric layer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/13—Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type

Definitions

  • the invention relates to the technical field of Micro-Electro-Mechanical (MEMS) devices, in particular to a bulk acoustic wave resonator and a preparation method thereof.
  • MEMS Micro-Electro-Mechanical
  • bulk acoustic wave resonators have been a research hotspot in recent years.
  • thin film bulk acoustic resonators Fin, FBAR
  • Lamb wave bulk acoustic resonators LWR
  • advantages of small size, low insertion loss, good out-of-band suppression, high power capacity, and easy integration has become the latest generation of bulk acoustic wave resonators.
  • FIG. 1 is a schematic structural diagram of FBAR in the prior art. As shown in FIG.
  • the FBAR 100 includes a silicon substrate 101, a supporting layer 103, a first electrode 104, a piezoelectric film 105, and a second electrode 106 stacked in this order from bottom to top, wherein the silicon substrate 101 includes a reverse etching Cavity 102, the back side etching cavity 102 is obtained by back side etching of the silicon wafer forming the silicon substrate 101, thereby forming an isolation band of sound waves, so as to limit the sound waves to the first electrode 104 and the piezoelectric film 105
  • the resonance piezoelectric stack formed with the second electrode 106 effectively prevents sound leakage.
  • a large area of silicon wafer needs to be etched away, resulting in poor device structural stability.
  • the embodiments of the present invention are dedicated to providing a bulk acoustic wave resonator and a method for manufacturing the same, to solve the problem of poor stability of the bulk acoustic wave resonator in the prior art.
  • a first aspect of the present invention provides a method for manufacturing a bulk acoustic wave resonator, including: providing a first silicon wafer and preparing a cavity with an open top on the first silicon wafer; providing a second silicon wafer on the second silicon wafer An insulating layer is prepared on the surface, and a resonant piezoelectric stack is prepared on the surface of the insulating layer.
  • the resonant piezoelectric stack includes a piezoelectric film and a first electrode and a second electrode that are in contact with the piezoelectric film and are independent of each other;
  • the first silicon dioxide layer is prepared on the surface.
  • the upper surface of the resonant piezoelectric stack includes one or more of the surface of the piezoelectric film, the surface of the first electrode, and the surface of the second electrode;
  • the upper surface of a silicon dioxide layer is bonded; the extraction pads of the first electrode and the second electrode are prepared.
  • a resonant piezoelectric stack is prepared on the upper surface of the insulating layer, the resonant piezoelectric stack includes a piezoelectric film and first and second electrodes that are in contact with the piezoelectric film and are independent of each other include: on the upper surface of the insulating layer A first metal layer is grown; a piezoelectric film is grown on the top surface of the first metal layer; a second metal layer is grown on the top surface of the piezoelectric film; wherein the first metal layer forms a first electrode and the second metal layer forms a second electrode.
  • the piezoelectric film is doped with metallic elements.
  • the method further includes: etching the first metal layer to form a first interdigitated finger and a second interdigitated finger, where the first interdigitated finger includes at least one first finger , The second interdigitated finger includes at least one second finger, at least one first finger and at least one second finger are alternately arranged at intervals; after growing the second metal layer on the upper surface of the piezoelectric film, the method further includes: engraving the second metal layer The erosion forms the third and fourth interdigitated fingers, the orthographic projections of the third and fourth interdigitated fingers coincide with the first and second interdigitated fingers, respectively; where the first interdigitated fingers form the first electrode, the second The interdigitated fingers form the second electrode.
  • a resonant piezoelectric stack is prepared on the upper surface of the insulating layer, the resonant piezoelectric stack includes a piezoelectric film and first and second electrodes that are in contact with the piezoelectric film and are independent of each other include: on the upper surface of the insulating layer Growing a first metal layer; etching the first metal layer to form a first interdigitated electrode and a second interdigitated electrode, the first interdigitated electrode includes at least one first interdigitated electrode, and the second interdigitated electrode includes at least one second interdigitated electrode Interdigitated fingers, at least one first interdigitated finger and at least one second interdigitated finger alternately arranged; a piezoelectric film is grown on the upper surface of the insulating layer, the upper surface of the first interdigitated electrode, and the upper surface of the second interdigitated electrode; One interdigitated electrode forms the first electrode, and the second interdigitated electrode forms the second electrode.
  • the method further includes: etching away the second silicon wafer to expose the insulating layer; The periphery of the interdigitated electrode starts to etch the trench downward from the surface of the insulating layer to the communication cavity.
  • the trench includes a first channel and a second channel, and the first channel and the second channel successively surround the first and second interdigital electrodes at predetermined intervals.
  • providing a first silicon wafer, and preparing a cavity with an open top on the first silicon wafer includes: providing a first silicon wafer; growing a second silicon dioxide layer on the upper surface of the first silicon wafer; The silicon dioxide layer is used as a mask to etch the cavity in the first silicon wafer.
  • providing a first silicon wafer, and preparing a cavity with an open top on the first silicon wafer includes: providing the first silicon wafer; using the photoresist as a mask, etching the cavity in the first silicon wafer body.
  • the orthographic projection of the first electrode and/or the second electrode in the vertical direction is an irregular polygon.
  • the depth of the cavity is 3-100 ⁇ m.
  • the insulating layer and the piezoelectric film have the same material.
  • a second aspect of the present invention provides a bulk acoustic wave resonator, which includes: a silicon substrate including a groove; a resonant piezoelectric stack, which is located on the silicon substrate and covers the groove to form a cavity, and a resonant piezoelectric
  • the stack includes a piezoelectric film and a first electrode and a second electrode that are in contact with the piezoelectric film and are independent of each other;
  • the lead-out pad includes a first pad and a second pad connected to the first electrode and the second electrode, respectively.
  • it further includes a trench that penetrates the silicon substrate where the resonant piezoelectric stack is located to communicate the cavity with the atmosphere.
  • the trench includes a first channel and a second channel, and the first channel and the second channel successively surround the first electrode and the second electrode at a predetermined interval.
  • the resonant piezoelectric stack includes a second metal layer, a piezoelectric film, and a first metal layer that are sequentially stacked on a silicon substrate;
  • the second metal layer includes a first sub-metal layer and a second independent of each other
  • the sub-metal layer, the first sub-metal layer forms a first electrode, and the second sub-metal layer and the first metal layer are electrically connected to form a second electrode.
  • the orthographic projection of the first metal layer and the first sub-metal layer on the silicon substrate covers the cavity.
  • the orthographic projections of the first electrode and the second electrode on the silicon substrate are irregular.
  • the resonant piezoelectric stack includes a piezoelectric film and a first metal layer stacked on a silicon substrate in sequence, the first metal layer includes a first interdigitated electrode and a second interdigitated electrode, the first interdigitated finger The electrode forms a first electrode, and the second interdigitated electrode forms a second electrode.
  • the resonant piezoelectric stack further includes a second metal layer between the piezoelectric film and the silicon substrate, the second metal layer includes a third interdigitated electrode and a fourth interdigitated electrode; the first interdigitated electrode The orthographic projection on the silicon substrate coincides with the third interdigitated electrode, and the orthographic projection of the second interdigitated electrode on the silicon substrate coincides with the fourth interdigitated electrode.
  • it also includes a silicon dioxide layer between the silicon substrate and the resonant piezoelectric stack.
  • a cavity is formed on the lower surface around the resonant piezoelectric stack by means of bonding.
  • the silicon substrate needs to be etched away to form a cavity
  • the structure is more stable.
  • FIG. 1 is a schematic structural diagram of FBAR in the prior art.
  • FIG. 2 is a flowchart of a method for manufacturing a bulk acoustic wave resonator according to an embodiment of the present invention.
  • FIGS. 3a-3i are schematic diagrams of device structures obtained during the preparation of the thin film bulk acoustic resonator according to the preparation method shown in FIG. 2 according to an embodiment of the present invention.
  • 4a-4i are schematic diagrams of device structures obtained during the process of preparing a Lamb wave bulk acoustic wave resonator according to the preparation method shown in FIG. 2 according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for manufacturing a bulk acoustic wave resonator according to an embodiment of the present invention. As shown in FIG. 2, the preparation method 200 includes:
  • Step S210 a first silicon wafer is provided, and a cavity with an open top is prepared on the first silicon wafer.
  • Step S220 a second silicon wafer is provided, an insulating layer is prepared on the upper surface of the second silicon wafer, and a resonant piezoelectric stack is prepared on the upper surface of the insulating layer.
  • the resonant piezoelectric stack is a core component of a bulk acoustic wave resonator, and includes a piezoelectric film and first and second electrodes that are in contact with the piezoelectric film and are independent of each other.
  • the working principle is that the first electrode and the second electrode are used as positive and negative electrodes.
  • the mechanical vibration is generated by the inverse piezoelectric effect of the piezoelectric film.
  • the frequency of the standing wave is equal to the frequency of the alternating voltage, resonance occurs.
  • Step S230 a first silicon dioxide layer is prepared on the upper surface of the resonant piezoelectric stack.
  • the upper surface of the resonant piezoelectric stack includes one or more of the surface of the piezoelectric film, the surface of the first electrode, and the surface of the second electrode .
  • Step S240 bonding the surface where the opening of the cavity is located and the upper surface of the first silicon dioxide layer.
  • Step S250 preparing extraction pads for the first electrode and the second electrode.
  • FIGS. 3a-3i are schematic diagrams of device structures obtained during the preparation of the thin film bulk acoustic resonator according to the preparation method shown in FIG. 2 according to an embodiment of the present invention.
  • the resonant piezoelectric stack in a film bulk acoustic resonator (Film Bulk Acoustic Resonator, FBAR) is a sandwich structure with a piezoelectric film sandwiched between the upper and lower electrodes, and its working principle is through the reverse piezoelectric of the piezoelectric film
  • the acoustic waves generated by the effect are transmitted longitudinally back and forth in the upper and lower surfaces of the piezoelectric film, thereby forming longitudinal resonance.
  • a first silicon substrate 311 is provided; a second silicon dioxide layer is grown on the surface of the first silicon substrate 311 using a liquid phase chemical vapor deposition (LPCVD) process 312, the thickness of the second silicon dioxide layer 312 is 500-6000A; using the second silicon dioxide layer 312 as a mask, a cavity 313 is etched by a photolithography process to form the device structure 310 shown in FIG. 3a, The depth of the cavity 313 may be 3-100 ⁇ m.
  • LPCVD liquid phase chemical vapor deposition
  • step S210 may also be performed by using photoresist as a mask to directly etch the cavity 313 on the upper surface of the first silicon wafer 311, that is, the upper surface of the first silicon substrate 311 There is no second silicon dioxide layer 312.
  • the material of the surface of the cavity opening in the device structure formed by the former is silicon dioxide, and the surface of the cavity structure of the device structure formed by the latter is silicon.
  • the surface where the opening of the cavity is located is subsequently used as a bonding party, thereby determining whether the subsequent bonding is SiO 2 -SiO 2 bonding or Si-SiO 2 bonding.
  • step S220 referring first to FIG. 3b, a second silicon wafer is provided as the second silicon substrate 321, an insulating layer 322 is grown on the surface of the second silicon substrate 321, and a first metal layer 323 is grown on the surface of the insulating layer 322.
  • a piezoelectric film 324 is grown on the upper surface of the first metal layer 323 along the c-axis direction.
  • the material of the insulating layer 322 includes silicon dioxide, silicon nitride, or aluminum nitride, and the thickness of the insulating layer 322 is 300-500 nm.
  • the material of the first metal layer 323 includes metal materials such as aluminum, molybdenum, palladium, and titanium. The thickness of the first metal layer 323 is 200-500 nm.
  • the material of the piezoelectric film 324 includes aluminum nitride, zinc oxide, lithium tantalate, etc.
  • the thickness of the piezoelectric film 324 is inversely related to the frequency of the FBAR resonator, so the piezoelectric film 324 can be reasonably determined according to the actual required resonance frequency
  • the thickness, for example, the thickness of the piezoelectric thin film 324 is 0.5-2um.
  • the material of the insulating layer 322 is aluminum nitride
  • the material of the first metal layer 323 is molybdenum or palladium. Since molybdenum or palladium has a good crystalline compatibility with the c-axis direction of the aluminum nitride film, therefore, better crystal quality and grain size can be obtained in this way.
  • the piezoelectric film 324 is doped with a metal element.
  • the doped metal elements include scandium, zirconium, calcium-titanium, magnesium-titanium, calcium-zirconium and the like. In this way, the effective coupling coefficient of the piezoelectric film 324 can be increased, and the effective coupling coefficient of the piezoelectric film 324 is proportional to the bandwidth of the resonator, so that the bandwidth of the resonator can be increased.
  • a second metal layer 325 is grown on the upper surface of the piezoelectric film 324, and the second metal layer 325 includes a first sub-metal layer 3251 and a second sub-metal layer 3252 that are spaced apart from each other, that is, the first sub-metal A gap H is included between the layer 3251 and the second sub-metal layer 3252.
  • the materials of the first sub-metal layer 3251 and the second sub-metal layer 3252 in the second metal layer 325 may be the same or different.
  • the forming process of the first sub-metal layer 3251 and the second sub-metal layer 3252 includes: growing a layer of second metal on the upper surface of the piezoelectric film 324 The layer 325 is then etched to form a first sub-metal layer 3251 and a second sub-metal layer 3252 which are independent of each other and are not connected to each other.
  • the forming process of the first sub-metal layer 3251 and the second sub-metal layer 3252 includes: using a mask plate on the upper surface of the piezoelectric film 324
  • the first sub-metal layer 3251 and the second sub-metal layer 3252 are grown in different regions, respectively.
  • a third silicon dioxide layer 326 is grown on the upper surface of the second metal layer 325 and the upper surface of the piezoelectric film 324 to form the device structure 320 shown in FIG. 3c.
  • the third silicon dioxide layer 326 includes a flat upper surface. In this way, it is advantageous for the subsequent film layer preparation.
  • the production process of the third silicon dioxide layer 326 may use the LPVCD process, and the thickness of the third silicon dioxide layer 326 may be, for example, 1000A-3000A.
  • step S340 referring to FIG. 3d, the upper surface of the device structure 310 shown in FIG. 3a and the upper surface of the device structure 320 shown in FIG. 3c are bonded to form the device structure 330 shown in FIG. 3d.
  • the upper surface of the device structure 310 shown in FIG. 3a includes the second silicon dioxide layer 302, SiO 2 is formed between the device structure 310 shown in FIG. 3a and the device structure 320 shown in FIG. 3c. -SiO 2 bonding; when the upper surface of the device structure 310 shown in FIG. 3a does not include the second silicon dioxide layer 302, Si is formed between the device structure 310 shown in FIG. 3a and the device structure 320 shown in FIG. 3c -SiO 2 bonding.
  • step S350 referring first to FIG. 3e, on the basis of the device structure 330 shown in FIG. 3d, a chemical mechanical polishing (CMP) process is used to remove the second silicon substrate 321 to expose the insulating layer 322.
  • CMP chemical mechanical polishing
  • a part of the insulating layer 322 and the first metal layer 323 under the part of the insulating layer 322 are etched away using a photolithography technique until the piezoelectric film 324 is exposed.
  • the insulating layer 322 in the edge area of the first metal layer 323 is removed by photolithography to obtain an exposed surface A of the first metal layer 323.
  • the insulating layer 322 and the piezoelectric film 324 are made of aluminum nitride.
  • the materials of the insulating layer 322 and the piezoelectric film 604 are the same, so when the insulating layer 322 in the edge region of the first metal layer 323 is photolithographically, the piezoelectric film 324 near the edge region of the first metal layer 323 A part of it will also be etched away, thereby forming a groove 3241 in the piezoelectric film 324.
  • a first contact hole 3271 and a second contact hole 3272 that communicate with the first sub-metal layer 3251 and the second sub-metal layer 3252 are etched on the upper surface of the piezoelectric film 324, respectively.
  • the first contact hole 3271 is further etched on the basis of the groove 3241, that is, the depth of the groove 3241 is deepened by the etching process to expose the first sub A metal layer 3251 to form a first contact hole 3271.
  • a lift-off technology is used to grow a first pad 3281 and a second pad 3282 in the first contact hole 3271 and the second contact hole 3272, respectively, wherein the exposed surface of the first metal layer 323 A and the first sub-metal layer 3251 are electrically connected to form a first electrode connected to the first pad 3281, and the second sub-metal layer 3252 forms a second electrode connected to the second pad 3282.
  • the first electrode is drawn out to the first pad 3281
  • the second electrode is drawn out to the second pad 3282.
  • the material of the first pad 3281 and the second pad 3282 are the same, and may be gold or titanium-tungsten alloy.
  • the thickness of the first pad 3281 and the second pad 3282 are 2000A-3000A.
  • the first pad 3281 and the second pad 3282 facilitate subsequent wire bonding, such as package testing or probe testing.
  • the orthographic projection of the first electrode and/or the second electrode in the vertical direction is an irregular polygon.
  • the irregular polygon mentioned here is the opposite concept of a regular polygon.
  • the orthographic projections of the first metal layer 323 and the first sub-metal layer 3215 forming the first electrode and the second sub-metal layer 3252 forming the second electrode in the vertical direction are irregular pentagons. In this way, parasitic modes formed by sound waves other than the sound waves that form the main resonance can be effectively reduced.
  • the orthographic projections of the first electrode and/or the second electrode in the vertical direction are irregular patterns.
  • an acoustic cavity that is, a cavity 313 is formed under the overlapping area of the first electrode and the second electrode, that is, the area where the first metal layer 323 and the second sub-metal layer 3252 are directly opposite
  • the lower surface of the second electrode (specifically, the second silicon dioxide layer 326) forms an air interface.
  • the acoustic impedance of air is approximately zero, it can be used as a good sound limiting boundary, so that the air interface on the lower surface of the second electrode and the air interface on the upper surface of the first electrode (specifically, the insulating layer 322) cooperate with each other.
  • the sound wave generated by the FBAR is confined within the piezoelectric oscillating stack composed of the first electrode, the second electrode, and the piezoelectric film 324.
  • FIG. 4a-4i are schematic diagrams of device structures obtained during the process of preparing a Lamb wave bulk acoustic wave resonator according to the preparation method shown in FIG. 2 according to an embodiment of the present invention.
  • the difference between Lamb wave bulk acoustic resonator (LWR) and FBAR in principle is that in LWR, acoustic waves propagate in a surface parallel to the piezoelectric film, thereby forming a lateral resonance.
  • the device structure 310 shown in FIG. 3a is obtained according to step S210. This process is the same as the process of preparing the device structure 310 in FBAR, and will not be repeated here.
  • step S220 referring first to FIG. 4a, a second wafer is provided as the second silicon substrate 411, an insulating layer 412 is deposited on the surface of the second silicon substrate 411, and a first metal layer is grown on the upper surface of the insulating layer 412. A metal layer is etched to form a first interdigitated electrode 4131 and a second interdigitated electrode 4132.
  • the formed device structure 410 is shown in FIG. 4a, and the top view of the device structure 410 is shown in FIG. 4b.
  • the first interdigitated electrode 4131 includes at least one first interdigitated finger
  • the second interdigitated electrode 4132 includes at least one second interdigitated finger.
  • the at least one first interdigitated finger and the at least one second interdigitated finger are alternately arranged at intervals.
  • the spacing L between two adjacent fingers determines the frequency of the Lamb wave bulk acoustic resonator. Specifically, the spacing L between two adjacent fingers and the frequency of the Lamb wave bulk acoustic resonator are negative Correlation, therefore, the spacing L between two adjacent interdigital fingers can be reasonably set according to the required frequency.
  • the number of the first and second interdigitated fingers can be any number, for example, the first interdigitated electrode 4131 shown in FIGS. 4a and 4b includes two interdigitated fingers, and the second interdigitated electrode 4132 also includes one Interdigitated.
  • the material of the first metal layer includes metal materials such as aluminum, molybdenum, palladium, and titanium.
  • the thickness of the first metal layer is 200-500 nm.
  • the material of the insulating layer 412 is aluminum nitride, and the material of the first metal layer is molybdenum or palladium. Since molybdenum or palladium has a good crystalline compatibility with the c-axis direction of the aluminum nitride film, therefore, better crystal quality and grain size can be obtained in this way.
  • a piezoelectric film 414 is grown on the surfaces of the first interdigitated electrode 4131, the second interdigitated electrode 4132 and the insulating layer 412.
  • the piezoelectric thin film 414 includes a flat upper surface, so as to facilitate subsequent preparation of each film layer.
  • the material of the piezoelectric film 414 includes aluminum nitride, zinc oxide, lithium tantalate, and the like.
  • the ratio of the wavelength of the acoustic wave to the thickness of the piezoelectric film 414 is less than 0.4, so that a higher acoustic wave propagation speed can be obtained.
  • a layer of piezoelectric film 414 is grown on the upper surfaces of the first and second interdigital electrodes 4131 and 4132 in the c-axis direction using LPCVD.
  • the piezoelectric film 414 is doped with a metal element.
  • the doped metal elements include scandium, zirconium, calcium-titanium, magnesium-titanium, calcium-zirconium and the like. In this way, the effective coupling coefficient of the piezoelectric film 414 can be increased, and the effective coupling coefficient of the piezoelectric film 414 is proportional to the bandwidth of the LWR resonator, so that the bandwidth of the LWR resonator can be increased.
  • a second metal layer is grown on the top surface of the piezoelectric film 414, and the second metal layer is etched to form a third interdigitated electrode 4151 and a fourth interdigitated electrode 4152, the third interdigitated electrode 4151 and the fourth
  • the orthographic projection of the interdigitated electrode 4152 coincides with the first interdigitated electrode 4131 and the second interdigitated electrode 4132, respectively.
  • the material of the second metal layer includes aluminum, molybdenum, palladium, titanium and other metal materials, and the thickness of the second metal layer is 200-500 nm.
  • the thickness of the second silicon dioxide layer 416 is 1000A-3000A.
  • the material of the piezoelectric film 414 is aluminum nitride
  • the material of the second metal layer is molybdenum or palladium. Since molybdenum or palladium has a good crystalline compatibility with the c-axis direction of the aluminum nitride film, therefore, better crystal quality and grain size can be obtained in this way.
  • a third silicon dioxide layer 416 is grown on the upper surfaces of the third interdigitated electrode 4151, the fourth interdigitated electrode 4152, and the piezoelectric film 414 to form the device structure 420 shown in FIG. 4d.
  • step S240 referring to FIG. 4f, the upper surface of the device structure 310 shown in FIG. 3a and the upper surface of the device structure 420 shown in FIG. 4e are bonded to form the device structure 430 shown in FIG. 4f.
  • the upper surface of the device structure 300 shown in FIG. 3a includes the first silicon dioxide layer 312, SiO 2 is formed between the device structure 300 shown in FIG. 3a and the device structure 420 shown in FIG. 4e. -SiO 2 bonding; when the upper surface of the device structure 300 shown in FIG. 3a does not include the first silicon dioxide layer 312, Si is formed between the device structure 300 shown in FIG. 3a and the device structure 420 shown in FIG. 4e -SiO 2 bonding.
  • step S250 referring first to FIG. 4g, on the basis of the device structure 430 shown in FIG. 4f, the second silicon substrate 411 is removed by a CMP process to expose the insulating layer 412.
  • the first contact hole and the second contact hole respectively communicating with the first interdigitated electrode 4131 and the second interdigitated electrode 4132 are etched on the upper surface of the insulating layer 412, and then lift-off technology is used to A first pad 4161 and a second pad 4162 corresponding to the first interdigitated electrode 4131 and the second interdigitated electrode 4132 are grown in the first contact hole and the second contact hole, respectively.
  • the material of the first pad 4161 and the second pad 4162 are the same, and may be gold or titanium-tungsten alloy.
  • the thickness of the first pad 4161 and the second pad 4162 are 2000A-3000A.
  • the first pad 4161 and the second pad 4162 facilitate subsequent wire bonding, such as package testing or probe testing.
  • the third interdigitated electrode 4151 and the fourth interdigitated electrode 4152 are floating, that is, no pad is drawn out, and no potential needs to be connected subsequently.
  • the preparation method shown in FIG. 2 further includes the step of preparing the air interface. Specifically, referring to FIG. 4i, a trench is etched on the surface of the insulating layer 412 using a photolithography process to communicate with the cavity, thereby forming an air interface to form an acoustic isolation band, and thus the LWR400 shown in FIG. 4i is obtained.
  • the trench includes a first channel 4171 and a second channel 4172, and the first channel 4171 and the second channel 4172 continue to surround the first interdigitated electrode 4131 and the second interdigitated electrode 4132 at predetermined intervals That is, the first channel 4171 and the second channel 4172 form a surrounding ring surrounding the first interdigital electrode 4131 and the second interdigital electrode 4132, and there is a gap between the first channel 4171 and the second channel 4172.
  • the interval between the first channel 4171 and the second channel 4172 can be used to provide space for the metal connection line between the first and second interdigitated electrodes 4131 and 4132 and the pad.
  • the groove forms an air reflection interface, thereby limiting the sound wave to the piezoelectric film 414 and the first interdigital electrode 4131.
  • the groove Within the lateral resonance piezoelectric stack formed by the second interdigitated electrode 4132.
  • the LWR in this embodiment is essentially an IDT-floating type LWR, that is, the third interdigitated electrode 4151 and the fourth interdigitated electrode 4152 in the second metal layer are not Need to connect any potential, they are just to get a higher coupling coefficient.
  • IDT-open electrode-type LWR which differs from the IDT-floating type LWR shown in FIG.
  • the third interdigitated electrode 4151 and the fourth interdigitated electrode 4152 in this case, the step of preparing the second metal layer and etching to form the third interdigitated electrode 4151 and the fourth interdigitated electrode 4152 is omitted; or The preparation of both upper and lower electrodes is an interdigital electrode (IDT-IDT) type LWR. In this case, a step of further preparing pads for the third interdigital electrode 4151 and the fourth interdigital electrode 4152 is required.
  • an air isolation band is formed around the resonant piezoelectric stack (including the lower surface or surroundings) by bonding, as compared with etching in the prior art
  • the device structure is more stable.
  • a sacrificial layer material such as phosphorous silicate glass

Abstract

一种体声波谐振器及其制备方法，制备方法包括：提供第一硅片，在第一硅片上制备顶部开口的腔体；提供第二硅片，在第二硅片上表面制备绝缘层，在绝缘层上表面制备谐振压电堆，谐振压电堆包括压电薄膜和分别与压电薄膜接触并且彼此独立的第一电极和第二电极；在谐振压电堆的上表面制备第一二氧化硅层，谐振压电堆的上表面包括压电薄膜的表面、第一电极的表面、第二电极的表面中的一个或多个；将腔体的开口所在表面和第一二氧化硅层的上表面键合；制备第一电极和第二电极的引出焊盘。

Description

一种体声波谐振器及其制备方法 技术领域
本发明涉及微机电系统(Micro-Electro-Mechanical System，MEMS)器件技术领域，具体涉及一种体声波谐振器及其制备方法。
背景技术
为了满足无线通信技术中对射频信号的质量的要求，体声波谐振器一直是近几年的研究热点，其中，薄膜体声波谐振器(Film，FBAR)及其衍生的兰姆波体声波谐振器(Lamb wave resonator，LWR)，凭借体积小、插入损耗低、带外抑制好、功率容量高、易集成等优点成为最新一代的体声波谐振器。
然而，对于现有的体声波谐振器而言，为了在谐振压电堆下方形成声波隔离带，通常需要在谐振压电堆下方制备一个大的空腔，该空腔的形成导致器件结构稳定性差。以FBAR为例，图1所示为现有技术中的FBAR的结构示意图。如图1所示，该FBAR100包括从下到上依次叠置的硅衬底101、支撑层103、第一电极104、压电薄膜105和第二电极106，其中硅衬底101包括反面刻蚀空腔102，该反面刻蚀空腔102是对形成硅衬底101的硅片进行反面刻蚀得到的，从而形成声波的隔离带，以将声波限制在由第一电极104、压电薄膜105和第二电极106构成的谐振压电堆中，从而有效防止声漏。然而，这种结构的FBAR，为了形成反面刻蚀空腔102，需要大面积刻蚀掉硅片，导致器件结构稳定性差。
发明内容
有鉴于此，本发明实施例致力于提供一种体声波谐振器及其制备方法，以解决现有技术中体声波谐振器稳定性差的问题。
本发明第一方面提供了一种体声波谐振器的制备方法，包括：提供第一硅片，在第一硅片上制备顶部开口的腔体；提供第二硅片，在第二硅片上表面制备绝缘层，在绝缘层上表面制备谐振压电堆，谐振压电堆包括压电薄膜和分别与压电薄膜接触并且彼此独立的第一电极和第二电极；在谐振压电堆的上表面制备第一二氧化硅层，谐振压电堆的上表面包括压电薄膜的表面、第一电极的表面、第二电极的表面中的一个或多个；将腔体的开口所在表面和第一二氧化硅层的上表面键合；制备第一电极和第二电极的引出焊盘。
在一个实施例中，在绝缘层上表面制备谐振压电堆，谐振压电堆包括压电薄膜和分别与压电薄膜接触并且彼此独立的第一电极和第二电极包括：在绝缘层上表面生长第一金属层；在第一金属层上表面生长压电薄膜；在压电薄膜上表面生长第二金属层；其中，第一 金属层形成第一电极，第二金属层形成第二电极。
在一个实施例中，压电薄膜掺杂有金属元素。
在一个实施例中，在绝缘层上表面生长第一金属层之后还包括：对第一金属层进行刻蚀以形成第一叉指和第二叉指，第一叉指包括至少一个第一手指，第二叉指包括至少一个第二手指，至少一个第一手指和至少一个第二手指交替间隔排布；在压电薄膜上表面生长第二金属层之后还包括：对第二金属层进行刻蚀形成第三叉指和第四叉指，第三叉指和第四叉指的正投影分别与第一叉指和第二叉指重合；其中，第一叉指形成第一电极，第二叉指形成第二电极。
在一个实施例中，在绝缘层上表面制备谐振压电堆，谐振压电堆包括压电薄膜和分别与压电薄膜接触并且彼此独立的第一电极和第二电极包括：在绝缘层上表面生长第一金属层；对第一金属层进行刻蚀形成第一叉指电极和第二叉指电极，第一叉指电极包括至少一个第一叉指，第二叉指电极包括至少一个第二叉指，至少一个第一叉指和至少一个第二叉指交替间隔排布；在绝缘层上表面、第一叉指电极上表面和第二叉指电极上表面生长压电薄膜；其中，第一叉指电极形成第一电极，第二叉指电极形成第二电极。
在一个实施例中，在将腔体的开口所在表面和第一二氧化硅层的上表面键合之后还包括：刻蚀掉第二硅片露出绝缘层；在第一叉指电极和第二叉指电极的外围，从绝缘层表面开始向下刻蚀沟槽至连通腔体。
在一个实施例中，沟槽包括第一沟道和第二沟道，第一沟道和第二沟道按照预定间隔接续环绕第一叉指电极和第二叉指电极。
在一个实施例中，提供第一硅片，在第一硅片上制备顶部开口的腔体包括：提供第一硅片；在第一硅片上表面生长第二二氧化硅层；以第二二氧化硅层作掩膜，在第一硅片中刻蚀出腔体。
在一个实施例中，提供第一硅片，在第一硅片上制备顶部开口的腔体包括：提供第一硅片；以光刻胶作掩膜，在第一硅片中刻蚀出腔体。
在一个实施例中，第一电极和/或第二电极在竖直方向上的正投影为不规则多边形。
在一个实施例中，腔体的深度为3～100μm。
在一个实施例中，绝缘层和压电薄膜的材料相同。
本发明第二方面提供了一种体声波谐振器，其特征在于，包括：硅衬底，包括凹槽；谐振压电堆，位于硅衬底上，覆盖凹槽以形成空腔，谐振压电堆包括压电薄膜和分别与压电薄膜接触并且彼此独立的第一电极和第二电极；引出焊盘，包括分别与第一电极和第二电极连接的第一焊盘和第二焊盘。
在一个实施例中，进一步包括沟槽，沟槽贯穿谐振压电堆所在的硅衬底，以将空腔与大气连通。
在一个实施例中，沟槽包括第一沟道和第二沟道，第一沟道和第二沟道按照预定间隔接续环绕第一电极和第二电极。
在一个实施例中，谐振压电堆包括依次叠置在硅衬底上的第二金属层、压电薄膜和第一金属层；第二金属层包括彼此独立的第一子金属层和第二子金属层，第一子金属层形成第一电极，第二子金属层和第一金属层电连接，以形成第二电极。
在一个实施例中，第一金属层和第一子金属层在硅衬底上的正投影覆盖空腔。
在一个实施例中，第一电极和第二电极在硅衬底上的正投影不规则。
在一个实施例中，谐振压电堆包括依次叠置在硅衬底上的压电薄膜和第一金属层，第一金属层包括第一叉指电极和第二叉指电极，第一叉指电极形成第一电极，第二叉指电极形成第二电极。
在一个实施例中，谐振压电堆进一步包括位于压电薄膜和硅衬底之间的第二金属层，第二金属层包括第三叉指电极和第四叉指电极；第一叉指电极在硅衬底上的正投影和第三叉指电极重合，第二叉指电极在硅衬底上的正投影和第四叉指电极重合。
在一个实施例中，还包括位于硅衬底和谐振压电堆之间的二氧化硅层。
根据本发明提供的体声波谐振器及其制备方法，采用键合的方式在谐振压电堆周围下表面形成空腔，相比于现有技术中需要刻蚀掉大部分硅衬底来形成空腔的器件而言，结构更稳定。
附图说明
图1所示为现有技术中的FBAR的结构示意图。
图2所示为本发明一实施例提供的体声波谐振器的制备方法流程图。
图3a-图3i为本发明一实施例提供的根据图2所示制备方法制备薄膜体声波谐振器的过程中得到的器件结构示意图。
图4a-图4i为本发明一实施例提供的根据图2所示制备方法制备兰姆波体声波谐振器的过程中得到的器件结构示意图。
具体实施方式
为使本申请的目的、技术手段和优点更加清楚明白，以下结合附图对本申请作进一步详细说明。
图2所示为本发明一实施例提供的体声波谐振器的制备方法流程图。如图2所示，该 制备方法200包括：
步骤S210，提供第一硅片，在第一硅片上制备顶部开口的腔体。
步骤S220，提供第二硅片，在第二硅片上表面制备绝缘层，在绝缘层上表面制备谐振压电堆。
谐振压电堆是体声波谐振器的核心部件，包括压电薄膜和分别与压电薄膜接触并且彼此独立的第一电极和第二电极。其工作原理是，将第一电极和第二电极作为正、负极，当第一电极和第二电极接通交流电压后，利用压电薄膜的逆压电效应产生机械震动，该机械震动以声波的形式在第一电极和第二电极之间进行传播形成驻波，当该驻波的频率与交流电压频率相等时，即产生谐振。
步骤S230，在谐振压电堆的上表面制备第一二氧化硅层，谐振压电堆的上表面包括压电薄膜的表面、第一电极的表面、第二电极的表面中的一个或多个。
步骤S240，将腔体的开口所在表面和第一二氧化硅层的上表面键合。
步骤S250，制备第一电极和第二电极的引出焊盘。
下面结合附图以具体实施例对图2所示的体声波谐振器的制备方法进行详细说明。
图3a-图3i为本发明一实施例提供的根据图2所示制备方法制备薄膜体声波谐振器的过程中得到的器件结构示意图。薄膜体声波谐振器(Film Bulk Acoustic Resonator，FBAR)中的谐振压电堆是上、下两个电极，中间夹着一个压电薄膜的三明治结构，其工作原理是通过压电薄膜的逆压电效应产生的声波在压电薄膜的上、下表面内纵向来回传输，从而形成纵向谐振。
根据步骤S210，参阅图3a，提供第一硅衬底311；采用液相化学汽相淀积(liquid phase chemical vapor deposition，LPCVD)工艺在第一硅衬底311上表面生长第二二氧化硅层312，该第二二氧化硅层312的厚度为500～6000A；以第二二氧化硅层312为掩膜，采用光刻工艺刻蚀出腔体313，形成图3a所示的器件结构310，该腔体313的深度可以是3～100μm。
在一个实施例中，步骤S210还可以执行为，采用光刻胶作为掩膜，直接在第一硅片311上表面刻蚀出腔体313，也就是说，第一硅衬底311的上表面没有第二二氧化硅层312。
上面两种制备过程的区别在于，前者所形成的器件结构中腔体的开口所在表面的材料是二氧化硅，后者所形成的器件结构中腔体的开口所在表面的材料是硅，而该腔体的开口所在表面后续作为键合的一方，从而决定了后续键合是SiO 2-SiO 2键合，还是Si-SiO 2键合。
根据步骤S220，首先参阅图3b，提供第二硅片作为第二硅衬底321，在第二硅衬底321上表面生长绝缘层322，在绝缘层322上表面生长第一金属层323，采用LPCVD工艺 在第一金属层323上表面沿c轴方向生长一层压电薄膜324。
绝缘层322的材料包括二氧化硅、氮化硅或者氮化铝，绝缘层322的厚度为300～500nm。第一金属层323的材料包括铝、钼、钯、钛等金属材料，第一金属层323的厚度为200～500nm。压电薄膜324的材料包括氮化铝、氧化锌、钽酸锂等，压电薄膜324的厚度与FBAR谐振器的频率呈负相关，因此可以根据实际需要的谐振频率合理确定压电薄膜324的厚度，例如，压电薄膜324的厚度为0.5～2um。
在一个实施例中，绝缘层322的材料为氮化铝，第一金属层323的材料为钼或钯。由于钼或钯与氮化铝薄膜的c轴方向有很好的结晶兼容性，因此，这样可以获得更好的结晶质量和晶粒尺寸。
在一个实施例中，向压电薄膜324内掺杂金属元素。该掺杂的金属元素包括钪、锆、钙-钛、镁-钛、钙-锆等。这样，可以提高压电薄膜324的有效耦合系数，而压电薄膜324的有效耦合系数和谐振器的带宽成正比，从而可以提高谐振器的带宽。
然后，参阅图3c，在压电薄膜324的上表面生长第二金属层325，该第二金属层325包括彼此间隔的第一子金属层3251和第二子金属层3252，即第一子金属层3251和第二子金属层3252之间包括一间隙H。
第二金属层325中的第一子金属层3251和第二子金属层3252的材料可以相同也可以不同。当第一子金属层3251和第二子金属层3252的材料相同时，第一子金属层3251和第二子金属层3252的形成过程包括：在压电薄膜324上表面生长一层第二金属层325，然后刻蚀形成彼此独立、互不连通的第一子金属层3251和第二子金属层3252。当第一子金属层3251和第二子金属层3252的材料不同时，第一子金属层3251和第二子金属层3252的形成过程包括：采用掩膜板，在压电薄膜324上表面的不同区域分别生长第一子金属层3251和第二子金属层3252。
根据步骤S330，继续参阅图3c，在第二金属层325的上表面和压电薄膜324的上表面生长第三二氧化硅层326，形成如图3c所示的器件结构320。
在一个实施例中，第三二氧化硅层326包括平坦上表面。这样，有利于后续膜层的制备。该第三二氧化硅层326的生成过程可以采用LPVCD工艺，第三二氧化硅层326的厚度例如可以是1000A～3000A。
根据步骤S340，参阅图3d，将图3a所示的器件结构310的上表面和图3c所示的器件结构320的上表面键合，形成如图3d所示的器件结构330。
这里需要说明的是，当图3a所示的器件结构310的上表面包括第二二氧化硅层302时，图3a所示的器件结构310和图3c所示的器件结构320之间形成SiO 2-SiO 2键合；当图3a所 示的器件结构310的上表面不包括第二二氧化硅层302时，图3a所示的器件结构310和图3c所示的器件结构320之间形成Si-SiO 2键合。
根据步骤S350，首先参阅图3e，在图3d所示器件结构330的基础上，采用化学机械抛光(Chemical&Mechanical Polishing，CMP)工艺去掉第二硅衬底321，露出绝缘层322。
然后参阅图3f，采用光刻技术刻蚀掉部分绝缘层322和该部分绝缘层322下方的第一金属层323，至露出压电薄膜324。
其次参阅图3g，光刻去掉第一金属层323边缘区域的绝缘层322，得到第一金属层323的一个裸露表面A。
在一实施例中，绝缘层322和压电薄膜324的材料均为氮化铝。这种情况下，绝缘层322和压电薄膜604的材料相同，因此当对第一金属层323边缘区域的绝缘层322进行光刻时，靠近第一金属层323的边缘区域的压电薄膜324也会被刻蚀掉一部分，从而在压电薄膜324中形成一个凹槽3241。
接着参阅图3h，在压电薄膜324上表面刻蚀分别连通第一子金属层3251和第二子金属层3252的第一接触孔3271和第二接触孔3272。
在一个实施例中，当压电薄膜324包括凹槽3241时，在凹槽3241的基础上进一步刻蚀形成第一接触孔3271，即采用刻蚀工艺将凹槽3241深度加深至露出第一子金属层3251，以形成第一接触孔3271。
再次参阅图3i，采用剥离工艺(lift-off technology)，在第一接触孔3271和第二接触孔3272分别生长第一焊盘3281和第二焊盘3282，其中第一金属层323的裸露表面A和第一子金属层3251电连接以形成与第一焊盘3281连接的第一电极，第二子金属层3252形成与第二焊盘3282连接的第二电极。
例如，如图3i所示，第一电极引出至第一焊盘3281，第二电极引出至第二焊盘3282。第一焊盘3281和第二焊盘3282的材料相同，可以是金或者钛钨合金。第一焊盘3281和第二焊盘3282厚度为2000A～3000A。该第一焊盘3281和第二焊盘3282便于后续的引线键合，例如封装测试或探针测试。
在一个实施例中，第一电极和/或第二电极在竖直方向的正投影为不规则多边形，这里提到的不规则多边形是与正多边形相反的概念。例如，形成第一电极的第一金属层323和第一子金属层3215，以及形成第二电极的第二子金属层3252在竖直方向的正投影均为不规则五边形。这样，可以有效减小除了形成主谐振的声波之外的其它声波所形成的寄生模态。
第一电极和/或第二电极在竖直方向的正投影均为不规则图形。根据本实施例提供的 FBAR，在第一电极和第二电极的交叠区域，即第一金属层323和第二子金属层3252正相对的区域下方形成一声腔，即腔体313，从而在第二电极(具体为第二二氧化硅层326)的下表面形成空气交界面。而由于空气的声阻抗近似为零，可以作为良好的声波限制边界，这样第二电极的下表面的空气交界面和第一电极(具体为绝缘层322)的上表面的空气交界面相互配合，将FBAR产生的声波限制在由第一电极、第二电极和压电薄膜324组成的压电震荡堆之内。
图4a-图4i为本发明一实施例提供的根据图2所示制备方法制备兰姆波体声波谐振器的过程中得到的器件结构示意图。兰姆波体声波谐振器(Lamb wave resonator，LWR)和FBAR相比在原理上的区别在于，在LWR中声波是在和压电薄膜平行的表面中传播，从而形成横向谐振。
根据步骤S210制备得到如图3a所示的器件结构310。该过程和制备FBAR中的器件结构310的过程相同，这里不予赘述。
根据步骤S220，首先参阅图4a，提供第二晶圆作为第二硅衬底411，在第二硅衬底411上表面沉积绝缘层412，在绝缘层412上表面生长第一金属层，对第一金属层进行刻蚀形成第一叉指电极4131和第二叉指电极4132，形成的器件结构410如图4a所示，该器件结构410的俯视图如图4b所示。
第一叉指电极4131包括至少一个第一叉指，第二叉指电极4132包括至少一个第二叉指，该至少一个第一叉指和至少一个第二叉指交替间隔排布。相邻两个叉指之间的间距L决定了兰姆波体声波谐振器的频率，具体而言，相邻两个叉指之间的间距L和兰姆波体声波谐振器的频率呈负相关，因此可以根据所需要的频率合理设置相邻两叉指之间的间距L。第一叉指和第二叉指的数量可以是任意多个，例如可以是图4a和图4b所示的第一叉指电极4131包括2个叉指，第二叉指电极4132也包括1个叉指。
第一金属层的材料包括铝、钼、钯、钛等金属材料，第一金属层的厚度为200～500nm。在一个实施例中，绝缘层412的材料为氮化铝，第一金属层的材料为钼或钯。由于钼或钯与氮化铝薄膜的c轴方向有很好的结晶兼容性，因此，这样可以获得更好的结晶质量和晶粒尺寸。
然后参阅图4c，在第一叉指电极4131、第二叉指电极4132和绝缘层412表面生长一层压电薄膜414。优选地，该压电薄膜414包括平坦上表面，以便于后续各膜层的制备。
压电薄膜414的材料包括氮化铝、氧化锌、钽酸锂等。声波波长和压电薄膜414的厚度的比值小于0.4，这样可以获得较高的声波传播速度。
在一个实施例中，采用LPCVD在第一叉指电极4131和第二叉指电极4132的上表面 沿c轴方向生长一层压电薄膜414。
在一个实施例中，向压电薄膜414内掺杂金属元素。该掺杂的金属元素包括钪、锆、钙-钛、镁-钛、钙-锆等。这样，可以提高压电薄膜414的有效耦合系数，而压电薄膜414的有效耦合系数和LWR谐振器的带宽成正比，从而可以提高LWR谐振器的带宽。
其次参阅图4d，在压电薄膜414上表面生长第二金属层，对第二金属层进行刻蚀形成第三叉指电极4151和第四叉指电极4152，第三叉指电极4151和第四叉指电极4152的正投影分别和第一叉指电极4131和第二叉指电极4132重合。
第二金属层的材料包括铝、钼、钯、钛等金属材料，第二金属层的厚度为200～500nm。第二二氧化硅层416的厚度为1000A～3000A。
在一个实施例中，压电薄膜414的材料为氮化铝，第二金属层的材料为钼或钯。由于钼或钯与氮化铝薄膜的c轴方向有很好的结晶兼容性，因此，这样可以获得更好的结晶质量和晶粒尺寸。
根据步骤S230，参阅图4e，在第三叉指电极4151、第四叉指电极4152和压电薄膜414的上表面生长第三二氧化硅层416，形成如图4d所示的器件结构420。
根据步骤S240，参阅图4f，将图3a所示的器件结构310的上表面和图4e所示的器件结构420的上表面键合，形成如图4f所示的器件结构430。
这里需要说明的是，当图3a所示的器件结构300的上表面包括第一二氧化硅层312时，图3a所示的器件结构300和图4e所示的器件结构420之间形成SiO 2-SiO 2键合；当图3a所示的器件结构300的上表面不包括第一二氧化硅层312时，图3a所示的器件结构300和图4e所示的器件结构420之间形成Si-SiO 2键合。
根据步骤S250，首先参阅图4g，在图4f所示器件结构430的基础上，采用CMP工艺去掉第二硅衬底411，露出绝缘层412。
接着参阅图4h，在绝缘层412上表面刻蚀分别连通第一叉指电极4131和第二叉指电极4132的第一接触孔和第二接触孔，然后采用剥离工艺(lift-off technology)在第一接触孔和第二接触孔中生长分别与第一叉指电极4131和第二叉指电极4132对应的第一焊盘4161和第二焊盘4162。
第一焊盘4161和第二焊盘4162的材料相同，可以是金或者钛钨合金。第一焊盘4161和第二焊盘4162厚度为2000A～3000A。该第一焊盘4161和第二焊盘4162便于后续的引线键合，例如封装测试或探针测试。
需要说明的是，第三叉指电极4151和第四叉指电极4152是悬空的，即没有引出焊盘，后续不需要接任何电位。
在制备LWR的过程中，图2所示制备方法还包括制备空气界面的步骤。具体来说，参阅图4i，采用光刻工艺在绝缘层412表面刻蚀沟槽，使之与腔体互通，从而形成空气界面以形成声波隔离带，至此得到图4i所示的LWR400。
在本实施例中，沟槽包括第一沟道4171和第二沟道4172，第一沟道4171和第二沟道4172按照预定间隔接续环绕第一叉指电极4131和第二叉指电极4132，即第一沟道4171和第二沟道4172形成环绕第一叉指电极4131和第二叉指电极4132的包围圈，并且第一沟道4171和第二沟道4172之间具有间隔。该第一沟道4171和第二沟道4172之间的间隔可以用于为第一叉指电极4131和第二叉指电极4132与焊盘之间的金属连接线提供空间。
根据本实施例提供的LWR，通过设置包围第一叉指4131和第二叉指4132的沟槽，该沟槽形成空气反射界面，从而将声波限制在由压电薄膜414、第一叉指电极4131、第二叉指电极4132构成的横向谐振压电堆之内。
本实施例中的LWR实质是一种顶叉指电极-底电极不接电位(IDT-floating)型的LWR，即第二金属层中的第三叉指电极4151和第四叉指电极4152不需要接任何电位，它们只是为了获得较高的耦合系数。本领域技术人员应当理解，采用同样的制备方法还可以制备顶叉指电极-无电极(IDT-open)型LWR，和图4i所示的IDT-floating型的LWR的区别仅在于，芯片中没有第三叉指电极4151和第四叉指电极4152，这种情况下相当于省略了制备第二金属层并刻蚀形成第三叉指电极4151和第四叉指电极4152的步骤；或者还可以制备上下电极均是叉指电极(IDT-IDT)型LWR，这种情况下则需要进一步制备第三叉指电极4151和第四叉指电极4152的焊盘的步骤。
根据本发明任一实施例提供的体声波谐振器的制备方法，采用键合的方式在谐振压电堆周围(包括下表面或四周)形成空气隔离带，相比于现有技术中采用刻蚀工艺形成的空气隔离带而言，器件结构更稳定。与此同时，相比于现有技术中采用深反应离子刻蚀形成腔体，再在腔体中填充牺牲层材料，例如磷硅玻璃，最后再进行释放以露出腔体的制备方法而言，制备工艺难度小，设备成本低廉。相比于现有技术中具有布拉格反射层的体声波谐振器而言，品质因素更高。
应当理解，本申请实施例描述中所用到的限定词“第一”、“第二”、“第三”和“第四”仅用于更清楚的阐述技术方案，并不能用于限制本申请的保护范围。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换等，均应包含在本申请的保护范围之内。

Claims (21)

  1. 一种体声波谐振器的制备方法，其特征在于，包括：
    提供第一硅片，在所述第一硅片上制备顶部开口的腔体；
    提供第二硅片，在所述第二硅片上表面制备绝缘层，在所述绝缘层上表面制备谐振压电堆，所述谐振压电堆包括压电薄膜和分别与所述压电薄膜接触并且彼此独立的第一电极和第二电极；
    在所述谐振压电堆的上表面制备第一二氧化硅层，所述谐振压电堆的上表面包括所述压电薄膜的表面、所述第一电极的表面、所述第二电极的表面中的一个或多个；
    将所述腔体的开口所在表面和所述第一二氧化硅层的上表面键合；
    制备所述第一电极和所述第二电极的引出焊盘。
  2. 如权利要求1所述的体声波谐振器的制备方法，其特征在于，在所述绝缘层上表面制备谐振压电堆，所述谐振压电堆包括压电薄膜和分别与所述压电薄膜接触并且彼此独立的第一电极和第二电极包括：
    在所述绝缘层上表面生长第一金属层；
    在所述第一金属层上表面生长所述压电薄膜；
    在所述压电薄膜上表面生长第二金属层；
    其中，所述第一金属层形成所述第一电极，所述第二金属层形成所述第二电极。
  3. 如权利要求2所述的体声波谐振器的制备方法，其特征在于，所述压电薄膜掺杂有金属元素。
  4. 如权利要求2所述的体声波谐振器的制备方法，其特征在于，在所述绝缘层上表面生长第一金属层之后还包括：
    对所述第一金属层进行刻蚀以形成第一叉指和第二叉指，所述第一叉指包括至少一个第一手指，所述第二叉指包括至少一个第二手指，所述至少一个第一手指和所述至少一个第二手指交替间隔排布；
    在所述压电薄膜上表面生长第二金属层之后还包括：
    对所述第二金属层进行刻蚀形成第三叉指和第四叉指，所述第三叉指和所述第四叉指的正投影分别与所述第一叉指和所述第二叉指重合；
    其中，所述第一叉指形成所述第一电极，所述第二叉指形成所述第二电极。
  5. 如权利要求1所述的体声波谐振器的制备方法，其特征在于，在所述绝缘层上表面制备谐振压电堆，所述谐振压电堆包括压电薄膜和分别与所述压电薄膜接触并且彼此独立的第一电极和第二电极包括：
    在所述绝缘层上表面生长第一金属层；
    对所述第一金属层进行刻蚀形成第一叉指电极和第二叉指电极，所述第一叉指电极包括至少一个第一叉指，所述第二叉指电极包括至少一个第二叉指，所述至少一个第一叉指和所述至少一个第二叉指交替间隔排布；
    在所述绝缘层上表面、所述第一叉指电极上表面和所述第二叉指电极上表面生长所述压电薄膜；
    其中，所述第一叉指电极形成所述第一电极，所述第二叉指电极形成所述第二电极。
  6. 如权利要求4或5所述的体声波谐振器的制备方法，其特征在于，在将所述腔体的开口所在表面和所述第一二氧化硅层的上表面键合之后还包括：
    刻蚀掉所述第二硅片露出所述绝缘层；
    在所述第一叉指电极和所述第二叉指电极的外围，从所述绝缘层表面开始向下刻蚀沟槽至连通所述腔体。
  7. 如权利要求6所述的体声波谐振器的制备方法，其特征在于，所述沟槽包括第一沟道和第二沟道，所述第一沟道和所述第二沟道按照预定间隔接续环绕所述第一叉指电极和所述第二叉指电极。
  8. 如权利要求1所述的体声波谐振器的制备方法，其特征在于，所述提供第一硅片，在所述第一硅片上制备顶部开口的腔体包括：
    提供所述第一硅片；
    在所述第一硅片上表面生长第二二氧化硅层；
    以所述第二二氧化硅层作掩膜，在所述第一硅片中刻蚀出所述腔体。
  9. 如权利要求1所述的体声波谐振器的制备方法，其特征在于，所述提供第一硅片，在所述第一硅片上制备顶部开口的腔体包括：
    提供所述第一硅片；
    以光刻胶作掩膜，在所述第一硅片中刻蚀出所述腔体。
  10. 如权利要求1所述的体声波谐振器的制备方法，其特征在于，所述第一电极和/或所述第二电极在竖直方向上的正投影为不规则多边形。
  11. 如权利要求1所述的体声波谐振器的制备方法，其特征在于，所述腔体的深度为3～100μm。
  12. 如权利要求1所述的体声波谐振器的制备方法，其特征在于，所述绝缘层和所述压电薄膜的材料相同。
  13. 一种体声波谐振器，其特征在于，包括：
    硅衬底，包括凹槽；
    谐振压电堆，位于所述硅衬底上，覆盖所述凹槽以形成空腔，所述谐振压电堆包括压电薄膜和分别与所述压电薄膜接触并且彼此独立的第一电极和第二电极；
    引出焊盘，包括分别与所述第一电极和所述第二电极连接的第一焊盘和第二焊盘。
  14. 根据权利要求13所述的体声波谐振器，其特征在于，进一步包括沟槽，所述沟槽贯穿所述谐振压电堆所在的硅衬底，以将所述空腔与大气连通。
  15. 根据权利要求14所述的体声波谐振器，其特征在于，所述沟槽包括第一沟道和第二沟道，所述第一沟道和所述第二沟道按照预定间隔接续环绕所述第一电极和所述第二电极。
  16. 根据权利要求13所述的体声波谐振器，其特征在于，所述谐振压电堆包括依次叠置在所述硅衬底上的第二金属层、所述压电薄膜和第一金属层；所述第二金属层包括彼此独立的第一子金属层和第二子金属层，所述第一子金属层形成所述第一电极，所述第二子金属层和所述第一金属层电连接，以形成所述第二电极。
  17. 根据权利要求16所述的体声波谐振器，其特征在于，所述第一金属层和所述第一子金属层在所述硅衬底上的正投影覆盖所述空腔。
  18. 根据权利要求16所述的体声波谐振器，其特征在于，所述第一电极和所述第二电极在所述硅衬底上的正投影不规则。
  19. 根据权利要求13所述的体声波谐振器，其特征在于，所述谐振压电堆包括依次叠置在所述硅衬底上的所述压电薄膜和第一金属层，所述第一金属层包括第一叉指电极和第二叉指电极，所述第一叉指电极形成所述第一电极，所述第二叉指电极形成所述第二电极。
  20. 根据权利要求19所述的体声波谐振器，其特征在于，所述谐振压电堆进一步包括位于所述压电薄膜和所述硅衬底之间的第二金属层，所述第二金属层包括第三叉指电极和第四叉指电极；所述第一叉指电极在所述硅衬底上的正投影和所述第三叉指电极重合，所述第二叉指电极在所述硅衬底上的正投影和所述第四叉指电极重合。
  21. 根据权利要求13所述的体声波谐振器，其特征在于，还包括位于所述硅衬底和所述谐振压电堆之间的二氧化硅层。
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