WO2020118931A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2020118931A1
WO2020118931A1 PCT/CN2019/077881 CN2019077881W WO2020118931A1 WO 2020118931 A1 WO2020118931 A1 WO 2020118931A1 CN 2019077881 W CN2019077881 W CN 2019077881W WO 2020118931 A1 WO2020118931 A1 WO 2020118931A1
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WO
WIPO (PCT)
Prior art keywords
array substrate
area
curved channel
display area
wiring
Prior art date
Application number
PCT/CN2019/077881
Other languages
English (en)
French (fr)
Inventor
冯校亮
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/467,044 priority Critical patent/US11322525B2/en
Publication of WO2020118931A1 publication Critical patent/WO2020118931A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • the full screen increases the consumer's visual experience by increasing the screen ratio and reducing the invalid area.
  • the so-called full screen of the traditional technology belongs to the narrow bezel technology category, and cannot be called a full screen in the true sense.
  • One of the main limiting factors from the narrow bezel to the full screen is that the edge routing of the display needs to occupy the display surface of the display area.
  • An object of the present application is to provide an array substrate and a display panel.
  • the area of the display area in the display surface of the array substrate and the display panel is increased.
  • An array substrate, the array substrate includes:
  • a flexible substrate having a first surface and a second surface opposite to the first surface, the first surface of the flexible substrate having a display area and a non-display area, the non-display area being located at the The periphery of the display area;
  • the peripheral wiring is disposed in the wiring area of the non-display area
  • a curved channel is located between the wiring area and the display area, and folded along the curved channel so that the peripheral wiring is located on the side where the second surface of the flexible substrate is located.
  • the array substrate further includes a conversion circuit, and the conversion circuit is disposed in a circuit conversion region, and the circuit conversion region is located between the curved channel and the display region.
  • the conversion circuit includes a first conductive layer, a first insulating layer, and a second conductive layer that are sequentially disposed on the first surface of the flexible substrate.
  • the array substrate further includes a gate driving circuit, the gate driving circuit is disposed in the wiring area, and is folded along the curved channel so that the gate driving circuit is located in the flexible The side where the second surface of the substrate is located.
  • the second conductive layer bridges the gate driving circuit and the first conductive layer through vias on the first insulating layer.
  • the first conductive layer is a scan line extending from the display area to the line conversion area.
  • the width of the line conversion area is 0.08 mm-0.12 mm.
  • the width of the line conversion area is 0.1 mm.
  • the array substrate further includes an organic insulating elastic layer, and the organic insulating elastic layer is disposed in the curved channel.
  • the surface of the organic insulating elastic layer in contact with the peripheral wiring is provided with organic insulating elastic protrusions.
  • the organic insulating elastic protrusions are hemispherical, trapezoidal, stepped or toothed.
  • the array substrate further includes conductive pads, and the conductive pads are disposed on the peripheral traces on both sides of the curved channel.
  • the conductive pad is an organic conductive pad.
  • the width of the conductive pad in the direction perpendicular to the straight line where the peripheral trace is located is 2-10 times the width of the peripheral trace.
  • the array substrate further includes an external control chip, the external control chip is bound in the binding area of the wiring area, and folded along the curved channel so that the external control chip is located in the The side where the second surface of the flexible substrate is located.
  • the curved channel is a cross-shaped channel.
  • a display panel the display panel includes an array substrate, the array substrate includes:
  • a flexible substrate having a first surface and a second surface opposite to the first surface, the first surface of the flexible substrate having a display area and a non-display area, the non-display area being located at the The periphery of the display area;
  • the peripheral wiring is disposed in the wiring area of the non-display area
  • a curved channel is located between the wiring area and the display area, and folded along the curved channel so that the peripheral wiring is located on the side where the second surface of the flexible substrate is located.
  • the array substrate further includes a gate driving circuit, the gate driving circuit is disposed in the wiring area, and folded along the curved channel so that the gate driving circuit is located in the flexible The side where the second surface of the substrate is located.
  • the array substrate further includes an external control chip, the external control chip is bound in the binding area of the wiring area, and folded along the curved channel so that the external control chip is located in the The side where the second surface of the flexible substrate is located.
  • the array substrate further includes an organic insulating elastic layer, and the organic insulating elastic layer is disposed in the curved channel.
  • the present application provides an array substrate and a display panel. By folding along the curved channel, the peripheral wiring is located on the back of the display area to increase the area of the display area in the display surface.
  • FIG. 1 is a schematic diagram of an array substrate before folding according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of the array substrate shown in FIG. 1 after being folded;
  • FIG. 3 is a schematic diagram of the back of the array substrate shown in FIG. 2;
  • FIG. 4 is a first partial enlarged view of the array substrate shown in FIG. 1;
  • FIG. 5 is a cross-sectional view of the array substrate shown in FIG. 4 along the A-A tangent direction;
  • FIG. 6 is a schematic diagram of the section shown in FIG. 5 after being folded along the curved channel;
  • FIG. 7 is a cross-sectional view of the array substrate shown in FIG. 4 along the B-B tangent direction;
  • FIG. 8 is a second partial enlarged view of the array substrate shown in FIG. 1;
  • FIG. 9 is a cross-sectional view of the array substrate shown in FIG. 8 along the C-C tangent direction;
  • FIG. 10 is a cross-sectional view of the array substrate shown in FIG. 8 along the D-D tangent direction.
  • circuit conversion area 170 conductive pad 11 first conductive layer 12 first insulating layer
  • Second conductive layer 13
  • Second conductive layer 14
  • Second insulating layer 15
  • First wire changing pad 16
  • FIG. 1 is an array substrate according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of the array substrate shown in FIG. 1 after being folded
  • FIG. 3 is a schematic diagram of the back of the array substrate shown in FIG.
  • the array substrate shown in Figure 1 includes:
  • the flexible substrate 100 has a first surface 102 and a second surface 104 opposite to the first surface 102.
  • the first surface 102 of the flexible substrate 100 has a display area 102a and a non-display area 102a', where the non-display area 102a' is located The periphery of the display area 102a;
  • Peripheral trace 110 which is disposed in the trace area of the non-display area 102a';
  • the curved channel 120a is located between the wiring area and the display area 102a, and is folded along the curved channel 120a so that the peripheral wiring 110 is located on the side where the second surface 104 of the flexible substrate 100 is located.
  • the above solution increases the area of the display area of the display surface by folding along the curved channel so that the peripheral wiring is located at the back of the display area.
  • the array substrate is a thin film transistor array substrate, and the substrate thereof is a flexible substrate 100 to make the array substrate foldable.
  • the preparation material of the flexible substrate 100 may be polyimide (Polyimide, PI), polyethylene terephthalate (Polyethylene terephthalate) terephthalate, PET) or other flexible materials.
  • the first surface 102 of the flexible substrate 100 has a display area 102a and a non-display area 102a'.
  • the display area 102a is provided with a plurality of data lines 130 and scanning lines 140 intersecting each other perpendicularly.
  • a plurality of thin film transistors (not shown) are provided in the area formed by the 140 cross, the scan line 140 is connected to the gate of the thin film transistor to input scan signals to the thin film transistor, and the data line 130 is connected to the source of the thin film transistor to input data to the thin film transistor signal.
  • Manufacturing the thin film transistor in the display area 102a includes the following steps:
  • An entire second conductive layer is formed on the first surface 102 where the second insulating layer is formed, and the second conductive layer in the display area 102a is patterned to form a source-drain electrode.
  • the source-drain electrode passes through the second insulating layer The hole is connected to the patterned channel layer.
  • the first conductive layer, the first insulating layer, the second conductive layer and the second insulating layer are sequentially formed in the non-display area 102a' Other lines in the non-display area 102a'.
  • the peripheral wiring 110 is disposed in the wiring area of the non-display area 102a', and the peripheral wiring 110 is disposed around the display area 102a.
  • the peripheral wiring includes but is not limited to power voltage (Voltage Drain Drain, VDD) wiring and ground voltage (Voltage Source-Source, VSS wiring, clock (Clock, CLK) wiring, External Clock (XCLK) wiring.
  • VDD Voltage Drain Drain
  • VSS Voltage Source-Source
  • CLK clock
  • XCLK External Clock
  • the VDD trace, the VSS trace, the CLK trace, and the XCLK trace are formed by patterning the second conductive layer in the non-display area 102a', that is, the second conductive layer is the source-drain electrode forming the thin film transistor in the display area 102a Conductive layer.
  • the curved channel 120a is located at the periphery of the display area 102a, which is a zigzag channel.
  • the curved channel may also be other structures, for example, the curved channel is inline and located on at least one side of the array substrate, respectively. Fold along the four vertically intersecting channels forming the cross-shaped channel in sequence so that the peripheral trace 110 disposed in the trace area of the non-display area 102a' is located on the side of the second surface 104 of the flexible substrate 100, that is, on the flexible substrate 100
  • the first surface 102 (the display surface of the array substrate) has only the display area 102a.
  • the array substrate folded along the curved channel 120a is shown in FIG. 2, and the back surface of the array substrate folded along the curved channel 120a is shown in FIG. 3. .
  • the cross-shaped curved channel 120a divides it into 8 areas, including a first trace corner area 1021, a second trace corner area 1022, a third trace corner area 1023, and a fourth trace Corner area 1024, the first main routing area 1025 between the first routing corner area 1021 and the second routing corner area 1022, the third routing corner area 1023 and the fourth routing corner area 1024
  • the fourth main routing area between 1024 is 1028.
  • the array substrate further includes a gate drive circuit (Gate On Array, GOA) 150.
  • the gate drive circuit 150 is disposed in the wiring area and folded along the curved channel 120a so that the gate drive circuit 150 is located on the first side of the flexible substrate 100. The side where the second surface 104 is located.
  • the gate driving circuit 150 is disposed in the third main wiring area 1027 and the fourth main wiring area 1028, and both ends of each scanning line 140 in the display area 102a are respectively connected to the gate driving circuit 150, that is Each scanning line 140 inputs a scanning driving signal through both ends.
  • the gate driving circuit 150 may also be disposed in the third main wiring area 1027 or the fourth main wiring area 1028, that is, each scanning line 140 inputs a driving signal through one end.
  • the gate driving circuit 150 is electrically connected to the peripheral wiring 110.
  • the gate driving circuit 150 and the scanning line 140 of the thin film transistor in the display area 102a are made in the same layer.
  • the array substrate further includes an external control chip (not shown).
  • the external control chip is bound in the binding area 103 of the wiring area, folded along the curved channel 120 a so that the external control chip is located on the flexible substrate 100 The side where the second surface 104 is located.
  • the external control chip includes a data drive control chip for outputting a drive signal to the data line and a chip for inputting a control signal to the peripheral trace 110.
  • the data line 130 and the peripheral trace 110 extend to the binding area 103, and pass through the flexible printed circuit board ( Flexible Printed Circuit, FPC) is electrically connected to an external control chip.
  • the external control chip bound to the binding area 103 is located in the second main wiring area 1026.
  • the array substrate further includes a conversion circuit 160, and the conversion circuit 160 is disposed in the circuit conversion region In 160a, the line switching area 160a is located between the curved channel 120a and the display area 102a.
  • the width of the line conversion area 160a is 0.08 mm-0.12 mm, for example, the width of the line conversion area 160a is 0.1 mm. Even if the conversion circuit 160 is added to the first surface 102a of the flexible substrate 100, the area percentage of the display surface occupied by the display area 102a is still as high as 99%.
  • FIG. 4 is a first partially enlarged view of the array substrate shown in FIG. 1, and FIG. 5 is a cross-sectional view of FIG. 4 along the A-A tangent direction.
  • the array substrate further includes conductive pads 170 that are disposed on the peripheral traces 110 on both sides of the curved channel 120a.
  • the conductive pad 170 is an organic conductive layer; the width d of the conductive pad 170 along the straight line perpendicular to the peripheral trace 110 is greater than the width of the peripheral trace.
  • the width d of the conductive pad 170 along the straight line perpendicular to the peripheral trace 110 is 2-10 times the width of the peripheral traces.
  • the distance between two adjacent peripheral traces 110 also increases correspondingly in the first trace corner area 1021. After entering the first main wiring area 1025, the distance between two adjacent peripheral wirings 110 is adjusted to be small.
  • the conductive pad 170 is formed in the second insulating layer 14 and is located on the peripheral trace 110.
  • the second insulating layer 14 is the second insulating layer in the non-display area 102a'.
  • the thickness of the conductive pad 170 and the second insulating layer 14 The thickness is the same. It can be understood that the conductive pad 170 may also be located on the peripheral trace 110 above the curved channel 120a.
  • the array substrate further includes an organic insulating elastic layer 120, and the organic insulating elastic layer 120 is disposed in the curved channel 120a.
  • the organic insulating elastic layer 120 When folded along the curved channel 120a, the organic insulating elastic layer 120 has elasticity so that it can provide the length required for bending during the bending process.
  • the preparation material of the organic insulating elastic layer 120 is a rubber material, such as EPDM, natural rubber, and the like.
  • the curved channel 120a is formed in the channel of the first insulating layer 12, before forming the source-drain electrode in the thin film transistor in the display area 102a, an organic insulating elastic layer 120 is formed in the curved channel 120a in the first insulating layer 12, the first The insulating layer 12 is the first insulating layer in the non-display area 102a'.
  • the surface of the organic insulating elastic layer 120 in contact with the peripheral wiring 110 is provided with an organic insulating elastic protrusion 121, and the organic insulating elastic protrusion 121 may be deformed when folded to further provide the organic insulating elastic layer 120 required for bending Is redundant, and the peripheral wiring 110 covering the organic insulating elastic protrusion 121 will also be deformed when the peripheral wiring 110 is folded to provide the length required for the peripheral wiring 120 to be bent, so the organic insulating elastic layer 120
  • the organic insulating elastic protrusion 121 can prevent the peripheral trace 120 from breaking when bent.
  • the organic insulating elastic protrusion 121 and the organic insulating elastic layer 120 may be manufactured through the same process, or may be manufactured through different processes.
  • the organic insulating elastic protrusion 121 may be hemispherical, trapezoidal, stepped, or toothed. It can be understood that a groove may be provided on the surface of the organic insulating elastic layer 120 in contact with the peripheral trace 110 to deform the peripheral trace 110 when folded to provide the redundancy required for the peripheral trace 110 to be folded.
  • FIG. 6 is a schematic diagram of the section shown in FIG. 5 after being folded along a curved channel.
  • the organic insulating elastic protrusion 121 deforms after being stretched to deform the peripheral wiring 110 to avoid breakage during the stretching of the peripheral wiring 110
  • the conductive pads 170 on the peripheral traces 110 on both sides of the curved channel 120a are in contact with each other, to further ensure that the peripheral traces on both sides of the curved channel 120a after folding can be electrically connected.
  • FIG. 7 is a cross-sectional view of FIG. 4 along the B-B tangent direction.
  • the scan line 140 in the display area 102 a needs to be connected to the gate driving circuit 150 in the trace area through the conversion line 160.
  • the second conductive layer 13 bridges the gate driving circuit 150 and the first conductive layer 11 through the vias on the first insulating layer 12, and when the second conductive layer 13 extends to the curved channel 120a, the second conductive layer 13 is located in the organic insulating elastic layer 120 surface.
  • the surface of the organic insulating elastic layer 120 in contact with the second conductive layer 13 is provided with an organic insulating elastic protrusion 121, and the organic insulating elastic protrusion 121 will be deformed when folded to further provide the length required when the organic insulating elastic layer 120 is bent, Moreover, the second conductive layer 13 covered on the organic insulating elastic protrusion 121 may also be deformed during folding to provide the redundancy required when the second conductive layer 13 is bent.
  • the conversion circuit 160 includes a first conductive layer 11, a first insulating layer 12, and a second conductive layer 13 that are sequentially disposed on the first surface 102 of the flexible substrate 100.
  • the first conductive layer 11 is a scan line 140 extending from the display area 102a to the line conversion area 160a
  • the first insulating layer 12 is the first insulating layer in the non-display area 102a'
  • the second conductive layer 14 is The second conductive layer in the non-display area 102a'.
  • the surface of the second conductive layer 14 also covers the second insulating layer 14, which is the second insulating layer in the non-display area 102a'.
  • FIG. 8 is a second partial enlarged view of the array substrate shown in FIG. 1.
  • FIG. 9 is a cross-sectional view of the array substrate 10 shown in FIG. 8 along the CC tangent direction.
  • the three main wiring regions 1027 extend to the third wiring corner region 1023, and the surface of the organic insulating elastic layer 120 in contact with the peripheral wiring 110 is provided with an organic insulating elastic protrusion 121, so that the peripheral wiring 110 can be stretched during the folding process Long to avoid breakage.
  • FIG. 10 is a cross-sectional view of the array substrate shown in FIG. 8 along the DD tangent direction.
  • the data line 130 passes through the curved channel 120a to extend to the bonding area 103. Before passing through the curved channel 120a, the data line 130 The line 160 needs to be changed. Specifically, the data line 130 is connected to the first line-changing pad 15 through the via on the first insulating layer 12, and the second conductive layer 13 extending from the line conversion area 160 a to the wiring area passes through the first insulating layer 12.
  • the hole bridges the first line-changing pad 15 and the second line-changing pad 16, and the second conductive pad 16 is connected to the second conductive layer 13 in the wiring area through the via on the first insulating layer 12, and the second The second conductive layer 13 extends to the binding area 103.
  • the first line changing pad 15 is located in the line switching area 160a
  • the second line changing pad 16 is located in the wiring area.
  • the first line changing pad 15 and the second line changing pad 16 both pass through the first pattern outside the display area 102a.
  • the conductive layer 11 is formed.
  • the surface of the organic insulating elastic layer 120 in contact with the second conductive layer 13 is provided with organic insulating elastic protrusions 121 so that the second conductive layer 13 can be stretched during folding to avoid breakage.
  • Another object of the present application is to provide a display panel including the above array substrate.
  • the display panel further includes an anode, a light emitting layer, and a cathode formed on the array substrate in sequence.

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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

本申请提供一种阵列基板及显示面板，阵列基板包括柔性基板、外围走线以及弯曲通道，沿着弯曲通道折叠使外围走线位于显示区的背面以增大显示面中显示区的面积。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
随着Iphone X和Sumsang盖乐世新产品的发布，窄边框以及U-Cut（刘海）全面屏等产品瞬息引爆消费市场，全面屏逐渐成为行业主流。
全面屏通过增大屏占比而减小无效区使得消费者的视觉体验感增强。然而，传统技术所谓的全面屏都属于窄边框技术范畴，不能称为真正意义上的全面屏，从窄边框到全面屏的主要限制因素之一是显示器的边缘走线需要占用显示器的显示面的区域。
 技术问题
本申请的目的在于提供一种阵列基板及显示面板，该阵列基板和显示面板的显示面中显示区的面积增大。
 技术解决方案
一种阵列基板，所述阵列基板包括：
柔性基板，所述柔性基板具有第一表面及与所述第一表面相对的第二表面，所述柔性基板的所述第一表面具有显示区和非显示区，所述非显示区位于所述显示区的外围；
外围走线，所述外围走线设置于所述非显示区的走线区中；
弯曲通道，所述弯曲通道位于所述走线区和所述显示区之间，沿着所述弯曲通道折叠使所述外围走线位于所述柔性基板的所述第二表面所在的一侧。
在上述阵列基板中，所述阵列基板还包括转换线路，所述转换线路设置于线路转换区，所述线路转换区位于所述弯曲通道和所述显示区之间。
在上述阵列基板中，所述转换线路包括依次设置于所述柔性基板的所述第一表面的第一导电层、第一绝缘层及第二导电层。
在上述阵列基板中，所述阵列基板还包括栅极驱动电路，所述栅极驱动电路设置于所述走线区中，沿着所述弯曲通道折叠使所述栅极驱动电路位于所述柔性基板的所述第二表面所在的一侧。
在上述阵列基板中，所述第二导电层通过所述第一绝缘层上的过孔桥接所述栅极驱动电路和所述第一导电层。
在上述阵列基板中，所述第一导电层为从所述显示区延伸至所述线路转换区的扫描线。
在上述阵列基板中，所述线路转换区的宽度为0.08毫米-0.12毫米。
在上述阵列基板中，所述线路转换区的宽度为0.1毫米。
在上述阵列基板中，所述阵列基板还包括有机绝缘弹性层，所述有机绝缘弹性层设置于所述弯曲通道中。
在上述阵列基板中，所述有机绝缘弹性层与所述外围走线接触的表面设置有有机绝缘弹性凸起。
在上述阵列基板中，所述有机绝缘弹性凸起为半球形、梯形、台阶型或者齿状。
在上述阵列基板中，所述阵列基板还包括导电垫，所述导电垫设置于所述弯曲通道两侧的所述外围走线上。
在上述阵列基板中，所述导电垫为有机导电垫。
在上述阵列基板中，所述导电垫沿垂直于所述外围走线所在直线方向的宽度为所述外围走线宽度的2-10倍。
在上述阵列基板中，所述阵列基板还包括外部控制芯片，所述外部控制芯片绑定于所述走线区的绑定区中，沿着所述弯曲通道折叠使所述外部控制芯片位于所述柔性基板的所述第二表面所在的一侧。
在上述阵列基板中，所述弯曲通道为井字形通道。
一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
柔性基板，所述柔性基板具有第一表面及与所述第一表面相对的第二表面，所述柔性基板的所述第一表面具有显示区和非显示区，所述非显示区位于所述显示区的外围；
外围走线，所述外围走线设置于所述非显示区的走线区中；
弯曲通道，所述弯曲通道位于所述走线区和所述显示区之间，沿着所述弯曲通道折叠使所述外围走线位于所述柔性基板的所述第二表面所在的一侧。
在上述显示面板中，所述阵列基板还包括栅极驱动电路，所述栅极驱动电路设置于所述走线区中，沿着所述弯曲通道折叠使所述栅极驱动电路位于所述柔性基板的所述第二表面所在的一侧。
在上述显示面板中，所述阵列基板还包括外部控制芯片，所述外部控制芯片绑定于所述走线区的绑定区中，沿着所述弯曲通道折叠使所述外部控制芯片位于所述柔性基板的所述第二表面所在的一侧。
在上述显示面板中，所述阵列基板还包括有机绝缘弹性层，所述有机绝缘弹性层设置于所述弯曲通道中。
 有益效果
本申请提供一种阵列基板及显示面板，通过沿着弯曲通道折叠使外围走线位于显示区的背面以增大显示面中显示区的面积。
 附图说明
图1为本申请一实施例的阵列基板折叠前的示意图；
图2为图1所示阵列基板折叠后的示意图；
图3为图2所示阵列基板背面的示意图；
图4为图1所示阵列基板的第一局部放大图；
图5为图4所示阵列基板沿A-A切线方向的截面图；
图6为图5所示截面沿着弯曲通道折叠后的示意图；
图7为图4所示阵列基板沿B-B切线方向的截面图；
图8为图1所示阵列基板的第二局部放大图；
图9为图8所示阵列基板沿C-C切线方向的截面图；
图10为图8所示阵列基板沿D-D切线方向的截面图。
附图标示：
100柔性基板102第一表面 104第二表面102a 显示区
102a’非显示区103绑定区 1021第一走线转角区
1022第二走线转角区 1023第三走线转角区 1024 第四走线转角区 1025第一主走线区 1026第二主走线区 1027 第三主走线区
1028第四主走线区 110外围走线 120a弯曲通道
120有机绝缘弹性层  121有机绝缘弹性凸起
130数据线 140扫描线  150 栅极驱动电路 160转换线路
160a 线路转换区170导电垫 11第一导电层 12 第一绝缘层
13 第二导电层 14 第二绝缘层15第一换线垫 16第二换线垫
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1、图2及图3，图1为本申请一实施例的阵列基板，图2为图1所示阵列基板折叠后的示意图，图3为图2所示阵列基板背面的示意图，图1所示阵列基板包括：
柔性基板100，柔性基板100具有第一表面102及与第一表面102相对的第二表面104，柔性基板100的第一表面102具有显示区102a和非显示区102a’，非显示区102a’位于显示区102a的外围；
外围走线110，外围走线110设置于非显示区102a’的走线区中；
弯曲通道120a，弯曲通道120a位于走线区和显示区102a之间，沿着弯曲通道120a折叠使外围走线110位于柔性基板100的第二表面104所在的一侧。
上述方案通过沿着弯曲通道折叠使外围走线位于显示区的背面以增大显示面的显示区的面积。
在本实施例中，阵列基板为薄膜晶体管阵列基板，其衬底为柔性基板100使阵列基板具有可折叠性。柔性基板100的制备材料可为聚酰亚胺（Polyimide, PI）、聚对苯二甲酸乙二醇酯（Polyethylene terephthalate, PET）或者其他柔性材料。
柔性基板100的第一表面102具有显示区102a和非显示区102a’，显示区102a中设置有多条相互垂直相交的数据线130和扫描线140，在多条数据线130和多条扫描线140交叉形成的区域中设置有多个薄膜晶体管（未示出），扫描线140连接薄膜晶体管的栅极以向薄膜晶体管输入扫描信号，数据线130连接薄膜晶体管的源极以向薄膜晶体管输入数据信号。制造显示区102a中的薄膜晶体管包括如下步骤：
于柔性基板100的第一表面102上形成第一导电层，图案化显示区102a中的第一导电层以形成栅极；
于形成栅极的第一表面102上继续形成一整面第一绝缘层；
于形成第一绝缘层的第一表面102上继续形成图案化的沟道层；
于形成图案化的沟道层的第一表面102上形成第二绝缘层并图案化显示区102a中的第二绝缘层以于第二绝缘层上形成过孔；
于形成第二绝缘层的第一表面102上形成一整面的第二导电层，图案化显示区102a中的第二导电层以形成源漏电极，源漏电极通过第二绝缘层上的过孔与图案化的沟道层连接。
需要说明的是，于显示区102a中形成薄膜晶体管的过程中，也同时会于非显示区102a’中依次形成第一导电层、第一绝缘层、第二导电层以及第二绝缘层以形成非显示区102a’中的其他线路。
外围走线110设置于非显示区102a’的走线区中，外围走线110环绕显示区102a设置，外围走线包括但不限于电源电压（Voltage Drain Drain, VDD）走线、接地电压（Voltage Source-Source, VSS）走线、时钟（Clock, CLK）走线、外部时钟（External Clock, XCLK）走线。VDD走线、VSS走线、CLK走线以及XCLK走线是通过图案化非显示区102a’中的第二导电层形成的，即第二导电层为形成显示区102a中薄膜晶体管的源漏电极的导电层。
弯曲通道120a位于显示区102a的外围，其为井字形通道，在其他实施例中，弯曲通道也可以为其他结构，例如弯曲通道为一字型且分别位于阵列基板的至少一侧。依次沿着构成井字型通道的四条垂直相交的通道折叠使设置于非显示区102a’的走线区的外围走线110位于柔性基板100的第二表面104所在侧，即在柔性基板100的第一表面102（阵列基板的显示面）只具有显示区102a，沿着弯曲通道120a折叠后的阵列基板如图2所示，沿着弯曲通道120a折叠后的阵列基板的背面如图3所示。
对于非显示区102a’，井字型弯曲通道120a将其划分为8个区域，包括第一走线转角区1021、第二走线转角区1022、第三走线转角区1023、第四走线转角区1024、位于第一走线转角区1021和第二走线转角区1022之间的第一主走线区1025、位于第三走线转角区1023和第四走线转角区1024之间的第二主走线区1026、位于第一走线转角区1021和第三走线转角区1023之间的第三主走线区1027、位于第二走线转角区1022和第四走线转角区1024之间的第四主走线区1028。
进一步地，阵列基板还包括栅极驱动电路（Gate On Array, GOA）150，栅极驱动电路150设置于走线区中，沿着弯曲通道120a折叠使栅极驱动电路150位于柔性基板100的第二表面104所在的一侧。
具体地，栅极驱动电路150设置于第三主走线区1027和第四主走线区1028中，显示区102a中的每一条扫描线140的两端分别与栅极驱动电路150连接，即每条扫描线140都是通过两端输入扫描驱动信号。在其他实施例中，栅极驱动电路150也可以设置于第三主走线区1027或第四主走线区1028中，即每条扫描线140都是通过一端输入驱动信号。另外，栅极驱动电路150与外围走线110电连接。栅极驱动电路150与显示区102a中薄膜晶体管的扫描线140是同层制作。
请继续参阅图1，阵列基板还包括外部控制芯片（未示出），外部控制芯片绑定于走线区的绑定区103中，沿着弯曲通道120a折叠使外部控制芯片位于柔性基板100的第二表面104所在的一侧。外部控制芯片包括用于向数据线输出驱动信号的数据驱动控制芯片以及向外围走线110输入控制信号的芯片，数据线130和外围走线110延伸至绑定区103，通过柔性印刷电路板（Flexible Printed Circuit, FPC）与外部控制芯片电连接。具体地，绑定于绑定区103的外部控制芯片位于第二主走线区1026中。
为了避免显示区102a中延伸至弯曲通道120a的关键线路（包括扫描线和数据线等）在弯曲通道120a折叠过程中断裂而失效，阵列基板还包括转换线路160，转换线路160设置于线路转换区160a中，线路转换区160a位于弯曲通道120a和显示区102a之间。线路转换区160a的宽度为0.08毫米-0.12毫米，例如线路转换区160a的宽度为0.1毫米。即使在柔性基板100的第一表面102a增加转换线路160，显示区102a所占用的显示面的面积百分比仍高达99%。
请参阅图4及图5，图4为图1所示阵列基板的第一局部放大图，图5为图4沿A-A切线方向的截面图。由图4可知，阵列基板还包括导电垫170，导电垫170设置于弯曲通道120a两侧的外围走线110上。导电垫170为有机导电层；导电垫170沿垂直于外围走线110所在直线方向的宽度d大于外围走线的宽度，例如，导电垫170沿垂直于外围走线110所在直线方向的宽度d为外围走线宽度的2-10倍，为了适应导电垫170的宽度比外围走线110的宽度大，相邻两条外围走线110的间距在第一走线转角区1021中也相应的增大，进入第一主走线区1025后，相邻两条外围走线110的距离调整小。导电垫170形成于第二绝缘层14的中且位于外围走线110上，第二绝缘层14为非显示区102a’中的第二绝缘层，导电垫170的厚度与第二绝缘层14的厚度相同。可以理解的是，导电垫170也可以位于弯曲通道120a上方的外围走线110上。
另外，阵列基板还包括有机绝缘弹性层120，有机绝缘弹性层120设置于弯曲通道120a中。沿着弯曲通道120a折叠时，有机绝缘弹性层120具有弹性从而使得其在弯折过程中能提供弯折需要的冗长。有机绝缘弹性层120的制备材料为橡胶材料，例如三元乙丙橡胶、天然橡胶等。弯曲通道120a形成于第一绝缘层12的通道中，在形成显示区102a中薄膜晶体管中的源漏电极前，于第一绝缘层12中的弯曲通道120a中形成有机绝缘弹性层120，第一绝缘层12为非显示区102a’中第一绝缘层。
进一步地，有机绝缘弹性层120与外围走线110接触的表面设置有有机绝缘弹性凸起121，有机绝缘弹性凸起121在折叠时会变形以进一步地提供有机绝缘弹性层120在弯折时需要的冗长，而且，覆盖在有机绝缘弹性凸起121上的外围走线110在外围走线110折叠时也会变形以提供外围走线120在弯折时需要的冗长，故有机绝缘弹性层120上的有机绝缘弹性凸起121能避免外围走线120在弯折时断裂。有机绝缘弹性凸起121与有机绝缘弹性层120可以通过同一制程制得，也可以通过不同的制程制得。有机绝缘弹性凸起121可以为半球形、梯形、台阶型或者齿状。可以理解的是，也可以有机绝缘弹性层120与外围走线110接触的表面设置凹槽以使外围走线110在折叠时也会变形以提供外围走线110在弯折时需要的冗长。
请参阅图6，图6为图5所示截面沿弯曲通道折叠后的示意图，有机绝缘弹性凸起121经拉伸后变形使得外围走线110也变形，避免外围走线110拉伸过程中断裂；折叠后弯曲通道120a两侧外围走线110上的导电垫170相互接触，进一步地保证折叠后弯曲通道120a两侧的外围走线能够电连接。
请参阅4及图7，图7为图4沿B-B切线方向的截面图，位于显示区102a中的扫描线140需要通过转换线路160以与位于走线区的栅极驱动电路150连接。第二导电层13通过第一绝缘层12上的过孔桥接栅极驱动电路150和第一导电层11，第二导电层13延伸至弯曲通道120a时，第二导电层13位于有机绝缘弹性层120的表面。有机绝缘弹性层120与第二导电层13接触的表面设置有有机绝缘弹性凸起121，有机绝缘弹性凸起121在折叠时会变形以进一步地提供有机绝缘弹性层120弯折时需要的冗长，而且，覆盖在有机绝缘弹性凸起121上的第二导电层13在折叠过程中也会变形以提供第二导电层13弯折时需要的冗长。
由图7可知，转化线路160包括依次设置于柔性基板100的第一表面102的第一导电层11、第一绝缘层12、第二导电层13。具体地，第一导电层11为从显示区102a中延伸至线路转换区160a中的扫描线140，第一绝缘层12为非显示区102a’中的第一绝缘层，第二导电层14为非显示区102a’中的第二导电层。第二导电层14的表面还覆盖第二绝缘层14，第二绝缘层14为非显示区102a’中的第二绝缘层。
请参阅图8及图9，图8为图1所示阵列基板的第二局部放大图，图9为图8所示阵列基板10沿C-C切线方向的截面图，外围走线110是直接从第三主走线区1027延伸至第三走线转角区1023，有机绝缘弹性层120与外围走线110接触的表面上设置有有机绝缘弹性凸起121，使得外围走线110在折叠过程中可伸长以避免断裂。
请参阅图8及图10，图10为图8所示阵列基板沿D-D切线方向的截面图，数据线130经过弯曲通道120a以延伸至绑定区103，在经过弯曲通道120a之前，数据线130需要转换线路160换线。具体地，数据线130通过第一绝缘层12上的过孔连接至第一换线垫15，从线路转换区160a延伸至走线区的第二导电层13通过第一绝缘层12上的过孔桥接第一换线垫15和第二换线垫16，第二导电垫16再通过第一绝缘层12上的过孔连接位于走线区的第二导电层13后，走线区的第二导电层13延伸至绑定区103。第一换线垫15位于线路转换区160a中，第二换线垫16为位于走线区中，第一换线垫15和第二换线垫16均通过图案化显示区102a外的第一导电层11形成。另外，有机绝缘弹性层120与第二导电层13接触的表面设置有有机绝缘弹性凸起121，使得第二导电层13在折叠过程中可伸长以避免断裂。
本申请的又一目的是提供一种显示面板，该显示面板包括上述阵列基板。
进一步地，显示面板还包括依次形成于阵列基板上的阳极、发光层以及阴极。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    柔性基板，所述柔性基板具有第一表面及与所述第一表面相对的第二表面，所述柔性基板的所述第一表面具有显示区和非显示区，所述非显示区位于所述显示区的外围；
    外围走线，所述外围走线设置于所述非显示区的走线区中；
    弯曲通道，所述弯曲通道位于所述走线区和所述显示区之间，沿着所述弯曲通道折叠使所述外围走线位于所述柔性基板的所述第二表面所在的一侧。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括转换线路，所述转换线路设置于线路转换区，所述线路转换区位于所述弯曲通道和所述显示区之间。
  3. 根据权利要求2所述的阵列基板，其中，所述转换线路包括依次设置于所述柔性基板的所述第一表面的第一导电层、第一绝缘层及第二导电层。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括栅极驱动电路，所述栅极驱动电路设置于所述走线区中，沿着所述弯曲通道折叠使所述栅极驱动电路位于所述柔性基板的所述第二表面所在的一侧。
  5. 根据权利要求4所述的阵列基板，其中，所述第二导电层通过所述第一绝缘层上的过孔桥接所述栅极驱动电路和所述第一导电层。
  6. 根据权利要求5所述的阵列基板，其中，所述第一导电层为从所述显示区延伸至所述线路转换区的扫描线。
  7. 根据权利要求2所述的阵列基板，其中，所述线路转换区的宽度为0.08毫米-0.12毫米。
  8. 根据权利要求7所述的阵列基板，其中，所述线路转换区的宽度为0.1毫米。
  9. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括有机绝缘弹性层，所述有机绝缘弹性层设置于所述弯曲通道中。
  10. 根据权利要求9所述的阵列基板，其中，所述有机绝缘弹性层与所述外围走线接触的表面设置有有机绝缘弹性凸起。
  11. 根据权利要求10所述的阵列基板，其中，所述有机绝缘弹性凸起为半球形、梯形、台阶型或者齿状。
  12. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括导电垫，所述导电垫设置于所述弯曲通道两侧的所述外围走线上。
  13. 根据权利要求12所述的阵列基板，其中，所述导电垫为有机导电垫。
  14. 根据权利要求12所述的阵列基板，其中，所述导电垫沿垂直于所述外围走线所在直线方向的宽度为所述外围走线宽度的2-10倍。
  15. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括外部控制芯片，所述外部控制芯片绑定于所述走线区的绑定区中，沿着所述弯曲通道折叠使所述外部控制芯片位于所述柔性基板的所述第二表面所在的一侧。
  16. 根据权利要求1所述的阵列基板，其中，所述弯曲通道为井字形通道。
  17. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括：
    柔性基板，所述柔性基板具有第一表面及与所述第一表面相对的第二表面，所述柔性基板的所述第一表面具有显示区和非显示区，所述非显示区位于所述显示区的外围；
    外围走线，所述外围走线设置于所述非显示区的走线区中；
    弯曲通道，所述弯曲通道位于所述走线区和所述显示区之间，沿着所述弯曲通道折叠使所述外围走线位于所述柔性基板的所述第二表面所在的一侧。
  18. 根据权利要求17所述的显示面板，其中，所述阵列基板还包括栅极驱动电路，所述栅极驱动电路设置于所述走线区中，沿着所述弯曲通道折叠使所述栅极驱动电路位于所述柔性基板的所述第二表面所在的一侧。
  19. 根据权利要求17所述的显示面板，其中，所述阵列基板还包括外部控制芯片，所述外部控制芯片绑定于所述走线区的绑定区中，沿着所述弯曲通道折叠使所述外部控制芯片位于所述柔性基板的所述第二表面所在的一侧。
  20. 根据权利要求17所述的显示面板，其中，所述阵列基板还包括有机绝缘弹性层，所述有机绝缘弹性层设置于所述弯曲通道中。
PCT/CN2019/077881 2018-12-13 2019-03-12 阵列基板及显示面板 WO2020118931A1 (zh)

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