WO2020118900A1 - 显示装置及其制造方法 - Google Patents

显示装置及其制造方法 Download PDF

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Publication number
WO2020118900A1
WO2020118900A1 PCT/CN2019/075655 CN2019075655W WO2020118900A1 WO 2020118900 A1 WO2020118900 A1 WO 2020118900A1 CN 2019075655 W CN2019075655 W CN 2019075655W WO 2020118900 A1 WO2020118900 A1 WO 2020118900A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
layer
transistor layer
display device
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Application number
PCT/CN2019/075655
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English (en)
French (fr)
Inventor
张伟彬
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/499,274 priority Critical patent/US20200258974A1/en
Publication of WO2020118900A1 publication Critical patent/WO2020118900A1/zh

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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
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    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a display device and a manufacturing method thereof, in particular to a display device and a method for manufacturing the same that increase the screen ratio.
  • the display device In recent years, with the more and more common use of display devices, the display device has developed toward a high screen ratio, and narrow bezels have become a trend in the development of display devices.
  • the current structure generally is to arrange some peripheral circuit structures (for example, a plurality of thin film transistor structures) in a non-active area around the display device.
  • the arrangement of the peripheral circuit structure will result in the screen ratio of the display device not being improved.
  • the current flexible display device usually adopts the bendable characteristic of the flexible substrate disposed under the display panel, and bends the flexible substrate along the bending area to the back of the display panel to increase the screen ratio of the display device .
  • circuit structures for example, a plurality of thin film transistor structures
  • some circuit structures are also provided in the bending area of the flexible display device, which is also one of the factors that cannot increase the screen ratio.
  • an inorganic layer is provided in the bending area to block the penetration of water and oxygen, which may cause deterioration or failure of display elements and materials of the display device.
  • the inorganic layer is susceptible to cracking after being bent many times or the resistance becomes larger due to the deterioration of the material of the display element.
  • the plurality of thin film transistor structures are also very vulnerable in the bending region.
  • the non-active area on the periphery of the display device and the bending area under the display device are often provided with multiple circuit structures, resulting in the problem that the screen ratio cannot be improved, and in the prior art, the inorganic layer of the bending area passes through many After the second bending, it is easy to break or cause a problem that the resistance of the display element becomes large due to the deterioration of the material of the display element or the structure of the thin film transistor is easily damaged.
  • the present invention provides a display device and a manufacturing method thereof, to solve that in the prior art, the non-active area around the display device and the bending area under the display device are often provided with multiple circuit structures, resulting in an inability to achieve a screen-to-body ratio
  • the main object of the present invention is to provide a display device and a manufacturing method thereof, which can increase the screen ratio of the display device.
  • the secondary object of the present invention is to provide a display device and a manufacturing method thereof, which can be provided in an active area by arranging a plurality of circuit structures provided in a non-active area on the periphery of the display device and a bending area under the display device, To increase the screen ratio of the display device.
  • Another object of the present invention is to provide a display device and a method for manufacturing the same, which can prevent the inorganic layer in the bending area of the display device from being easily broken after being bent many times or increasing the resistance due to the deterioration of the material of the display element And the thin film transistor structure is extremely vulnerable to damage in the bending area, resulting in product failure.
  • an embodiment of the invention provides a display device including: a substrate; a first buffer layer disposed on the substrate; and a first thin film transistor layer disposed on the first On the buffer layer; a second buffer layer on the first thin film transistor layer; a second thin film transistor layer on the second buffer layer; a deep hole on the second thin film transistor layer Between at least two thin film transistors, and penetrates the first thin film transistor layer, the second buffer layer, and the second thin film transistor layer; and a planarization layer disposed on the second thin film transistor layer And fill in the deep hole.
  • the first thin film transistor layer includes a scanning line circuit and an emission control line (EM) circuit.
  • EM emission control line
  • the first thin film transistor layer is a 10T3C circuit or an 8T2C circuit.
  • the second thin film transistor layer is an internal compensation circuit.
  • the second thin film transistor layer is a 7T1C circuit.
  • the display device further includes: a via penetrating through the second buffer layer, the second thin film transistor layer and the planarization layer; and an anode metal layer disposed on On the planarization layer, the first thin film transistor layer is connected to the anode metal layer through the via hole.
  • the first thin film transistor layer and the second thin film transistor layer are arranged in a staggered manner.
  • another embodiment of the present invention provides a display device, including: a bending region and a non-bending region, the non-bending region having an active region; and a first thin film transistor layer and a first Two thin film transistor layers are disposed in the active area, wherein the second thin film transistor layer is disposed on the first thin film transistor layer.
  • the first thin film transistor layer includes a scanning line circuit and an emission control line (EM) circuit.
  • EM emission control line
  • the second thin film transistor layer is an internal compensation circuit.
  • the second thin film transistor layer is a 7T1C circuit.
  • the display device further includes: a substrate; a first buffer layer disposed on the substrate, and the first thin film transistor layer disposed on the first buffer layer; one A second buffer layer is provided on the first thin film transistor layer, the second thin film transistor layer is provided on the second buffer layer; and a planarization layer is provided on the second thin film transistor layer.
  • the bending region has a deep hole penetrating the first thin film transistor layer, the second buffer layer, and the second thin film transistor layer, wherein the planarization layer is filled in In the deep hole.
  • the display device further includes: a via penetrating through the second buffer layer, the second thin film transistor layer and the planarization layer; and an anode metal layer disposed on On the planarization layer, the first thin film transistor layer is connected to the anode metal layer through the via hole.
  • the first thin film transistor layer and the second thin film transistor layer are arranged in a staggered manner.
  • yet another embodiment of the present invention provides a method for manufacturing a display device, including the steps of: providing a substrate; forming a first buffer layer on the substrate; forming a first thin film transistor layer on the first buffer Forming a second buffer layer on the first thin film transistor layer; forming a second thin film transistor layer on the second buffer layer; forming a deep hole in at least two of the second thin film transistor layer Between two thin film transistors, and penetrates the first thin film transistor layer, the second buffer layer and the second thin film transistor layer; and a planarization layer is provided on the second thin film transistor layer and filled in Narrated in the deep hole.
  • the first thin film transistor layer includes a scanning line circuit and an emission control line (EM) circuit.
  • EM emission control line
  • the second thin film transistor layer is an internal compensation circuit.
  • the second thin film transistor layer is a 7T1C circuit.
  • the first thin film transistor layer and the second thin film transistor layer are arranged in a staggered manner.
  • the display device and the manufacturing method of the present invention can be arranged in the active area by arranging a plurality of circuit structures provided in the non-active area on the periphery of the display device and the bending area under the display device in this way The screen ratio of the display device can be improved.
  • the display device and the manufacturing method of the present invention can be provided with deep holes in the bending area of the display device and through the inorganic layer of the bending area of the display device, so that the bending of the display device in the prior art can be solved
  • the inorganic layer of the region is prone to fracture after being bent many times, or the problem that the resistance of the display element becomes larger due to the deterioration of the material of the display element or the structure of the thin film transistor is extremely vulnerable.
  • FIG. 1 is a schematic cross-sectional view of a display device according to an embodiment of the invention.
  • an embodiment of the present invention provides a display device 1 to achieve the aforementioned object of the present invention.
  • the display device 1 includes a first thin film transistor layer and a second thin film transistor layer, the second thin film transistor layer is disposed on the first thin film transistor layer.
  • the first thin film transistor layer includes a scanning line circuit and an emission control line (EM) circuit.
  • the second thin film transistor layer is an internal compensation circuit.
  • the second thin film transistor layer is an internal compensation circuit.
  • the first thin film transistor layer is a 10T3C circuit or an 8T2C circuit, wherein the 10T3C circuit is composed of 10 TFTs and 3 storage capacitors, and the 8T2C circuit is composed of 8 TFTs and 2 storage capacitors.
  • the second thin film transistor layer is a 7T1C circuit, wherein the 7T1C circuit is composed of 7 TFTs and 1 storage capacitor.
  • the first thin-film transistor layer has at least two groups of thin-film transistors, wherein a first group of thin-film transistors is arranged to sequentially turn on a signal of a scanning gate in the first thin-film transistor layer to complete pixel reset and data Write to determine the gray level of light emission, one of the second group of thin film transistors is set to turn on the gate signal of the light emitting control line in the first thin film transistor layer in order to control whether a whole row of pixels emit light.
  • the display device 1 includes: a bending area BA and a non-bending area, the non-bending area has an active area AA.
  • a first thin film transistor layer and a second thin film transistor layer are disposed in the active area AA, wherein the second thin film transistor layer is disposed on the first thin film transistor layer.
  • the display device 1 further includes a substrate 102, a first buffer layer 103, a first thin film transistor layer, a second buffer layer 106, a second thin film transistor layer, and a planarization layer 109.
  • the substrate 102 may be a flexible substrate, for example, a polyimide substrate.
  • a carrier board 101 may be disposed under the substrate 102, for example, a glass substrate.
  • the first buffer layer 103 is provided on the substrate 102.
  • the first thin film transistor layer is disposed on the first buffer layer 103.
  • the first thin film transistor layer includes: a first active layer 111, a first gate insulating layer 104, a first gate 113, a second gate insulating layer 105, and a first source The electrode/drain 114 and a first source/drain via 115.
  • the first active layer 111 is disposed on the first buffer layer 103, and the first active layer 111 has a first active layer impurity region 112.
  • the first gate insulating layer 104 is disposed on the first active layer 111 and covers the first active layer 111.
  • the first gate 113 is disposed on the first gate insulating layer 104.
  • the second gate insulating layer 105 is disposed on the first gate 113 and covers the first gate 113.
  • the first source/drain 114 is disposed on the second gate insulating layer 105, and is connected to the first active layer 111 through the first source/drain via 115.
  • the second buffer layer 106 is disposed on the first thin film transistor layer.
  • the second thin film transistor layer is disposed on the second buffer layer 106.
  • the second thin film transistor layer includes: a second active layer 116, a third gate insulating layer 107, a second gate 1117, a fourth gate insulating layer 108, and a second source The electrode/drain 118 and a second source/drain via 119.
  • the second active layer 116 is disposed on the second buffer layer 106.
  • the third gate insulating layer 107 is disposed on the second active layer 116 and covers the second active layer 116.
  • the second gate 117 is disposed on the third gate insulating layer 107.
  • the fourth gate insulating layer 108 is disposed on the second gate 117 and covers the second gate 117.
  • the second source/drain 118 is disposed on the fourth gate insulating layer 108 and connected to the second active layer 116 through the second source/drain via 119.
  • the planarization layer 109 is disposed on the second thin film transistor layer.
  • the planarization layer 109 is disposed on the fourth gate insulating layer 108.
  • the bending area BA has a deep hole 120 penetrating the first thin film transistor layer, the second buffer layer 106 and the second thin film transistor layer, wherein the planarization layer 109 is filled into the Deep hole 120.
  • the deep hole 120 further penetrates the first gate insulating layer 104, the second gate insulating layer 105, the third gate insulating layer 107, and the fourth gate insulating layer 108 .
  • the display device 1 further includes: a first via 121, a second via 122, and an anode metal layer 123.
  • the first via 121 penetrates the second buffer layer 106, the second thin film transistor layer and the planarization layer 109.
  • the anode metal layer 123 is disposed on the planarization layer 109, wherein the first thin film transistor layer is connected to a first anode 123A in the anode metal layer 123 through the first via 121.
  • the first via 121 also penetrates the third gate insulating layer 107 and the fourth gate insulating layer 108.
  • the second via 122 penetrates the planarization layer 109, wherein the second thin film transistor layer is connected to a second anode 123B in the anode metal layer 123 through the second via 122.
  • the display device 1 further includes: a pixel defining layer 110 and a photoresist spacer layer 124.
  • the pixel defining layer 110 is disposed on the planarization layer 109.
  • the pixel defining layer 110 has a plurality of openings 125 exposing the anode metal layer 123.
  • the photoresist spacer layer 124 is disposed on the pixel defining layer 110 and is disposed relative to the plurality of openings 125.
  • the second thin film transistor layer is disposed on Zheng Shangfang of the first thin film transistor layer.
  • the first thin film transistor layer and the second thin film transistor layer are arranged in a staggered manner.
  • a thickness of the second buffer layer 106 is thicker than a thickness of the first buffer layer 103 to avoid mutual interference of the first thin film transistor layer and the second thin film transistor layer.
  • the second buffer layer 106 may be further provided with another organic layer to improve mutual interference between the first thin film transistor layer and the second thin film transistor layer.
  • the display device 1 has two active areas AA disposed on both sides of the bending area.
  • One of the two active regions AA has the structure of the first thin film transistor layer and the second thin film transistor layer as described above, while the other of the two active regions AA is provided only with the second Thin film transistor layer.
  • the carrier board 101 may be removed or retained after the display device 1 is manufactured.
  • another embodiment of the present invention provides a method for manufacturing a display device 1 including the steps of: providing a substrate 102; forming a first buffer layer 103 on the substrate; forming a first thin film transistor layer on the substrate Forming a second buffer layer 106 on the first thin film transistor layer; forming a second thin film transistor layer on the second buffer layer 106; forming a deep hole 120 on the first buffer layer 103; Between at least two thin film transistors of the two thin film transistor layers, and penetrates the first thin film transistor layer, the second buffer layer 106 and the second thin film transistor layer; and a planarization layer 109 is provided on the first The two thin film transistor layers are filled into the deep hole 120.
  • the step of forming the first thin film transistor layer in the manufacturing method further includes the steps of: forming a first active layer 111 on the first buffer layer 103; and forming a first active layer impurity region 112 on the The first active layer 111; forming a first gate insulating layer 104 on the first active layer 111 and covering the first active layer 111; forming a first gate 113 on the first Forming a second gate insulating layer 10 on the first gate 113 and covering the first gate 113; forming a first source/drain 114 on the second gate On the electrode insulating layer 105; and forming a first source/drain via 115 to connect to the first active layer 111.
  • the step of forming the second thin film transistor layer in the manufacturing method further includes the steps of: forming a second active layer 116 on the second buffer layer 106; forming a third gate insulating layer 107 on the first Two active layers 116 and covering the second active layer 116; forming a second gate 117 on the third gate insulating layer 107; forming a fourth gate insulating layer 108 on the second Covering the second gate 117 on the gate 117; and forming a second source/drain 118 on the fourth gate insulating layer 108 and passing through a second source/drain via 119 Connect the second active layer 116.
  • the deep hole 120 is disposed at a bending area BA of the display device 1.
  • the deep hole 120 penetrates the first thin film transistor layer, the second buffer layer 106 and the second thin film transistor layer, wherein the planarization layer 109 is filled into the deep hole 120.
  • the deep hole 120 further penetrates the first gate insulating layer 104, the second gate insulating layer 105, the third gate insulating layer 107, and the fourth gate insulating layer 108 .
  • the manufacturing method further includes the step of forming an anode metal layer 123 on the planarization layer 109, wherein the first thin film transistor layer passes through a first via 121 and the anode metal layer 123 A first anode 123A is connected.
  • the first via 121 also penetrates the third gate insulating layer 107 and the fourth gate insulating layer 108.
  • the manufacturing method further includes the step of forming a second via 122 through the planarization layer 109, wherein the second thin film transistor layer passes through a second of the second via 122 and the anode metal layer 123 The two anodes 123B are connected.
  • the manufacturing method further includes the steps of: forming a pixel defining layer 110 on the planarization layer 109, the pixel defining layer 110 has a plurality of openings 125, exposing the anode metal layer 123; and forming a The photoresist spacer layer 124 is on the pixel defining layer 110 and is disposed relative to the plurality of openings 125.
  • the display device and the manufacturing method of the present invention provide a plurality of circuit structures in the non-active area around the display device and the bending area under the display device in the active area to increase the screen ratio of the display device.
  • the display device and the manufacturing method of the present invention can be provided with deep holes in the bending area of the display device and through the inorganic layer of the bending area of the display device, so that the bending of the display device in the prior art can be solved
  • the inorganic layer of the region is prone to fracture after being bent many times, or the problem that the resistance of the display element becomes larger due to the deterioration of the material of the display element or the structure of the thin film transistor is extremely vulnerable.

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Abstract

本发明公开一种显示装置及其制造方法。所述显示装置包含：一弯折区及一非弯折区，所述非弯折区具有一有源区域；及一第一薄膜晶体管层及一第二薄膜晶体管层，设置于所述有源区域内，其中所述第二薄膜晶体管层设置于所述第一薄膜晶体管层上。本发明通过将原本设计在非显示区的外围电路设置到有源区域的薄膜晶体管层下方，以达到避免外围电路占用屏幕的非有源区域,从而提升显示装置的屏占比。

Description

显示装置及其制造方法 技术领域
本发明是有关于一种显示装置及其制造方法，特别是有关于一种提升屏占比的显示装置及其制造方法。
 背景技术
近年来，随着显示装置越来越普遍的使用，显示装置走向高屏占比的发展，窄边框已经成为显示装置发展的一种趋势。对于柔性显示装置而言，目前结构普遍通过将一些外围电路结构（例如，多个薄膜晶体管结构）设置在显示装置周围的非有源区域。但是，所述外围电路结构的设置将导致显示装置的屏占比无法提高。再者，目前柔性显示装置通常是采用设置于显示面板下方的柔性基板的可弯折特性，将所述柔性基板沿着弯折区弯折到显示面板的背面，以提高显示装置的屏占比。但是由于所述柔性显示装置的弯折区也会设置一些电路结构（例如，多个薄膜晶体管结构），其也是造成屏占比无法提高的因素之一。另外，弯折区会设置无机层以阻隔水氧渗透进入造成显示装置的显示元件及材料的劣化或失效。但所述无机层在经过多次弯折后易发生断裂或因显示元件的材料劣化造成电阻变大。另外，所述多个薄膜晶体管结构在弯折区也会极易受损。
故，有必要提供一种显示装置及其制造方法，以解决现有技术所存在的问题。
 技术问题
现有技术中显示装置外围的非有源区域及显示装置下方的弯折区往往会设置多个电路结构造成屏占比无法提高的问题，以及现有技术中弯折区的无机层在经过多次弯折后易发生断裂或因显示元件的材料劣化造成电阻变大或薄膜晶体管结构极易受损的问题。
 技术解决方案
有鉴于此，本发明提供一种显示装置及其制造方法，以解决现有技术中显示装置外围的非有源区域及显示装置下方的弯折区往往会设置多个电路结构造成屏占比无法提高的问题，以及解决现有技术中弯折区的无机层在经过多次弯折后易发生断裂或因显示元件的材料劣化造成电阻变大或薄膜晶体管结构极易受损的问题。
本发明的主要目的在于提供一种显示装置及其制造方法，其可以提高显示装置的屏占比。
本发明的次要目的在于提供一种显示装置及其制造方法，其可以通过将设置在显示装置外围的非有源区域及显示装置下方的弯折区的多个电路结构设置在有源区域，以提高显示装置的屏占比。
本发明的另一目的在于提供一种显示装置及其制造方法，其可以避免显示装置的弯折区的无机层在经过多次弯折后易发生断裂或因显示元件的材料劣化造成电阻变大及薄膜晶体管结构在弯折区极易受损造成产品失效。
为达成本发明的前述目的，本发明一实施例提供一种显示装置，包含：一基板；一第一缓冲层，设置于所述基板上；一第一薄膜晶体管层，设置于所述第一缓冲层上；一第二缓冲层，设置于所述第一薄膜晶体管层上；一第二薄膜晶体管层，设置于所述第二缓冲层上；一深孔，于所述第二薄膜晶体管层的至少两个薄膜晶体管之间，并贯穿所述第一薄膜晶体管层、所述第二缓冲层及所述第二薄膜晶体管层；及一平坦化层，设置于所述第二薄膜晶体管层上并填入所述深孔中。
在本发明的一实施例中，所述第一薄膜晶体管层包含一扫描线电路及一发光控制线(EM)电路。
在本发明的一实施例中，所述第一薄膜晶体管层为一个10T3C电路或8T2C电路。
在本发明的一实施例中，所述第二薄膜晶体管层为一内部补偿型电路。
在本发明的一实施例中，所述第二薄膜晶体管层为一个7T1C电路。
在本发明的一实施例中，所述显示装置更包含：一过孔，贯穿所述第二缓冲层、所述第二薄膜晶体管层及所述平坦化层；及一阳极金属层，设置于所述平坦化层上，其中所述第一薄膜晶体管层通过所述过孔与所述阳极金属层相连接。
在本发明的一实施例中，所述第一薄膜晶体管层及所述第二薄膜晶体管层成交错方式设置。
再者，本发明另一实施例提供一种显示装置，包含：一弯折区及一非弯折区，所述非弯折区具有一有源区域；及一第一薄膜晶体管层及一第二薄膜晶体管层，设置于所述有源区域内，其中所述第二薄膜晶体管层设置于所述第一薄膜晶体管层上。
在本发明的一实施例中，所述第一薄膜晶体管层包含一扫描线电路及一发光控制线(EM)电路。
在本发明的一实施例中，所述第二薄膜晶体管层为一内部补偿型电路。
在本发明的一实施例中，所述第二薄膜晶体管层为一个7T1C电路。
在本发明的一实施例中，所述显示装置更包含：一基板；一第一缓冲层，设置于所述基板上，所述第一薄膜晶体管层设置于所述第一缓冲层上；一第二缓冲层，设置于所述第一薄膜晶体管层上，所述第二薄膜晶体管层设置于所述第二缓冲层上；及一平坦化层，设置于所述第二薄膜晶体管层上。
在本发明的一实施例中，所述弯折区具有一深孔贯穿所述第一薄膜晶体管层、所述第二缓冲层及所述第二薄膜晶体管层，其中所述平坦化层填入所述深孔中。
在本发明的一实施例中，所述显示装置更包含：一过孔，贯穿所述第二缓冲层、所述第二薄膜晶体管层及所述平坦化层；及一阳极金属层，设置于所述平坦化层上，其中所述第一薄膜晶体管层通过所述过孔与所述阳极金属层相连接。
在本发明的一实施例中，所述第一薄膜晶体管层及所述第二薄膜晶体管层成交错方式设置。
另外，本发明又一实施例另提供一种显示装置的制造方法，包含步骤：提供一基板；形成一第一缓冲层于所述基板上；形成一第一薄膜晶体管层于所述第一缓冲层上；形成一第二缓冲层于所述第一薄膜晶体管层上；形成一第二薄膜晶体管层于所述第二缓冲层上；形成一深孔于所述第二薄膜晶体管层的至少两个薄膜晶体管之间，并贯穿所述第一薄膜晶体管层、所述第二缓冲层及所述第二薄膜晶体管层；及设置一平坦化层于所述第二薄膜晶体管层上并填入所述深孔中。
在本发明的一实施例中，所述第一薄膜晶体管层包含一扫描线电路及一发光控制线(EM)电路。
在本发明的一实施例中，所述第二薄膜晶体管层为一内部补偿型电路。
在本发明的一实施例中，所述第二薄膜晶体管层为一个7T1C电路。
在本发明的一实施例中，所述第一薄膜晶体管层及所述第二薄膜晶体管层成交错方式设置。
 有益效果
与现有技术相比较，本发明的显示装置及其制造方法，可以通过将设置在显示装置外围的非有源区域及显示装置下方的弯折区的多个电路结构设置在有源区域，这样可以提高显示装置的屏占比。再者，本发明的显示装置及其制造方法，可以通过将深孔设置在显示装置的弯折区并贯穿显示装置的弯折区的无机层，如此可以解决现有技术中显示装置的弯折区的无机层在经过多次弯折后易发生断裂或因显示元件的材料劣化造成电阻变大或薄膜晶体管结构极易受损的问题。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1是本发明实施例的显示装置的剖面示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图1所示，本发明实施例为达成本发明的前述目的，提供一种显示装置1。所述显示装置1包含：一第一薄膜晶体管层及一第二薄膜晶体管层，所述第二薄膜晶体管层设置于所述第一薄膜晶体管层上。优选地，所述第一薄膜晶体管层包含一扫描线电路及一发光控制线(EM)电路。所述第二薄膜晶体管层为一内部补偿型电路。优选地，所述第二薄膜晶体管层为一内部补偿型电路。可选地，所述第一薄膜晶体管层为一个10T3C电路或8T2C电路，其中10T3C电路是由10个TFT和3个存储电容组成，8T2C电路是由8个TFT和2个存储电容组成。可选地，所述第二薄膜晶体管层为一个7T1C电路，其中7T1C电路是由7个TFT和1个存储电容组成。可选地，所述第一薄膜晶体管层具有至少两组薄膜晶体管，其中一第一组的薄膜晶体管设置为依次打开所述第一薄膜晶体管层中扫描栅极的讯号，完成像素的复位与数据写入，以决定发光的灰阶，其中一第二组的薄膜晶体管设置为依次打开所述第一薄膜晶体管层中所述发光控制线的栅极讯号，以控制一整行像素发光与否。
本发明将于下文利用图1逐一详细说明本发明实施例上述各元件的细部构造、组装关系及其运作原理。所述显示装置1包含：一弯折区BA及一非弯折区，所述非弯折区具有一有源区域AA。一第一薄膜晶体管层及一第二薄膜晶体管层，设置于所述有源区域AA内，其中所述第二薄膜晶体管层设置于所述第一薄膜晶体管层上。另外地，所述显示装置1更包含：一基板102、一第一缓冲层103、一第一薄膜晶体管层、一第二缓冲层106、一第二薄膜晶体管层及一平坦化层109。所述基板102可以为一柔性基板，例如，一聚酰亚胺基板。可选地，所述基板102的下方可设置有一载板101，例如，一玻璃基板。所述第一缓冲层103，设置于所述基板102上。所述第一薄膜晶体管层设置于所述第一缓冲层103上。可选地，所述第一薄膜晶体管层包含：一第一有源层111、一第一栅极绝缘层104、一第一栅极113、一第二栅极绝缘层105、一第一源极/漏极114、一第一源极/漏极过孔115。所述第一有源层111，设置于所述第一缓冲层103上，且所述第一有源层111具有一第一有源层参杂区112。所述第一栅极绝缘层104，设置于所述第一有源层111上并覆盖所述第一有源层111。所述第一栅极113，设置于所述第一栅极绝缘层104。所述第二栅极绝缘层105，设置于所述第一栅极113上并覆盖所述第一栅极113。所述第一源极/漏极114，设置于所述第二栅极绝缘层105上，并通过所述第一源极/漏极过孔115连接所述第一有源层111。所述第二缓冲层106，设置于所述第一薄膜晶体管层上。所述第二薄膜晶体管层设置于所述第二缓冲层106上。可选地，所述第二薄膜晶体管层包含：一第二有源层116、一第三栅极绝缘层107、一第二栅极1117、一第四栅极绝缘层108、一第二源极/漏极118及一第二源极/漏极过孔119。所述第二有源层116，设置于所述第二缓冲层106上。所述第三栅极绝缘层107，设置于所述第二有源层116上并覆盖所述第二有源层116。所述第二栅极117，设置于所述第三栅极绝缘层107。所述第四栅极绝缘层108，设置于所述第二栅极117上并覆盖所述第二栅极117。所述第二源极/漏极118，设置于所述第四栅极绝缘层108上，并通过所述第二源极/漏极过孔119连接所述第二有源层116。所述平坦化层109，设置于所述第二薄膜晶体管层上。可选地，所述平坦化层109设置于所述第四栅极绝缘层108上。优选地，所述弯折区BA具有一深孔120贯穿所述第一薄膜晶体管层、所述第二缓冲层106及所述第二薄膜晶体管层，其中所述平坦化层109填入所述深孔120中。可选地，所述深孔120还贯穿所述第一栅极绝缘层104、所述第二栅极绝缘层105、所述第三栅极绝缘层107及所述第四栅极绝缘层108。可选地，所述深孔120的一底部与所述第一栅极绝缘层104的一底表面齐平。换句话说，所述深孔120仅开孔到第一栅极绝缘层104并暴露出所述第一缓冲层103的一上表面。可选地，所述显示装置1还包含：一第一过孔121、一第二过孔122及一阳极金属层123。所述第一过孔121贯穿所述第二缓冲层106、所述第二薄膜晶体管层及所述平坦化层109。所述阳极金属层123，设置于所述平坦化层109上，其中所述第一薄膜晶体管层通过所述第一过孔121与所述阳极金属层123中的一第一阳极123A相连接。可选地，所述第一过孔121还贯穿所述第三栅极绝缘层107及所述第四栅极绝缘层108。所述第二过孔122贯穿所述平坦化层109，其中所述第二薄膜晶体管层通过所述第二过孔122与所述阳极金属层123中的一第二阳极123B相连接。优选地，所述显示装置1还包含：一像素界定层110及一光阻间隔物层124。所述像素界定层110设置于所述平坦化层109上。所述像素界定层110具有多个开口125，暴露出所述阳极金属层123。所述光阻间隔物层124设置于所述像素界定层110上，并相对于所述多个开口125设置。可选地，所述第二薄膜晶体管层设置于所述第一薄膜晶体管层的郑尚方。替代地，所述第一薄膜晶体管层及所述第二薄膜晶体管层以交错方式设置。可选地，所述第二缓冲层106的一厚度比所述第一缓冲层103的一厚度较厚，以避免所述第一薄膜晶体管层及所述第二薄膜晶体管层的相互干涉。可选地，所述第二缓冲层106可进一步设置另一有机层，以改善所述第一薄膜晶体管层及所述第二薄膜晶体管层的相互干涉。可选地，所述显示装置1具有两个有源区域AA设置于所述弯折区的两侧。所述两个有源区域AA中的一个具有如上所述的第一薄膜晶体管层及第二薄膜晶体管层的结构，而所述两个有源区域AA中的另一个仅设置有所述第二薄膜晶体管层。可选地，所述载板101可以在所述显示装置1制造完成后移除或保留。
再者，本发明的另一实施例提供一种显示装置1的制造方法包含步骤：提供一基板102；形成一第一缓冲层103于所述基板上；形成一第一薄膜晶体管层于所述第一缓冲层103上；形成一第二缓冲层106于所述第一薄膜晶体管层上；形成一第二薄膜晶体管层于所述第二缓冲层106上；形成一深孔120于所述第二薄膜晶体管层的至少两个薄膜晶体管之间，并贯穿所述第一薄膜晶体管层、所述第二缓冲层106及所述第二薄膜晶体管层；及设置一平坦化层109于所述第二薄膜晶体管层上并填入所述深孔120中。所述制造方法中形成所述第一薄膜晶体管层的步骤还包含步骤：形成一第一有源层111于所述第一缓冲层103上；形成一第一有源层参杂区112于所述第一有源层111；形成一第一栅极绝缘层104于所述第一有源层111上并覆盖所述第一有源层111；形成一第一栅极113于所述第一栅极绝缘层104上；形成一第二栅极绝缘层10于所述第一栅极113上并覆盖所述第一栅极113；形成第一源极/漏极114于所述第二栅极绝缘层105上；及形成一第一源极/漏极过孔115连接所述第一有源层111。所述制造方法中形成所述第二薄膜晶体管层的步骤还包含步骤：形成一第二有源层116于所述第二缓冲层106上；形成一第三栅极绝缘层107于所述第二有源层116上并覆盖所述第二有源层116；形成一第二栅极117于所述第三栅极绝缘层107上；形成一第四栅极绝缘层108于所述第二栅极117上并覆盖所述第二栅极117；及形成一第二源极/漏极118于所述第四栅极绝缘层108上，并通过一第二源极/漏极过孔119连接所述第二有源层116。可选地，所述深孔120设置于所述显示装置1的一弯折区BA处。所述深孔120贯穿所述第一薄膜晶体管层、所述第二缓冲层106及所述第二薄膜晶体管层，其中所述平坦化层109填入所述深孔120中。可选地，所述深孔120还贯穿所述第一栅极绝缘层104、所述第二栅极绝缘层105、所述第三栅极绝缘层107及所述第四栅极绝缘层108。可选地，所述制造方法还包含步骤：形成一阳极金属层123于所述平坦化层109上，其中所述第一薄膜晶体管层通过一第一过孔121与所述阳极金属层123中的一第一阳极123A相连接。可选地，所述第一过孔121还贯穿所述第三栅极绝缘层107及所述第四栅极绝缘层108。所述制造方法还包含步骤：形成一第二过孔122贯穿所述平坦化层109，其中所述第二薄膜晶体管层通过所述第二过孔122与所述阳极金属层123中的一第二阳极123B相连接。优选地，所述制造方法还包含步骤：形成一像素界定层110于所述平坦化层109上，所述像素界定层110具有多个开口125，暴露出所述阳极金属层123；及形成一光阻间隔物层124于所述像素界定层110上，并相对于所述多个开口125设置。
如上所述，相较于现有显示装置有源区域周围的非有源区域及显示装置下方的弯折区往往会设置多个电路结构造成屏占比无法提高的问题，以及解决现有技术中弯折区的无机层在经过多次弯折后易发生断裂或因显示元件的材料劣化造成电阻变大或薄膜晶体管结构极易受损的问题。本发明的显示装置及其制造方法通过将设置显示装置外围的非有源区域及显示装置下方的弯折区的多个电路结构设置在有源区域，以提高显示装置的屏占比。再者，本发明的显示装置及其制造方法，可以通过将深孔设置在显示装置的弯折区并贯穿显示装置的弯折区的无机层，如此可以解决现有技术中显示装置的弯折区的无机层在经过多次弯折后易发生断裂或因显示元件的材料劣化造成电阻变大或薄膜晶体管结构极易受损的问题。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (20)

  1. 一种显示装置，包含：
    一基板；
    一第一缓冲层，设置于所述基板上；
    一第一薄膜晶体管层，设置于所述第一缓冲层上；
    一第二缓冲层，设置于所述第一薄膜晶体管层上；
    一第二薄膜晶体管层，设置于所述第二缓冲层上；
    一深孔，于所述第二薄膜晶体管层的至少两个薄膜晶体管之间，并贯穿所述第一薄膜晶体管层、所述第二缓冲层及所述第二薄膜晶体管层；及
    一平坦化层，设置于所述第二薄膜晶体管层上并填入所述深孔中。
  2. 如权利要求1所述的显示装置，其中所述第一薄膜晶体管层包含一扫描线电路及一发光控制线(EM)电路。
  3. 如权利要求1所述的显示装置，其中所述第一薄膜晶体管层为一个10T3C电路或8T2C电路。
  4. 如权利要求1所述的显示装置，其中所述第二薄膜晶体管层为一内部补偿型电路。
  5. 如权利要求4所述的显示装置，其中所述第二薄膜晶体管层为一个7T1C电路。
  6. 如权利要求1所述的显示装置，其中所述显示装置更包含：
    一过孔，贯穿所述第二缓冲层、所述第二薄膜晶体管层及所述平坦化层；及
    一阳极金属层，设置于所述平坦化层上，
    其中所述第一薄膜晶体管层通过所述过孔与所述阳极金属层相连接。
  7. 如权利要求1所述的显示装置，其中所述第一薄膜晶体管层及所述第二薄膜晶体管层成交错方式设置。
  8. 一种显示装置，其中所述显示装置包含：
    一弯折区及一非弯折区，所述非弯折区具有一有源区域；及
    一第一薄膜晶体管层及一第二薄膜晶体管层，设置于所述有源区域内，
    其中所述第二薄膜晶体管层设置于所述第一薄膜晶体管层上。
  9. 如权利要求8所述的显示装置，其中所述第一薄膜晶体管层包含一扫描线电路及一发光控制线(EM)电路。
  10. 如权利要求8所述的显示装置，其中所述第二薄膜晶体管层为一内部补偿型电路。
  11. 如权利要求10所述的显示装置，其中所述第二薄膜晶体管层为一个7T1C电路。
  12. 如权利要求8所述的显示装置，其中所述显示装置更包含：
    一基板；
    一第一缓冲层，设置于所述基板上，所述第一薄膜晶体管层设置于所述第一缓冲层上；
    一第二缓冲层，设置于所述第一薄膜晶体管层上，所述第二薄膜晶体管层设置于所述第二缓冲层上；及
    一平坦化层，设置于所述第二薄膜晶体管层上。
  13. 如权利要求12所述的显示装置，其中所述弯折区具有一深孔贯穿所述第一薄膜晶体管层、所述第二缓冲层及所述第二薄膜晶体管层，其中所述平坦化层填入所述深孔中。
  14. 如权利要求12所述的显示装置，其中所述显示装置更包含：
    一过孔，贯穿所述第二缓冲层、所述第二薄膜晶体管层及所述平坦化层；及
    一阳极金属层，设置于所述平坦化层上，
    其中所述第一薄膜晶体管层通过所述过孔与所述阳极金属层相连接。
  15. 如权利要求8所述的显示装置，其中所述第一薄膜晶体管层及所述第二薄膜晶体管层成交错方式设置。
  16. 一种显示装置的制造方法，其中所述制造方法包含步骤：
    提供一基板；
    形成一第一缓冲层于所述基板上；
    形成一第一薄膜晶体管层于所述第一缓冲层上；
    形成一第二缓冲层于所述第一薄膜晶体管层上；
    形成一第二薄膜晶体管层于所述第二缓冲层上；
    形成一深孔于所述第二薄膜晶体管层的至少两个薄膜晶体管之间，并贯穿所述第一薄膜晶体管层、所述第二缓冲层及所述第二薄膜晶体管层；及
    设置一平坦化层于所述第二薄膜晶体管层上并填入所述深孔中。
  17. 如权利要求16所述的显示装置的制造方法，其中所述第一薄膜晶体管层包含一扫描线电路及一发光控制线(EM)电路。
  18. 如权利要求16所述的显示装置的制造方法，其中所述第二薄膜晶体管层为一内部补偿型电路。
  19. 如权利要求18所述的显示装置的制造方法，其中所述第二薄膜晶体管层为一个7T1C电路。
  20. 如权利要求16所述的显示装置的制造方法，其中所述第一薄膜晶体管层及所述第二薄膜晶体管层成交错方式设置。
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