WO2020118847A1 - 显示装置及其驱动方法 - Google Patents

显示装置及其驱动方法 Download PDF

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Publication number
WO2020118847A1
WO2020118847A1 PCT/CN2019/071819 CN2019071819W WO2020118847A1 WO 2020118847 A1 WO2020118847 A1 WO 2020118847A1 CN 2019071819 W CN2019071819 W CN 2019071819W WO 2020118847 A1 WO2020118847 A1 WO 2020118847A1
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Prior art keywords
gate
display area
phase
display device
sub
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French (fr)
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高翔
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to display arrangement, in particular to a display device and a driving method thereof.
  • the prior art implements compensation by adjusting the phase of the gate driving signal. More specifically, the display device is divided into multiple areas, and the timing controller provides multiple gate drive signals (for example, twelve) to the gate drive circuit. For example, the display device is divided into three areas, the timing controller provides twelve gate drive signals CK1-CK12 to the gate drive circuit corresponding to each area, and then the scan signal is generated by the gate drive circuit corresponding to each area .
  • the display device is divided into multiple areas, and the timing controller provides multiple gate drive signals (for example, twelve) to the gate drive circuit.
  • the display device is divided into three areas, the timing controller provides twelve gate drive signals CK1-CK12 to the gate drive circuit corresponding to each area, and then the scan signal is generated by the gate drive circuit corresponding to each area .
  • the gate drive circuit corresponding to the first area, the gate drive circuit corresponding to the second area, and the gate drive circuit corresponding to the third area receive the gate drive signal CK1 at the same time. Then, the gate drive circuit corresponding to the first area, the gate drive circuit corresponding to the second area, and the gate drive circuit corresponding to the third area receive the gate drive signal CK2 at the same time.
  • the prior art is to adjust the phase of the gate drive circuit corresponding to the second area to receive the gate drive signal CK1 later than the gate drive corresponding to the first area
  • the circuit receives the phase of the gate drive signal CK1 and adjusts the phase of the gate drive circuit corresponding to the third area to receive the gate drive signal CK1 later than the phase of the gate drive circuit corresponding to the second area to receive the gate drive signal CK1 .
  • the timing controller provides the source drive unit with the same trigger pulse (TP) signal (that is, the signal that latches the data and writes the data) corresponding to the first region to the third region.
  • TP trigger pulse
  • the purpose of the present disclosure is to provide a display device and a driving method thereof, which can solve the problems of complicated calculation and resource consumption in the prior art.
  • a display device has a display area, the display area includes a plurality of sub-display areas, the display device includes a plurality of source lines; a plurality of gate lines, the plurality of sources A plurality of pixels are defined by the electrode lines and the plurality of gate lines; at least one source driving unit is used to provide data signals to the plurality of source lines; at least one gate driving unit includes a plurality of A gate driving circuit that provides scanning signals by the plurality of gate lines; and a timing controller for providing a plurality of gate driving signals to the plurality of gate driving circuits and providing the source driving unit through adjustment
  • the phase of the trigger pulse signal to adjust the pixel charging time of the plurality of sub-display areas, wherein the timing controller adjusts the phase of the trigger pulse signal corresponding to the sub-display area that receives the scan signal later is earlier and earlier
  • the phase of the trigger pulse signal corresponding to the sub-display area receiving the scan signal, the phase of the trigger pulse signal is obtained according to the first gate line
  • the timing controller provides the same gate driving signal to the plurality of gate driving circuits in the same phase.
  • the display device further has a non-display area, and the plurality of gate driving circuits are disposed on the non-display area.
  • a display device has a display area, the display area includes a plurality of sub-display areas, the display device includes a plurality of source lines; a plurality of gate lines, the plurality of sources A plurality of pixels are defined by the electrode lines and the plurality of gate lines; at least one source driving unit is used to provide data signals to the plurality of source lines; at least one gate driving unit includes a plurality of A gate driving circuit that provides scanning signals by the plurality of gate lines; and a timing controller for providing a plurality of gate driving signals to the plurality of gate driving circuits and providing the source driving unit through adjustment The phase of the trigger pulse signal to adjust the pixel charging time of the multiple sub-display areas.
  • the timing controller adjusts the phase of the trigger pulse signal corresponding to the sub display area receiving the scan signal later than the trigger pulse signal corresponding to the sub display area receiving the scan signal earlier Phase.
  • the phase of the trigger pulse signal is obtained according to the first gate line, the gate line located in the middle of the display area, and the last gate line.
  • the timing controller provides the same gate driving signal to the plurality of gate driving circuits in the same phase.
  • the display device further has a non-display area, and the plurality of gate driving circuits are disposed on the non-display area.
  • the display device has a display area, the display area includes a plurality of sub-display areas, the display device includes a plurality of source lines, a plurality of gate lines, at least A source driving unit, at least one gate driving unit, and a timing controller, the plurality of source lines and the plurality of gate lines define a plurality of pixels, and the gate driving unit includes a plurality of gate drives Circuit, the driving method of the display device includes: the timing controller provides a plurality of gate driving signals to the plurality of gate driving circuits; and the timing controller provides the source driving unit by adjusting the Trigger the phase of the pulse signal to adjust the pixel charging time of the plurality of sub-display areas.
  • the timing controller adjusts the phase of the trigger pulse signal corresponding to the sub display area receiving the scan signal later than the trigger pulse signal corresponding to the sub display area receiving the scan signal earlier Phase.
  • the phase of the trigger pulse signal is obtained according to the first gate line, the gate line located in the middle of the display area, and the last gate line.
  • the timing controller provides the same gate driving signal to the plurality of gate driving circuits in the same phase.
  • the display device further has a non-display area, and the plurality of gate driving circuits are disposed on the non-display area.
  • the timing controller adjusts the pixel charging time of different sub-display areas by adjusting the phase of the trigger pulse signal provided to the source driving unit.
  • the timing controller does not adjust the phase of the gate driving signal provided to the gate driving circuit.
  • the disclosed method for adjusting the phase of the trigger pulse signal is simpler in operation and consumes less resources.
  • FIG. 1 shows a display device according to an embodiment of the present disclosure.
  • FIG. 2 shows the gate driving signals provided by the timing controller of FIG. 1 to the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit, and the timing controller provides to the source driving unit Timing diagram of the trigger pulse signal.
  • Figure 3 shows the relationship between the phase number of the trigger pulse signal and the gate line.
  • Figure 4 shows the relationship between charging time and gate line.
  • FIG. 5 shows a flowchart of a driving method of a display device according to an embodiment of the present disclosure.
  • FIG. 1 shows a display device according to an embodiment of the present disclosure.
  • the display device has a display area 10 and a non-display area 20.
  • the display device includes a plurality of source lines S1-S3840, a plurality of gate lines G1-G2160, at least one source driving unit 12 (one source driving unit 12 is shown in the figure), and at least one gate driving unit 14 (FIG. Shows a gate drive unit), and a timing controller (Timing Controller) 16.
  • the plurality of source lines S1-S3840 and the plurality of gate lines G1-G2160 are disposed on the display area 10. More specifically, the plurality of source lines S1-S3840 are disposed on the display area 10 and extend to the source driving unit 12. The plurality of gate lines G1-G2160 are disposed on the display area 10 and extend to the gate driving unit 14. The plurality of source lines S1-S3840 are formed along a first direction. The plurality of gate lines G1-G2160 are formed along a second direction. The first direction is perpendicular to the second direction.
  • the source lines S1-S3840 and the gate lines G1-G2160 define a plurality of pixels 18. Each pixel 18 is electrically connected to a thin film transistor 20.
  • the source driving unit 12 is disposed on the non-display area 20.
  • the source driving unit 12 is electrically connected to the plurality of source lines S1-S3840 and is used to provide data signals to the plurality of source lines S1-S3840, and the data signals are used to write the pixels 18 .
  • the gate driving unit 14 is disposed on the non-display area 20.
  • the gate driving unit 14 includes a plurality of gate driving circuits for providing scan signals to the gate lines G1-G2160.
  • the gate driving unit 14 includes a first gate driving circuit 140, a second gate driving circuit 142, and a third gate driving circuit 144.
  • the gate driving unit 14 of the present disclosure is not limited to three gate driving circuits.
  • the first gate driving circuit 140, the second gate driving circuit 142 and the third gate driving circuit 144 are disposed on the non-display area 20.
  • the first gate driving circuit 140, the second gate driving circuit 142, and the third gate driving circuit 144 are gate driver on array (GOA) circuits.
  • GOA gate driver on array
  • the first gate driving circuit 140 is electrically connected to the gate lines G1-G720 and used to provide scan signals to the gate lines G1-G720 to turn on the thin film corresponding to the gate lines G1-G720 Transistor 20.
  • the second gate driving circuit 142 is electrically connected to the gate lines G721-G1440 and used to provide scan signals to the gate lines G721-G1440 to turn on the thin film corresponding to the gate lines G721-G1440 Transistor 20.
  • the third gate driving circuit 144 is electrically connected to the gate lines G1441-G2160 and used to provide scan signals to the gate lines G1441-G2160 to turn on the thin film corresponding to the gate lines G1441-G2160 Transistor 20.
  • the timing controller 16 is disposed on the non-display area 20 and is electrically connected to the source driving unit 12 and the gate driving unit 14. The timing controller 16 is used to control the timing when the source driving unit 12 writes to the pixel 18.
  • the timing controller 16 sequentially provides a plurality of gate driving signals CK1-CK12 to the first gate driving circuit 140, the second gate driving circuit 142, and the third gate driving circuit 144 (such as 2), so that the first gate driving circuit 140, the second gate driving circuit 142, and the third gate driving circuit 144 generate a scan signal that turns on the thin film transistor 20.
  • the display area 10 includes multiple sub-display areas.
  • the display area 10 includes a first sub-display area A1, a second sub-display area A2, and a third sub-display area A3.
  • the display area 10 of the present disclosure is not limited to three sub-display areas.
  • the first sub-display area A1 includes gate lines G1-G720 and corresponds to the first gate driving circuit 140.
  • the second sub-display area A2 includes gate lines G721-G1440 and corresponds to the second gate driving circuit 142.
  • the third sub-display area A3 includes gate lines G1441-G2160 and corresponds to the third gate driving circuit 144.
  • FIG. 2 shows the gate driving signals provided by the timing controller 16 of FIG. 1 to the first gate driving circuit 140, the second gate driving circuit 142 and the third gate driving circuit 144.
  • CK1-CK12 and the timing diagram of the trigger pulse signal TP that is, the signal to latch data and write data provided by the timing controller 16 to the source driving unit 12.
  • the gate drive signals CK1-CK12 output by the timing controller 16 are sequentially provided to the first gate drive circuit 140, the second gate drive circuit 142, and the third gate drive circuit 144.
  • the same gate drive signal provided by the timing controller 16 to the first gate drive circuit 140, the second gate drive circuit 142, and the third gate drive circuit 144 has the same phase.
  • the timing controller 16 supplies the first gate driving circuit 140, the second gate driving circuit 142, and the third gate driving circuit 144 with the same phase of the gate driving signal CK1 .
  • the timing controller 16 supplies the first gate driving circuit 140, the second gate driving circuit 142, and the third gate driving circuit 144 with the same phase of the gate driving signal CK2, and so on .
  • the gate driving signals CK1-CK12 output by the timing controller 16 and the data signals written by the source driving unit 12 have a delay inconsistency problem, resulting in the charging of the pixels 18 in the second sub-display area A2
  • the time is shorter than the charging time of the pixels 18 of the first sub-display area A1
  • the charging time of the pixels 18 of the third sub-display area A3 is shorter than the charging time of the pixels 18 of the second sub-display area A2.
  • the timing controller 16 does not adjust the phase of the gate driving signals CK1-CK12.
  • the timing controller 16 adjusts the trigger pulse signal TP (that is, the lock) provided to the source driving unit 12 Adjust the pixel charging time of the first sub-display area A1, the second sub-display area A2 and the third sub-display area A3.
  • the timing controller 16 adjusts the phase of the trigger pulse signal TP corresponding to the sub-display area receiving the scan signal later than the phase of the trigger pulse signal TP corresponding to the sub-display area receiving the scan signal earlier.
  • the second sub-display area A2 receives the scan signal later than the first sub-display area A1 receives the scan signal
  • the third sub-display area A3 receives the scan signal later than the second sub-display area A2
  • the time to receive the scan signal is late. Therefore, as shown in FIG.
  • the timing controller 16 adjusts the phase of the trigger pulse signal TP corresponding to the second sub-display area A2 earlier than that of the trigger pulse signal TP corresponding to the first sub-display area A1 And adjust the phase of the trigger pulse signal TP corresponding to the third sub-display area A3 earlier than the phase of the trigger pulse signal TP corresponding to the second sub-display area A2, whereby the second sub The charging time of the pixels 18 in the display area A2 and the charging time of the pixels 18 in the third sub-display area A3.
  • the following will explain how to calculate the phase of the trigger pulse signal TP corresponding to different sub-display areas.
  • the target of the charging time T_chargetop of the first gate line G1 is set to 1 microsecond ( ⁇ s)
  • the target of the charging time T_chargemid of the gate line G1080 located in the middle of the display area 10 is set to 1.3 ⁇ s
  • the target of the charging time T_chargebtm of the last gate line G2160 is set to 1.5 ⁇ s.
  • the clock frequency Fclk of the display device is 74.26 MHz (MegaHertz, MHz)
  • the source driving unit 12 starts to receive the trigger pulse signal TP transmitted by the timing controller 16 Count and write a data signal to the pixel 18 electrically connected to the first gate line G1 when counting the 200th pulse.
  • the trigger pulse signal TP_up(n of the gate line (ie the upper half of the display area 10) between the first gate line G1 and the gate line G1080 (located in the middle of the display area 10) ) Is calculated as follows. First, find the phase of a pulse that adjusts the trigger pulse signal TP every few gate lines:
  • TP_up_c Number of gate line rows/((T_chargemid-T_chargetop)/Tclk)
  • phase TP_up(n) of the trigger pulse signal of the gate line in the nth row can be calculated by the following formula:
  • the charging time T_up_charge(n) of the pixel 18 of the gate line of the nth row can be calculated by the following formula:
  • T_up_charge(n) T_chargetop+(TP_up(n)-initial value) ⁇ Tclk
  • the trigger pulse signal TP_down(n(n) of the gate line between the gate line G1081 (located in the middle of the display area 10) and the gate line G2160 (ie, the lower half of the display area 10) ) Is calculated as follows. First, find the phase of a pulse that adjusts the trigger pulse signal TP every few gate lines:
  • TP_down_c Number of gate line rows/((T_chargebtm-T_chargemid)/Tclk)
  • phase TP_down(n) of the trigger pulse signal of the gate line in the nth row can be calculated by the following formula:
  • TP_down(n) TP_up(1080)-(n-1080)/TP_down_c
  • the charging time T_down_charge(n) of the pixel 18 of the gate line of the nth row can be calculated by the following formula:
  • T_down_charge(n) T_chargetop+(TP_down(n)-initial value) ⁇ Tclk
  • FIG. 3 shows the relationship between the phase of the trigger pulse signal TP and the gate line.
  • Figure 4 shows the relationship between charging time and gate line.
  • the phase corresponding to the gate line G1 is 200.
  • the phase corresponding to the gate line G1080 is about 177 (representing that the source driving unit 12 starts counting after receiving the trigger pulse signal TP transmitted by the timing controller 16, and writes the data signal when counting the 177th pulse Into the pixel 18 electrically connected to the gate line G1080.
  • the phase corresponding to the gate line G2160 is about 162, which represents that the source driving unit 12 receives the trigger pulse signal TP transmitted by the timing controller 16 Counting is started, and a data signal is written to the pixel 18 electrically connected to the gate line G2160 when counting the 162nd pulse.
  • the timing controller 16 adjusts the phase of the trigger pulse signal TP corresponding to the sub display area receiving the scan signal later than the trigger pulse signal corresponding to the sub display area receiving the scan signal earlier TP phase. Therefore, as shown in FIG. 4, the charging time of the gate line of the second sub-display area A2 is longer than the charging time of the gate line of the first sub-display area A1, and the third sub-display area A3 The charging time of the gate line of is longer than the charging time of the gate line of the first sub-display area A2.
  • phase of the trigger pulse signal TP is based on the first gate line, the gate line located in the middle of the display area (may be one of the second sub-display areas A2), and the last gate line Got.
  • FIG. 5 is a flowchart of a driving method of a display device according to an embodiment of the present disclosure.
  • the display device has a display area, and the display area includes a plurality of sub-display areas.
  • the display device includes multiple source lines, multiple gate lines, at least one source driving unit, at least one gate driving unit, and a timing controller.
  • the plurality of source lines and the plurality of gate lines define a plurality of pixels.
  • the gate driving unit includes a plurality of gate driving circuits.
  • the driving method of the display device includes the following operations.
  • the timing controller provides a plurality of gate driving signals to the plurality of gate driving circuits.
  • the timing controller adjusts the pixel charging time of the plurality of sub-display areas by adjusting the phase of the trigger pulse signal provided to the source driving unit.
  • the timing controller adjusts the phase of the trigger pulse signal corresponding to the sub display area receiving the scan signal later than the trigger pulse signal corresponding to the sub display area receiving the scan signal earlier Phase.
  • the phase of the trigger pulse signal is obtained according to the first gate line, the gate line located in the middle of the display area, and the last gate line.
  • the plurality of gate drive signals provided by the timing controller to the plurality of gate drive circuits have the same phase.
  • the display device further has a non-display area, and the plurality of gate driving circuits are disposed on the non-display area.
  • the timing controller adjusts the pixel charging time of different sub-display areas by adjusting the phase of the trigger pulse signal provided to the source driving unit.
  • the timing controller does not adjust the phase of the gate driving signal provided to the gate driving circuit.
  • the disclosed method for adjusting the phase of the trigger pulse signal is simpler in operation and consumes less resources.

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Abstract

一种显示装置及其驱动方法，具有一显示区（10），显示区（10）包括多个子显示区（A1、A2、A3），显示装置包括多条源极线（S1-S3840）；多条栅极线（G1-G2160），多条源极线（S1-S3840）及多条栅极线（G1-G2160）定义出多个像素（18）；至少一源极驱动单元（12），用于向多条源极线（S1-S3840）提供数据信号；至少一栅极驱动单元（14），包括多个用于向多条栅极线（G1-G2160）提供扫描信号的栅极驱动电路（140、142、144）；以及时序控制器（16），用于向多个栅极驱动电路（140、142、144）提供多个栅极驱动信号（CK1-CK12）并通过调整向源极驱动单元（12）提供的触发脉冲信号（TP）的相位来调整多个子显示区（A1、A2、A3）的像素充电时间。

Description

显示装置及其驱动方法 技术领域
本揭示涉及显示排列，特别是涉及一种显示装置及其驱动方法。
 背景技术
为了解决栅极驱动信号与数据信号延迟不一致的问题，现有技术是通过调整栅极驱动信号的相位来实现补偿。更明确地说，显示装置会分成多个区域，时序控制器向栅极驱动电路提供多个栅极驱动信号（例如十二个）。举例来说，显示装置分成三个区域，时序控制器提供十二个栅极驱动信号CK1-CK12给每一个区域对应的栅极驱动电路，再由每一个区域对应的栅极驱动电路产生扫描信号。
理论上，第一个区域对应的栅极驱动电路、第二个区域对应的栅极驱动电路及第三个区域对应的栅极驱动电路会同时接收栅极驱动信号CK1。然后，第一个区域对应的栅极驱动电路、第二个区域对应的栅极驱动电路及第三个区域对应的栅极驱动电路会同时接收栅极驱动信号CK2。栅极驱动信号CK2-3-CK12依此类推。
然而，为了解决栅极驱动信号与数据信号延迟不一致的问题，现有技术是调整第二个区域对应的栅极驱动电路接收栅极驱动信号CK1的相位晚于第一个区域对应的栅极驱动电路接收栅极驱动信号CK1的相位，并调整第三个区域对应的栅极驱动电路接收栅极驱动信号CK1的相位晚于第二个区域对应的栅极驱动电路接收栅极驱动信号CK1的相位。时序控制器向源极驱动单元提供与第一个区域至第三个区域的对应的触发脉冲（TP）信号（即锁存数据与写入数据的信号）的相位则相同。也就是说，通过延迟与第二个区域及第三个区域对应的栅极驱动信号CK1-CK12的相位来增加第二个区域及第三个区域的画素充电时间，藉此达到补偿的目的。
由于需要同时调整十二个栅极驱动信号CK1-CK12的相位，造成运算复杂且耗费资源的问题。
因此需要对现有技术中的问题提出解决方法。
 技术问题
本揭示的目的在于提供一种显示装置及其驱动方法，其能解决现有技术中运算复杂且耗费资源的问题。
 技术解决方案
为解决上述问题，本揭示提供的一种显示装置具有一显示区，所述显示区包括多个子显示区，所述显示装置包括多条源极线；多条栅极线，所述多条源极线及所述多条栅极线定义出多个像素；至少一源极驱动单元，用于向所述多条源极线提供数据信号；至少一栅极驱动单元，包括多个用于向所述多条栅极线提供扫描信号的栅极驱动电路；以及时序控制器，用于向所述多个栅极驱动电路提供多个栅极驱动信号并通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整所述多个子显示区的像素充电时间，其中所述时序控制器调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号的相位，所述触发脉冲信号的相位根据第一条栅极线、位于所述显示区中间的栅极线以及最后一条栅极线而得。
于一实施例中，所述时序控制器向所述多个栅极驱动电路提供的同一个栅极驱动信号的相位相同。
于一实施例中，所述显示装置还具有一非显示区，所述多个栅极驱动电路设置于所述非显示区上。
为解决上述问题，本揭示提供的一种显示装置具有一显示区，所述显示区包括多个子显示区，所述显示装置包括多条源极线；多条栅极线，所述多条源极线及所述多条栅极线定义出多个像素；至少一源极驱动单元，用于向所述多条源极线提供数据信号；至少一栅极驱动单元，包括多个用于向所述多条栅极线提供扫描信号的栅极驱动电路；以及时序控制器，用于向所述多个栅极驱动电路提供多个栅极驱动信号并通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整所述多个子显示区的像素充电时间。
于一实施例中，所述时序控制器调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号的相位。
于一实施例中，所述触发脉冲信号的相位根据第一条栅极线、位于所述显示区中间的栅极线以及最后一条栅极线而得。
于一实施例中，所述时序控制器向所述多个栅极驱动电路提供的同一个栅极驱动信号的相位相同。
于一实施例中，所述显示装置还具有一非显示区，所述多个栅极驱动电路设置于所述非显示区上。
本揭示提供的一种显示装置的驱动方法中，所述显示装置具有一显示区，所述显示区包括多个子显示区，所述显示装置包括多条源极线、多条栅极线、至少一源极驱动单元、至少一栅极驱动单元以及时序控制器，所述多条源极线及所述多条栅极线定义出多个像素，所述栅极驱动单元包括多个栅极驱动电路，所述显示装置的驱动方法包括：所述时序控制器向所述多个栅极驱动电路提供多个栅极驱动信号；以及所述时序控制器通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整所述多个子显示区的像素充电时间。
于一实施例中，所述时序控制器调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号的相位。
于一实施例中，所述触发脉冲信号的相位根据第一条栅极线、位于所述显示区中间的栅极线以及最后一条栅极线而得。
于一实施例中，所述时序控制器向所述多个栅极驱动电路提供的同一个栅极驱动信号的相位相同。
于一实施例中，所述显示装置还具有一非显示区，所述多个栅极驱动电路设置于所述非显示区上。
 有益效果
本揭示之显示装置及其驱动方法中，所述时序控制器通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整不同子显示区的像素充电时间。所述时序控制器不调整向所述栅极驱动电路提供的栅极驱动信号的相位。本揭示调整触发脉冲信号的相位与现有技术中调整栅极驱动信号的相位相比，运算较为简便且耗费资源较少。
 附图说明
图1显示根据本揭示一实施例之显示装置。
图2显示图1的时序控制器向第一栅极驱动电路、第二栅极驱动电路及所述第三栅极驱动电路提供的栅极驱动信号，以及时序控制器向源极驱动单元提供的触发脉冲信号的时序图。
图3显示触发脉冲信的相位号与栅极线的关系图。
图4显示充电时间与栅极线的关系图。
图5显示根据本揭示一实施例之显示装置的驱动方法流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
请参阅图1，图1显示根据本揭示一实施例之显示装置。
所述显示装置具有一显示区10以及一非显示区20。所述显示装置包括多条源极线S1-S3840、多条栅极线G1-G2160、至少一源极驱动单元12（图中显示一个源极驱动单元12）至少一栅极驱动单元14（图中显示一个栅极驱动单元）、以及一时序控制器（Timing Controller）16。
所述多条源极线S1-S3840及所述多条栅极线G1-G2160设置于所述显示区10上。更明确地说，所述多条源极线S1-S3840设置于所述显示区10上并延伸至所述源极驱动单元12。所述多条栅极线G1-G2160设置于所述显示区10上并延伸至所述栅极驱动单元14。所述多条源极线S1-S3840沿一第一方向形成。所述多条栅极线G1-G2160沿一第二方向形成。所述第一方向垂直于所述第二方向。所述源极线S1-S3840及所述栅极线G1-G2160定义出多个像素18。每一所述像素18电性连接至一薄膜晶体管20。
所述源极驱动单元12设置于所述非显示区20上。所述源极驱动单元12电性连接至所述多条源极线S1-S3840并用于向所述多条源极线S1-S3840提供数据信号，所述数据信号用于写入所述像素18。
所述栅极驱动单元14设置于所述非显示区20上。所述栅极驱动单元14包括多个用于向所述栅极线G1-G2160提供扫描信号的栅极驱动电路。于本实施例中，所述栅极驱动单元14包括第一栅极驱动电路140、第二栅极驱动电路142以及第三栅极驱动电路144。然而本揭示之栅极驱动单元14并不限于三个栅极驱动电路。所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144设置于所述非显示区20上。也就是说，所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144为阵列基板行驱动（Gate driver On Array，GOA）电路。所述第一栅极驱动电路140电性连接至所述栅极线G1-G720并用于向所述栅极线G1-G720提供扫描信号以导通与所述栅极线G1-G720对应的薄膜晶体管20。所述第二栅极驱动电路142电性连接至所述栅极线G721-G1440并用于向所述栅极线G721-G1440提供扫描信号以导通与所述栅极线G721-G1440对应的薄膜晶体管20。所述第三栅极驱动电路144电性连接至所述栅极线G1441-G2160并用于向所述栅极线G1441-G2160提供扫描信号以导通与所述栅极线G1441-G2160对应的薄膜晶体管20。
所述时序控制器16设置于所述非显示区20上并电性连接至所述源极驱动单元12及所述栅极驱动单元14。所述时序控制器16用于控制所述源极驱动单元12写入所述像素18的时序。
所述时序控制器16向所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144依序提供多个栅极驱动信号CK1-CK12（如图2所示），以使所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144产生导通所述薄膜晶体管20的扫描信号。
所述显示区10包括多个子显示区。于本实施例中，所述显示区10包括第一子显示区A1、第二子显示区A2以及第三子显示区A3。然而本揭示之显示区10并不限于三个子显示区。所述第一子显示区A1包括栅极线G1-G720且对应至所述第一栅极驱动电路140。所述第二子显示区A2包括栅极线G721-G1440且对应至所述第二栅极驱动电路142。所述第三子显示区A3包括栅极线G1441-G2160且对应至所述第三栅极驱动电路144。
请参阅图1以及图2，图2显示图1的时序控制器16向第一栅极驱动电路140、第二栅极驱动电路142及所述第三栅极驱动电路144提供的栅极驱动信号CK1-CK12，以及时序控制器16向源极驱动单元12提供的触发脉冲信号TP（即锁存数据与写入数据的信号）的时序图。
所述时序控制器16输出的栅极驱动信号CK1-CK12依序提供给所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144。所述时序控制器16向所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144提供的同一个栅极驱动信号的相位相同。也就是说，所述时序控制器16向所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144提供的栅极驱动信号CK1的相位相同。所述时序控制器16向所述第一栅极驱动电路140、所述第二栅极驱动电路142以及所述第三栅极驱动电路144提供的栅极驱动信号CK2的相位相同，依此类推。
由于所述时序控制器16输出的栅极驱动信号CK1-CK12与所述源极驱动单元12写入的数据信号会有延迟不一致的问题，导致所述第二子显示区A2的像素18的充电时间短于所述第一子显示区A1的像素18的充电时间，且所述第三子显示区A3的像素18的充电时间短于所述第二子显示区A2的像素18的充电时间。
于现有技术中，调整提供给所述第二栅极驱动电路142的栅极驱动信号CK1的相位晚于提供给所述第一栅极驱动电路140的栅极驱动信号CK1的相位，并调整提供给所述第三栅极驱动电路144的栅极驱动信号CK1的相位晚于提供给所述第二栅极驱动电路142的栅极驱动信号CK1的相位。同样地，栅极驱动信号CK2-CK12的相位也需要调整。然而，由于需要调整十二个栅极驱动信号CK1-CK12的相位，造成运算复杂且耗费资源的问题。
本揭示之显示装置中，所述时序控制器16不调整栅极驱动信号CK1-CK12的相位，所述时序控制器16通过调整向所述源极驱动单元12提供的触发脉冲信号TP（即锁存数据与写入数据的信号）的相位来调整所述第一子显示区A1、所述第二子显示区A2以及所述第三子显示区A3的像素充电时间。
所述时序控制器16调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号TP的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号TP的相位。第二子显示区A2接收所述扫描信号的时间比第一子显示区A1接收所述扫描信号的时间晚，且第三子显示区A3接收所述扫描信号的时间比第二子显示区A2接收所述扫描信号的时间晚。因此，如图2所示，所述时序控制器16调整与所述第二子显示区A2对应的触发脉冲信号TP的相位早于与所述第一子显示区A1对应的触发脉冲信号TP的相位，并调整与所述第三子显示区A3对应的触发脉冲信号TP的相位早于与所述第二子显示区A2对应的触发脉冲信号TP的相位，藉此可以增加所述第二子显示区A2的像素18的充电时间以及所述第三子显示区A3的像素18的充电时间。
以下将说明如何计算不同子显示区对应的触发脉冲信号TP的相位。假设所述第一条栅极线G1的充电时间T_chargetop的目标设定为1微秒（microsecond，μs），位于所述显示区10中间的栅极线G1080的充电时间T_chargemid的目标设定为1.3μs，所述最后一条栅极线G2160的充电时间T_chargebtm的目标设定为1.5μs。所述显示装置的时钟频率Fclk为74.26兆赫（MegaHertz，MHz），时钟周期Tclk（Tclk = 1/Fclk）为13.466纳秒（nanosecond，ns）。
假设与所述第一条栅极线G1对应的触发脉冲信号TP的相位的初始值为200，代表所述源极驱动单元12在收到所述时序控制器16所传送的触发脉冲信号TP开始计数，并在计数第200个脉冲时将数据信号写入与所述第一条栅极线G1电性相连的像素18。
所述第一条栅极线G1与所述栅极线G1080（位于所述显示区10中间）之间的栅极线（即所述显示区10的上半部）的触发脉冲信号TP_up(n)的相位计算如下。首先求出每隔几条栅极线调整触发脉冲信号TP的一个脉冲的相位：
TP_up_c=栅极线行数/((T_chargemid-T_chargetop)/Tclk)
    =1080/((1.3μs-1μs)/ 13.466 ns)=48.47≈48
也就是说，每48条栅极线调整一个脉冲的相位。因此，第n行栅极线的触发脉冲信号的相位TP_up(n)可由下式计算：
TP_up(n)=初始值-(n-1)/TP_up_c =200-(n-1)/48
第n行栅极线的像素18的充电时间T_up_charge(n)可由下式计算：
T_up_charge(n)= T_chargetop+(TP_up(n)-初始值) ×Tclk
= 1.0+(TP_up(n)-200) ×Tclk
同样地，所述栅极线G1081（位于所述显示区10中间）与所述栅极线G2160之间的栅极线（即所述显示区10的下半部）的触发脉冲信号TP_down(n)的相位计算如下。首先求出每隔几条栅极线调整触发脉冲信号TP的一个脉冲的相位：
TP_down_c=栅极线行数/((T_chargebtm-T_chargemid)/Tclk)
    =1080/((1.5μs-1.3μs)/ 13.466 ns)=72.7≈73
也就是说，每73条栅极线调整一个脉冲的相位。因此，第n行栅极线的触发脉冲信号的相位TP_down(n)可由下式计算：
TP_down(n)=TP_up(1080)-(n-1080)/TP_down_c
=177-(n-1080)/73
第n行栅极线的像素18的充电时间T_down_charge(n)可由下式计算：
T_down_charge(n)= T_chargetop+(TP_down(n)-初始值) ×Tclk
= 1.0+(TP_ down(n)-200) ×Tclk
请参阅图3以及图4，图3显示触发脉冲信号TP的相位与栅极线的关系图。图4显示充电时间与栅极线的关系图。
如图3所示，栅极线G1对应的相位为200。栅极线G1080对应的相位约为177（代表所述源极驱动单元12在收到所述时序控制器16所传送的触发脉冲信号TP开始计数，并在计数第177个脉冲时将数据信号写入与所述栅极线G1080电性相连的像素18。栅极线G2160对应的相位约为162，代表所述源极驱动单元12在收到所述时序控制器16所传送的触发脉冲信号TP开始计数，并在计数第162个脉冲时将数据信号写入与所述栅极线G2160电性相连的像素18。
从上述可知，所述时序控制器16调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号TP的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号TP的相位。因此，如图4所示，所述第二子显示区A2的栅极线的充电时间比所述第一子显示区A1的栅极线的充电时间长，且所述第三子显示区A3的栅极线的充电时间比所述第一子显示区A2的栅极线的充电时间长。
此外，从上述可知所述触发脉冲信号TP的相位根据第一条栅极线、位于所述显示区中间的栅极线（可以为第二子显示区A2的其中一条）以及最后一条栅极线而得。
请参阅图5，图5显示根据本揭示一实施例之显示装置的驱动方法流程图。
所述显示装置具有一显示区，所述显示区包括多个子显示区。所述显示装置包括多条源极线、多条栅极线、至少一源极驱动单元、至少一栅极驱动单元以及时序控制器。所述多条源极线及所述多条栅极线定义出多个像素。所述栅极驱动单元包括多个栅极驱动电路。所述显示装置的驱动方法包括下列操作。
于操作S10中，所述时序控制器向所述多个栅极驱动电路提供多个栅极驱动信号。
于操作S20中，所述时序控制器通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整所述多个子显示区的像素充电时间。
于一实施例中，所述时序控制器调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号的相位。
所述触发脉冲信号的相位根据第一条栅极线、位于所述显示区中间的栅极线以及最后一条栅极线而得。
所述时序控制器向所述多个栅极驱动电路提供的所述多个栅极驱动信号的相位相同。
所述显示装置还具有一非显示区，所述多个栅极驱动电路设置于所述非显示区上。
本揭示之显示装置及其驱动方法中，所述时序控制器通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整不同子显示区的像素充电时间。所述时序控制器不调整向所述栅极驱动电路提供的栅极驱动信号的相位。本揭示调整触发脉冲信号的相位与现有技术中调整栅极驱动信号的相位相比，运算较为简便且耗费资源较少。
综上所述，虽然本揭示已以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种显示装置，具有一显示区，所述显示区包括多个子显示区，所述显示装置包括：
    多条源极线；
    多条栅极线，所述多条源极线及所述多条栅极线定义出多个像素；
    至少一源极驱动单元，用于向所述多条源极线提供数据信号；
    至少一栅极驱动单元，包括多个用于向所述多条栅极线提供扫描信号的栅极驱动电路；以及
    时序控制器，用于向所述多个栅极驱动电路提供多个栅极驱动信号并通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整所述多个子显示区的像素充电时间，
    其中所述时序控制器调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号的相位，所述触发脉冲信号的相位根据第一条栅极线、位于所述显示区中间的栅极线以及最后一条栅极线而得。
  2. 根据权利要求1所述的显示装置，其中所述时序控制器向所述多个栅极驱动电路提供的同一个栅极驱动信号的相位相同。
  3. 根据权利要求1所述的显示装置，其中所述显示装置还具有一非显示区，所述多个栅极驱动电路设置于所述非显示区上。
  4. 一种显示装置，具有一显示区，所述显示区包括多个子显示区，所述显示装置包括：
    多条源极线；
    多条栅极线，所述多条源极线及所述多条栅极线定义出多个像素；
    至少一源极驱动单元，用于向所述多条源极线提供数据信号；
    至少一栅极驱动单元，包括多个用于向所述多条栅极线提供扫描信号的栅极驱动电路；以及
    时序控制器，用于向所述多个栅极驱动电路提供多个栅极驱动信号并通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整所述多个子显示区的像素充电时间。
  5. 根据权利要求4所述的显示装置，其中所述时序控制器调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号的相位。
  6. 根据权利要求4所述的显示装置，其中所述触发脉冲信号的相位根据第一条栅极线、位于所述显示区中间的栅极线以及最后一条栅极线而得。
  7. 根据权利要求4所述的显示装置，其中所述时序控制器向所述多个栅极驱动电路提供的同一个栅极驱动信号的相位相同。
  8. 根据权利要求4所述的显示装置，其中所述显示装置还具有一非显示区，所述多个栅极驱动电路设置于所述非显示区上。
  9. 一种显示装置的驱动方法，所述显示装置具有一显示区，所述显示区包括多个子显示区，所述显示装置包括多条源极线、多条栅极线、至少一源极驱动单元、至少一栅极驱动单元以及时序控制器，所述多条源极线及所述多条栅极线定义出多个像素，所述栅极驱动单元包括多个栅极驱动电路，所述显示装置的驱动方法包括：
    所述时序控制器向所述多个栅极驱动电路提供多个栅极驱动信号；以及
    所述时序控制器通过调整向所述源极驱动单元提供的触发脉冲信号的相位来调整所述多个子显示区的像素充电时间。
  10. 根据权利要求9所述的显示装置的驱动方法，其中所述时序控制器调整与越晚接收所述扫描信号的子显示区对应的触发脉冲信号的相位早于与越早接收所述扫描信号的子显示区对应的触发脉冲信号的相位。
  11. 根据权利要求9所述的显示装置的驱动方法，其中所述触发脉冲信号的相位根据第一条栅极线、位于所述显示区中间的栅极线以及最后一条栅极线而得。
  12. 根据权利要求9所述的显示装置的驱动方法，其中所述时序控制器向所述多个栅极驱动电路提供的所述多个栅极驱动信号的相位相同。
  13. 根据权利要求9所述的显示装置的驱动方法，其中所述显示装置还具有一非显示区，所述多个栅极驱动电路设置于所述非显示区上。
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