WO2020117797A1 - Composant d'appareil d'impression remplaçable - Google Patents

Composant d'appareil d'impression remplaçable Download PDF

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Publication number
WO2020117797A1
WO2020117797A1 PCT/US2019/064226 US2019064226W WO2020117797A1 WO 2020117797 A1 WO2020117797 A1 WO 2020117797A1 US 2019064226 W US2019064226 W US 2019064226W WO 2020117797 A1 WO2020117797 A1 WO 2020117797A1
Authority
WO
WIPO (PCT)
Prior art keywords
sensor
print apparatus
apparatus component
digital
replaceable print
Prior art date
Application number
PCT/US2019/064226
Other languages
English (en)
Inventor
Michael W. Cumbie
Scott A. Linn
James Michael GARDNER
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2019/026161 external-priority patent/WO2020117308A1/fr
Priority claimed from PCT/US2019/026152 external-priority patent/WO2020204951A1/fr
Priority to PL19823870T priority Critical patent/PL3691905T3/pl
Priority to AU2019392466A priority patent/AU2019392466A1/en
Priority to CA3121174A priority patent/CA3121174A1/fr
Priority to KR1020217016831A priority patent/KR20210087977A/ko
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to MX2021006233A priority patent/MX2021006233A/es
Priority to BR112021010632-4A priority patent/BR112021010632A2/pt
Priority to EP19823870.1A priority patent/EP3691905B1/fr
Priority to US16/768,652 priority patent/US11345159B2/en
Priority to ES19823870T priority patent/ES2868132T3/es
Priority to CN201980077942.0A priority patent/CN113165388B/zh
Publication of WO2020117797A1 publication Critical patent/WO2020117797A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17566—Ink level or ink residue control
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17513—Inner structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17526—Electrical contacts to the cartridge
    • B41J2/1753—Details of contacts on the cartridge, e.g. protection of contacts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17543—Cartridge presence detection or type identification
    • B41J2/17546—Cartridge presence detection or type identification electronically
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17553—Outer structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17556—Means for regulating the pressure in the cartridge
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F23/00—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm
    • G01F23/22—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water
    • G01F23/24—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of resistance of resistors due to contact with conductor fluid
    • G01F23/246—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of resistance of resistors due to contact with conductor fluid thermal devices
    • G01F23/247—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of resistance of resistors due to contact with conductor fluid thermal devices for discrete levels
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F23/00—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm
    • G01F23/80—Arrangements for signal processing
    • G01F23/802—Particular electronic circuits for digital processing equipment
    • G01F23/804—Particular electronic circuits for digital processing equipment containing circuits handling parameters other than liquid level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17566—Ink level or ink residue control
    • B41J2002/17586—Ink level or ink residue control using ink bag deformation for ink level indication
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F25/00—Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume
    • G01F25/20—Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume of apparatus for measuring liquid level

Definitions

  • Subcomponents of apparatus may communicate with one another in a number of ways. For example, Serial Peripheral Interface (SPI) protocol, Bluetooth Low Energy (BLE), Near Field Communications (NFC) or other types of digital or analog communications may be used.
  • SPI Serial Peripheral Interface
  • BLE Bluetooth Low Energy
  • NFC Near Field Communications
  • Some two-dimensional (2D) and three-dimensional (3D) printing systems include one or more replaceable print apparatus components, such as print material containers (e.g., inkjet cartridges, toner cartridges, ink supplies, 3D printing agent supplies, build material supplies etc.), inkjet printhead
  • print material containers e.g., inkjet cartridges, toner cartridges, ink supplies, 3D printing agent supplies, build material supplies etc.
  • inkjet printhead e.g., inkjet printhead
  • logic circuitry associated with the replaceable print apparatus component(s) communicate with logic circuitry of the print apparatus in which they are installed, for example communicating information such as their identity, capabilities, status and the like.
  • print material containers may include circuitry to execute one or more monitoring functions such as print material level sensing.
  • Figure 1 illustrates one example of a printing system.
  • Figure 2 illustrates one example of a replaceable print apparatus component.
  • Figure 3 illustrates one example of a print apparatus.
  • Figures 4A-4E illustrate examples of logic circuitry packages and processing circuitry.
  • Figure 5A illustrates one example arrangement of a fluid level sensor.
  • Figure 5B illustrates a perspective view of one example of a print cartridge.
  • Figure 6 illustrates another example of a replaceable print apparatus component.
  • Figure 7 illustrates another example of a printing system.
  • Inter-integrated Circuit (l 2 C, or I2C, which notation is adopted herein) protocol allows at least one‘master’ integrated circuit (1C) to communicate with at least one‘slave’ 1C, for example via a bus.
  • I2C, and other communications protocols communicate data according to a clock period. For example, a voltage signal may be generated, where the value of the voltage is associated with data. For example, a voltage value above X volts may indicate a logic“1” whereas a voltage value below X volts may indicate a logic“0”, where X is a predetermined numerical value.
  • a voltage value above X volts may indicate a logic“1”
  • a voltage value below X volts may indicate a logic“0”, where X is a predetermined numerical value.
  • Certain example print material containers have slave logic that utilize I2C communications, although in other examples, other forms of digital or analog communications could also be used.
  • a master 1C may generally be provided as part of the print apparatus (which may be referred to as the‘host’) and a replaceable print apparatus component would comprise a‘slave’ 1C, although this need not be the case in all examples.
  • the slave IC(s) may include a processor to perform data operations before responding to requests from logic circuitry of the print system.
  • Logic circuitry within a print apparatus may receive information from logic circuitry associated with a replaceable print apparatus component via a communications interface, and/or may send commands to the replaceable print apparatus component logic circuitry, which may include commands to write data to a memory associated therewith, or to read data therefrom.
  • a logic circuitry package is described. The logic circuitry package may be associated with a replaceable print apparatus component, for example being internally or externally affixed thereto, for example at least partially within the housing, and is adapted to communicate data with a print apparatus controller via a bus provided as part of the print apparatus.
  • A‘logic circuitry package’ as the term is used herein refers to one logic circuit, or more logic circuits that may be interconnected or communicatively linked to each other. Where more than one logic circuit is provided, these may be encapsulated as a single unit, or may be separately encapsulated, or not encapsulated, or some combination thereof.
  • the package may be arranged or provided on a single substrate or a plurality of substrates. In some examples, the package may be directly affixed to a cartridge wall. In some examples, the package may include an interface, for example including pads or pins.
  • the package interface may be intended to connect to a communication interface of the print apparatus component that in turn connects to a print apparatus logic circuit, or the package interface may connect directly to the print apparatus logic circuit.
  • Example packages may be configured to communicate via a serial bus interface. Where more than one logic circuit is provided, these logic circuits may be connected to each other or to the interface, to communicate through the same interface.
  • each logic circuitry package is provided with at least one processor and memory.
  • the logic circuitry package may be, or may function as, a microcontroller or secure microcontroller.
  • the logic circuitry package may be adhered to or integrated with the replaceable print apparatus component.
  • a logic circuitry package may alternatively be referred to as a logic circuitry assembly, or simply as logic circuitry or processing circuitry.
  • the logic circuitry package may respond to various types of requests (or commands) from a host (e.g., a print apparatus).
  • a first type of request may include a request for data, for example identification and/or authentication information.
  • a second type of request from a host may be a request to perform a physical action, such as performing at least one
  • a third type of request may be a request for a data processing action. There may be additional types of requests.
  • a command is also a type of request.
  • different requests are handled by different logic circuits of the package.
  • the different logic circuits may be associated with different addresses. For example,
  • cryptographically authenticated communications may be associated with secure microcontroller functions and a first I2C address, while other communications may be associated with a sensor circuit and a second and/or reconfigured I2C address. In certain examples, these other communications via the second and/or reconfigured address can be scrambled or otherwise secured, not using the key used for the secure microcontroller functions.
  • a plurality of such logic circuitry packages may be connected to an I2C bus.
  • at least one address of the logic circuitry package may be an I2C compatible address (herein after, an I2C address), for example in accordance with an I2C protocol, to facilitate directing communications between master to slaves in accordance with the I2C protocol.
  • an I2C address for example in accordance with an I2C protocol, to facilitate directing communications between master to slaves in accordance with the I2C protocol.
  • a standard I2C communications address may be 7 or 10 bits in length. In other examples, other forms of digital and/or analog communication can be used.
  • Figure 1 illustrates one example of a printing system 100.
  • the printing system 100 includes a print apparatus 102 in communication with logic circuitry associated with a replaceable print apparatus component 104 via a
  • the communications link 106 may include an I2C capable or compatible bus (herein after, an I2C bus).
  • I2C bus an I2C capable or compatible bus
  • the replaceable print apparatus component 104 is shown as external to the print apparatus 102, in some examples, the replaceable print apparatus component 104 may be housed within the print apparatus.
  • the replaceable print apparatus component 104 may include, for example, a print material container or cartridge (which could be a build material container for 3D printing, a liquid or dry toner container for 2D printing, or an ink or liquid print agent container for 2D or 3D printing), which may in some examples include a print head or other dispensing or transfer component.
  • the replaceable print apparatus component 104 may, for example, contain a consumable resource of the print apparatus 102, or a component which is likely to have a lifespan which is less (in some examples, considerably less) than that of the print apparatus 102.
  • replaceable print apparatus component 104 there may be a plurality of replaceable print apparatus components, for example including print agent containers of different colors, print heads (which may be integral to the containers), or the like.
  • the print apparatus components 104 could include service components, for example to be replaced by service personnel, examples of which could include print heads, toner process cartridges, or logic circuit package by itself to adhere to corresponding print apparatus component and communicate to a compatible print apparatus logic circuit.
  • Figure 2 illustrates one example of a replaceable print apparatus component 200, which may provide the replaceable print apparatus component 104 of Figure 1.
  • the replaceable print apparatus component 200 includes a data interface 202 and a logic circuitry package 204.
  • the logic circuitry package 204 decodes data received via the data interface 202.
  • the logic circuitry may perform other functions as set out below.
  • the data interface 202 may include an I2C or other interface. In certain examples, the data interface 202 may be part of the same package as the logic circuitry package 204.
  • the logic circuitry package 204 may be further configured to encode data for transmission via the data interface 202. In some examples, there may be more than one data interface 202 provided. In some examples, the logic circuitry package 204 may be arranged to act as a‘slave’ in I2C communications.
  • Figure 3 illustrates one example of a print apparatus 300.
  • the print apparatus 300 may provide the print apparatus 102 of Figure 1.
  • the print apparatus 300 may serve as a host for replaceable components.
  • the print apparatus 300 includes an interface 302 for communicating with a replaceable print apparatus component and a controller 304.
  • the controller 304 includes logic circuitry.
  • the interface 302 is an I2C interface.
  • controller 304 may be configured to act as a host, or a master, in I2C communications.
  • the controller 304 may generate and send commands to at least one replaceable print apparatus component 200, and may receive and decode responses received therefrom.
  • the controller 304 may communicate with the logic circuitry package 204 using any form of digital or analog communication.
  • the print apparatus 102, 300 and replaceable print apparatus component 104, 200, and/or the logic circuitry thereof, may be manufactured and/or sold separately.
  • a user may acquire a print apparatus 102, 300 and retain the apparatus 102, 300 for a number of years, whereas a plurality of replaceable print apparatus components 104, 200 may be purchased in those years, for example as print agent is used in creating a printed output.
  • Figure 4A illustrates one example of a logic circuitry package 400a, which may for example provide the logic circuitry package 204 described in relation to Figure 2.
  • the logic circuitry package 400a may be associated with, or in some examples affixed to and/or be incorporated at least partially within, a
  • the logic circuitry package 400a is addressable via a first address and includes a first logic circuit 402a, wherein the first address is an I2C address for the first logic circuit 402a.
  • the first address may be configurable.
  • the first address is a fixed address (e.g.,“hard-wired”) intended to remain the same address during the lifetime of the first logic circuit 402a.
  • the first address may be associated with the logic circuitry package 400a at and during the connection with the print apparatus logic circuit, outside of the time periods that are associated with a second address, as will be set out below.
  • the first addresses can be considered standard I2C
  • the logic circuitry package 400a is also addressable via a second address.
  • the second address may be associated with different logic functions or, at least partially, with different data than the first address.
  • the second address may be associated with a different hardware logic circuit or a different virtual device than the first address.
  • the hardware logic circuit can include analog sensor functions.
  • the logic circuitry package 400a may include a memory to store the second address (in some examples in a volatile manner).
  • the memory may include a programmable address memory register for this purpose.
  • the second address may have a default second address while the second address (memory) field may be reconfigurable to a different address.
  • the second address may be reconfigurable to a temporary address by a second address command, whereby it is set (back) to the default second address after or at each time period command to enable the second address.
  • the second address may be set to its default address in an out-of-reset state whereby, after each reset, it is reconfigurable to the temporary (i.e., reconfigured) address.
  • the package 400a is configured such that, in response to a first command indicative of a first time period sent to the first address (and in some examples a task), the package 400a may respond in various ways.
  • the package 400a is configured such that it is accessible via at least one second address for the duration of the time period.
  • the package may perform a task, which may be the task specified in the first command.
  • the package may perform a different task.
  • the first command may, for example, be sent by a host such as a print apparatus in which the logic circuitry package 400a (or an associated replaceable print apparatus component) is installed.
  • the task may include activating a heater or obtaining a sensor reading.
  • Further communication may be directed to memory addresses to be used to request information associated with these memory addresses.
  • the memory addresses may have a different configuration than the first and second address of the logic circuitry package 400a.
  • a host apparatus may request that a particular memory register is read out onto the bus by including the memory address in a read command.
  • a host apparatus may have a knowledge and/or control of the arrangement of a memory.
  • there may be a plurality of memory registers and corresponding memory addresses associated with the second address.
  • a particular register may be associated with a value, which may be static or reconfigurable. The host apparatus may request that the register be read out onto the bus by identifying that register using the memory address.
  • the registers may include any or any combination of address register(s), parameter register(s) (for example to store gain and/or offset parameters), sensor identification register(s) (which may store an indication of a type of sensor), sensor reading register(s) (which may store values read or determined using a sensor), sensor number register(s) (which may store a number or count of sensors), version identity register(s), memory register(s) to store a count of clock cycles, memory register(s) to store a value indicative of a read/write history of the logic circuitry, or other registers.
  • address register(s) for example to store gain and/or offset parameters
  • sensor identification register(s) which may store an indication of a type of sensor
  • sensor reading register(s) which may store values read or determined using a sensor
  • sensor number register(s) which may store a number or count of sensors
  • version identity register(s) memory register(s) to store a count of clock cycles
  • memory register(s) to store a value indicative of a read/write history of the logic
  • Figure 4B illustrates another example of a logic circuitry package 400b.
  • the package 400b includes a first logic circuit 402b, in this example, including a first timer 404a, and a second logic circuit 406a, in this example, including a second timer 404b. While in this example, each of the first and second logic circuits 402b, 406a include its own timer 404a, 404b, in other examples, they may share a timer or reference at least one external timer. In a further example, the first logic circuit 402b and the second logic circuit 406a are linked by a dedicated signal path 408. In other examples, that are not the topic of Figure 4B, a single integrated logic circuit may simulate the functions of the second logic circuit.
  • the logic circuitry package 400b may receive a first command including two data fields.
  • a first data field is a one byte data field setting a requested mode of operation.
  • the first command may include additional fields, such as an address field and/or a request for acknowledgement.
  • the logic circuitry package 400b is configured to process the first command. If the first command cannot be complied with (for example, a command parameter is of an invalid length or value, or it is not possible to enable the second logic circuit 406a), the logic circuitry package 400b may generate an error code and output this to a communication link to be returned to host logic circuitry, for example in the print apparatus.
  • the logic circuitry package 400b measures the duration of the time period included in the first command, for example utilizing the timer 404a.
  • the timer 404a may include a digital“clock tree”.
  • the timer 404a may include an RC circuit, a ring oscillator, or some other form of oscillator or timer.
  • the timer may include a plurality of delay circuits each of which is set to expire after a certain time period, whereby depending on the timer period indicated in a first command, the delay circuit is chosen.
  • the first logic circuit 402b in response to receiving a valid first command, enables the second logic circuit 406a and effectively disables the first address, for example by tasking the first logic circuit 402b with a processing task.
  • enabling the second logic circuit 406a includes sending, by the first logic circuit 402b, an activation signal to the second logic circuit 406a.
  • the logic circuitry package 400b is configured such that the second logic circuit 406a is selectively enabled by the first logic circuit 402b.
  • the first logic circuit 402b is configured to use the first timer 404a to determine the duration of the enablement, that is, to set the time period of the enablement.
  • the second logic circuit 406a is enabled by the first logic circuit 402b sending a signal via a signal path 408, which may or may not be a dedicated signal path 408, that is, dedicated to enable the second logic circuit 406a.
  • the first logic circuit 402b may have a dedicated contact pin or pad connected to the signal path 408, which links the first logic circuit 402b and the second logic circuit 406a.
  • the dedicated contact pin or pad may be a General Purpose Input/Output (a GPIO) pin of the first logic circuit 402b.
  • the contact pin/pad may serve as an enablement contact of the second logic circuit 406a.
  • the second logic circuit 406a is addressable via at least one second address.
  • the second logic circuit 406a when the second logic circuit 406a is activated or enabled, it may have an initial, or default, second address, which may be an I2C address or have some other address format.
  • the second logic circuit 406a may receive instructions from a master or host logic circuitry to reconfigure the initial second address to a temporary second address.
  • the temporary second address may be an address which is selected by the master or host logic circuitry. This may allow the second logic circuit 406a to be provided in one of a plurality of packages 400 on the same I2C bus which, at least initially, share the same initial second address. This shared, default, address may later be set to a specific temporary address by the print apparatus logic circuit, thereby allowing the plurality of packages to have different second addresses during their temporary use, facilitating
  • the second logic circuit 406a may include a memory.
  • the memory may include a programmable address register to store the initial and/or temporary second address (in some examples in a volatile manner).
  • the second address may be set following, and/or by executing, an I2C write command.
  • the second address may be settable when the enablement signal is present or high, but not when it is absent or low.
  • the second address may be set to a default address when an enablement signal is removed and/or on restoration of enablement of the second logic circuit 406a. For example, each time the enable signal over the signal path 408 is low, the second logic circuit 406a, or the relevant part(s) thereof, may be reset.
  • the default address may be set when the second logic circuit 406a, or the relevant part(s) thereof, is switched out-of-reset.
  • the default address is a 7-bit or 10-bit identification value.
  • the default address and the temporary second address may be written in turn to a single, common, address register. For example, while the first address of the first logic circuit is different for each different associated print material (e.g., different color inks have different first addresses), the second logic circuits can be the same for the different print materials and have the same initial second address.
  • the second logic circuit 406a includes a first array 410 of cells and at least one second cell 412 or second array of second cells of a different type than the cells of the first array 410.
  • the second logic circuit 406a may include additional sensor cells of a different type than the cells of the first array 410 and the at least one second cell 412.
  • Each of the plurality of sensor types may be identifiable by a different sensor ID, while each cell in a cell array of the same type may also be identifiable by sensor ID.
  • the sensor ID may include both the sensor type ID to select the array or type and the sensor cell ID to select the cell in the selected type or array, whereby the latter may also be called“sub-“ID.
  • the sensor IDs may include a combination of addresses and values, for example register addresses and values.
  • the addresses of the sensor cell array ID and the sensor cell ID may be different. For example, an address selects a register that has a function to select a particular sensor or cell, and in the same transaction, the value selects the sensor or cell, respectively.
  • the second logic circuit may include registers and multiplex circuitry to select sensor cells in response to sensor IDs. In examples where there is only one cell of a certain sensor type, one sensor ID may be sufficient to select that cell. At the same time, for that single sensor cell, different sensor“sub-“IDs will not affect the sensor cell selection because there is only one sensor cell. In this disclosure, sensor ID parameters are described.
  • a sensor ID parameter may include a sensor ID.
  • a sensor ID parameter may include a sensor type ID or a sensor cell ID. The same sensor ID (e.g., to select a sensor type) and different sensor sub-IDs (e.g., to select a sensor cell) may be used to select different sensor cells.
  • the sensor ID parameters can include only the sensor sub-ID, for example where the sensor type has been previously set so that only the sensor cell needs to be selected.
  • the first cells 416a-416f, 414a-414f and the at least one second cell 412 can include resistors.
  • the first cells 416a-416f, 414a-414f and the at least one second cell 412 can include sensors.
  • the first cell array 410 includes a print material level sensor and the at least one second cell 412 includes another sensor and/or another sensor array, such as an array of strain gauges.
  • Further sensor types may include temperature sensors, resistors, diodes, crack detectors (e.g., crack sense resistors), etc. In this disclosure, different sensor types may also be referred to as different sensor classes.
  • the first cell array 410 includes a sensor configured to detect a print material level of a print supply, which may in some examples be a solid but in examples described herein is a liquid, for example, an ink or other liquid print agent.
  • the first cell array 410 may include a series of temperature sensor cells (e.g., cells 414a-414f) and a series of heating elements (e.g., cells 416a-416f), for example similar in structure and function as compared to the level sensor arrays described in WO2017/074342, WO2017/184147, and WO2018/022038.
  • the resistance of a resistor cell 414 is linked to its temperature.
  • the heater cells 416 may be used to heat the sensor cells 414 directly or indirectly using a medium.
  • the subsequent behavior of the sensor cells 414 depends on the medium in which they are submerged, for example whether they are in liquid (or in some examples, encased in a solid medium) or in air.
  • a liquid level may be determined based on which of the resistor cells 414 are exposed to the air, and this may be determined based on a reading of their resistance following (at least the start of) a heat pulse provided by the associated heater cell 416.
  • temperature sensor cells 414a-414f are used for print material level sensing, whereas other temperature sensors, of a different type, may be used to detect an ambient and/or fluid temperature.
  • each sensor cell 414 and heater cell 416 are stacked with one being directly on top of the other.
  • the heat generated by each heater cell 416 may be substantially spatially contained within the heater element layout perimeter, so that heat delivery is substantially confined to the sensor cell 414 stacked directly above the heater cell 416.
  • each sensor cell 414 may be arranged between an associated heater cell 416 and the fluid/air interface.
  • the second cell array 412 includes a plurality of different cells that may have a different function such as different sensing function(s).
  • the first and second cell array 410, 412 may include different resistor types. Different cells arrays 410, 412 for different functions may be provided in the second logic circuit 406a. More than two different sensor types may be provided, for example three, four, five or more sensor types, may be provided, wherein each sensor type may be represented by one or more sensor cells. Certain cells or cell arrays may function as stimulators (e.g., heaters) or reference cells, rather than as sensors.
  • FIG. 4C illustrates an example of how a first logic circuit 402c and a second logic circuit 406b of a logic circuitry package 400c, which may have any of the attributes of the circuits/packages described above, may connect to an I2C bus and to each other.
  • each of the circuits 402c, 406b has four pads (or pins) 418a-418d connecting to the Power, Ground, Clock, and Data lines of an I2C bus.
  • four common connection pads are used to connect both logic circuits 402c, 406b to four corresponding connection pads of the print apparatus controller interface. It is noted that in some examples, instead of four connection pads, there may be fewer connection pads.
  • power may be harvested from the clock pad; an internal clock may be provided; or the package could be grounded through another ground circuit; so that, one or more of the pads may be omitted or made redundant.
  • the package could use only two or three interface pads and/or could include“dummy” pads.
  • Each of the circuits 402c, 406b has a contact pin 420, which are connected by a common signal line 422.
  • the contact pin 420 of the second circuit serves as an enablement contact thereof.
  • each of the first logic circuit 402c and the second logic circuit 406b include a memory 423a, 423b.
  • the memory 423a of the first logic circuit 402c stores information including cryptographic values (for example, a cryptographic key and/or a seed value from which a key may be derived) and identification data and/or status data of the associated replaceable print apparatus component.
  • the memory 423a may store data representing characteristics of the print material, for example, any part, or any combination of its type, color, color map, recipe, batch number, age, etc.
  • the first logic circuit 402c may be, or function as, a microcontroller or secure microcontroller.
  • memory 423b of the second logic circuit 406b includes a programmable address register to contain an initial address of the second logic circuit 406b when the second logic circuit 406b is first enabled and to
  • the memory 423b may further include programmable registers to store any, or any combination of a read/write history data, cell (e.g., resistor or sensor) count data, Analog to Digital converter data (ADC and/or DAC), and a clock count, in a volatile or non-volatile manner.
  • the memory 423b may also receive and/or store calibration parameters, such as offset and gain parameters. Use of such data is described in greater detail below. Certain characteristics, such as cell count or ADC or DAC
  • the memory 423b of the second logic circuit 406b stores any or any combination of an address, for example the second I2C address; an identification in the form of a revision ID; and the index number of the last cell (which may be the number of cells less one, as indices may start from 0), for example for each of different cell arrays or for multiple different cell arrays if they have the same number of cells.
  • the memory 423b of the second logic circuit 406 may store any or any combination of timer control data, which may enable a timer of the second circuit, and/or enable frequency dithering therein in the case of some timers such as ring oscillators; a dither control data value (to indicate a dither direction and/or value); and a timer sample test trigger value (to trigger a test of the timer by sampling the timer relative to clock cycles measureable by the second logic circuit 406b).
  • some timers such as ring oscillators
  • a dither control data value to indicate a dither direction and/or value
  • a timer sample test trigger value to trigger a test of the timer by sampling the timer relative to clock cycles measureable by the second logic circuit 406b.
  • the memories 423a, 423b may include a single or multiple memory devices, and may include any or any combination of volatile memory (e.g., DRAM, SRAM, registers, etc.) and non-volatile memory (e.g., ROM, EEPROM, Flash, EPROM, memristor, etc.).
  • volatile memory e.g., DRAM, SRAM, registers, etc.
  • non-volatile memory e.g., ROM, EEPROM, Flash, EPROM, memristor, etc.
  • Figure 4D illustrates an example of processing circuitry 424 which is for use with a print material container.
  • the processing circuitry 424 may be affixed or integral thereto.
  • the processing circuitry 424 may include any of the features of, or be the same as, any other logic circuitry package of this disclosure.
  • the processing circuitry 424 includes a memory 426 and a first logic circuit 402d which enables a read operation from memory 426.
  • the processing circuitry 424 is accessible via an interface bus of a print apparatus in which the print material container is installed and is associated with a first address and at least one second address.
  • the bus may be an I2C bus.
  • the first address may be an I2C address of the first logic circuit 402d.
  • the first logic circuit 402d may have any of the attributes of the other examples
  • the first logic circuit 402d is adapted to participate in authentication of the print materials container by a print apparatus in which the container is installed.
  • this may include a cryptographic process such as any kind of cryptographically authenticated communication or message exchange, for example based on a key stored in the memory 426, and which can be used in conjunction with information stored in the printer.
  • a printer may store a version of a key which is compatible with a number of different print material containers to provide the basis of a‘shared secret’.
  • authentication of a print material container may be carried out based on such a shared secret.
  • the first logic circuit 402d may participate in a message to derive a session key with the print apparatus and messages may be signed using a message authentication code based on such a session key. Examples of logic circuits configured to cryptographically authenticate
  • the memory 426 may store data including:
  • the memory 426 further includes cell count data (e.g., sensor count data) and clock count data.
  • Clock count data may indicate a clock speed of a first and/or second timer 404a, 404b (i.e., a timer associated with the first logic circuit or the second logic circuit).
  • at least a portion of the memory 426 is associated with functions of a second logic circuit, such as a second logic circuit 406a as described in relation to Figure 4B above.
  • at least a portion of the data stored in the memory 426 is to be communicated in response to commands received via the second address, for example the earlier mentioned initial or reconfigured/temporary second address.
  • the memory 426 includes a programmable address register or memory field to store a second address of the processing circuitry (in some examples in a volatile manner).
  • the first logic circuit 402d may enable read operation from the memory 426 and/or may perform processing tasks.
  • the memory 426 may, for example, include data representing
  • the memory 426 may, for example, include data to be communicated in response to commands received via the first address.
  • the processing circuitry may include a first logic circuit to enable read operations from the memory and perform processing tasks.
  • the processing circuitry 424 is configured such that, following receipt of the first command indicative of a task and a first time period sent to the first logic circuit 402d via the first address, the processing circuitry 424 is accessible by at least one second address for a duration of the first time period.
  • the processing circuitry 424 may be configured such that in response to a first command indicative of a task and a first time period sent to the first logic circuit 402d addressed using the first address, the processing circuitry 424 is to disregard (e.g.,‘ignore’ or‘not respond to’) I2C traffic sent to the first address for substantially the duration of the time period as measured by a timer of the processing circuitry 424 (for example a timer 404a, 404b as described above).
  • the processing circuitry may additionally perform a task, which may be the task specified in the first command.
  • the term‘disregard’ or‘ignore’ as used herein with respect to data sent on the bus may include any or any combination of not receiving (in some examples, not reading the data into a memory), not acting upon (for example, not following a command or instruction) and/or not responding (i.e., not providing an acknowledgement, and/or not responding with requested data).
  • the processing circuitry 424 may have any of the attributes of the logic circuitry packages 400 described herein.
  • the processing circuitry 424 may further include a second logic circuit wherein the second logic circuit is accessible via the second address.
  • the second logic circuit may include at least one sensor which is readable by a print apparatus in which the print material container is installed via the second address.
  • such a sensor may include a print material level sensor.
  • the processing circuitry 424 may include a single, integral logic circuit, and one or more sensors of one or more types.
  • Figure 4E illustrates another example of a first logic circuit 402e and second logic circuit 406c of a logic circuitry package 400d, which may have any of the attributes of the circuits/packages of the same names described herein, which may connect to an I2C bus (Clock, Data, Power, and Ground) via respective interfaces 428a, 428b and to each other.
  • I2C bus Lock, Data, Power, and Ground
  • the respective interfaces 428a, 428b are connected to the same contact pad array, with only one data pad for both logic circuits 402e, 406c, connected to the same serial I2C bus.
  • communications addressed to the first and the second address are received via the same data pad.
  • the first logic circuit 402e includes a microcontroller 430, a memory 432, and a timer 434.
  • the microcontroller 430 may be a secure microcontroller or customized integrated circuitry adapted to function as a microcontroller, secure or non-secure.
  • First logic circuit 402e may be referred to as a memory chip controller and may be used to calibrate functions of second logic circuit 406c based on calibration parameters stored in memory 432. For example, registers 438 of the second logic circuit 406c may be initiated to a default state.
  • the second logic circuit 406c includes a transmit/receive module 436, which receives a clock signal and a data signal from a bus to which the package 400d is connected, data registers 438 (e.g., flip flops and/or latches), a multiplexer 440, a digital controller 442, an analog bias circuit and analog to digital converter 444, at least one sensor or cell array 446 (which may in some examples include a level sensor with one or multiple arrays of resistor elements), and a power-on reset (POR) device 448.
  • the POR device 448 may be used to allow operation of the second logic circuit 406c without use of a contact pin 420.
  • Digital controller 442 generates a clock signal for timing operations of second logic circuit 406c.
  • the operations may include initiating the sensor array(s) 446 and sensors 450, 452, 454 based on values stored in registers 438 and generating outputs (transmitted via transmit/receive module 436) of the sensor array(s) 446 and sensors 450, 452, 454.
  • the digital controller 442 generates derivative clock signals from a reference clock signal for timing operations of the second logic circuit 406c, such as operations performed by transmit/receive module 436, registers 438, and analog bias circuit and analog to digital converter 444.
  • registers 438 are accessible by read and/or write logic of the digital controller 442 to shift data into and/or out of the registers to update the state of the registers and/or to update the state of the digital bus.
  • the analog bias circuit and analog to digital converter 444 receives readings from the sensor array(s) 446 and from additional sensors 450, 452,
  • the analog bias circuit may generate a constant current or a constant voltage to bias a sensor and the resultant voltage or resultant current, respectively, may be converted to a digital value by the analog to digital converter.
  • the analog to digital converter is a successive approximation analog to digital converter that uses a derivative clock signal generated by the digital controller 442.
  • the digital value from the analog to digital converter may be stored in a register 438 and read out (i.e., transmitted as serial data bits, or as a‘bitstream’) over the I2C bus.
  • the analog bias circuit and analog to digital converter 444 may utilize parameters, for example, gain and/or offset parameters, which may be stored in registers 438.
  • Second logic circuit 406c also includes a test pad 441.
  • the multiplexer 440 is electrically coupled to the digital controller 442, the sensor array(s) 446 and sensors 450, 452, 454 (e.g., via analog bias circuit and analog to digital converter 444), and the test pad 441.
  • the multiplexer 440 may pass a selected one of a clock signal (e.g., generated by digital controller 442) and an analog sensor signal from a sensor (e.g., sensor array(s) 446 or sensor 450, 452, 454) to the test pad 441.
  • a point temperature sensor 450 may sense the temperature of print material (e.g., fluid) when the print material level is above the location of the point temperature sensor.
  • the point temperature sensor 450 may sense the temperature of the air inside the component when the print material level is below the location of the point temperature sensor. In many cases, the air temperature and print material temperature will be the same. If the component has recently been transported, however, there is a chance that the component may be frozen. The air volume will warm faster than the print material volume once exposed to warmer ambient conditions.
  • a print system may first reference the last known print material level stored in a memory to ensure the print material level is sufficiently near or above the point temperature sensor to achieve an accurate measurement dependent on thermal conduction between the print material and the logic circuitry package where the point temperature sensor is located. In some examples, the point temperature sensor may only be read upon new component installation.
  • the crack detector 452 may sense a structural integrity of a die on which the logic circuitry is provided.
  • the distributed temperature sensor 454 (e.g., a
  • temperature sensitive resistor may sense the average temperature of print material and/or air over its length.
  • the point and/or distributed temperature sensor may be different than the temperature sensor cells of the sensor 410 intended for fluid level sensing.
  • Figure 5A illustrates an example of a possible practical arrangement of a second logic circuit embodied by a sensor assembly 500 in association with a circuitry package 502.
  • the sensor assembly 500 may include a thin film stack and include at least one sensor array such as a fluid level sensor array.
  • the arrangement has a high length to width aspect ratio (e.g., as measured along a substrate surface), for example being around 0.2 mm in width, for example less than 1 mm, 0.5 mm, or 0.3 mm, and around 20 mm in length, for example more than 10 mm, leading to length to width aspect ratios equal to or above approximately 20:1 , 40:1 , 60:1 , 80:1 , or 100:1.
  • the length may be measured along the height.
  • the logic circuit in this example may have a thickness of less than 1 mm, less than 0.5 mm, or less than 0.3 mm, as measured between the bottom of the (e.g., silicon) substrate and the opposite outer surface. These dimensions mean that the individual cells or sensors are small.
  • the sensor assembly 500 may be provided on a relatively rigid carrier 504, which in this example also carries Ground, Clock, Power and Data I2C bus contacts.
  • Figure 5B illustrates a perspective view of a print cartridge 512 including a logic circuitry package of any of the examples of this disclosure.
  • the print cartridge 512 has a housing 514 that has a width W less than its height FI and that has a length L or depth that is greater than the height FI.
  • a print liquid output 516 (in this example, a print agent outlet provided on the underside of the cartridge 512), an air input 518 and a recess 520 are provided in a front face of the cartridge 512.
  • the recess 520 extends across the top of the cartridge 512 and I2C bus contacts (i.e., pads) 522 of a logic circuitry package 502 (for example, a logic circuitry package 400a-400d as described above) are provided at a side of the recess 520 against the inner wall of the side wall of the housing 514 adjacent the top and front of the housing 514.
  • the data contact is the lowest of the contacts 522.
  • the logic circuitry package 502 is provided against the inner side of the side wall.
  • the logic circuitry package 502 includes a sensor assembly as shown in Figure 5A.
  • a replaceable print apparatus component includes a logic circuitry package of any of the examples described herein, wherein the component further includes a volume of liquid.
  • the component may have a height H that is greater than a width W and a length L that is greater than the height, the width extending between two sides.
  • Interface pads of the package may be provided at the inner side of one of the sides facing a cut-out for a data interconnect to be inserted, the interface pads extending along a height direction near the top and front of the component, and the data pad being the bottom-most of the interface pads, the liquid and air interface of the component being provided at the front on the same vertical reference axis parallel to the height H direction wherein the vertical axis is parallel to and distanced from the axis that intersects the interface pads (i.e., the pads are partially inset from the edge by a distance D).
  • the rest of the logic circuitry package may also be provided against the inner side.
  • a damaged sensor may provide inaccurate measurements, and result in inappropriate decisions by a print apparatus when evaluating the
  • communications with the logic circuitry based on a specific communication sequence provide expected results. This may validate the operational health of the logic circuitry.
  • FIG. 6 illustrates another example of a replaceable print apparatus component 600.
  • Replaceable print apparatus component 600 includes a print material reservoir 602 and a print material within the reservoir.
  • Replaceable print apparatus component 600 also includes a sensing system 604 (e.g., a logic circuitry package) including a memory chip controller 606 and an
  • Sensing system 604 may include any of the features of logic circuitry packages 400a-400d or of processing circuitry 424 previously described.
  • the integrated circuit 608 may include any of the features of a second logic circuit previously described above, such as second logic circuit 406a, 406b, or 406c.
  • the integrated circuit 608 includes an interface 610, a memory array 612, a digital controller 614, an analog to digital converter 616, an analog bias circuit 617, at least one sensor 618, a multiplexer 620, and a test pad 622.
  • the digital controller 614 is electrically coupled to the interface 610, the memory array 612, the analog to digital converter 616 and the analog bias circuit 617.
  • the at least one sensor 618 is electrically coupled to the analog to digital converter 616 and the analog bias circuit 617. In one example, the at least one sensor 618 is in direct contact with the print material within print material reservoir 602.
  • the digital controller 614 generates a clock signal for timing operations of the integrated circuit 608.
  • the operations may include initiating the at least one sensor 618 based on values stored in the memory array 612 and generating outputs of the at least one sensor 618 via the analog to digital converter 616.
  • the digital controller may generate derivative clock signals from a reference clock signal for timing operations of the integrated circuit 608.
  • the digital controller may generate the clock signal to time operations of the analog to digital converter 616, the digital bus (e.g., via interface 610), and read and/or write accesses to the memory array 612 to initiate the sensing system state and/or to store results of outputs from the analog to digital converter 616.
  • the digital bus is an I2C serial bus and interface 610 is an I2C interface to enable the integrated circuit 608 to connect to and
  • Memory chip controller 606 is electrically coupled to digital controller 614.
  • the memory chip controller 606 is for sensor reference calibration, read initiation, measurement configuration, and retrieval of a digital representation of a print material level within the reservoir 602.
  • Memory chip controller 606 may include the features of a first logic circuit previously described above, such as first logic circuit 402a, 402b, 402c, 402d, or 402e.
  • Multiplexer 620 is electrically coupled to the digital controller 614, the at least one sensor 618, and the test pad 622 to pass a selected one of the clock signal (from digital controller 614) and an analog sensor signal from the at least one sensor 618 to the test pad 622.
  • memory array 612 includes flip flops and/or latches.
  • memory array 612 includes registers. The registers may be initiated to a default state and accessible by read and/or write logic of the digital controller 614 to shift data into and/or out of the registers to update the state of the registers and/or to update the state of the digital bus.
  • the analog to digital converter 618 is configured to convert an analog signal from the at least one sensor 618 to a digital value.
  • the analog to digital converter 618 includes a successive approximation analog to digital converter.
  • Analog bias circuit 617 is electrically coupled to the at least one sensor 618 and the digital controller 614 to bias the at least one sensor.
  • the analog bias circuit 617 generates a constant voltage to bias the at least one sensor 618.
  • the analog bias circuit 617 generates a constant current to bias the at least one sensor 618.
  • the at least one sensor 618 may include at least one of a temperature sensor, a strain gauge, a crack detector, a print material level sensor, and a sensor configured to detect a pneumatic actuation of the print apparatus component 600.
  • the integrated circuit 608 includes a plurality of sensors of different types (as previously described) including the at least one sensor 618. In this case, each of the plurality of sensors are electrically coupled to the digital controller (e.g., via analog to digital converter 616 and/or analog bias circuit 617).
  • integrated circuit 608 includes a shared analog bus electrically coupled between the digital controller 614 and each of the plurality of sensors for analog biasing and analog to digital conversion to access the state of the print material over the print material level sensor or a localized strain at a strain gauge.
  • the at least one sensor 618 may include an array of sensors (e.g., 414a-414f of Figure 4B).
  • Integrated circuit 608 may be a high- aspect-ratio integrated circuit in a O.35pm-3.3V-CMOS process.
  • the integrated circuit 608 may include a length and a width less than the length and the sensors of the array of sensors may be distributed along the length of the integrated circuit at greater than 60 sensors per centimeter.
  • the array of sensors includes 126 sensors.
  • the integrated circuit 608 may also include an array of heaters (e.g., 416a-416f of Figure 4B) associated with the array of sensors. In this case, each heater may be actuated for a register- based programmable time duration (e.g., stored in memory array 612) by a digital pulse generated from a clock reference conversion (e.g., by digital controller 614).
  • the at least one sensor 618 may include a plurality of sensor cores.
  • Each sensor core may be configured to perform at least one of heating, thermal sensing, strain sensing, optical sensing, and memory access.
  • the plurality of sensor cores may be used to detect a print material level within the print material reservoir 602 and/or to detect a pneumatic pneumatic actuation of the print apparatus component 600.
  • FIG. 7 illustrates another example of a printing system 700.
  • Printing system 700 includes a print apparatus host logic circuit 702, a digital bus 704, and a plurality of replaceable print apparatus components 706a-706d.
  • Each replaceable print apparatus component 706a-706d may include a different colored print material, such as cyan, magenta, yellow, and black ink.
  • Each replaceable print apparatus component 706a-706d includes a logic circuitry package 708a-708d, respectively, which may be a logic circuitry package 400a- 400d, processing circuitry 424, or a sensing system 604 as previously
  • a printing system may include the replaceable print apparatus component 600 of Figure 6 and a further replaceable print apparatus component.
  • the further replaceable print apparatus component may include a further print material reservoir (e.g., 602), a further print material within the further reservoir, and a further sensing system (e.g., 604) including a further integrated circuit (e.g., 608) configured to connect to and communicate over the digital bus 704.
  • the host logic circuit 702 and the logic circuitry packages 708a-708d are in communication via a common digital bus 704 (e.g., an I2C serial bus).
  • a common digital bus 704 e.g., an I2C serial bus.
  • each of the logic circuitry packages 708a-708d has a different first address. Therefore, each of the logic circuitry packages 708a- 708d (and by extension, each of the replaceable print apparatus components) may be addressed uniquely by the host logic circuit 702.
  • a first command may be sent to a particular one of the replaceable print apparatus component logic circuitry packages 708a-708d (i.e., being addressed using the unique first address for that logic circuitry package), instructing the logic circuitry package to enable its (at least one) second address for a corresponding‘first command’ time period. Therefore, that replaceable print apparatus component 708 may, for example, enable at least one second address and/or, in some examples, its associated functions. In some examples, this results in enabling a second logic circuit as described above.
  • the addressed logic circuitry package 708 may ignore (e.g., not acknowledge and/or not respond to) traffic sent to the first address of that logic circuitry package 708 for the duration of the first command time period, for example in response to the same command or a separate command.
  • the other print apparatus components 708 may also be sent a second command resulting in them ignoring traffic sent to their first addresses for the duration of a‘second command’ time period.
  • component/package ignoring traffic sent to their first addresses for the duration of the first command time period, and/or a second command may also result in an addressed component/package being accessible via at least one second address.
  • a host device such as logic circuit 702 in this example wishing to communicate with a particular logic circuitry package 708 via its second address - in this example logic circuitry package 708a - may issue commands so as to instruct the other logic circuitry packages 708b-708d to act in a manner which results in them ignoring traffic on the digital bus 704.
  • This may include the logic circuit 702 serially sending three commands addressed to a unique address of each of the other logic circuitry packages 708b-708d, each command specifying a first mode of operation and a time period.
  • the first mode of operation may result in traffic on the digital bus 704 being ignored by logic circuitry packages 708b-708d.
  • the logic circuit 702 may send a dedicated command to the target logic circuitry package 708a via its first address, the command specifying a second mode of operation and a time period.
  • the second mode of operation may include an instruction resulting in traffic on the digital bus 704 sent to a first address being ignored and
  • the first command time period and the second command time period for which traffic is ignored by different logic circuitry packages 708 may be specified to overlap with one another, in some examples based on the delay with which instructions will be received.
  • the host logic circuit 702 may then communicate with the selected logic circuitry package 708a via its second address for the duration of the time period. During this time period, in some examples no other devices are‘listening’ to the digital bus 704 and any communication protocol (including in some examples a non-l2C compliant protocol) may be used for communicating with the selected logic circuitry package 708a via its second address. In other examples, some or all logic circuitry packages 708a-708d may be accessible via a second address concurrently, or a mixture of first and second addresses of respective logic circuitry packages may be accessible.
  • the logic circuitry packages described herein mainly include hardwired routings, connections, and interfaces between different components.
  • the logic circuitry packages may also include at least one wireless connection, wireless communication path, or wireless interface, for internal and/or external signaling, whereby a wirelessly connected element may be considered as included in the logic circuitry package and/or replaceable component.
  • certain sensors may be wireless connected to communicate wirelessly to the logic circuit/sensor circuit.
  • sensors such as pressure sensors and/or print material level sensors may communicate wirelessly with other portions of the logic circuit.
  • the external interface of the logic circuitry package, to communicate with the print apparatus logic circuit may include a wireless interface.
  • a power source such as a battery or a power harvesting source that may harvest power from data or clock signals.
  • Certain example circuits of this disclosure relate to outputs that vary in a certain way in response to certain commands, events and/or states. It is also explained that, unless calibrated in advance, responses to these same events and/or states may be“clipped”, for example so that they cannot be
  • the logic circuitry package outputs count values in response to read requests.
  • each separate count value is output in response to each read request.
  • a logic circuit is configured to output a series or plurality of count values in response to a single read request. In other examples, output may be generated without a read request.
  • Each of the logic circuitry packages 400a-400d described herein may have any feature of any other logic circuitry packages 400a-400d described herein or of the processing circuitry 424 or sensing system 604. Any first logic circuit may have any attribute of any second logic circuit, and vice versa.
  • Examples in the present disclosure can be provided as methods, systems or machine readable instructions, such as any combination of software, hardware, firmware or the like.
  • Such machine readable instructions may be included on a machine readable storage medium (including but not limited to EEPROM, PROM, flash memory, disc storage, CD-ROM, optical storage, etc.) having machine readable program codes therein or thereon.
  • the machine readable instructions may, for example, be executed by a general purpose computer, a special purpose computer, an embedded processor or processors of other programmable data processing devices to realize the functions described in the description and diagrams.
  • a processor or processing circuitry may execute the machine readable instructions.
  • functional modules of the apparatus and devices may be implemented by a processor executing machine readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry.
  • the term ‘processor’ is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate array etc.
  • the methods and functional modules may all be performed by a single processor or divided amongst several processors.
  • Such machine readable instructions may also be stored in a machine readable storage (e.g., a tangible machine readable medium) that can guide the computer or other programmable data processing devices to operate in a specific mode.
  • a machine readable storage e.g., a tangible machine readable medium
  • Such machine readable instructions may also be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing, thus the instructions executed on the computer or other programmable devices realize functions specified by block(s) in the block diagrams.
  • teachings herein may be implemented in the form of a computer software product, the computer software product being stored in a storage medium and comprising a plurality of instructions for making a computer device implement the methods recited in the examples of the present

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Fluid Mechanics (AREA)
  • Theoretical Computer Science (AREA)
  • Thermal Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Ink Jet (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)

Abstract

La présente invention concerne un composant d'appareil d'impression remplaçable qui comprend un réservoir de matériau d'impression, un matériau d'impression à l'intérieur du réservoir et un système de détection comprenant un circuit intégré conçu pour se connecter à un bus numérique et communiquer sur ce dernier. Le système de détection comprend au moins un capteur, un dispositif de commande numérique, un convertisseur analogique-numérique couplé électriquement au dispositif de commande numérique, et un réseau de mémoire couplé électriquement au dispositif de commande numérique. Le dispositif de commande numérique est conçu pour générer un signal d'horloge pour des opérations de synchronisation du circuit intégré. Les opérations comprennent l'initialisation du ou des capteurs sur la base de valeurs mémorisées dans le réseau de mémoire et la génération de sorties du ou des capteurs par l'intermédiaire du convertisseur analogique-numérique.
PCT/US2019/064226 2018-12-03 2019-12-03 Composant d'appareil d'impression remplaçable WO2020117797A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
CN201980077942.0A CN113165388B (zh) 2018-12-03 2019-12-03 可更换打印设备部件和打印系统
ES19823870T ES2868132T3 (es) 2018-12-03 2019-12-03 Componente reemplazable del aparato de impresión
AU2019392466A AU2019392466A1 (en) 2018-12-03 2019-12-03 Replaceable print apparatus component
CA3121174A CA3121174A1 (fr) 2018-12-03 2019-12-03 Composant d'appareil d'impression remplacable
KR1020217016831A KR20210087977A (ko) 2018-12-03 2019-12-03 교체 가능한 인쇄 장치 구성요소
PL19823870T PL3691905T3 (pl) 2018-12-03 2019-12-03 Wymienny komponent urządzenia drukującego
MX2021006233A MX2021006233A (es) 2018-12-03 2019-12-03 Componente reemplazable del aparato de impresion.
BR112021010632-4A BR112021010632A2 (pt) 2018-12-03 2019-12-03 Componente de aparelho de impressão substituível
EP19823870.1A EP3691905B1 (fr) 2018-12-03 2019-12-03 Composant d'appareil d'impression remplaçable
US16/768,652 US11345159B2 (en) 2018-12-03 2019-12-03 Replaceable print apparatus component

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Application Number Priority Date Filing Date Title
USPCT/US2018/063631 2018-12-03
PCT/US2019/026161 WO2020117308A1 (fr) 2018-12-03 2019-04-05 Circuiterie logique
PCT/US2019/026133 WO2020117304A1 (fr) 2018-12-03 2019-04-05 Ensemble de circuits logiques
USPCT/US2019/026161 2019-04-05
USPCT/US2019/026152 2019-04-05
PCT/US2019/026152 WO2020204951A1 (fr) 2019-04-05 2019-04-05 Capteur de propriétés de fluide
USPCT/US2019/026133 2019-04-05

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PCT/US2019/057980 WO2020117391A1 (fr) 2018-12-03 2019-10-25 Ensemble de circuits logiques
PCT/US2019/057989 WO2020117393A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057987 WO2020117392A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057991 WO2020117394A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058201 WO2020117402A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057977 WO2020117389A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuiterie logique
PCT/US2019/058006 WO2020117396A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuiterie logique
PCT/US2019/058048 WO2020117397A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058001 WO2020117395A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058172 WO2020117401A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/064226 WO2020117797A1 (fr) 2018-12-03 2019-12-03 Composant d'appareil d'impression remplaçable
PCT/US2019/064213 WO2020117786A1 (fr) 2018-12-03 2019-12-03 Boîtier de circuit logique
PCT/US2019/064192 WO2020117774A1 (fr) 2018-12-03 2019-12-03 Boîtier de circuiterie logique
PCT/US2019/064297 WO2020117848A1 (fr) 2018-12-03 2019-12-03 Circuits logiques

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PCT/US2019/057980 WO2020117391A1 (fr) 2018-12-03 2019-10-25 Ensemble de circuits logiques
PCT/US2019/057989 WO2020117393A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057987 WO2020117392A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057991 WO2020117394A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058201 WO2020117402A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057977 WO2020117389A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuiterie logique
PCT/US2019/058006 WO2020117396A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuiterie logique
PCT/US2019/058048 WO2020117397A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058001 WO2020117395A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058172 WO2020117401A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique

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PCT/US2019/064192 WO2020117774A1 (fr) 2018-12-03 2019-12-03 Boîtier de circuiterie logique
PCT/US2019/064297 WO2020117848A1 (fr) 2018-12-03 2019-12-03 Circuits logiques

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WO2020117394A1 (fr) 2020-06-11
WO2020117391A1 (fr) 2020-06-11
WO2020117392A1 (fr) 2020-06-11
WO2020117395A1 (fr) 2020-06-11
WO2020117393A1 (fr) 2020-06-11
WO2020117848A1 (fr) 2020-06-11
WO2020117774A1 (fr) 2020-06-11
WO2020117402A1 (fr) 2020-06-11
WO2020117389A1 (fr) 2020-06-11
WO2020117786A1 (fr) 2020-06-11
WO2020117396A1 (fr) 2020-06-11
WO2020117397A1 (fr) 2020-06-11

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