WO2020117397A1 - Boîtier de circuit logique - Google Patents

Boîtier de circuit logique Download PDF

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Publication number
WO2020117397A1
WO2020117397A1 PCT/US2019/058048 US2019058048W WO2020117397A1 WO 2020117397 A1 WO2020117397 A1 WO 2020117397A1 US 2019058048 W US2019058048 W US 2019058048W WO 2020117397 A1 WO2020117397 A1 WO 2020117397A1
Authority
WO
WIPO (PCT)
Prior art keywords
logic circuit
sensor
logic circuitry
circuitry package
data
Prior art date
Application number
PCT/US2019/058048
Other languages
English (en)
Inventor
Scott A. Linn
Michael W. Cumbie
James Michael GARDNER
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2019/026161 external-priority patent/WO2020117308A1/fr
Priority claimed from PCT/US2019/026152 external-priority patent/WO2020204951A1/fr
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to CN201980077718.1A priority Critical patent/CN113168446A/zh
Priority to US16/768,321 priority patent/US11407228B2/en
Priority to EP19805451.2A priority patent/EP3688643A1/fr
Publication of WO2020117397A1 publication Critical patent/WO2020117397A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17566—Ink level or ink residue control
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17513—Inner structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17526—Electrical contacts to the cartridge
    • B41J2/1753—Details of contacts on the cartridge, e.g. protection of contacts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17543—Cartridge presence detection or type identification
    • B41J2/17546—Cartridge presence detection or type identification electronically
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17553—Outer structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17556—Means for regulating the pressure in the cartridge
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F23/00—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm
    • G01F23/22—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water
    • G01F23/24—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of resistance of resistors due to contact with conductor fluid
    • G01F23/246—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of resistance of resistors due to contact with conductor fluid thermal devices
    • G01F23/247—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of resistance of resistors due to contact with conductor fluid thermal devices for discrete levels
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F23/00—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm
    • G01F23/80—Arrangements for signal processing
    • G01F23/802—Particular electronic circuits for digital processing equipment
    • G01F23/804—Particular electronic circuits for digital processing equipment containing circuits handling parameters other than liquid level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17566—Ink level or ink residue control
    • B41J2002/17586—Ink level or ink residue control using ink bag deformation for ink level indication
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F25/00—Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume
    • G01F25/20—Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume of apparatus for measuring liquid level

Definitions

  • Subcomponents of apparatus may communicate with one another in a number of ways. For example, Serial Peripheral Interface (SPI) protocol, Bluetooth Low Energy (BLE), Near Field Communications (NFC) or other types of digital or analog communications may be used.
  • SPI Serial Peripheral Interface
  • BLE Bluetooth Low Energy
  • NFC Near Field Communications
  • Some two-dimensional (2D) and three-dimensional (3D) printing systems include one or more replaceable print apparatus components, such as print material containers (e.g., inkjet cartridges, toner cartridges, ink supplies, 3D printing agent supplies, build material supplies etc.), inkjet printhead
  • print material containers e.g., inkjet cartridges, toner cartridges, ink supplies, 3D printing agent supplies, build material supplies etc.
  • inkjet printhead e.g., inkjet printhead
  • logic circuitry associated with the replaceable print apparatus component(s) communicate with logic circuitry of the print apparatus in which they are installed, for example communicating information such as their identity, capabilities, status and the like.
  • print material containers may include circuitry to execute one or more monitoring functions such as print material level sensing.
  • Figure 1 illustrates one example of a printing system.
  • Figure 2 illustrates one example of a replaceable print apparatus component.
  • Figure 3 illustrates one example of a print apparatus.
  • Figures 4A-4E illustrate examples of logic circuitry packages and processing circuitry.
  • Figure 5A illustrates one example arrangement of a fluid level sensor.
  • Figure 5B illustrates a perspective view of one example of a print cartridge.
  • Figures 6A-6E are flow diagrams illustrating one example of a method that may be carried out by a logic circuitry package.
  • Figure 7 illustrates another example of a logic circuitry package.
  • Figure 8A-8C illustrate state machines that may be implemented by a logic circuitry package.
  • Figures 9A-9B are flow diagrams illustrating another example of a method that may be carried out by a logic circuitry package.
  • Figure 10 illustrates another example of a logic circuitry package.
  • Inter-integrated Circuit (l 2 C, or I2C, which notation is adopted herein) protocol allows at least one‘master’ integrated circuit (1C) to communicate with at least one‘slave’ 1C, for example via a bus.
  • I2C, and other communications protocols communicate data according to a clock period. For example, a voltage signal may be generated, where the value of the voltage is associated with data. For example, a voltage value above X volts may indicate a logic“1” whereas a voltage value below X volts may indicate a logic“0”, where X is a predetermined numerical value.
  • a voltage value above X volts may indicate a logic“1”
  • a voltage value below X volts may indicate a logic“0”, where X is a predetermined numerical value.
  • Certain example print material containers have slave logic that utilize I2C communications, although in other examples, other forms of digital or analog communications could also be used.
  • a master 1C may generally be provided as part of the print apparatus (which may be referred to as the‘host’) and a replaceable print apparatus component would comprise a‘slave’ 1C, although this need not be the case in all examples.
  • the slave IC(s) may include a processor to perform data operations before responding to requests from logic circuitry of the print system.
  • Communications between print apparatus and replaceable print apparatus components installed in the apparatus may facilitate various functions.
  • Logic circuitry within a print apparatus may receive information from logic circuitry associated with a replaceable print apparatus component via a communications interface, and/or may send commands to the replaceable print apparatus component logic circuitry, which may include commands to write data to a memory associated therewith, or to read data therefrom.
  • logic circuitry associated with a replaceable print apparatus component may include an interface (e.g., an I2C interface) that is used to control all operations of the logic circuitry package by read and write commands to a memory (non-volatile or volatile) of the logic circuitry package.
  • the logic circuitry package may also include an array of heaters and corresponding thermal sensors to detect an ink level of a replaceable print apparatus component.
  • a conversion state machine of the logic circuitry package may, in response to receiving a write command indicating a sensor and corresponding heater(s), select the sensor and the corresponding heater(s), turn on the heater(s) for a first predetermined period, and convert an output signal of the sensor to a digital value after a second predetermined period.
  • the logic circuitry package may be associated with a replaceable print apparatus component, for example being internally or externally affixed thereto, for example at least partially within the housing, and is adapted to communicate data with a print apparatus controller via a bus provided as part of the print apparatus.
  • A‘logic circuitry package’ as the term is used herein refers to one logic circuit, or more logic circuits that may be interconnected or communicatively linked to each other. Where more than one logic circuit is provided, these may be encapsulated as a single unit, or may be separately encapsulated, or not encapsulated, or some combination thereof.
  • the package may be arranged or provided on a single substrate or a plurality of substrates. In some examples, the package may be directly affixed to a cartridge wall. In some examples, the package may include an interface, for example including pads or pins.
  • the package interface may be intended to connect to a communication interface of the print apparatus component that in turn connects to a print apparatus logic circuit, or the package interface may connect directly to the print apparatus logic circuit.
  • Example packages may be configured to communicate via a serial bus interface. Where more than one logic circuit is provided, these logic circuits may be connected to each other or to the interface, to communicate through the same interface.
  • each logic circuitry package is provided with at least one processor and memory.
  • the logic circuitry package may be, or may function as, a microcontroller or secure microcontroller.
  • the logic circuitry package may be adhered to or integrated with the replaceable print apparatus component.
  • a logic circuitry package may alternatively be referred to as a logic circuitry assembly, or simply as logic circuitry or processing circuitry.
  • the logic circuitry package may respond to various types of requests (or commands) from a host (e.g., a print apparatus).
  • a first type of request may include a request for data, for example identification and/or authentication information.
  • a second type of request from a host may be a request to perform a physical action, such as performing at least one measurement.
  • a third type of request may be a request for a data processing action. There may be additional types of requests.
  • a command is also a type of request.
  • different requests are handled by different logic circuits of the package.
  • the different logic circuits may be associated with different addresses. For example,
  • cryptographically authenticated communications may be associated with secure microcontroller functions and a first I2C address, while other communications may be associated with a sensor circuit and a second and/or reconfigured I2C address. In certain examples, these other communications via the second and/or reconfigured address can be scrambled or otherwise secured, not using the key used for the secure microcontroller functions.
  • a plurality of such logic circuitry packages (each of which may be associated with a different replaceable print apparatus component) may be connected to an I2C bus.
  • At least one address of the logic circuitry package may be an I2C compatible address (herein after, an I2C address), for example in accordance with an I2C protocol, to facilitate directing communications between master to slaves in accordance with the I2C protocol.
  • an I2C address for example in accordance with an I2C protocol, to facilitate directing communications between master to slaves in accordance with the I2C protocol.
  • a standard I2C communications address may be 7 or 10 bits in length. In other examples, other forms of digital and/or analog communication can be used.
  • Figure 1 illustrates one example of a printing system 100.
  • the printing system 100 includes a print apparatus 102 in communication with logic circuitry associated with a replaceable print apparatus component 104 via a
  • the communications link 106 may include an I2C capable or compatible bus (herein after, an I2C bus).
  • I2C bus an I2C capable or compatible bus
  • the replaceable print apparatus component 104 is shown as external to the print apparatus 102, in some examples, the replaceable print apparatus component 104 may be housed within the print apparatus.
  • the replaceable print apparatus component 104 may include, for example, a print material container or cartridge (which could be a build material container for 3D printing, a liquid or dry toner container for 2D printing, or an ink or liquid print agent container for 2D or 3D printing), which may in some examples include a print head or other dispensing or transfer component.
  • the replaceable print apparatus component 104 may, for example, contain a consumable resource of the print apparatus 102, or a component which is likely to have a lifespan which is less (in some examples, considerably less) than that of the print apparatus 102.
  • replaceable print apparatus component 104 there may be a plurality of replaceable print apparatus components, for example including print agent containers of different colors, print heads (which may be integral to the containers), or the like.
  • the print apparatus components 104 could include service components, for example to be replaced by service personnel, examples of which could include print heads, toner process cartridges, or logic circuit package by itself to adhere to corresponding print apparatus component and communicate to a compatible print apparatus logic circuit.
  • Figure 2 illustrates one example of a replaceable print apparatus component 200, which may provide the replaceable print apparatus component 104 of Figure 1 .
  • the replaceable print apparatus component 200 includes a data interface 202 and a logic circuitry package 204.
  • the logic circuitry package 204 decodes data received via the data interface 202.
  • the logic circuitry may perform other functions as set out below.
  • the data interface 202 may include an I2C or other interface. In certain examples, the data interface 202 may be part of the same package as the logic circuitry package 204.
  • the logic circuitry package 204 may be further configured to encode data for transmission via the data interface 202. In some examples, there may be more than one data interface 202 provided. In some examples, the logic circuitry package 204 may be arranged to act as a‘slave’ in I2C communications.
  • Figure 3 illustrates one example of a print apparatus 300.
  • the print apparatus 300 may provide the print apparatus 102 of Figure 1 .
  • the print apparatus 300 may serve as a host for replaceable components.
  • the print apparatus 300 includes an interface 302 for communicating with a replaceable print apparatus component and a controller 304.
  • the controller 304 includes logic circuitry.
  • the interface 302 is an I2C interface.
  • controller 304 may be configured to act as a host, or a master, in I2C communications.
  • the controller 304 may generate and send commands to at least one replaceable print apparatus component 200, and may receive and decode responses received therefrom.
  • the controller 304 may communicate with the logic circuitry package 204 using any form of digital or analog communication.
  • the print apparatus 102, 300 and replaceable print apparatus component 104, 200, and/or the logic circuitry thereof, may be manufactured and/or sold separately.
  • a user may acquire a print apparatus 102, 300 and retain the apparatus 102, 300 for a number of years, whereas a plurality of replaceable print apparatus components 104, 200 may be purchased in those years, for example as print agent is used in creating a printed output.
  • Figure 4A illustrates one example of a logic circuitry package 400a, which may for example provide the logic circuitry package 204 described in relation to Figure 2.
  • the logic circuitry package 400a may be associated with, or in some examples affixed to and/or be incorporated at least partially within, a
  • the logic circuitry package 400a is addressable via a first address and includes a first logic circuit 402a, wherein the first address is an I2C address for the first logic circuit 402a.
  • the first address may be configurable.
  • the first address is a fixed address (e.g.,“hard-wired”) intended to remain the same address during the lifetime of the first logic circuit 402a.
  • the first address may be associated with the logic circuitry package 400a at and during the connection with the print apparatus logic circuit, outside of the time periods that are associated with a second address, as will be set out below.
  • first addresses can be considered standard I2C addresses for logic circuitry packages 400a or replaceable print components.
  • the logic circuitry package 400a is also addressable via a second address.
  • the second address may be associated with different logic functions or, at least partially, with different data than the first address.
  • the second address may be associated with a different hardware logic circuit or a different virtual device than the first address.
  • the hardware logic circuit can include analog sensor functions.
  • the logic circuitry package 400a may include a memory to store the second address (in some examples in a volatile manner).
  • the memory may include a programmable address memory register for this purpose.
  • the second address may have a default second address while the second address (memory) field may be reconfigurable to a different address.
  • the second address may be reconfigurable to a temporary address by a second address command, whereby it is set (back) to the default second address after or at each time period command to enable the second address.
  • the second address may be set to its default address in an out-of-reset state whereby, after each reset, it is reconfigurable to the temporary (i.e., reconfigured) address.
  • the package 400a is configured such that, in response to a first command indicative of a first time period sent to the first address (and in some examples a task), the package 400a may respond in various ways.
  • the package 400a is configured such that it is accessible via at least one second address for the duration of the time period.
  • the package may perform a task, which may be the task specified in the first command.
  • the package may perform a different task.
  • the first command may, for example, be sent by a host such as a print apparatus in which the logic circuitry package 400a (or an associated replaceable print apparatus component) is installed.
  • the task may include turning on a heater and obtaining a sensor reading of a level sensor.
  • Further communication may be directed to memory addresses to be used to request information associated with these memory addresses.
  • the memory addresses may have a different configuration than the first and second address of the logic circuitry package 400a.
  • a host apparatus may request that a particular memory register is read out onto the bus by including the memory address in a read command.
  • a host apparatus may have a knowledge and/or control of the arrangement of a memory.
  • there may be a plurality of memory registers and corresponding memory addresses associated with the second address.
  • a particular register may be associated with a value, which may be static or reconfigurable. The host apparatus may request that the register be read out onto the bus by identifying that register using the memory address.
  • the registers may include any or any combination of address register(s), parameter register(s) (for example to store gain and/or offset parameters), sensor identification register(s) (which may store an indication of a type of sensor), sensor reading register(s) (which may store values read or determined using a sensor), sensor number register(s) (which may store a number or count of sensors), version identity register(s), memory register(s) to store a count of clock cycles, memory register(s) to store a value indicative of a read/write history of the logic circuitry, or other registers.
  • address register(s) for example to store gain and/or offset parameters
  • sensor identification register(s) which may store an indication of a type of sensor
  • sensor reading register(s) which may store values read or determined using a sensor
  • sensor number register(s) which may store a number or count of sensors
  • version identity register(s) memory register(s) to store a count of clock cycles
  • memory register(s) to store a value indicative of a read/write history of the logic
  • Figure 4B illustrates another example of a logic circuitry package 400b.
  • the package 400b includes a first logic circuit 402b, in this example, including a first timer 404a, and a second logic circuit 406a, in this example, including a second timer 404b. While in this example, each of the first and second logic circuits 402b, 406a include its own timer 404a, 404b, in other examples, they may share a timer or reference at least one external timer. In a further example, the first logic circuit 402b and the second logic circuit 406a are linked by a dedicated signal path 408. In other examples, that are not the topic of Figure 4B, a single integrated logic circuit may simulate the functions of the second logic circuit.
  • the logic circuitry package 400b may receive a first command including two data fields.
  • a first data field is a one byte data field setting a requested mode of operation.
  • the first command may include additional fields, such as an address field and/or a request for acknowledgement.
  • the logic circuitry package 400b is configured to process the first command.
  • the logic circuitry package 400b may generate an error code and output this to a communication link to be returned to host logic circuitry, for example in the print apparatus.
  • the logic circuitry package 400b measures the duration of the time period included in the first command, for example utilizing the timer 404a.
  • the timer 404a may include a digital“clock tree”.
  • the timer 404a may include an RC circuit, a ring oscillator, or some other form of oscillator or timer.
  • the timer may include a plurality of delay circuits each of which is set to expire after a certain time period, whereby depending on the timer period indicated in a first command, the delay circuit is chosen.
  • the first logic circuit 402b in response to receiving a valid first command, enables the second logic circuit 406a and effectively disables the first address, for example by tasking the first logic circuit 402b with a processing task.
  • enabling the second logic circuit 406a includes sending, by the first logic circuit 402b, an activation signal to the second logic circuit 406a.
  • the logic circuitry package 400b is configured such that the second logic circuit 406a is selectively enabled by the first logic circuit 402b.
  • the first logic circuit 402b is configured to use the first timer 404a to determine the duration of the enablement, that is, to set the time period of the enablement.
  • the second logic circuit 406a is enabled by the first logic circuit 402b sending a signal via a signal path 408, which may or may not be a dedicated signal path 408, that is, dedicated to enable the second logic circuit 406a.
  • the first logic circuit 402b may have a dedicated contact pin or pad connected to the signal path 408, which links the first logic circuit 402b and the second logic circuit 406a.
  • the dedicated contact pin or pad may be a General Purpose Input/Output (a GPIO) pin of the first logic circuit 402b.
  • the contact pin/pad may serve as an enablement contact of the second logic circuit 406a.
  • the second logic circuit 406a is addressable via at least one second address.
  • the second logic circuit 406a when the second logic circuit 406a is activated or enabled, it may have an initial, or default, second address, which may be an I2C address or have some other address format.
  • the second logic circuit 406a may receive instructions from a master or host logic circuitry to reconfigure the initial second address to a temporary second address.
  • the temporary second address may be an address which is selected by the master or host logic circuitry. This may allow the second logic circuit 406a to be provided in one of a plurality of packages 400 on the same I2C bus which, at least initially, share the same initial second address. This shared, default, address may later be set to a specific temporary address by the print apparatus logic circuit, thereby allowing the plurality of packages to have different second addresses during their temporary use, facilitating
  • the second logic circuit 406a may include a memory.
  • the memory may include a programmable address register to store the initial and/or temporary second address (in some examples in a volatile manner).
  • the second address may be set following, and/or by executing, an I2C write command.
  • the second address may be settable when the enablement signal is present or high, but not when it is absent or low.
  • the second address may be set to a default address when an enablement signal is removed and/or on restoration of enablement of the second logic circuit 406a. For example, each time the enable signal over the signal path 408 is low, the second logic circuit 406a, or the relevant part(s) thereof, may be reset.
  • the default address may be set when the second logic circuit 406a, or the relevant part(s) thereof, is switched out-of-reset.
  • the default address is a 7-bit or 10-bit identification value.
  • the default address and the temporary second address may be written in turn to a single, common, address register. For example, while the first address of the first logic circuit is different for each different associated print material (e.g., different color inks have different first addresses), the second logic circuits can be the same for the different print materials and have the same initial second address.
  • the second logic circuit 406a includes a first array 410 of cells and at least one second cell 412 or second array of second cells of a different type than the cells of the first array 410.
  • the second logic circuit 406a may include additional sensor cells of a different type than the cells of the first array 410 and the at least one second cell 412.
  • Each of the plurality of sensor types may be identifiable by a different sensor ID, while each cell in a cell array of the same type may also be identifiable by sensor ID.
  • the sensor ID may include both the sensor type ID to select the array or type and the sensor cell ID to select the cell in the selected type or array, whereby the latter may also be called“sub-“ID.
  • the sensor IDs may include a combination of addresses and values, for example register addresses and values.
  • the addresses of the sensor cell array ID and the sensor cell ID may be different. For example, an address selects a register that has a function to select a particular sensor or cell, and in the same transaction, the value selects the sensor or cell, respectively.
  • the second logic circuit may include registers and multiplex circuitry to select sensor cells in response to sensor IDs. In examples where there is only one cell of a certain sensor type, one sensor ID may be sufficient to select that cell. At the same time, for that single sensor cell, different sensor“sub-“IDs will not affect the sensor cell selection because there is only one sensor cell. In this disclosure, sensor ID parameters are described.
  • a sensor ID parameter may include a sensor ID.
  • a sensor ID parameter may include a sensor type ID or a sensor cell ID. The same sensor ID (e.g., to select a sensor type) and different sensor sub-IDs (e.g., to select a sensor cell) may be used to select different sensor cells.
  • the sensor ID parameters can include only the sensor sub-ID, for example where the sensor type has been previously set so that only the sensor cell needs to be selected.
  • the first cells 416a-416f, 414a-414f and the at least one second cell 412 can include resistors.
  • the first cells 416a-416f, 414a-414f and the at least one second cell 412 can include sensors.
  • the first cell array 410 includes a print material level sensor and the at least one second cell 412 includes another sensor and/or another sensor array, such as an array of strain sensing cells.
  • Further sensor types may include temperature sensors, resistors, diodes, crack sensors (e.g., crack sense resistors), etc.
  • the first cell array 410 includes a sensor configured to detect a print material level of a print supply, which may in some examples be a solid but in examples described herein is a liquid, for example, an ink or other liquid print agent.
  • the first cell array 410 may include a series of temperature sensors (e.g., cells 414a-414f) and a series of heating elements (e.g., cells 416a-416f), for example similar in structure and function as compared to the level sensor arrays described in WO2017/074342, WO2017/184147, and WO2018/022038.
  • the resistance of a resistor cell 414 is linked to its temperature.
  • the heater cells 416 may be used to heat the sensor cells 414 directly or indirectly using a medium.
  • the subsequent behavior of the sensor cells 414 depends on the medium in which they are submerged, for example whether they are in liquid (or in some examples, encased in a solid medium) or in air. Those which are submerged in liquid/encased may generally lose heat quicker than those which are in air because the liquid or solid may conduct heat away from the resistor cells 414 better than air. Therefore, a liquid level may be determined based on which of the resistor cells 414 are exposed to the air, and this may be determined based on a reading of their resistance following (at least the start of) a heat pulse provided by the associated heater cell 416.
  • each sensor cell 414 and heater cell 416 are stacked with one being directly on top of the other.
  • the heat generated by each heater cell 416 may be substantially spatially contained within the heater element layout perimeter, so that heat delivery is substantially confined to the sensor cell 414 stacked directly above the heater cell 416.
  • each sensor cell 414 may be arranged between an associated heater cell 416 and the fluid/air interface.
  • the second cell array 412 includes a plurality of different cells that may have a different function such as different sensing function(s).
  • the first and second cell array 410, 412 may include different resistor types. Different cells arrays 410, 412 for different functions may be provided in the second logic circuit 406a. More than two different sensor types may be provided, for example three, four, five or more sensor types, may be provided, wherein each sensor type may be represented by one or more sensor cells. Certain cells or cell arrays may function as stimulators (e.g., heaters) or reference cells, rather than as sensors.
  • FIG. 4C illustrates an example of how a first logic circuit 402c and a second logic circuit 406b of a logic circuitry package 400c, which may have any of the attributes of the circuits/packages described above, may connect to an I2C bus and to each other.
  • each of the circuits 402c, 406b has four pads (or pins) 418a-418d connecting to the Power, Ground, Clock, and Data lines of an I2C bus.
  • four common connection pads are used to connect both logic circuits 402c, 406b to four corresponding connection pads of the print apparatus controller interface. It is noted that in some examples, instead of four connection pads, there may be fewer connection pads.
  • power may be harvested from the clock pad; an internal clock may be provided; or the package could be grounded through another ground circuit; so that, one or more of the pads may be omitted or made redundant.
  • the package could use only two or three interface pads and/or could include“dummy” pads.
  • Each of the circuits 402c, 406b has a contact pin 420, which are connected by a common signal line 422.
  • the contact pin 420 of the second circuit serves as an enablement contact thereof.
  • each of the first logic circuit 402c and the second logic circuit 406b include a memory 423a, 423b.
  • the memory 423a of the first logic circuit 402c stores information including cryptographic values (for example, a cryptographic key and/or a seed value from which a key may be derived) and identification data and/or status data of the associated replaceable print apparatus component.
  • the memory 423a may store data representing characteristics of the print material, for example, any part, or any combination of its type, color, color map, recipe, batch number, age, etc.
  • the first logic circuit 402c may be, or function as, a microcontroller or secure microcontroller.
  • memory 423b of the second logic circuit 406b includes a programmable address register to contain an initial address of the second logic circuit 406b when the second logic circuit 406b is first enabled and to subsequently contain a new (temporary) second address (in some examples in a volatile manner) after that new second address has been communicated by the print apparatus.
  • the new, e.g., temporary, second address may be programmed into the second address register after the second logic circuit 406b is enabled, and may be effectively erased or replaced at the end of an enablement period.
  • the memory 423b may further include programmable registers to store any, or any combination of a read/write history data, cell (e.g., resistor or sensor) count data, Analog to Digital converter data (ADC and/or DAC), and a clock count, in a volatile or non-volatile manner.
  • the memory 423b may also receive and/or store calibration parameters, such as offset and gain parameters. Use of such data is described in greater detail below. Certain characteristics, such as cell count or ADC or DAC
  • the memory 423b of the second logic circuit 406b stores any or any combination of an address, for example the second I2C address; an identification in the form of a revision ID; and the index number of the last cell (which may be the number of cells less one, as indices may start from 0), for example for each of different cell arrays or for multiple different cell arrays if they have the same number of cells.
  • the memory 423b of the second logic circuit 406 may store any or any combination of timer control data, which may enable a timer of the second circuit, and/or enable frequency dithering therein in the case of some timers such as ring oscillators; a dither control data value (to indicate a dither direction and/or value); and a timer sample test trigger value (to trigger a test of the timer by sampling the timer relative to clock cycles measureable by the second logic circuit 406b).
  • timer control data may enable a timer of the second circuit, and/or enable frequency dithering therein in the case of some timers such as ring oscillators; a dither control data value (to indicate a dither direction and/or value); and a timer sample test trigger value (to trigger a test of the timer by sampling the timer relative to clock cycles measureable by the second logic circuit 406b).
  • the memories 423a, 423b are shown as separate memories here, they could be combined as a shared memory resource, or divided in some other way.
  • the memories 423a, 423b may include a single or multiple memory devices, and may include any or any combination of volatile memory (e.g., DRAM, SRAM, registers, etc.) and non-volatile memory (e.g., ROM, EEPROM, Flash, EPROM, memristor, etc.).
  • Figure 4D illustrates an example of processing circuitry 424 which is for use with a print material container.
  • the processing circuitry 424 may be affixed or integral thereto.
  • the processing circuitry 424 may include any of the features of, or be the same as, any other logic circuitry package of this disclosure.
  • the processing circuitry 424 includes a memory 426 and a first logic circuit 402d which enables a read operation from memory 426.
  • the processing circuitry 424 is accessible via an interface bus of a print apparatus in which the print material container is installed and is associated with a first address and at least one second address.
  • the bus may be an I2C bus.
  • the first address may be an I2C address of the first logic circuit 402d.
  • the first logic circuit 402d may have any of the attributes of the other examples
  • the first logic circuit 402d is adapted to participate in authentication of the print materials container by a print apparatus in which the container is installed.
  • this may include a cryptographic process such as any kind of cryptographically authenticated communication or message exchange, for example based on a key stored in the memory 426, and which can be used in conjunction with information stored in the printer.
  • a printer may store a version of a key which is compatible with a number of different print material containers to provide the basis of a‘shared secret’.
  • authentication of a print material container may be carried out based on such a shared secret.
  • the first logic circuit 402d may participate in a message to derive a session key with the print apparatus and messages may be signed using a message authentication code based on such a session key. Examples of logic circuits configured to cryptographically authenticate messages in accordance with this paragraph are described in US patent publication No. 9619663.
  • the memory 426 may store data including:
  • the memory 426 further includes cell count data (e.g., sensor count data) and clock count data.
  • Clock count data may indicate a clock speed of a first and/or second timer 404a, 404b (i.e., a timer associated with the first logic circuit or the second logic circuit).
  • at least a portion of the memory 426 is associated with functions of a second logic circuit, such as a second logic circuit 406a as described in relation to Figure 4B above.
  • at least a portion of the data stored in the memory 426 is to be communicated in response to commands received via the second address, for example the earlier mentioned initial or reconfigured/temporary second address.
  • the memory 426 includes a programmable address register or memory field to store a second address of the processing circuitry (in some examples in a volatile manner).
  • the first logic circuit 402d may enable read operation from the memory 426 and/or may perform processing tasks.
  • the memory 426 may, for example, include data representing
  • the memory 426 may, for example, include data to be communicated in response to commands received via the first address.
  • the processing circuitry may include a first logic circuit to enable read operations from the memory and perform processing tasks.
  • the processing circuitry 424 is configured such that, following receipt of the first command indicative of a task and a first time period sent to the first logic circuit 402d via the first address, the processing circuitry 424 is accessible by at least one second address for a duration of the first time period.
  • the processing circuitry 424 may be configured such that in response to a first command indicative of a task and a first time period sent to the first logic circuit 402d addressed using the first address, the processing circuitry 424 is to disregard (e.g.,‘ignore’ or‘not respond to’) I2C traffic sent to the first address for substantially the duration of the time period as measured by a timer of the processing circuitry 424 (for example a timer 404a, 404b as described above).
  • the processing circuitry may additionally perform a task, which may be the task specified in the first command.
  • the term‘disregard’ or‘ignore’ as used herein with respect to data sent on the bus may include any or any combination of not receiving (in some examples, not reading the data into a memory), not acting upon (for example, not following a command or instruction) and/or not responding (i.e., not providing an acknowledgement, and/or not responding with requested data).
  • the processing circuitry 424 may have any of the attributes of the logic circuitry packages 400 described herein.
  • the processing circuitry 424 may further include a second logic circuit wherein the second logic circuit is accessible via the second address.
  • the second logic circuit may include at least one sensor which is readable by a print apparatus in which the print material container is installed via the second address.
  • such a sensor may include a print materials level sensor.
  • the processing circuitry 424 may include a single, integral logic circuit, and one or more sensors of one or more types.
  • Figure 4E illustrates another example of a first logic circuit 402e and second logic circuit 406c of a logic circuitry package 400d, which may have any of the attributes of the circuits/packages of the same names described herein, which may connect to an I2C bus via respective interfaces 428a, 428b and to each other.
  • the respective interfaces 428a, 428b are connected to the same contact pad array, with only one data pad for both logic circuits 402e, 406c, connected to the same serial I2C bus.
  • communications addressed to the first and the second address are received via the same data pad.
  • the first logic circuit 402e includes a microcontroller 430, a memory 432, and a timer 434.
  • the microcontroller 430 may be a secure microcontroller or customized integrated circuitry adapted to function as a microcontroller, secure or non-secure.
  • the second logic circuit 406c includes a transmit/receive module 436, which receives a clock signal and a data signal from a bus to which the package 400d is connected, data registers 438, a multiplexer 440, a digital controller 442, an analog bias and analog to digital converter 444, at least one sensor or cell array 446 (which may in some examples include a level sensor with one or multiple arrays of resistor elements), and a power-on reset (POR) device 448.
  • the POR device 448 may be used to allow operation of the second logic circuit 406c without use of a contact pin 420.
  • the analog bias and analog to digital converter 444 receives readings from the sensor array(s) 446 and from additional sensors 450, 452, 454. For example, a current may be provided to a sensing resistor and the resultant voltage may be converted to a digital value. That digital value may be stored in a register and read out (i.e., transmitted as serial data bits, or as a‘bitstream’) over the I2C bus.
  • the analog to digital converter 444 may utilize parameters, for example, gain and/or offset parameters, which may be stored in registers.
  • an ambient temperature sensor 450 may sense, respectively, an ambient temperature, a structural integrity of a die on which the logic circuitry is provided, and a fluid temperature.
  • Digital controller 442 is communicatively coupled to the I2C interface 428b (e.g., via transmit/receive module 436) and the data registers 438.
  • Digital controller 442 may receive, via the I2C interface 428b, read commands to read data from the data registers 438 and write commands to write data to the data registers 438.
  • digital controller 442 may initiate a function of the logic circuitry package 400d.
  • the function may include a sensor read function (e.g., of a sensor of sensor array 446, ambient temperature sensor 450, crack detector 452, or fluid temperature sensor 454), a clock sampling function, a calibration function, or another function.
  • Data registers 438 may store parameters for configuring the logic circuitry package 400d and data generated within the logic circuitry package 400d.
  • Each of the data registers may include an 8-bit register.
  • Figure 5A illustrates an example of a possible practical arrangement of a second logic circuit embodied by a sensor assembly 500 in association with a circuitry package 502.
  • the sensor assembly 500 may include a thin film stack and include at least one sensor array such as a fluid level sensor array.
  • the arrangement has a high length to width aspect ratio (e.g., as measured along a substrate surface), for example being around 0.2 mm in width, for example less than 1 mm, 0.5 mm, or 0.3 mm, and around 20 mm in length, for example more than 10 mm, leading to length to width aspect ratios equal to or above approximately 20:1 , 40:1 , 60:1 , 80:1 , or 100:1 .
  • the length may be measured along the height.
  • the logic circuit in this example may have a thickness of less than 1 mm, less than 0.5 mm, or less than 0.3 mm, as measured between the bottom of the (e.g., silicon) substrate and the opposite outer surface. These dimensions mean that the individual cells or sensors are small.
  • the sensor assembly 500 may be provided on a relatively rigid carrier 504, which in this example also carries Ground, Clock, Power and Data I2C bus contacts.
  • Figure 5B illustrates a perspective view of a print cartridge 512 including a logic circuitry package of any of the examples of this disclosure.
  • the print cartridge 512 has a housing 514 that has a width W less than its height H and that has a length L or depth that is greater than the height H.
  • a print liquid output 516 (in this example, a print agent outlet provided on the underside of the cartridge 512), an air input 518 and a recess 520 are provided in a front face of the cartridge 512.
  • the recess 520 extends across the top of the cartridge 512 and I2C bus contacts (i.e., pads) 522 of a logic circuitry package 502 (for example, a logic circuitry package 400a-400d as described above) are provided at a side of the recess 520 against the inner wall of the side wall of the housing 514 adjacent the top and front of the housing 514.
  • the data contact is the lowest of the contacts 522.
  • the logic circuitry package 502 is provided against the inner side of the side wall.
  • the logic circuitry package 502 includes a sensor assembly as shown in Figure 5A.
  • a replaceable print apparatus component includes a logic circuitry package of any of the examples described herein, wherein the component further includes a volume of liquid.
  • the component may have a height H that is greater than a width W and a length L that is greater than the height, the width extending between two sides.
  • Interface pads of the package may be provided at the inner side of one of the sides facing a cut-out for a data interconnect to be inserted, the interface pads extending along a height direction near the top and front of the component, and the data pad being the bottom-most of the interface pads, the liquid and air interface of the component being provided at the front on the same vertical reference axis parallel to the height H direction wherein the vertical axis is parallel to and distanced from the axis that intersects the interface pads (i.e., the pads are partially inset from the edge by a distance D).
  • the rest of the logic circuitry package may also be provided against the inner side.
  • a damaged sensor may provide inaccurate measurements, and result in inappropriate decisions by a print apparatus when evaluating the
  • communications with the logic circuitry based on a specific communication sequence provide expected results. This may validate the operational health of the logic circuitry.
  • Figures 6A-6E are flow diagrams illustrating one example of a method 600 that may be carried out by a logic circuitry package, such as logic circuitry package 400a-440d, 502, or by processing circuitry 424.
  • the logic circuitry package may be attached to a replaceable component, such as the print cartridge 512 of Figure 5B.
  • the logic circuitry package may receive, via the I2C interface, communications directed to a second I2C address.
  • the communications directed to the second I2C address may include commands directed to memory (e.g., register) addresses of the logic circuit.
  • Each command may include the default second and/or reconfigured second I2C address for addressing the logic circuit and a memory address for addressing one of multiple logic functions of that logic circuit.
  • the functions may generate certain data, which may be output (e.g., to a register having a certain read address) in response to a read command.
  • different read commands to different read addresses are associated with different functions of the logic circuit.
  • the term“transmit” refers to passing data from the logic circuitry package to a print apparatus logic circuit via the I2C interface, whether the data is passed in response to a read command from a print apparatus logic circuit to a read field of the logic circuitry package or in response to a function of the logic circuitry package itself.
  • At least one logic circuit of the logic circuitry package may respond to communications over the I2C interface that are directed to an initial or reconfigured I2C address.
  • the at least one logic circuit may receive, via the I2C interface, a write command to a first memory address of the logic circuit to initiate a first function of the logic circuit.
  • logic circuit 406c of logic circuitry package 400d of Figure 4E may receive, via the I2C interface 428b, a write command to a first address of data registers 438 to initiate a first function of logic circuit 406c.
  • the at least one logic circuit may generate first data in response to the first function.
  • the at least one logic circuit may receive, via the I2C interface, a first read command to a second memory address of the logic circuit.
  • the at least one logic circuit is to transmit, via the I2C interface, the first data in response to the first read command to the second memory address.
  • the first and second memory addresses may be memory field (e.g., register) addresses.
  • the first memory address is for a sensor register
  • the first function is a sensor function.
  • the first data may be a digital value corresponding to the output of a sensor.
  • the second memory address is for a second data register or first read field.
  • the at least one logic circuit may further receive, via the I2C interface, a write command to a third memory address of the logic circuit to initiate a second function of the logic circuit different from the first function.
  • the at least one logic circuit may generate second data in response to the second function.
  • the at least one logic circuit may receive, via the I2C interface, a second read command to the second memory address of the logic circuit.
  • the at least one logic circuit may transmit, via the I2C interface, the second data in response to the second read command to the second memory address.
  • the second function includes a clock sampling function, and the second data is a first portion of a cycle count of the sampled clock.
  • the at least one logic circuit may further receive, via the I2C interface, a write command to a third memory address of the logic circuit to initiate a second function of the logic circuit different from the first function.
  • the at least one logic circuit may generate second data in response to the second function.
  • the at least one logic circuit may receive, via the I2C interface, a read command to a fourth memory address of the logic circuit.
  • the at least one logic circuit may transmit, via the I2C interface, the second data in response to the read command to the fourth memory address.
  • the first function includes a sensor read function.
  • the at least one logic circuit may select a sensor in response to the write command to the first memory address and generate the first data including a digital value corresponding to an output signal of the sensor.
  • the first address, the second address, and the further addresses are memory field (e.g., register) addresses of the at least one logic circuit.
  • the at least one logic circuit may further receive, via the I2C interface, the write command to the first memory address to write to a first memory field (e.g., data register) of the logic circuit to initiate the first function of the logic circuit.
  • the at least one logic circuit may receive, via the I2C interface, the first read command to the second memory address to read a second memory field (e.g., a second data register or first read field) of the logic circuit that has been written to with the first data.
  • the at least one logic circuit may transmit, via the I2C interface, the first data stored in the second memory field (e.g., second data register or first read field) in response to the first read command to the second memory address.
  • the at least one logic circuit may further receive, via the I2C interface, a write command to write to a third memory field (e.g., third data register) of the logic circuit to initiate a second function of the logic circuit different from the first function.
  • the second function may be a clock sampling function to obtain a digital value representing a sampled clock value.
  • the at least one logic circuit may receive, via the I2C interface, a read command to read a fourth memory field (e.g., fourth data register or second read field) of the logic circuit that has been written to in response to the second function.
  • the at least one logic circuit may transmit, via the I2C interface, the data stored in the fourth memory field (e.g., fourth data register or second read field).
  • the first function includes a sensor read function.
  • the first data register (or first memory field) stores a sensor address for a sensor to read and the second data register (or second memory field or first read field) stores a digital value corresponding to an output signal of the sensor.
  • the sensor may include an ink level sensor, a strain gauge sensor, a thermal sensor, or another suitable sensor.
  • the second function includes a clock sampling function and the fourth data register stores at least a portion of a cycle count of the sampled clock.
  • the at least one logic circuit may also be configured to receive, via the I2C interface, a read command to read a fifth data register of the logic circuit that has been written to in response to the second function.
  • the at least one logic circuit may transmit, via the I2C interface, the data stored in the fifth data register.
  • the fifth data register stores another portion of a cycle count of the sampled clock.
  • the first function includes a calibration function.
  • the first data register stores a calibration parameter and the second data register stores a digital value corresponding to an output signal of a sensor calibrated based on the calibration parameter.
  • the first data register may include an 8-bit register and the second data register may include an 8-bit register.
  • Figure 7 illustrates another example of a logic circuitry package 700.
  • Logic circuitry package 700 may be provided on a replaceable print apparatus component.
  • Logic circuitry package 700 includes a controller 702, a memory 704, a clock generator 710, a counter 712, an analog to digital converter 714, and a sensor array and corresponding heaters 716.
  • Controller 702 is electrically coupled to memory 704, clock generator 710, counter 712, analog to digital converter 714, and sensor array and corresponding heaters 716.
  • the sensor array of 716 is electrically coupled to analog to digital converter 714.
  • Memory 704 stores a heat count parameter 706 and a conversion count parameter 708.
  • Heat count parameter 706 is a count of a counter (e.g., counter 712) corresponding to a period during which a selected heater of 716 is turned on as will be described below.
  • the conversion count parameter is a count of a counter (e.g., counter 712) corresponding to a waiting period prior to converting a selected sensor signal of a sensor of 716 to a digital value (e.g., via analog to digital converter 714) as will be described below.
  • Controller 702 controls the sensor array and corresponding heaters 716, the clock generator 710, the counter 712, and the analog to digital converter 714 to implement a heat and convert function of the logic circuity package as will be described below with reference to Figures 8A-9B.
  • Counter 712 is to count cycles of a clock signal to provide a count.
  • the clock signal may be generated by clock generator 710.
  • the analog to digital converter 714 includes a successive approximation analog to digital converter.
  • Each sensor of the sensor array of 716 may include a thermal sensor 414 corresponding to a heater cell 416 as previously described and illustrated with reference to first cell array 410 of Figure 4B.
  • memory 704 includes a first 8-bit register to store the heat count parameter 706 and a second 8-bit register to store the conversion count parameter 708.
  • Figure 8A-8C illustrate state machines that may be implemented by a logic circuitry package, such as logic circuitry package 400a-440d, 700, or by processing circuitry 424.
  • Figure 8A illustrates a top level heat and convert state machine 730 for selecting a sensor and a corresponding heater(s), turning on the heater(s) for a first predetermined period, and converting the selected sensor signal to a digital value after a second predetermined period. The digital value corresponding to the sensor signal may be used as part of a level sensor reading.
  • Figure 8B illustrates a heating state machine 750 dependent upon state machine 730 for turning on a selected heater for the first predetermined period.
  • Figure 8C illustrates a converter (e.g., a successive approximation (SAR) converter) state machine 770 dependent upon state machine 730 for converting the selected sensor signal to a digital value after the second predetermined period elapses.
  • SAR successive approximation
  • top level heat and convert state machine 730 includes an idle state 732, a shift state 738, and a count state 744. State machine 730 remains in the idle state 732 as indicated at 734 until a command is received to start heating and converting as indicated at 736. The command includes data identifying which sensor and corresponding heater(s) are to be selected. In response to the command to start, state machine 730 transitions to the shift state 738. The shift state 738 shifts the received data through sensor/heater select scan chains to select the identified sensor and
  • State machine 738 remains in the shift state 738 as indicated at 740 until the shifting is done as indicated at 742 and the identified sensor and corresponding heater(s) are selected. With the shifting done, state machine 730 transitions to the count state 744.
  • the count state 744 starts a counter (e.g., counter 712 of Figure 7) for state machine 750 of Figure 8B and state machine 770 of Figure 8C.
  • State machine 730 remains in the count state 744 as indicated at 746 and continues to increment the count (e.g., for each cycle of clock generator 710) until the heating of state machine 750 is done and the conversion of state machine 770 is done as indicated at 748. With the heating of state machine 750 done and the conversion of state machine 770 done, state machine 730 resets the count and returns to the idle state 732 and awaits the next command to start.
  • heating state machine 750 includes an idle state 752 and a heat state 758.
  • State machine 750 remains in the idle state 752 as indicated at 754 until the shifting of shift state 738 of state machine 730 of Figure 8A is done as indicated at 756. With the shifting done, state machine 750 transitions to the heat state 758.
  • the heat state 758 turns on the selected heater(s).
  • State machine 750 remains in the heat state 758 with the selected heater(s) turned on as indicated at 760 until the count (of count state 744 of state machine 730) is greater than or equal to the heat count parameter (e.g., the heat count parameter 706 stored in memory 704). With the count greater than or equal to the heat count parameter as indicated at 762, the selected heater(s) is turned off and state machine 750 returns to the idle state 752 and awaits for the next shifting to be done.
  • the heat count parameter e.g., the heat count parameter 706 stored in memory 704
  • converter state machine 770 includes an idle state 772, a wait state 778, and a convert state 784.
  • State machine 770 remains in the idle state 772 as indicated at 774 until the shifting of shift state 738 of state machine 730 of Figure 8A is done as indicated at 776. With the shifting done, state machine 770 transitions to the wait state 778.
  • State machine 770 remains in the wait state 778 as indicated at 780 until the count (of count state 744 of state machine 730) is equal to the conversion count parameter (e.g., the conversion count parameter 708 stored in memory 704). With the count equal to the conversion count parameter as indicated at 782, state machine 770 transitions to the convert state at 784.
  • the convert state 784 converts the selected sensor signal to a digital value corresponding to the sensor signal (e.g., via analog to digital converter 714).
  • State machine 770 remains in the convert state 784 as indicated at 786 until the conversion is done. With the conversion done as indicated at 788, the state machine 770 returns to the idle state 772 and awaits for the next shifting to be done.
  • FIGS 9A-9B are flow diagrams illustrating another example of a method 800 that may be carried out by a logic circuitry package, such as logic circuitry package 400a-440d, 700, or by processing circuitry 424.
  • a controller e.g., controller 702 of Figure 7 of the logic circuitry package may select a first sensor and a corresponding first heater of the array (e.g., of array 716) in response to a first command.
  • the controller may enable the counter (e.g., counter 712) with the first sensor and the corresponding first heater selected.
  • the controller may turn on the first heater while the count is less than the heat count parameter.
  • the controller may enable the analog to digital converter (e.g., ADC 714) to convert an output signal of the first sensor to a digital value once the count equals the conversion count parameter.
  • ADC 714 analog to digital converter
  • the controller may further reset the counter.
  • the controller may select a second sensor and a corresponding second heater of the array in response to a second command.
  • the controller may enable the counter with the second sensor and the
  • the controller may turn on the second heater while the count is less than the heat count parameter.
  • the controller may enable the analog to digital converter to convert an output signal of the second sensor to a digital value once the count equals the conversion count parameter. In one example, the heat count parameter is greater than the conversion count parameter.
  • Figure 10 illustrates another example of a logic circuitry package 900.
  • Figure 10 illustrates how the logic circuitry package 900 may generate a digital output (e.g., output count value) based on inputs including a sensor ID, write commands and/or read commands.
  • Logic circuitry package 900 includes a logic circuit with a processor 902 communicatively coupled to a memory 904.
  • Memory 904 may store look up table(s) and/or list(s) 906 and/or algorithm(s)
  • Logic circuitry package 900 may also include any of the features of logic circuitry packages 400a-400d, 700 or processing circuitry 424 as previously described.
  • the logic circuitry package 900 may include at least one sensor 910, or multiple sensors of different types.
  • the logic circuit may be configured to consult a respective sensor 910, in combination with the LUT(s)/list(s) 906 and/or algorithm(s) 908, based on the sensor ID and read and/or write commands, to generate the digital output.
  • the at least one sensor 910 may include a sensor to detect an effect of a pneumatic actuation of the print apparatus upon the replaceable print component, and/or a sensor to detect an approximate temperature, and/or other sensors.
  • the logic circuitry package 900 may include a plurality of sensors of different types, for example, at least two sensors of different types, wherein the logic circuit may be configured to select and consult one of the sensors based on the sensor ID, and output a digital value based on a signal of the selected sensor.
  • the output count values may be generated using the LUT(s) and or list(s) 906 and/or algorithm(s) 908 whereby the read and write commands may be used as input.
  • a signal of at least one sensor 910 may be consulted as input for the LUT.
  • the output count values may be digitally generated, rather than obtained from analog sensor measurements or other functions.
  • logic circuitry package 900 may implement the method 600 of Figures 6A-6E without implementing any actual functions and without converting any actual sensor measurements.
  • analog sensor measurements may be used to thereafter digitally generate the output count value, not necessarily directly converted, but rather, using a LUT, list or algorithm, whereby the sensor signal is used to choose a portion or function of the LUT, list or algorithm.
  • the example logic circuitry package 900 may be used as an alternative to the complex thin film sensor arrays addressed elsewhere in this disclosure.
  • the example logic circuitry package 900 may be configured to generate outputs that are validated by the same print apparatus logic circuit designed to be
  • the alternative package 900 may be cheaper or simpler to manufacture, or simply be used as an alternative to the earlier mentioned packages, for example to facilitate printing and validation by the print apparatus.
  • the logic circuitry packages described herein mainly include hardwired routings, connections, and interfaces between different components.
  • the logic circuitry packages may also include at least one wireless connection, wireless communication path, or wireless interface, for internal and/or external signaling, whereby a wirelessly connected element may be considered as included in the logic circuitry package and/or replaceable component.
  • certain sensors may be wireless connected to communicate wirelessly to the logic circuit/sensor circuit.
  • sensors such as pressure sensors and/or print material level sensors may communicate wirelessly with other portions of the logic circuit.
  • the external interface of the logic circuitry package, to communicate with the print apparatus logic circuit may include a wireless interface.
  • a power source such as a battery or a power harvesting source that may harvest power from data or clock signals.
  • Certain example circuits of this disclosure relate to outputs that vary in a certain way in response to certain commands, events and/or states. It is also explained that, unless calibrated in advance, responses to these same events and/or states may be“clipped”, for example so that they cannot be characterized or are not relatable to these commands, events and/or states.
  • Certain alternative (at least partly)“virtual” embodiments discussed in this disclosure may operate with LUTs or algorithms, which may similarly generate, before calibration or installation, clipped values, and after calibration or installation, characterizable values whereby such alternative embodiment, should also be considered as already configured or adapted to provide for the characterizable output, even before calibration/installation.
  • the logic circuitry package outputs count values in response to read requests. In many examples, the output of count values is discussed. In certain examples, each separate count value is output in response to each read request. In another example, a logic circuit is configured to output a series or plurality of count values in response to a single read request. In other examples, output may be generated without a read request.
  • Each of the logic circuitry packages 400a-400d, 700 described herein may have any feature of any other logic circuitry packages 400a-400d, 700 described herein or of the processing circuitry 424. Any logic circuitry packages 400a-400d, 700 or the processing circuitry 424 may be configured to carry out at least one method block of the methods described herein. Any first logic circuit may have any attribute of any second logic circuit, and vice versa.
  • Examples in the present disclosure can be provided as methods, systems or machine readable instructions, such as any combination of software, hardware, firmware or the like. Such machine readable instructions may be included on a machine readable storage medium (including but not limited to EEPROM, PROM, flash memory, disc storage, CD-ROM, optical storage, etc.) having machine readable program codes therein or thereon.
  • a machine readable storage medium including but not limited to EEPROM, PROM, flash memory, disc storage, CD-ROM, optical storage, etc.
  • the machine readable instructions may, for example, be executed by a general purpose computer, a special purpose computer, an embedded processor or processors of other programmable data processing devices to realize the functions described in the description and diagrams.
  • a processor or processing circuitry may execute the machine readable instructions
  • processors may be implemented by a processor executing machine readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry.
  • the term ‘processor’ is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate array etc.
  • the methods and functional modules may all be performed by a single processor or divided amongst several processors.
  • Such machine readable instructions may also be stored in a machine readable storage (e.g., a tangible machine readable medium) that can guide the computer or other programmable data processing devices to operate in a specific mode.
  • a machine readable storage e.g., a tangible machine readable medium
  • Such machine readable instructions may also be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing, thus the instructions executed on the computer or other programmable devices realize functions specified by block(s) in the flow charts and/or in the block diagrams.
  • teachings herein may be implemented in the form of a computer software product, the computer software product being stored in a storage medium and comprising a plurality of instructions for making a computer device implement the methods recited in the examples of the present disclosure.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Fluid Mechanics (AREA)
  • Theoretical Computer Science (AREA)
  • Thermal Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Ink Jet (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)

Abstract

L'invention concerne un boîtier de circuit logique pour un composant d'appareil d'impression remplaçable qui comprend une interface I2C pour communiquer avec un circuit logique d'appareil d'impression et au moins un circuit logique. Le ou les circuits logiques sont configurés pour répondre à des communications sur l'interface I2C qui sont dirigées vers une adresse I2C initiale ou reconfigurée. Le ou les circuits logiques sont configurés pour recevoir, par l'intermédiaire de l'interface I2C, une instruction d'écriture à une première adresse de mémoire du circuit logique pour initier une première fonction du circuit logique. Le ou les circuits logiques sont configurés pour générer des premières données en réponse à la première fonction. Le ou les circuits logiques sont configurés pour recevoir, par l'intermédiaire de l'interface I2C, une première instruction de lecture à une seconde adresse de mémoire du circuit logique. Le ou les circuits logiques sont configurés pour transmettre, par l'intermédiaire de l'interface I2C, les premières données en réponse à la première instruction de lecture à la seconde adresse de mémoire.
PCT/US2019/058048 2018-12-03 2019-10-25 Boîtier de circuit logique WO2020117397A1 (fr)

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CN201980077718.1A CN113168446A (zh) 2018-12-03 2019-10-25 逻辑电路系统封装
US16/768,321 US11407228B2 (en) 2018-12-03 2019-10-25 Logic circuitry package
EP19805451.2A EP3688643A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique

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USPCT/US2018/063631 2018-12-03
PCT/US2019/026161 WO2020117308A1 (fr) 2018-12-03 2019-04-05 Circuiterie logique
PCT/US2019/026133 WO2020117304A1 (fr) 2018-12-03 2019-04-05 Ensemble de circuits logiques
USPCT/US2019/026161 2019-04-05
USPCT/US2019/026152 2019-04-05
PCT/US2019/026152 WO2020204951A1 (fr) 2019-04-05 2019-04-05 Capteur de propriétés de fluide
USPCT/US2019/026133 2019-04-05

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PCT/US2019/057987 WO2020117392A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057991 WO2020117394A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058201 WO2020117402A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057977 WO2020117389A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuiterie logique
PCT/US2019/058006 WO2020117396A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuiterie logique
PCT/US2019/058048 WO2020117397A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058001 WO2020117395A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058172 WO2020117401A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/064226 WO2020117797A1 (fr) 2018-12-03 2019-12-03 Composant d'appareil d'impression remplaçable
PCT/US2019/064213 WO2020117786A1 (fr) 2018-12-03 2019-12-03 Boîtier de circuit logique
PCT/US2019/064192 WO2020117774A1 (fr) 2018-12-03 2019-12-03 Boîtier de circuiterie logique
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PCT/US2019/057987 WO2020117392A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057991 WO2020117394A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/058201 WO2020117402A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuit logique
PCT/US2019/057977 WO2020117389A1 (fr) 2018-12-03 2019-10-25 Boîtier de circuiterie logique
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PCT/US2019/064226 WO2020117797A1 (fr) 2018-12-03 2019-12-03 Composant d'appareil d'impression remplaçable
PCT/US2019/064213 WO2020117786A1 (fr) 2018-12-03 2019-12-03 Boîtier de circuit logique
PCT/US2019/064192 WO2020117774A1 (fr) 2018-12-03 2019-12-03 Boîtier de circuiterie logique
PCT/US2019/064297 WO2020117848A1 (fr) 2018-12-03 2019-12-03 Circuits logiques

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WO2020117395A1 (fr) 2020-06-11
WO2020117393A1 (fr) 2020-06-11
WO2020117848A1 (fr) 2020-06-11
WO2020117774A1 (fr) 2020-06-11
WO2020117402A1 (fr) 2020-06-11
WO2020117389A1 (fr) 2020-06-11
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WO2020117797A1 (fr) 2020-06-11

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