WO2020113896A1 - Goa 阵列基板的制作方法及液晶显示器 - Google Patents

Goa 阵列基板的制作方法及液晶显示器 Download PDF

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Publication number
WO2020113896A1
WO2020113896A1 PCT/CN2019/084270 CN2019084270W WO2020113896A1 WO 2020113896 A1 WO2020113896 A1 WO 2020113896A1 CN 2019084270 W CN2019084270 W CN 2019084270W WO 2020113896 A1 WO2020113896 A1 WO 2020113896A1
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Prior art keywords
goa
metal layer
array substrate
signal line
display area
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PCT/CN2019/084270
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English (en)
French (fr)
Inventor
陈仁禄
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to the field of display technology, and in particular to a method for manufacturing an array substrate row driver (GOA) array substrate and a liquid crystal display.
  • GOA array substrate row driver
  • LCD liquid crystal displays
  • OLED Organic Light Emitting Diode
  • LCD display panel mainly includes a thin film transistor (TFT) array substrate, a color filter (CF) substrate, and a liquid crystal layer (Liquid Crystal) disposed between the two substrates Layer).
  • TFT thin film transistor
  • CF color filter
  • Liquid Crystal liquid crystal layer
  • the GOA circuit uses multiple TFT tubes, the channel length of each tube, the source/drain etch and the final completion value are critical to the normal operation and stability of the entire circuit.
  • the source signal of each level of GOA comes from the bus area of GOA. If the second metal layer (M2) transmitting the signal in the GOA Busline area of the panel is short-circuited with the first metal layer (M1) on the bottom layer, it will cause GOA If the clock signal is disordered, there will be a high temperature which will lead to screen burn and display failure. In view of this, how to improve the probability of short-circuiting of the GOA bus areas M2 and M1 of the display panel is an urgent problem to be solved.
  • the purpose of the present invention is to provide a method for manufacturing an array substrate row drive (GOA) array substrate, so that the traces between the upper and lower cross-over regions of the GOA drive circuit and the passivation layer can be gently contacted to reduce the parasitic capacitance, In order to avoid the injury caused by electrostatic discharge and reduce the risk of black screen.
  • GOA array substrate row drive
  • Another object of the present invention is to provide a liquid crystal display, which includes a GOA array substrate to reduce the probability of short-circuiting of the GOA bus area in the display panel and improve the stability and reliability of the display device product.
  • the present invention provides a method for manufacturing an array substrate row drive (GOA) array substrate, which includes: defining a display area and a non-display area on a base substrate, and the non-display area has Bus area; a GOA driver circuit is formed in the non-display area, which includes a plurality of connected GOA units, each of the GOA units includes a first metal layer, and a second metal layer above the first metal layer ; And forming a passivation layer on the GOA drive circuit, and forming support pillars and color film substrates on the passivation layer; wherein the second metal layer is a half-tone mask, which includes at least one A non-full-transmissive area with a mask penetration rate, and a patterned signal line is formed on the second metal layer through a photolithography process, and the signal line includes a main portion and a relative portion of the main portion A side wall formed by two sides gently inclined, wherein the signal line of the second metal layer is located in the bus area and spans
  • GOA array
  • the non-full-transmissive area of the half-tone mask has a variety of mask penetration rates, including low penetration rate, medium penetration rate greater than low penetration rate, and greater than
  • the high transmittances with medium transmittances are arranged in sequence in the non-total transmittance areas, and the locations with low transmittances of the non-total transmittance areas are closest to the trunk of the signal line.
  • the lithography process includes an exposure operation, and when the exposure operation performs exposure with a minimum exposure line width through an exposure machine, the predetermined spacing between the plurality of narrow lines is less than Or equal to the difference between the minimum exposure line width and one micrometer, and the line distance is less than or equal to the difference between the minimum exposure line width of the exposure machine and the predetermined pitch.
  • the invention further provides a method for manufacturing an array substrate row drive (GOA) array substrate, comprising: defining a display area and a non-display area on a base substrate; forming a GOA drive circuit in the non-display area, which includes a plurality of Connected GOA units, each of the GOA units includes a first metal layer, and a second metal layer above the first metal layer; and a passivation layer is formed on the GOA driving circuit, and the Support pillars and color filter substrates are formed on the passivation layer; wherein the second metal layer is a half-tone mask, and through the photolithography process, the second metal layer is formed with patterned signal lines, and the The signal line includes a trunk portion and a side wall formed by gently sloping opposite sides of the trunk portion.
  • GOA array substrate row drive
  • the half-tone mask used for the signal line forming the second metal layer includes a non-total transmission region, and the non-total transmission region has at least one mask penetration rate , Used to form the side walls of the main portion of the signal line that are gently inclined on opposite sides.
  • the non-total transmission area of the half-tone mask has a variety of mask penetration rates, including low penetration rate, medium penetration rate greater than low penetration rate, and High transmittances greater than the medium transmittance, which are arranged in sequence in the non-total light transmission area, and the location of the low transmittance of the non-total light transmission area is closest to the trunk of the signal line .
  • the two sidewalls of the signal line form a plurality of narrow lines arranged at a predetermined pitch through a photolithography process, wherein each of the narrow lines has a line distance, which is smaller than the Predetermined spacing.
  • the lithography process includes an exposure operation, and when the exposure operation performs exposure with a minimum exposure line width through an exposure machine, the predetermined spacing between the plurality of narrow lines is less than Or equal to the difference between the minimum exposure line width and one micrometer, and the line distance is less than or equal to the difference between the minimum exposure line width of the exposure machine and the predetermined pitch.
  • the non-display area defines a bus area
  • the signal line of the second metal layer is located in the bus area and spans above the first metal layer .
  • each of the GOA units includes a thin film transistor structure, the first metal layer formed on the thin film transistor structure, and a gate electrode provided on the first metal layer An insulating layer, and the second metal layer formed on the gate insulating layer.
  • the present invention further includes a TFT array structure formed on the display area of the base substrate, the TFT array structure includes a plurality of parallel scan lines; the G0A driving circuit is used for Driving the plurality of scan lines.
  • the present invention further provides a liquid crystal display, including an array substrate row drive (GOA) array substrate, characterized in that the GOA array substrate includes: a substrate substrate, which defines a display area and a non-display area; a GOA drive circuit, provided On the non-display area, the GOA driving circuit includes a plurality of connected GOA units, each of the GOA units includes a first metal layer, and a second metal layer above the first metal layer; A passivation layer, which is provided on the GOA driving circuit, and a support post is provided on the passivation layer, and a color filter substrate provided on the support post; wherein the second metal layer includes a patterned signal
  • the signal line includes a trunk portion and a side wall formed by the two sides of the trunk portion being gently inclined.
  • the signal line is a half-tone mask and is formed by a photolithography process, wherein the half-tone mask includes a non-total light transmission area, and the non-total light transmission area has At least one reticle transmittance is used to form the side walls of the main portion of the signal line that are gently inclined relative to both sides.
  • the manufacturing method of the GOA array substrate of the present invention uses a half-tone mask and uses a photolithography process to form the signal lines of the second metal layer in the bus area to form gently sloping sidewalls, effectively improving the signal lines of the second metal layer Crossing the position of the first metal layer, it is easy to generate parasitic capacitance, easy to cause electrostatic discharge damage, and the risk of black screen, and can reduce the risk of short circuit with the upper board and increase the stability of the product.
  • FIG. 1 is a schematic partial cross-sectional view of a GOA array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic plan view of the GOA array substrate of the present invention.
  • FIG. 3 is a flowchart of a method for manufacturing a GOA array substrate according to a preferred embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a partial structure of the GOA array substrate of the present invention.
  • FIG. 5 is a schematic diagram of partial wiring of a GOA array substrate according to a preferred embodiment of the present invention.
  • FIG. 6 is a schematic diagram of partial wiring of a GOA array substrate according to another preferred embodiment of the present invention.
  • FIG. 7 is a schematic diagram of partial wiring of a GOA array substrate according to another preferred embodiment of the present invention.
  • the invention is a method for manufacturing an array substrate row driver (GOA) array substrate for a liquid crystal display (LCD).
  • FIG. 1 is a partial cross-sectional schematic diagram of a GOA array substrate according to a preferred embodiment of the present invention
  • FIG. 2 is a plan schematic diagram of the GOA array substrate of the present invention.
  • the present invention provides a method for manufacturing an array substrate row drive (GOA) array substrate, which includes the steps shown in FIG. 3.
  • GAA array substrate row drive
  • Step S10 Define a display area 11 and a non-display area 12 (as shown in FIG. 1) on a base substrate 1, wherein the non-display area 12 surrounds the display area 11 (as shown in FIG. 2), that is, It is the frame part of the display panel, and the non-display area 12 defines a bus line 121 (as shown in FIG. 1), and the display area 11 is an area for displaying a picture.
  • the present invention further includes a TFT array structure formed on the display area 11 of the base substrate 1, and the TFT array structure includes a plurality of parallel scan lines (not labeled).
  • the GOA driving circuit is used to drive the plurality of scanning lines.
  • Step S20 forming a GOA driving circuit in the non-display area 12, which includes a plurality of connected GOA units 2, each of the GOA units 2 includes a first metal layer 21, and is located above the first metal layer 21 ⁇ 22 ⁇ The second metal layer 22.
  • each of the GOA units 2 includes a thin film transistor structure 20, the first metal layer 21 formed on the thin film transistor structure 20, and a gate insulating layer provided on the first metal layer 21 211, and the second metal layer 22 formed on the gate insulating layer 211.
  • Step S30 forming a passivation layer 3 on the GOA driving circuit, and forming support pillars 4 and color filter substrates 5 on the passivation layer 3, respectively, wherein the passivation layer 3 and the second metal
  • An indium tin oxide (ITO) conductive film (not labeled) is formed between the layers 22, and another ITO conductive film is provided on the bottom side of the color film machine board 5.
  • ITO indium tin oxide
  • step S20 a photolithography process of exposing, developing, and etching the photoresist material using a half-tone mask 6 (as shown in FIG. 4) is performed.
  • the second metal 22 layer is formed with patterned signal lines, and the signal lines are located in the bus area 121 and span over the first metal layer 21, that is, the signal lines are clocks ( CK) signal line.
  • FIG. 5 is a schematic diagram of partial wiring of a GOA array substrate according to a preferred embodiment of the present invention.
  • the present invention uses the half-tone mask 6 to form the signal line through the photolithography process.
  • the half-tone mask 6 includes a non-total light transmission area 61, and the non-total light transmission area 61 has at least one mask penetration rate.
  • the non-total light transmission area 61 has a single mask transmittance.
  • the single mask transmittance is less than or equal to 100% transmittance, for example, 80% mask transmittance
  • the signal line 23 is formed by one patterning process, and the The signal line 23 includes a trunk portion 231 and a side wall 232 that is gently inclined from opposite sides of the trunk portion 231.
  • the manufacturing method of the GOA array substrate according to the present invention is used to gently incline the two sides of the signal lines, greatly reducing the generation of larger corners.
  • the non-fully transparent region 61 of the half-tone mask 6 has a variety of mask penetration rates, including low penetration rate, medium penetration rate greater than low penetration rate, and greater than
  • the high transmittance of medium transmittance is arranged in sequence in the non-total light transmission area, and the position of the low transmittance of the non-total light transmission area 61 is closest to the main of the signal line 23 Cadre 231.
  • the low transmittance is 30% reticle transmittance
  • the medium transmittance is 50%
  • the high transmittance is 70%.
  • the low transmittance of the half-tone mask 6 corresponds to the portion where the signal line 23 starts to incline gently from the trunk portion 231, followed by the medium transmittance and the high transmittance, thereby forming a gentle incline Second sidewall 232.
  • the manufacturing method of the GOA array substrate of the present invention uses a half-tone mask and uses a photolithography process to form the signal lines of the second metal layer in the bus area to form gently sloping sidewalls, effectively improving the signal lines of the second metal layer Crossing the position of the first metal layer, it is easy to generate parasitic capacitance, easy to cause electrostatic discharge damage, and the risk of black screen, and can reduce the risk of short circuit with the upper board and increase the stability of the product.
  • FIG. 7 is a schematic diagram of partial wiring of a GOA array substrate according to another preferred embodiment of the present invention.
  • the manufacturing method of the GOA array substrate of the present invention can not only form the gentle sidewalls 232 on both sides of the second metal layer 22, but also form a plurality of narrow line 233 configurations on the sidewall 232 with a predetermined interval .
  • the two sidewalls 232 of the signal line 23 form a plurality of narrow lines 233 arranged at a predetermined distance d through a photolithography process, wherein each of the narrow lines 233 has a line distance w, which is smaller than the predetermined Spacing d.
  • the photolithography process includes an exposure operation, wherein when the exposure operation performs exposure with a minimum exposure line width via an exposure machine (not shown), the predetermined distance d between the plurality of narrow lines 233 is less than or equal to The difference between the minimum exposure line width and one micrometer (um), and the line distance w is less than or equal to the difference between the minimum exposure line width of the exposure machine and the predetermined distance d.
  • the predetermined distance d is 2um (that is, the difference between 3um and 1um)
  • the line of the narrow line 233 The distance is 1um (that is, the difference of 3um-2um).
  • the side wall 232 formed by the narrow line 233 can also reduce parasitic capacitance, avoid damage from electrostatic discharge, and reduce black screen generation due to the reduction of a large area Risk and other effects.
  • the present invention further provides a liquid crystal display including an array substrate row drive (GOA) array substrate.
  • GOA array substrate row drive

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Abstract

一种制作阵列基板行驱动(GOA)阵列基板的方法，包含：在衬底基板（1）上定义显示区域（11）及非显示区域（12）。在非显示区域（12）形成GOA驱动电路，其包括多个相连接的GOA单元（2）。每一GOA单元（2）包括第一金属层（21），及位于第一金属层（21）上方的第二金属层（22）。在GOA驱动电路上形成钝化层（3），并在钝化层（3）上分别形成支撑柱（4）及彩膜基板（5）。第二金属层（22）是采用半色调光罩（6），并通过光刻工艺，使第二金属层（22）形成有图案化的信号线（23），且信号线（23）包括主干部（231）及由主干部（231）的相对二侧平缓倾斜形成的侧壁（232）。

Description

GOA阵列基板的制作方法及液晶显示器 技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板行驱动(gate driver on array, GOA)阵列基板的制作方法及液晶显示器。
 背景技术
现今显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，0LED)已广泛应用于日常生活中，如手机或电视等。以LCD的显示面板为例，其主要是由一薄膜晶体管(Thin Film Transistor，TFT)阵列基板、一彩色滤光片(Color Filter，CF)基板、以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成。随着TFT 性能的提升，直接将栅极电路形成于薄膜晶体管阵列技术(gate driver on array, GOA)目前已经普遍应用于显示面板中。
LCD TV产品目前大量使用GOA技术，实现无边框设计。随著影像品质的提升,GOA电路运用了多颗TFT管子，各管子的沟道长度，源/漏极蚀刻完最终完成值攸关整个电路的运作功能正常与稳定性。但每一级GOA源头信号是来自于GOA的总线(Busline)区，若面板GOA Busline区内传递信号的第二金属层(M2)与底层的第一金属层(M1)短路时，会导致GOA时钟信號错乱，会有较高的温度进而导致烧屏，无法显示等风险。有鉴于此，如何改善显示面板的GOA总线区M2与M1短路的几率，实为亟需解决的课题。
 技术问题
本发明的目的在于提供一种阵列基板行驱动(GOA)阵列基板的制作方法，使GOA驱动电路的上、下层跨线区域的走线与钝化层之间平缓接触，用以降低寄生电容，进而避免造成静电放电的炸伤，及减低黑屏的风险。
本发明的另一目的在于提供一种液晶显示器，其包括GOA阵列基板，用以降低显示面板内GOA总线区的走线短路的机率，并提高显示器件产品的稳定性与可靠度。
 技术解决方案
为实现上述目的，本发明提供一种制作阵列基板行驱动(GOA)阵列基板的方法，其特征在于，包含：在一衬底基板上定义显示区域及非显示区域，且所述非显示区域具有总线区；在所述非显示区域形成GOA驱动电路，其包括多个相连接的GOA单元、每一所述GOA单元包括第一金属层，及位于所述第一金属层上方的第二金属层；及在所述GOA驱动电路上形成钝化层，并在所述钝化层上分别形成支撑柱及彩膜基板；其中所述第二金属层是采用半色调光罩，其包括具有至少一种光罩穿透率的非全透光区，并通过光刻工艺，使所述第二金属层形成有图案化的信号线，且所述信号线包括主干部及由所述主干部的相对二侧平缓倾斜形成的侧壁，其中所述第二金属层的信号线位于所述总线区内，并横跨于所述第一金属层的上方。
依据本发明的一优选实施例中，所述半色调光罩的非全透光区具有多种光罩穿透率，包括低穿透率、大于低穿透率的中穿透率，及大于中穿透率的高穿透率，其分别依序排列设置于所述非全透光区，且所述非全透光区的低穿透率的位置最靠近所述信号线的主干部。
依据本发明的另一优选实施例中，所述光刻工艺包括曝光作业，所述曝光作业经由曝光机以最小曝光线宽进行曝光时，所述多个狭线之间的所述预定间距小于或等于所述最小曝光线宽和一微米的差值，而所述线距为小于或等于所述曝光机的最小曝光线宽和所述预定间距的差值。
本发明另外提供一种制作阵列基板行驱动(GOA)阵列基板的方法，包含：在一衬底基板上定义显示区域及非显示区域；在所述非显示区域形成GOA驱动电路，其包括多个相连接的GOA单元、每一所述GOA单元包括第一金属层，及位于所述第一金属层上方的第二金属层；及在所述GOA驱动电路上形成钝化层，并在所述钝化层上分别形成支撑柱及彩膜基板；其中所述第二金属层是采用半色调光罩，并通过光刻工艺，使所述第二金属层形成有图案化的信号线，且所述信号线包括主干部及由所述主干部的相对二侧平缓倾斜形成的侧壁。
依据本发明的一优选实施例中，形成所述第二金属层的信号线所采用的半色调光罩包括非全透光区，所述非全透光区具有至少一种光罩穿透率，用以形成所述信号线的主干部的相对二侧平缓倾斜的侧壁。
依据本发明的另一优选实施例中，所述半色调光罩的非全透光区具有多种光罩穿透率，包括低穿透率、大于低穿透率的中穿透率，及大于中穿透率的高穿透率，其分别依序排列设置于所述非全透光区，且所述非全透光区的低穿透率的位置最靠近所述信号线的主干部。
依据本发明的另一优选实施例中，所述信号线的二侧壁经由光刻工艺形成多个以一预定间距排列的狭线，其中每一所述狭线具有一线距，其小于所述预定间距。
依据本发明的另一优选实施例中，所述光刻工艺包括曝光作业，所述曝光作业经由曝光机以最小曝光线宽进行曝光时，所述多个狭线之间的所述预定间距小于或等于所述最小曝光线宽和一微米的差值，而所述线距为小于或等于所述曝光机的最小曝光线宽和所述预定间距的差值。
依据本发明的另一优选实施例中，所述非显示区域定义有总线区，且所述第二金属层的信号线位于所述总线区内，并横跨于所述第一金属层的上方。
依据本发明的另一优选实施例中，每一所述GOA单元包括薄膜晶体管结构、形成于所述薄膜晶体管结构上的所述第一金属层、设于所述第一金属层上的栅极绝缘层，及形成于所述栅极绝缘层上的所述第二金属层。
依据本发明的另一优选实施例中，还包括形成于所述衬底基板的显示区域上的TFT阵列结构，所述TFT阵列结构包括多条相平行的扫描线;所述G0A 驱动电路用于对所述多条扫描线进行驱动。
本发明另外提供一种液晶显示器，包括阵列基板行驱动(GOA)阵列基板，其特征在于，所述GOA阵列基板包括：衬底基板，其定义有显示区域及非显示区域；GOA驱动电路，设于所述非显示区域上，所述GOA驱动电路包括多个相连接的GOA单元、每一所述GOA单元包括第一金属层，及位于所述第一金属层上方的第二金属层；钝化层，设于所述GOA驱动电路上，且所述钝化层上设有支撑柱，及设于所述支撑柱上的彩膜基板；其中所述第二金属层包括具有图案化的信号线，所述信号线包括主干部及由所述主干部的相对二侧平缓倾斜形成的侧壁。
依据本发明的一优选实施例中，所述信号线是采用半色调光罩，并通过光刻工艺形成，其中所述半色调光罩包括非全透光区，所述非全透光区具有至少一种光罩穿透率，用以形成所述信号线的主干部的相对二侧平缓倾斜的侧壁。
 有益效果
本发明GOA阵列基板的制作方法，采用半色调光罩，并通过光刻工艺，使位于总线区内第二金属层的信号线，形成平缓倾斜的侧壁，有效改进第二金属层的信号线横跨第一金属层的位置，易于产生寄生电容，容易造成静电放电的炸伤，及产生黑屏的风险，并可降低与上板短路的风险，增加产品的稳定度。
 附图说明
图1为根据本发明的一较佳实施例的GOA阵列基板的局部剖面示意图。
图2为本发明的GOA阵列基板的平面示意图。
图3为根据本发明的一较佳实施例的GOA阵列基板的制作方法的流程图。
图4为本发明的GOA阵列基板的局部结构的剖面示意图。
图5为根据本发明的一较佳实施例的GOA阵列基板的局部走线的示意图。
图6为根据本发明的另一较佳实施例的GOA阵列基板的局部走线的示意图。
图7为根据本发明的另一较佳实施例的GOA阵列基板的局部走线的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本发明为一种用于液晶显示器(liquid crystal display， LCD)的阵列基板行驱动(gate driver on array, GOA)阵列基板的制作方法。图1为根据本发明的一较佳实施例的GOA阵列基板的局部剖面示意图，而图2为本发明的GOA阵列基板的平面示意图。
请参阅图3配合图1至图4观之。本发明提供一种制作阵列基板行驱动(GOA)阵列基板的方法，包括图3所示的步骤。
步骤S10：在一衬底基板1上定义显示区域11及非显示区域12(如图1所示)，其中所述非显示区域12围绕所述显示区域11(如图2所示)，亦即为显示面板的边框部份，且所述非显示区域12定义有总线区(busline)121(如图1所示)，而所述显示区域11即为显示画面的区域。
后述有关本发明GOA阵列基板的局部结构请配合参阅图4。图4的局部结构用于表示本案GOA驱动电路在所述总线区121的局部结构。如图2所示，本发明还包括形成于所述衬底基板1的显示区域11上的TFT阵列结构，所述TFT阵列结构包括多条相平行的扫描线(未标号)。所述G0A 驱动电路用于对所述多条扫描线进行驱动。
步骤S20：在所述非显示区域12形成GOA驱动电路，其包括多个相连接的GOA单元2、每一所述GOA单元2包括第一金属层21，及位于所述第一金属层21上方的第二金属层22。具体而言，每一所述GOA单元2包括薄膜晶体管结构20、形成于所述薄膜晶体管结构20上的所述第一金属层21、设于所述第一金属层21上的栅极绝缘层211，及形成于所述栅极绝缘层211上的所述第二金属层22。
步骤S30：在所述GOA驱动电路上形成钝化层3，并在所述钝化层3上分别形成支撑柱4及彩膜基板5，其中在所述钝化层3和所述第二金属层22之间形成有氧化铟锡(Indium tin oxide, ITO)导电膜(未标号)，而在所述彩膜机板5的底侧设有另一ITO导电膜。
特别说明的是，依据本发明GOA阵列基板的制作方法，在步骤S20中，采用半色调光罩6(如图4所示)对光阻材料进行曝光、显影及蚀刻的光刻工艺，使所述第二金属22层形成有图案化的信号线，且所述信号线位于所述总线区121内，并横跨于所述第一金属层21的上方，亦即所述信号线为时钟(CK)信号线。
图5为根据本发明的一较佳实施例的GOA阵列基板的局部走线的示意图。如前所述，本发明采用半色调光罩6通过光刻工艺形成信号线。具体而言，所述半色调光罩6包括非全透光区61，所述非全透光区61具有至少一种光罩穿透率。如图5所示，所述非全透光区61具有具有单一光罩穿透率。于此较佳实施例中，所述单一光罩穿透率为小于或等于百分之百穿透率，例如，百分之八十的光罩穿透率，通过一次构图工艺形成信号线23，且所述信号线23包括主干部231，及由所述主干部231的相对二侧平缓倾斜的侧壁232。相较于传统GOA驱动电路的走线(亦即信号线)，依据本发明GOA阵列基板的制作方法用以使信号线的二侧平缓倾斜，大幅减低较大边角的产生。
图6为根据本发明的另一较佳实施例的GOA阵列基板的局部走线的示意图。于此较佳实施例中，所述半色调光罩6的非全透光区61具有多种光罩穿透率，包括低穿透率、大于低穿透率的中穿透率，及大于中穿透率的高穿透率，其分别依序排列设置于所述非全透光区，且所述非全透光区61的低穿透率的位置最靠近所述信号线23的主干部231。具体而言，所述低穿透率为百分之三十光罩穿透率、所述中穿透率为百分之五十，及所述高穿透率为百分之七十。所述半色调光罩6的低穿透率，对应于所述信号线23由所述主干部231开始平缓倾斜的部位，紧接著是中穿透率及高穿透率，进而形成平缓倾斜的二侧壁232。
本发明GOA阵列基板的制作方法，采用半色调光罩，并通过光刻工艺，使位于总线区内第二金属层的信号线，形成平缓倾斜的侧壁，有效改进第二金属层的信号线横跨第一金属层的位置，易于产生寄生电容，容易造成静电放电的炸伤，及产生黑屏的风险，并可降低与上板短路的风险，增加产品的稳定度。
图7为根据本发明的另一较佳实施例的GOA阵列基板的局部走线的示意图。本发明GOA阵列基板的制作方法，除了可以形成所述第二金属层22二侧的平缓侧壁232，更可于所述侧壁232形成具有多个以预定间距间隔排列的狭线233构型。具体而言，所述信号线23的二侧壁232经由光刻工艺形成多个以一预定间距d排列的狭线233，其中每一所述狭线233具有一线距w，其小于所述预定间距d。所述光刻工艺包括曝光作业，其中所述曝光作业经由曝光机(未图示)以最小曝光线宽进行曝光时，所述多个狭线233之间的所述预定间距d为小于或等于所述最小曝光线宽和一微米(um)的差值，而所述线距w为小于或等于所述曝光机的最小曝光线宽和所述预定间距d的差值。于一具体实施中，如曝光机绕射极限最小可曝出的线宽为3um时，则所述预定间距d为2um(即为3um-1um的差值)，而所述狭线233的线距为1um(即为3um-2um的差值)。
如前所述，于图7所示的实施例中，所述狭线233构成的侧壁232，由于减少了大幅面积，同样可达到降低寄生电容，避免静电放电的炸伤，及减少黑屏产生的风险等功效。
本发明另外提供一种液晶显示器，包括阵列基板行驱动(GOA)阵列基板。所述GOA阵列基板的结构已详述于前述各个实施例中，于此不再复述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种制作阵列基板行驱动(GOA)阵列基板的方法，包括：
    在一衬底基板上定义显示区域及非显示区域，且所述非显示区域具有总线区；
    在所述非显示区域形成GOA驱动电路，其包括多个相连接的GOA单元、每一所述GOA单元包括第一金属层，及位于所述第一金属层上方的第二金属层；及
    在所述GOA驱动电路上形成钝化层，并在所述钝化层上分别形成支撑柱及彩膜基板；
    其中所述第二金属层是采用半色调光罩，其包括具有至少一种光罩穿透率的非全透光区，并通过光刻工艺，使所述第二金属层形成有图案化的信号线，且所述信号线包括主干部及由所述主干部的相对二侧平缓倾斜形成的侧壁，其中所述第二金属层的信号线位于所述总线区内，并横跨于所述第一金属层的上方。
  2. 如权利要求1制作GOA阵列基板的方法，其中所述半色调光罩的非全透光区具有多种光罩穿透率，包括低穿透率、大于低穿透率的中穿透率，及大于中穿透率的高穿透率，其分别依序排列设置于所述非全透光区，且所述非全透光区的低穿透率的位置最靠近所述信号线的主干部。
  3. 如权利要求1制作GOA阵列基板的方法，其中所述光刻工艺包括曝光作业，所述曝光作业经由曝光机以最小曝光线宽进行曝光时，所述多个狭线之间的所述预定间距小于或等于所述最小曝光线宽和一微米的差值，而所述线距为小于或等于所述曝光机的最小曝光线宽和所述预定间距的差值。
  4. 一种制作阵列基板行驱动(GOA)阵列基板的方法，包括：
    在一衬底基板上定义显示区域及非显示区域；
    在所述非显示区域形成GOA驱动电路，其包括多个相连接的GOA单元、每一所述GOA单元包括第一金属层，及位于所述第一金属层上方的第二金属层；及
    在所述GOA驱动电路上形成钝化层，并在所述钝化层上分别形成支撑柱及彩膜基板；
    其中所述第二金属层是采用半色调光罩，并通过光刻工艺，使所述第二金属层形成有图案化的信号线，且所述信号线包括主干部及由所述主干部的相对二侧平缓倾斜形成的侧壁。
  5. 如权利要求4制作GOA阵列基板的方法，其中形成所述第二金属层的信号线所采用的半色调光罩包括非全透光区，所述非全透光区具有至少一种光罩穿透率，用以形成所述信号线的主干部的相对二侧平缓倾斜的侧壁。
  6. 如权利要求5制作GOA阵列基板的方法，其中所述半色调光罩的非全透光区具有多种光罩穿透率，包括低穿透率、大于低穿透率的中穿透率，及大于中穿透率的高穿透率，其分别依序排列设置于所述非全透光区，且所述非全透光区的低穿透率的位置最靠近所述信号线的主干部。
  7. 如权利要求4制作GOA阵列基板的方法，其中所述信号线的二侧壁经由光刻工艺形成多个以一预定间距排列的狭线，其中每一所述狭线具有一线宽，其小于所述预定间距。
  8. 如权利要求7制作GOA阵列基板的方法，其中所述光刻工艺包括曝光作业，所述曝光作业经由曝光机以最小曝光线宽进行曝光时，所述多个狭线之间的所述预定间距小于或等于所述最小曝光线宽和一微米的差值，而所述线距为小于或等于所述曝光机的最小曝光线宽和所述预定间距的差值。
  9. 如权利要求4制作GOA阵列基板的方法，其中所述非显示区域定义有总线区，且所述第二金属层的信号线位于所述总线区内，并横跨于所述第一金属层的上方。
  10. 如权利要求4制作GOA阵列基板的方法，其中每一所述GOA单元包括薄膜晶体管结构、形成于所述薄膜晶体管结构上的所述第一金属层、设于所述第一金属层上的栅极绝缘层、及形成于所述栅极绝缘层上的所述第二金属层。
  11. 如权利要求4制作GOA阵列基板的方法，其中所述制作GOA阵列基板的方法还包括形成于所述衬底基板的显示区域上的TFT阵列结构，所述TFT阵列结构包括多条相平行的扫描线;所述G0A 驱动电路用于对所述多条扫描线进行驱动。
  12. 一种液晶显示器，包括阵列基板行驱动(GOA)阵列基板，所述GOA阵列基板包括：
    衬底基板，其定义有显示区域及非显示区域；
    GOA驱动电路，设于所述非显示区域上，所述GOA驱动电路包括多个相连接的GOA单元、每一所述GOA单元包括第一金属层，及位于所述第一金属层上方的第二金属层；
    钝化层，设于所述GOA驱动电路上，且所述钝化层上设有支撑柱，及设于所述支撑柱上的彩膜基板；
    其中所述第二金属层包括具有图案化的信号线，所述信号线包括主干部及由所述主干部的相对二侧平缓倾斜形成的侧壁。
  13. 如权利要求12的液晶显示器，其中所述信号线是采用半色调光罩，并通过光刻工艺形成，其中所述半色调光罩包括非全透光区，所述非全透光区具有至少一种光罩穿透率，用以形成所述信号线的主干部的相对二侧平缓倾斜的侧壁。
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