WO2020113729A1 - 阵列基板行驱动电路及显示装置 - Google Patents

阵列基板行驱动电路及显示装置 Download PDF

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Publication number
WO2020113729A1
WO2020113729A1 PCT/CN2018/124986 CN2018124986W WO2020113729A1 WO 2020113729 A1 WO2020113729 A1 WO 2020113729A1 CN 2018124986 W CN2018124986 W CN 2018124986W WO 2020113729 A1 WO2020113729 A1 WO 2020113729A1
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WIPO (PCT)
Prior art keywords
array substrate
active switch
unit
level
output
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PCT/CN2018/124986
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US17/043,713 priority Critical patent/US11462187B2/en
Publication of WO2020113729A1 publication Critical patent/WO2020113729A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present application relates to the technical field of electronic circuits, in particular to an array substrate row driving circuit and a display device.
  • the main purpose of the present application is to propose an array substrate row drive circuit and a display device, aiming to improve the picture quality of the display device.
  • the present application proposes an array substrate row drive circuit, the array substrate row drive circuit includes:
  • each of the array substrate row drive units includes a signal input terminal, a pull-up control signal terminal, and a gate drive signal output terminal;
  • Each auxiliary circuit unit includes a first timing signal input terminal, a second timing signal input terminal, a first controlled terminal and an output terminal;
  • the first timing signal input terminal of the N-level auxiliary circuit unit is connected to the N-1 level timing control signal, and the second timing signal input terminal of the N-level auxiliary circuit unit is connected to the N+1 level timing control signal ,
  • the controlled end of the auxiliary circuit unit of the Nth stage is connected to the pull-up control signal terminal of the row drive unit of the array substrate of the Nth stage, and the output end of the auxiliary circuit unit of the Nth stage is connected to the array of the Nth stage
  • the gate driving signal output terminal of the substrate row driving unit wherein,
  • the Nth-level array substrate row drive unit is configured to output the Nth-level gate drive signal when the signal input terminal receives the gate drive signal output from the N-2th-level array substrate row drive unit, to Perform the Nth level pre-charge and sub-pixel charge;
  • the auxiliary circuit unit of the Nth stage is configured to be connected with the N-1th stage timing control signal connected to the first timing signal input terminal and the N+1th stage timing control signal connected to the second timing signal input terminal At a high level, controlling the Nth-level array substrate row driving unit not to perform pre-charging;
  • N is a positive integer greater than or equal to 2.
  • the present application also proposes an array substrate row drive circuit.
  • the array substrate row drive circuit includes:
  • each of the array substrate row drive units includes a signal input terminal, a pull-up control signal terminal, and a gate drive signal output terminal;
  • Each auxiliary circuit unit includes a first timing signal input terminal, a second timing signal input terminal, a first controlled terminal and an output terminal;
  • the first timing signal input terminal of the N-level auxiliary circuit unit is connected to the N-1 level timing control signal, and the second timing signal input terminal of the N-level auxiliary circuit unit is connected to the N+1 level timing control signal ,
  • the controlled end of the auxiliary circuit unit of the Nth stage is connected to the pull-up control signal terminal of the row drive unit of the array substrate of the Nth stage, and the output end of the auxiliary circuit unit of the Nth stage is connected to the array of the Nth stage
  • the gate driving signal output terminal of the substrate row driving unit wherein,
  • the Nth-level array substrate row drive unit is configured to output the Nth-level gate drive signal when the signal input terminal receives the gate drive signal output from the N-2th-level array substrate row drive unit, to Perform the Nth level pre-charge and sub-pixel charge;
  • the auxiliary circuit unit of the Nth stage is configured to be connected with the N-1th stage timing control signal connected to the first timing signal input terminal and the N+1th stage timing control signal connected to the second timing signal input terminal At a high level, controlling the Nth-level array substrate row driving unit not to perform pre-charging;
  • N is a positive integer greater than or equal to 2;
  • Each of the auxiliary circuit units includes a first active switch, a second active switch, and a third active switch. At least one of the first active switch, the second active switch, and the third active switch is a thin film transistor.
  • This application also proposes a display device, the display device comprising:
  • a display panel the display panel having opposite sides, the display panel including a pixel array
  • the array substrate row drive circuit includes N array substrate row drive units arranged in cascade and an auxiliary circuit unit provided corresponding to each of the array substrate row drive units, N stages
  • the row drive unit and the auxiliary circuit unit of the array substrate are provided on both sides of the display panel correspondingly.
  • the array substrate row drive circuit of the present application comprises N array substrate row drive units arranged in cascade, and an auxiliary circuit unit corresponding to each of the array substrate row drive units, and the array substrate row drive unit at the Nth stage
  • its signal input terminal receives the gate drive signal output from the row drive unit of the array substrate in the N-2th stage, it outputs the gate drive signal in the Nth stage to perform the Nth stage precharge and the sub-pixel charging.
  • the N-level auxiliary circuit unit has the N-1 level timing control signal connected to the first timing signal input terminal and the N+1 level timing control signal connected to the second timing signal input terminal, both are high level, Controlling the Nth stage of the array substrate row driving unit not to perform pre-charging.
  • This application pre-charges the Nth-level sub-pixels by pre-charging to compensate for the voltage portion of the sub-pixels in the N-th row that is not saturated due to the need for ramping when performing pixel charging, and through the Nth-level auxiliary circuit Since the data voltage charged by the sub-pixel in the N-1th row jumps from the positive level to the positive level to the positive-level data voltage, the sub-pixel in the Nth row stops precharging to avoid charging data with opposite polarities Voltage, and increase the ramp-up time for the N-th row of sub-pixels to charge.
  • the waveform of the gate driving signal is designed through the row drive unit of the Nth-level array substrate and the Nth-level auxiliary circuit unit to ensure that the subpixels of the Nth line are fully charged and the voltage of the data signal is switched from the positive polarity to the negative polarity. Or when switching from negative polarity to positive polarity, ensure that each sub-pixel has the same charging effect and the same brightness.
  • This application solves the phenomenon that when the polarity of the data signal voltage is reversed, due to the relatively large cross-voltage, there is a difference in the degree of charge saturation between two adjacent sub-pixels sharing a data line, and a low gray-scale bright and dark line appears. The application improves the picture quality of the display device.
  • FIG. 1 is a schematic diagram of a circuit structure of an embodiment of an array substrate row drive unit in an array substrate row drive circuit of the present application;
  • FIG. 2 is a schematic diagram of a circuit structure of an embodiment of an auxiliary circuit unit in an array substrate row drive circuit of the present application
  • FIG. 3 is a schematic structural diagram of an embodiment of a pixel arrangement of a display panel in this application.
  • FIG. 4 is a schematic structural diagram of an embodiment of a display device in this application.
  • FIG. 5 is a schematic structural diagram of an embodiment of a display panel in this application.
  • FIG. 6 is a schematic diagram of a circuit structure of an embodiment of a display device in this application.
  • FIG. 7 is a timing diagram of an embodiment of a display device in this application.
  • This application proposes an array substrate row drive circuit, which should be installed in a display device with a display panel, such as a mobile phone, a computer, and a TV.
  • the row drive of the array substrate is to use the thin film transistor liquid crystal display array manufacturing process to fabricate the gate row scanning drive signal circuit on the array substrate of the display panel to realize the progressive scanning of the gate, which has a reduced production
  • the cost and the advantages of achieving the narrow bezel design of the panel are used by a variety of displays.
  • the pixel driving structure can be divided into a 1G1D structure that turns on only one row at a time, and turns on at a time.
  • the dual-gate pixel structure may be used for implementation.
  • the array substrate row drive circuit Since the row scanning line of the dual-gate pixel structure is doubled and the data line is doubled in the display panel, correspondingly, the array substrate row drive circuit The number will be doubled, and the number of source drive circuits can be reduced by half, because the cost of source drive circuits is much higher than the cost of integrated chips in gate drive chips, so the use of dual gate pixel drive structure can effectively reduce The production cost of the display device.
  • the line writing time will be reduced to half of the original, and in the design of the liquid crystal display panel, the important factor to consider the pixel drive structure is to ensure that the pixel has a sufficient pixel charge rate, The shortening of the line writing time will affect the reduction of the pixel charging rate.
  • the image quality of the panel is good, and the display panel is usually equipped with 1+2
  • the line or 2 line inversion method is used to drive the polarity inversion of the capacitor in the pixel array.
  • the line polarity inversion method is used to drive the polarity inversion of the capacitor in the pixel array.
  • the AC drive of the liquid crystal molecules is equivalent to the potential of the other electrode of the capacitor relative to the common electrode. Changes in potential from high to low. That is, the data signal increases or decreases relative to the common electrode voltage.
  • the data signal voltage rises relative to the common electrode voltage Vcom and switches from a negative voltage to a positive voltage, or decreases to switch from a positive voltage to a negative voltage
  • the data signal voltage crossover voltage is relatively large, and Because of the RC load, the voltage switching requires a ramp time.
  • the charging rate of the sub-pixels that need to undergo voltage switching is lower than the charging rate of the sub-pixels whose voltage tends to be stable, that is, the charging saturation of the former pixel is less than that of the latter
  • the degree of saturation, and the brightness of a pixel that is saturated with charge is greater than a pixel that is not fully saturated with charge.
  • adjacent odd-numbered thin-film transistors and even-numbered thin-film transistors are electrically connected to the same data line, and the gates of adjacent odd-numbered thin-film transistors and even-numbered thin-film transistors are respectively formed by phases. Two adjacent scan lines are controlled.
  • the gates of the sub-pixels in the first row and first column are connected to the scanning line G1, and the source is connected to the data line D1
  • the gates of the sub-pixels in the first row and second column are connected to the scanning line G2, and the source is connected to the data Line D1 is connected.
  • the two adjacent sub-pixels use the 2-line pixel line signal inversion method for polarity inversion, the polarities of the two sub-pixels are the same, or the 1+2 line pixel line signal inversion method is used for polarity inversion.
  • the first line of the scan line has a single polarity, and the polarities of two adjacent sub-pixels in the remaining scan lines are the same.
  • This embodiment will be described by taking an example of a 2-line pixel line signal inversion method.
  • the G1 row scanning line is turned on first, and the G2 row scanning line is turned on; in the l+2 row pixel row line signal inversion mode, the G2 row scanning line is turned on first.
  • G3 row scan line is turned on), the polarity of the color sub-pixel in the first row and first column is reversed from positive to negative.
  • the data voltage on the data line D2 will be Gradually decrease from high level to low level, that is, switch from positive to negative and maintain low level. At this time, the voltage across the data signal is relatively large.
  • the scanning line in the G1 row is turned off, and the scanning line in the G2 row is turned on, thereby charging the sub-pixels in the first row and the second column, and charging the sub-pixels in the first row and the second column.
  • the data voltage on the data line D1 is maintained at a low level, which is equivalent to switching from a negative electrode to a negative electrode.
  • the data signal voltage crossover voltage is small or no crossover voltage, so the sub-pixel When the pixel is fully charged, the saturation is high. In this way, the brightness of the color sub-pixels in the first row and second column will be higher than the brightness of the color sub-pixels in the first row and first column, and so on. The phenomenon of dark lines.
  • the array substrate row driving circuit 100 includes:
  • each of the array substrate row drive units 10 includes a signal input terminal, a pull-up control signal terminal, and a gate drive signal output terminal;
  • the auxiliary circuit unit 20 is provided corresponding to each of the array substrate row driving units 10, and each of the auxiliary circuit units 20 includes a first timing signal input terminal Ck(n-1) and a second timing signal input terminal Ck(n+ 1), the first controlled terminal Q(n) and the output terminal; wherein, the first timing signal input terminal Ck(n-1) of the auxiliary circuit unit 20 of the Nth stage is connected to the N-1th stage timing control signal , The second timing signal input terminal Ck(n+1) of the auxiliary circuit unit 20 of the Nth stage is connected to the N+1 stage timing control signal, the controlled terminal of the auxiliary circuit unit 20 of the Nth stage and the Nth The pull-up control signal terminal of the array substrate row drive unit 10 is connected, and the output terminal of the auxiliary circuit unit 20 of the Nth stage is connected to the gate drive signal output terminal of the array substrate row drive unit 10 of the Nth stage; wherein ,
  • the Nth stage array substrate row drive unit 10 is configured to output the Nth stage gate drive signal when the signal input terminal receives the gate drive signal output by the N-2th stage array substrate row drive unit 10 To perform the Nth-level pre-charging and sub-pixel charging;
  • the auxiliary circuit unit 20 of the Nth stage is provided with an N-1th stage timing control signal and a second timing signal input terminal Ck(n+1) connected to the first timing signal input terminal Ck(n-1)
  • the array substrate row drive unit 10 of the Nth level is controlled not to perform precharging;
  • N is a positive integer greater than or equal to 2.
  • the display panel 200 has a display area and a non-display area, and each cascaded array substrate row driving unit 10 is disposed in the non-display area, and the non-display area may be disposed on one side or according to the size of the display panel 200 On both sides, this embodiment can be optional on both sides.
  • each array substrate row drive unit 10 can enable the precharge function, so that the signal of the subsequent array substrate row drive unit 10 is turned on in advance, and the pixel voltage of the row is directed in advance The target polarity voltage of the current frame changes.
  • the array substrate row driving unit and the auxiliary circuit unit may be a circuit unit composed of a plurality of thin film transistors.
  • the polarity of the sub-pixel polarity of the current row is opposite to the polarity of the adjacent sub-pixels.
  • three adjacent sub-pixels The pixels are called a first subpixel, a second subpixel, and a third subpixel, respectively.
  • the first row of subpixels is switched from negative Sex jump to positive polarity is used as an example to illustrate, the first row of sub-pixels need to go through the climbing time, while the second row of sub-pixels' data voltage is a voltage that tends to be stable and positive, without going through the climbing time, and the third The power of the sub-pixel jumps from positive to negative, so it also needs to do its best to climb the hill.
  • the charging time of the first row of sub-pixels can be divided into the charging time t1 from the negative level voltage to the negative voltage of the reference voltage, and the charging time from the reference voltage to the positive level voltage Charging time t1', within the charging time t1, the polarities of the first row of sub-pixels and the third row of sub-pixels are the same, so the third row of sub-pixels can be turned on, so that the third row of sub-pixels start pre-charging, and The charged voltage polarity is the same as the voltage polarity of the current pixel of the third row of sub-pixels.
  • the charging time is t2.
  • the auxiliary circuit unit 20 pulls the gate drive signal low at this time, and the third row of sub-pixels stops precharging until the third row of sub-pixels starts to charge (corresponding to the charging time t3). At this time, the auxiliary circuit unit 20 does not work and the array substrate
  • the row driving unit 10 outputs a gate driving signal to the third row of sub-pixels, so that the third row of sub-pixels perform pixel charging.
  • this embodiment takes the fifth row of sub-pixels as an example, and combines the fifth-level array substrate row drive unit 10, fifth-stage auxiliary circuit unit 20, and fifth-row sub-pixel corresponding to the fifth-row sub-pixel
  • the change of the polarity of the data voltage and the timing signal and data signal output diagram are taken as an example for description.
  • the signal input terminal of the fifth-level array substrate row driving unit 10 The received gate drive signal is output from the third-level array substrate row drive unit 10, and the first timing signal input terminal Ck (n-1) of the fifth-level auxiliary circuit unit 20 receives the fourth-level timing signal Ck4 and the second timing
  • the signal input terminal Ck (n+1) receives the sixth-stage timing signal Ck6, and the first controlled terminal Q (n) receives the control signal Q5 output from the pull-up control signal terminal.
  • the output terminal outputs the pull-down driving signal of G5.
  • the fifth stage Both the auxiliary circuit and the fifth-level array substrate row drive unit 10 are triggered at a high level, that is, the high level works, and the low level stops working.
  • the gate drive signal G3 of the third-level array substrate row drive unit 10 is at a high level, thereby triggering the fifth-level array substrate row
  • the drive unit 10 works.
  • the fifth-level array substrate row drive unit 10 outputs a high-level gate drive signal G5 to the fifth-row sub-pixel when its timing control signal Ck5 is at a high level, thereby driving the fifth-row sub-pixel to start pre-charging.
  • the data voltage corresponding to the sub-pixels in the third row jumps from the negative level to the positive level, and the pre-charged sub-pixels in the fifth row are the data voltages of the negative level.
  • the array substrate row driving unit 10 drives the fifth row of sub-pixels for pre-charging.
  • the precharge time can be set according to the time when the data voltage corresponding to the third row of sub-pixels rises from the negative level to the common electrode voltage Vcom, that is, the third row of sub-pixels rises from the common electrode voltage Vcom to the positive electrode
  • the fifth-level sub-pixel stops pre-charging. With this setting, the fifth-level sub-pixels can be pre-charged through pre-charging to compensate for the voltage portion of the fifth sub-pixel that does not saturate the charge due to the need for ramping when performing pixel charging.
  • the gate drive signal G4 of the fourth-level array substrate row drive unit 10 When the fourth-level array substrate row drive unit 10 charges the fourth-row sub-pixels, the gate drive signal G4 of the fourth-level array substrate row drive unit 10 is at a high level, and the fourth-level timing signal Ck4 is High level. At this time, since the sixth-level sub-pixel needs to be precharged, the sixth-level timing signal Ck6 is at a high level, and the fourth-level timing signal Ck4 is at a high level, the fifth-level array substrate row driving unit 10 is on the third-level array substrate Under the action of the gate driving voltage G3 of the row driving unit 10, the pull-up control signal terminal of the row driving unit 10 of the fifth-level array substrate maintains a high level, thereby driving the fifth-stage auxiliary circuit unit 20 to work, and outputs a low level Gate drive signal G5 to the fifth row of sub-pixels.
  • the sub-pixels in the fifth row stop pre-charging because the data voltages charged by the sub-pixels in the fourth row jump from the positive level to the positive level to the positive voltage. Avoid charging data voltages with opposite polarities, and increase the ramp-up time for the fifth row of sub-pixel charging.
  • the fifth-level array substrate row drive unit 10 When the fifth-level array substrate row drive unit 10 charges the fifth-row sub-pixels, the G3 received by the fifth-level array substrate row drive unit 10 still maintains a high level, and the fifth-level timing signal Ck5 is a high level , Thereby outputting the gate drive signal G5 of the high level to the fifth row of sub-pixels, at this time, the fourth-level timing signal Ck4 is low level, the sixth-level timing signal Ck6 is high level, and the fifth-level auxiliary circuit unit 20 does not In operation, the fifth-level array substrate row driving unit 10 drives the fifth row of sub-pixels to charge.
  • this embodiment takes the operation of the fifth-level array substrate row drive unit 10 as an example for description, and the other-level array substrate row drive unit 10 can be obtained by analogy to obtain this level array substrate row drive unit
  • the working status of 10 will not be listed here one by one.
  • the sum of pre-charging and charging is equal to the total of its capacity, so when charging to the maximum value of its capacitance The value, that is, the voltage across the energy storage capacitor of the sub-pixel will remain stable and remain unchanged when fully charged.
  • pre-charging can compensate the charging voltage of the sub-pixels whose polarity is reversed, and increase the charging rate of the sub-pixels, while in the sub-pixels whose polarity does not need to be reversed, pre-charging can improve the Charge rate.
  • the array substrate row drive circuit 100 of the present application is provided by arranging N array substrate row drive units 10 arranged in cascade, and an auxiliary circuit unit 20 provided corresponding to each of the array substrate row drive units 10, and at the Nth level of the array
  • the signal input terminal of the substrate row driving unit 10 receives the gate driving signal output by the array substrate row driving unit 10 of the N-2th stage, it outputs the gate driving signal of the Nth stage to perform the Nth stage precharge and
  • the array substrate row drive unit 10 of the Nth stage is controlled not to perform precharge.
  • This application pre-charges the Nth-level sub-pixels by pre-charging to compensate for the voltage portion of the sub-pixels in the N-th row that is not saturated due to the need for ramping when performing pixel charging, and through the Nth-level auxiliary circuit
  • the unit 20 shifts the data voltage charged by the sub-pixels in the N-1th row from the positive level to the positive level to the positive-level data voltage, and the sub-pixels in the Nth row stop pre-charging, thereby avoiding charging the opposite polarities
  • the data voltage increases the ramp-up time for the N-th row of sub-pixels to charge.
  • This application uses the Nth-level array substrate row drive unit 10 and the Nth-level auxiliary circuit unit 20 to design the waveform of the gate drive signal to ensure that the sub-pixels in the Nth line are charged and saturated, which is conducive to the switching of the voltage of the data signal from positive polarity to negative polarity When switching from negative polarity to positive polarity, ensure that each sub-pixel has the same charging effect and the same brightness.
  • This application solves the phenomenon that when the polarity of the data signal voltage is reversed, due to the relatively large cross-voltage, there is a difference in the degree of charge saturation between two adjacent sub-pixels sharing a data line, and a low gray-scale bright and dark line appears. The application improves the picture quality of the display device.
  • each of the auxiliary circuit units 20 includes a first active switch T1, a second active switch T2, and a third active switch T3.
  • the controlled end of the first active switch T1 is the auxiliary circuit unit 20.
  • the first timing signal input terminal Ck (n-1), the input terminal of the first active switch T1 is the second timing signal input terminal Ck (n+1) of the auxiliary circuit unit 20, the first The output terminal of the active switch T1 is connected to the input terminal of the second active switch T2.
  • the controlled terminal of the second active switch T2 is the first controlled terminal Q(n) of the auxiliary circuit unit 20.
  • the output end of the second active switch T2 is connected to the controlled end of the third active switch T3, the input end of the third active switch T3 is connected to the gate close signal, and the output end of the third active switch T3 is The output of the auxiliary circuit unit 20 is described.
  • At least one of the first active switch T1, the second active switch T2, and the third active switch T3 is a thin film transistor.
  • the first active switch T1, the second active switch T2, and the third active switch may be selected.
  • T3 is set to N-type thin film transistors, that is, all are high-level conduction.
  • the first active switch T1 is controlled based on the N-1th stage timing signal Ck(n+1), and the second active switch T2 is controlled based on the pull-up signal Q(n) of the pull-up point control terminal, and all three are
  • the third active switch T3 is controlled based on the N+1th stage timing signal Ck (N+1), when the first active switch T1 is in the N+1th stage timing signal Ck (n+1) is high level Turn on, and output the timing signal Ck(n-1) of the N-1th stage, the second active switch T2 is turned on when the pull-up signal Q(n) is high, and the third active switch T3 is on the first active switch
  • T1 and the second active switch T2 are turned on, and when the timing signal Ck(n-1) of the N-1th stage input at the input end of the first active switch T1 is at a high level, the Nth-level array substrate is driven row by row The voltage of the gate drive signal output terminal of the unit 10 is pulled down, so that the
  • each of the array substrate row driving units 10 includes a charging unit 11, a reset unit 12, and an output unit 13.
  • the charging unit 11, the output unit 13, and the reset unit 12 are specifically circuit structures implemented by thin film transistors.
  • the input terminal of the charging unit 11 is a signal input terminal of the array substrate row driving unit 10, and the output terminal of the charging unit 11 is a pull-up control signal terminal of the array substrate row driving unit 10, and is connected to the It is connected to the controlled end of the output unit 13, the input end of the output unit 13 is connected to the current stage timing signal, and the output end of the output unit 13 is the gate drive signal output of the array substrate row drive unit 10 end.
  • each first array substrate row drive unit 10 includes a charging unit 11, an output unit 13, and a reset unit 12, and the charging unit 11 is mainly configured to output a pull-up control signal.
  • the input terminal of the output unit 13 is connected to the pull-up control signal output terminal Q(n) output by the charging unit 11, and is mainly configured to output the gate drive signal G(n) according to the pull-up control signal Q(n).
  • the reset unit 12 is respectively connected to the controlled terminal of the output unit 13 of the charging unit 11 and the gate drive signal output terminal of the output unit 13, and after completing the scanning of the pixel unit of the current row, pulls up the control signal Q(n) And the line scan signal G(n) is pulled down to low level.
  • a bootstrap capacitor may also be provided.
  • the first pole of the bootstrap capacitor is connected to the pull-up control signal output terminal Q(n), and the second pole thereof is connected to the gate drive signal output terminal G(n) of the current-stage array substrate row drive unit 10 ).
  • the bootstrap capacitor C is set to maintain the voltage between the output units 13 and stabilize the output of the output unit 13.
  • the gate drive signal output terminal G(n) outputs a high-level gate drive signal to turn on the thin film transistor corresponding to the N-th row of sub-pixels, thereby driving the N-th row of sub-pixels to be charged or pre-charged.
  • the N-2th stage array substrate row drive unit 10 drives the Nth stage array substrate row drive unit 10
  • the N+2th-level array substrate row drive unit 10 is also driving the N+2th sub-pixels for pre-charging, and when the N+2th-row sub-pixels are charged, the N+2th level
  • the gate drive signal output by the array substrate row drive unit 10 is output to the controlled end of the reset unit 12 of the N-2th-level array substrate row drive unit 10, thereby controlling the operation of the reset unit 12, and outputs a gate-off signal to the output unit 13 In order to control the output unit 13 to stop working, and then turn off the thin-film transistor corresponding to the sub-pixel in the Nth row.
  • the charging unit 11 includes a fourth active switch T4.
  • the input terminal and the controlled terminal of the fourth active switch T4 are the input terminals of the charging unit 11, so The output terminal of the fourth active switch T4 is the output terminal of the charging unit 11.
  • the reset unit 12 includes a fifth active switch T5 and a sixth active switch T6, the controlled ends of the fifth active switch T5 and the sixth active switch T6 are connected to the N+4th level array substrate
  • the gate driving signal output by the row driving unit 10 the input terminals of the fifth active switch T5 and the sixth active switch T6 are respectively connected to the gate closing signal; the output terminal of the fifth active switch T5 and the pull-up control The signal terminal is connected, and the output terminal of the sixth active switch T6 is connected to the gate drive signal output terminal.
  • the output unit 13 includes a seventh active switch T7 and an eighth active switch T8, the controlled end of the seventh active switch T7 is the controlled end of the output unit 13, and is connected to the eighth The controlled end of the active switch T8, the input end of the seventh active switch T7 is the input end of the output unit 13, and is connected to the input end of the eighth active switch T8, the seventh active switch T7
  • the output terminal is the output terminal of the output unit 13, the output terminal of the eighth active switch T8 and the signal input terminal of the N+2 stage array substrate row drive unit 10.
  • each active switch may be implemented using a thin film transistor, and specifically may be implemented using an N-type thin film transistor with high-level conduction.
  • Each array substrate row driving unit 10 further includes a pull-down unit and a pull-down driving unit. The pull-down unit is configured to output a reset signal to the output terminal and the controlled terminal of the output unit 13 to control the output unit 13 to stop working.
  • the present application also provides an array substrate row drive circuit.
  • the array substrate row drive circuit 100 includes:
  • each of the array substrate row drive units 10 includes a signal input terminal, a pull-up control signal terminal, and a gate drive signal output terminal;
  • the auxiliary circuit unit 20 is provided corresponding to each of the array substrate row driving units 10, and each of the auxiliary circuit units 20 includes a first timing signal input terminal Ck(n-1) and a second timing signal input terminal Ck(n+ 1), the first controlled terminal Q(n) and the output terminal G(n); wherein, the first timing signal input terminal Ck(n-1) of the auxiliary circuit unit 20 of the Nth stage is connected to the N-1th Level timing control signal, the second timing signal input terminal Ck(n+1) of the auxiliary circuit unit 20 of the Nth level is connected to the N+1 level timing control signal, the control of the auxiliary circuit unit 20 of the Nth level Is connected to the pull-up control signal terminal of the array substrate row drive unit 10 of the Nth stage, and the output terminal of the auxiliary circuit unit 20 of the Nth stage is connected to the gate drive signal of the array substrate row drive unit 10 of the Nth stage Output; where,
  • the Nth stage array substrate row drive unit 10 is configured to output the Nth stage gate drive signal when the signal input terminal receives the gate drive signal output by the N-2th stage array substrate row drive unit 10 To perform the Nth-level pre-charging and sub-pixel charging;
  • the auxiliary circuit unit 20 of the Nth stage is provided with an N-1th stage timing control signal and a second timing signal input terminal Ck(n+1) connected to the first timing signal input terminal Ck(n-1)
  • the array substrate row driving unit 10 of the Nth level is controlled not to perform precharging;
  • N is a positive integer greater than or equal to 2;
  • Each of the auxiliary circuit units 20 includes a first active switch T1, a second active switch T2 and a third active switch T3, the first active switch T1, the second active switch T2 and the third active switch T3 At least one is a thin film transistor.
  • the array substrate row drive circuit 100 of the present application is provided by arranging N array substrate row drive units 10 arranged in cascade, and an auxiliary circuit unit 20 provided corresponding to each of the array substrate row drive units 10, and at the Nth level of the array
  • the signal input terminal of the substrate row driving unit 10 receives the gate driving signal output by the array substrate row driving unit 10 of the N-2th stage, it outputs the gate driving signal of the Nth stage to perform the Nth stage precharge and
  • the array substrate row drive unit 10 of the Nth stage is controlled not to perform precharge.
  • This application pre-charges the Nth-level sub-pixels by pre-charging to compensate for the voltage portion of the sub-pixels in the N-th row that is not saturated due to the need for ramping when performing pixel charging, and through the Nth-level auxiliary circuit
  • the unit 20 shifts the data voltage charged by the sub-pixels in the N-1th row from the positive level to the positive level to the positive-level data voltage, and the sub-pixels in the Nth row stop pre-charging, thereby avoiding charging the opposite polarities
  • the data voltage increases the ramp-up time for the N-th row of sub-pixels to charge.
  • This application uses the Nth-level array substrate row drive unit 10 and the Nth-level auxiliary circuit unit 20 to design the waveform of the gate drive signal to ensure that the sub-pixels in the Nth line are charged and saturated, which is conducive to the switching of the voltage of the data signal from positive polarity to negative polarity When switching from negative polarity to positive polarity, ensure that each sub-pixel has the same charging effect and the same brightness.
  • This application solves the phenomenon that when the polarity of the data signal voltage is reversed, due to the relatively large cross-voltage, there is a difference in the degree of charge saturation between two adjacent sub-pixels sharing a data line, and a low gray-scale bright and dark line appears. The application improves the picture quality of the display device.
  • the application also proposes a display device.
  • the display device includes: a display panel 200 having opposite sides, and the display panel 200 includes a pixel array 240;
  • the array substrate row drive circuit 100 includes N array substrate row drive units 10 arranged in cascade and auxiliary circuit units provided corresponding to each of the array substrate row drive units 10 20.
  • N array cascaded row drive units 10 and auxiliary circuit units 20 are correspondingly provided on both sides of the display panel 200.
  • the display panel 200 may be an organic light emitting diode display panel 200 or a TFT-LCD display panel 200.
  • the display panel 200 is divided into gate driver designs and can be divided into two types: SOC type and array substrate row drive type.
  • the array substrate row driving circuit 100 is a process technology in which the gate driving circuit is directly fabricated on the array substrate of the display device, instead of a driving chip made of an external silicon wafer. The application of this technology can reduce production process procedures, reduce product process costs, and can improve the integration of the display panel 200.
  • the array substrate row drive type display panel 200 has a narrower bezel. With the advancement of technology and higher requirements for visual effects, the narrow border of the display panel 200 is the mainstream trend in the future.
  • the array substrate row drive type display panel 200 is a more important application than the SOC type display panel 200.
  • liquid crystal molecules are filled between the upper and lower glass substrates and sealed with a sealing material around; among them, the liquid crystal is a polymer material because of its special physical, chemical, Optical characteristics are widely used in thin and light display technology.
  • the pixel array 240 of the display panel 200 is composed of multiple sub-pixels, and three sub-pixels (red, green, and blue) constitute one pixel.
  • three sub-pixels red, green, and blue
  • each The on-time of one sub-pixel is consistent.
  • the sub-pixels in the same row are turned on at the same time, and the data signal is output to The time of each sub-pixel is the same, which will inevitably lead to uneven charging of the principle gate drive and the close gate drive, resulting in uneven brightness of the display panel 200.
  • the gate drive is often provided on the left and right sides of the display panel 200, and the timing controller outputs the frame start signal, the scan clock pulse signal, the clock signals Ck1 ⁇ Ckx, and the low frequency signals LC1&LC2 and other array substrate row drive drivers The signal is transmitted to the array substrate row drive circuit 100 on the left and right sides of the panel. After the array substrate row drive unit 10 operates normally, the scan lines in the display panel 200 are turned on row by row to achieve bilateral driving.
  • the display device is further provided with a source driver 500, a timing controller 300, and a driving power supply 400.
  • the source driver 500 is configured as a source driver 500 for inputting data signals, and the source driver 500 is installed on a driving board.
  • the source driver 500 is connected to a timing controller, and a plurality of output terminals of the source driver 500 are respectively connected to corresponding data lines of the pixel array 240, and the timing controller receives external control circuits, such as data signals and controls output by the control system SOC of the television
  • the signals and clock signals are converted into data signals, control signals and clock signals suitable for each array substrate row drive circuit 100 and source driver 500.
  • the source driver 500 outputs the data signals to the corresponding pixels through the data lines to achieve The image of the display panel 200 is displayed.
  • the number of source drivers 500 is multiple, which can be specifically set according to the size of the display panel 200. In this embodiment, two examples are used for description.
  • the driving power supply 400, the output end of the driving power supply 400 is connected to the array substrate row driving circuit 100 and the source driver 500; the driving power supply 400 integrates a plurality of DC-DC conversion circuits with different circuit functions, and each conversion circuit outputs a different Voltage value.
  • the input voltage of the input terminal of the driving power supply 40 is generally 5V or 12V, and the output voltage includes the operating voltage DVDD provided to the timing controller 11, and the gate on voltage VGH and the off voltage VGL provided to the gate driver.
  • the display panel 200 includes:
  • Pixel array 240
  • the first substrate 210 has a display area and a peripheral area; the pixel array 240 is disposed on the first substrate 210 and is located in the display area; the N cascaded array substrate row driving units 10 and The auxiliary circuit unit 20 is disposed on the first substrate 210 and located in the peripheral area;
  • the second substrate 220 is disposed opposite to the first substrate 210;
  • a liquid crystal layer is disposed between the first substrate 210 and the second substrate 220.
  • the liquid crystal layer includes a plurality of liquid crystal molecules, and the pixel array 240 is configured to control the actions of the plurality of liquid crystal molecules.
  • the first substrate 210 and the second substrate 220 are generally both transparent substrates such as glass substrates or plastic substrates.
  • the second substrate 220 is disposed opposite to the first substrate 210, and a corresponding circuit may be disposed between the first substrate 210 and the second substrate 220.
  • the pixel array 240 is disposed on the first substrate 210 and located in the display area AA. Under the driving control of the array substrate row driving circuit 100, the pixel array 240 can generate control signals to control the display of the display panel 200.
  • the array substrate row drive circuit 100 is disposed on the first substrate 210 and is located in the non-display area BB. Accordingly, the array substrate row drive circuit 100 can isolate the array substrate row drive circuit 100 from the liquid crystal layer 23 through an isolation structure, thereby arraying A liquid crystal-free region is formed between the substrate row driving circuit 100 and the second substrate 220 respectively.
  • the display panel 200 further includes a sealant 250 disposed in the non-display area BB between the first substrate 210 and the second substrate 220 and surrounding the liquid crystal layer 23, and the array substrate row driving circuit 100 is located between the sealant 250 and the display area AA.
  • the sealant 250 may be coated on the first substrate 210 or the second substrate 220 with a sealant to connect the first substrate 210 and the second substrate 220, thereby realizing the assembly process of the display panel 200.
  • the pixel array 240 is a pixel array 240 of a half-source driving architecture.
  • the pixel array 240 includes a plurality of sub-pixels, each of the sub-pixels includes an active switch (thin film transistor) and a pixel electrode, the active switch T Is electrically connected to the scan line corresponding to the sub-pixel, the source of the active switch is electrically connected to the data line corresponding to the pixel unit, and the drain of the active switch is electrically connected to the pixel electrode of the sub-pixel connection.
  • the pixel array 240 further includes a pixel electrode array connected to the active switching element array.
  • the display panel 200 is composed of a plurality of pixels, and each pixel is composed of three sub-pixels of red, green, and blue.
  • Each sub-pixel circuit structure is generally provided with a thin film transistor and a capacitor, the gate of the thin film transistor is connected to the gate driver through the scan line, the source of the thin film transistor is connected to the source driver 500 through the data line, and the drain of the thin film transistor Connect to one end of the capacitor.
  • a plurality of thin film transistors constitute the thin film transistor array of this embodiment (not shown in the figure).
  • the thin-film transistors 31 located in the same column are connected to the source driver 500 through a data line, and the thin-film transistors located in the same row are connected to the gate driver through a scan line, thus forming a thin-film transistor array.
  • the array substrate row driving circuit 100 supplies voltage to the gates of several thin film transistors. These thin film transistors can be a-S thin film transistors or polysilicon thin film transistors, of which Poly-Si thin film transistors can use LTPS Other technologies.
  • the thin film transistors in odd columns in each row are respectively connected to the scan lines in even rows, and the thin film transistors in even columns in each row are electrically connected to the scan lines in odd rows, respectively.
  • the adjacent odd-numbered thin film transistors and even-numbered thin film transistors are electrically connected to the same data line.
  • the thin film transistors of odd columns in each row are respectively connected to the scan lines of odd rows, the thin film transistors of even columns in each row are electrically connected to the scan lines of even rows, and adjacent thin film of odd columns
  • the transistor and the thin film transistors in even columns are electrically connected to the same data line.
  • the polarity inversion mode of the switch array is 1+2 pixel line signal inversion.
  • the polarity reversal mode of the switch array is a 2-line pixel line signal inversion.

Abstract

一种阵列基板行驱动电路（100）及显示装置，该阵列基板行驱动电路（100）包括：N个级联设置的阵列基板行驱动单元（10），第N级阵列基板行驱动单元（10），设置为在其信号输入端接收到第N-2级阵列基板行驱动单元（10）输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电；第N级辅助电路单元（20），设置为在其第一时序信号输入端接入的第N-1级时序控制信号及第二时序信号输入端接入的第N+1级时序控制信号均为高电平时，控制第N级阵列基板行驱动单元（10）不进行预充电；N为大于等于2的正整数。该阵列基板行驱动电路（100）解决了数据信号电压在极性反转时，由于跨压比较大，出现低灰阶亮暗线的现象，提高了显示装置的画面品质。

Description

阵列基板行驱动电路及显示装置
相关专利
本申请要求2018年12月05日，申请号为201811484038.5，申请名称为“阵列基板行驱动电路及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及电子电路技术领域，特别涉及一种阵列基板行驱动电路及显示装置。
背景技术
目前，在液晶显示面板采用双栅像素驱动结构的设计中，通常是送2dot（点）讯号来改善闪烁现象，然而在数据信号在转换时波型会有一个爬升阶段这爬升阶段会影响像素充电，可能由于数据电压的跨压过大，而导致相邻的两个像素的充电效率不一致而出现亮暗线现象，使得显示面板的画面品质降低。
申请内容
本申请的主要目的是提出一种阵列基板行驱动电路及显示装置，旨在提高显示装置的画面品质。
为实现上述目的，本申请提出一种阵列基板行驱动电路，所述阵列基板行驱动电路包括：
N个级联设置的阵列基板行驱动单元，每一所述阵列基板行驱动单元包括信号输入端，上拉控制信号端及栅极驱动信号输出端；
辅助电路单元，对应每一所述阵列基板行驱动单元设置，每一所述辅助电路单元包括第一时序信号输入端、第二时序信号输入端、第一受控端及输出端；其中，第N级所述辅助电路单元的第一时序信号输入端接入第N-1级时序控制信号，第N级所述辅助电路单元的第二时序信号输入端接入第N+1级时序控制信号，第N级所述辅助电路单元的受控端与第N级所述阵列基板行驱动单元的上拉控制信号端连接，第N级所述辅助电路单元的输出端与第N级所述阵列基板行驱动单元的栅极驱动信号输出端；其中，
第N级所述阵列基板行驱动单元，设置为在其信号输入端接收到第N-2级所述阵列基板行驱动单元输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电；
第N级所述辅助电路单元，设置为在其第一时序信号输入端接入的第N-1级时序控制信号及第二时序信号输入端接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元不进行预充电；
N 为大于等于2的正整数。
本申请还提出一种阵列基板行驱动电路，所述阵列基板行驱动电路包括：
N个级联设置的阵列基板行驱动单元，每一所述阵列基板行驱动单元包括信号输入端，上拉控制信号端及栅极驱动信号输出端；
辅助电路单元，对应每一所述阵列基板行驱动单元设置，每一所述辅助电路单元包括第一时序信号输入端、第二时序信号输入端、第一受控端及输出端；其中，第N级所述辅助电路单元的第一时序信号输入端接入第N-1级时序控制信号，第N级所述辅助电路单元的第二时序信号输入端接入第N+1级时序控制信号，第N级所述辅助电路单元的受控端与第N级所述阵列基板行驱动单元的上拉控制信号端连接，第N级所述辅助电路单元的输出端与第N级所述阵列基板行驱动单元的栅极驱动信号输出端；其中，
第N级所述阵列基板行驱动单元，设置为在其信号输入端接收到第N-2级所述阵列基板行驱动单元输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电；
第N级所述辅助电路单元，设置为在其第一时序信号输入端接入的第N-1级时序控制信号及第二时序信号输入端接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元不进行预充电；
N 为大于等于2的正整数；
每一所述辅助电路单元包括第一主动开关、第二主动开关及第三主动开关，所述第一主动开关、所述第二主动开关及所述第三主动开关至少一个为薄膜晶体管。
本申请还提出一种显示装置，所述显示装置包括：
显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；
以及如上所述的阵列基板行驱动电路，所述阵列基板行驱动电路包括N个级联设置的阵列基板行驱动单元和对应每一所述阵列基板行驱动单元设置的辅助电路单元，N个级联设置的所述阵列基板行驱动单元和辅助电路单元对应设置于所述显示面板的两侧。
本申请阵列基板行驱动电路通过设置N个级联设置的阵列基板行驱动单元，以及对应每一所述阵列基板行驱动单元设置的辅助电路单元，并在第N级所述阵列基板行驱动单元的其信号输入端接收到第N-2级所述阵列基板行驱动单元输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电时，通过第N级所述辅助电路单元在其第一时序信号输入端接入的第N-1级时序控制信号及第二时序信号输入端接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元不进行预充电。本申请通过预充电而对第N级子像素进行预充电，以补偿第N行子像素在进行像素充电时，由于需要进行爬坡而导致充电不饱和的电压部分，并通过第N级辅助电路单元对由于第N-1行子像素充的数据电压由正准位向正准位跳转为正准位的数据电压，第N行子像素停止预充电，从而避免充入极性相反的数据电压，而增加第N行子像素充电的爬坡时间。本申请通过第N级阵列基板行驱动单元和第N级辅助电路单元设计栅极驱动信号的波形，以保证第N行子像素充电饱和，有利于数据信号的电压从正极性切换至负极性，或者从负极性切换至正极性时，保证每一子像素的充电效果相同，且亮度一致。本申请解决了数据信号电压在极性反转时，由于跨压比较大，导致共用一数据线的两相邻子像素之间的充电饱和程度存在差异而出现低灰阶亮暗线的现象，本申请提高了显示装置的画面品质。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请阵列基板行驱动电路中阵列基板行驱动单元一实施例的电路结构示意图；
图2为本申请阵列基板行驱动电路中辅助电路单元一实施例的电路结构示意图；
图3为本申请中显示面板像素排列一实施例的结构示意图；
图4为本申请中显示装置一实施例的结构示意图；
图5为本申请中显示面板一实施例的结构示意图；
图6为本申请中显示装置一实施例的电路结构示意图；
图7为本申请中显示装置一实施例的时序图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做可选地说明。
具体实施方式
本申请提出一种阵列基板行驱动电路，应设置为手机、电脑、电视等具有显示面板的显示装置中。
可以理解的是，阵列基板行驱动，是利用薄膜晶体管液晶显示器阵列制程将栅极行扫描驱动信号电路制作在显示面板的阵列基板上，以实现对栅极逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。
在显示面板中，像素的排列方式有多种，根据某一时刻，行开启的数量以及对应的像素信号的输入，像素驱动结构可以分为某一时刻只开启一行的1G1D结构、某时刻同时开两行的2G2D结构、或者双栅像素驱动结构以及三栅像素驱动结构。本实施例可选为采用双栅像素结构来实现，由于在显示面板中，双栅像素结构的行扫描线增加了一倍，同时数据线减少了一倍，相应的，阵列基板行驱动电路的数量会增加一倍，而源极驱动电路的数量可以减少一半，由于源极驱动电路的造价成本远高于栅极驱动芯片中集成芯片的造价成本，因此采用双栅像素驱动结构可以有效的降低显示装置的生产成本。
相较于1G1D结构，双栅像素驱动结构中，行写入时间会下降为原来的一半，而在液晶显示面板的设计中，考量像素驱动结构的重要因素即确保像素具备充足的像素充电率，而行写入时间的缩短会影响到像素充电率降低，为了保证像素充电率高，面板的画质良好，显示面板通常会搭配1+2 line或2 line反转方式来驱动像素阵列中电容的极性反转。
由于显示面板在采用2 line或者1+2 line极性反转方式来驱动像素阵列中的电容极性反转时，在公共电极电位保持不变的情况下，实现液晶分子的交流驱动就相当于电容的另外一个电极的电位相对于公共电极电位时高时低的变化。也即数据信号相对公共电极电压升高或者降低。而在数据信号电压相对公共电极电压Vcom升高由负极性的电压切换为正极性的电压，或者降低来实现由正极性电压切换为负极性的过程中，数据信号电压的跨压比较大，且因为RC负载的原因，电压切换需要爬坡时间。因此在充电时间一定的情况下，需要经历电压切换即爬坡时间的子像素的充电率要低于电压趋于平稳的子像素的充电率，也即前者的像素充电饱和程度要小于后者的饱和程度，而充电饱和的像素的亮度要大于充电不完全饱和的像素。例如在本实施例显示面板中，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接，且相邻的奇数列薄膜晶体管和偶数列薄膜晶体管的栅极分别由相邻的两条扫描线控制。位于第一行第一列的子像素的栅极与扫描线G1连接，源极与数据线D1连接，位于第一行第二列的子像素的栅极与扫描线G2连接，源极与数据线D1连接。该相邻的两个子像素在采用2行画素行线信号反转方式进行极性反转时，两者的极性是一致的，或者采用1+2行画素行线信号反转方式进行极性反转时，扫描线的第一行为单独极性，其余扫描行中相邻的两个子像素的极性相同。本实施例以2行画素行线信号反转方式为例进行说明。阵列基板行驱动电路在进行逐行扫描时，G1行扫描线先打开，G2行扫描线后打开；在l+2行画素行线信号反转)方式中，则是G2行扫描线先打开，G3行扫描线后打开），第一行第一列的色子像素的极性从正极反转为负极，在第一行第一列的子像素充电过程中，数据线D2上的数据电压会由高电平逐渐降低为低电平，也即由正极切换为负极并保持低电平，此时数据信号的电压跨压较大，在第一行第一列的子像素充电完成时，并未充电饱和。在第一行第一列的色子像素完成充电后，G1行扫描线关断，G2行扫描线打开，从而给第一行第二列的子像素充电，而给第一行第二列的子像素充电的过程中，数据线D1上的数据电压是保持为低电平的，相当于有负极切换为负极，此时，数据信号的电压跨压较小或者没有跨压，因此在该子像素充电完成时，饱和程度较高。这样，将导致第一行第二列的色子像素的亮度要高于第一行第一列的色子像素的亮度，以此类推，由于视觉停留，将在整个液晶面板上呈现出亮/暗线的现象。
为了解决上述现象，参照图1至图7，在本申请一实施例中，该阵列基板行驱动电路100包括：
N个级联设置的阵列基板行驱动单元10，每一所述阵列基板行驱动单元10包括信号输入端，上拉控制信号端及栅极驱动信号输出端；
辅助电路单元20，对应每一所述阵列基板行驱动单元10设置，每一所述辅助电路单元20包括第一时序信号输入端Ck（n-1)、第二时序信号输入端Ck（n+1)、第一受控端Q（n)及输出端；其中，第N级所述辅助电路单元20的第一时序信号输入端Ck（n-1)接入第N-1级时序控制信号，第N级所述辅助电路单元20的第二时序信号输入端Ck（n+1)接入第N+1级时序控制信号，第N级所述辅助电路单元20的受控端与第N级所述阵列基板行驱动单元10的上拉控制信号端连接，第N级所述辅助电路单元20的输出端与第N级所述阵列基板行驱动单元10的栅极驱动信号输出端；其中，
第N级所述阵列基板行驱动单元10，设置为在其信号输入端接收到第N-2级所述阵列基板行驱动单元10输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电；
第N级所述辅助电路单元20，设置为在其第一时序信号输入端Ck（n-1)接入的第N-1级时序控制信号及第二时序信号输入端Ck（n+1)接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元10不进行预充电；
N 为大于等于2的正整数。
本实施例中，显示面板200具有显示区及非显示区，各个级联的阵列基板行驱动单元10设置于非显示区，并且，非显示区可以根据显示面板200的尺寸，设置于一侧或者两侧，本实施例可选为两侧。为了消除亮暗线现象，以及为了使像素快速完成充电，各阵列基板行驱动单元10可以启用预充电功能，使后级的阵列基板行驱动单元10信号提前开启，提前使该行的像素电压朝着当前帧的目标极性电压转变。其中，阵列基板行驱动单元和辅助电路单元可以为由多个薄膜晶体管组成的电路单元。
根据双栅驱动架构可知，在开启当前行的行扫描线时，当前行的子像素极性的极性与其相邻的子像素的极性是相反的，本实施例将三个相邻的子像素分别称为第一子像素、第二子像素及第三子像素。在开启第一行子像素时，第一行子像素的数据电压的极性由正极性跳转为负极性，或者由负极性跳转为正极性，本实施例以第一行子像素由负极性跳转为正极性为例进行说明，第一行子像素需要经历爬坡时间，而在第二行子像素的数据电压是趋于平稳正极性的电压，无需经历爬坡时间，而第三子像素的电则是由正跳转为负，因此同样需要尽力爬坡时间。由于数据电压需要经历爬坡时间，因此第一行子像素的充电时间可以分为由负准位电压增加到基准电压的负极性电压的充电时间t1，以及由基准电压增加至正准位电压的充电时间t1’，在充电时间t1内，第一行子像素和第三行子像素的极性是相同的，因此可以开启第三行子像素，从而让第三行子像素开始预充电，并且所充的电压极性与第三行子像素当前帧的电压极性相同。而在第二行子像素开始充电时，其充电时间为t2，由于第二行子像素的数据电压不需要经历爬坡，因此第二子像素的极性从负跳转为正的时间较短，第二行子像素的正极性与第三行子像素的负极性相反。辅助电路单元20将此时的栅极驱动信号拉低，第三行子像素停止预充电，直至第三行子像素开始充电（对应充电时间t3)，此时辅助电路单元20不工作，阵列基板行驱动单元10输出栅极驱动信号至第三行子像素，从而使第三行子像素进行像素充电。
具体地，参照图1及图2，本实施例以第五行子像素为例，结合第五行子像素对应的第五级阵列基板行驱动单元10、第五级辅助电路单元20、第五行子像素的数据电压极性的变化，以及各个时序信号及数据信号输出图为例进行说明，在第五行子像素对应的阵列基板行驱动单元10中，第五级阵列基板行驱动单元10的信号输入端接收的为第三级阵列基板行驱动单元10输出的栅极驱动信号，第五级辅助电路单元20的第一时序信号输入端Ck（n-1)接收第四级时序信号Ck4、第二时序信号输入端Ck（n+1)接收第六级时序信号Ck6、第一受控端Q（n)接收上拉控制信号端输出的控制信号Q5的输出端输出G5的下拉驱动信号，第五级辅助电路及第五级阵列基板行驱动单元10均为高电平触发，也即高电平工作，低电平停止工作。
在第三级阵列基板行驱动单元10在对第三行子像素充电时，此时第三级阵列基板行驱动单元10的栅极驱动信号G3为高电平，从而触发第五级阵列基板行驱动单元10工作。第五级阵列基板行驱动单元10在其时序控制信号Ck5为高电平时，输出高电平的栅极驱动信号G5至第五行子像素，从而驱动第五行子像素开始预充电。此时第三行子像素对应的数据电压由负准位向正准位跳转，第五行子像素的预充的为负准位的数据电压。此时由于第四级子像素需要预充，因此第四级时序信号Ck4为高电平，而第六级时序信号Ck6为低电平，第五级辅助电路单元20不工作，由第五级阵列基板行驱动单元10驱动第五行子像素进行预充电。其中，预充电的时间可以根据第三行子像素对应的数据电压从负准位升高至公共电极电压Vcom的时间进行设置，也即在第三行子像素从公共电极电压Vcom升高至正极性电压以后，第五级子像素停止预充电。如此设置，可以通过预充电而对第五级子像素进行预充电，以补偿第五子像素在进行像素充电时，由于需要进行爬坡而导致充电不饱和的电压部分。
在第四级阵列基板行驱动单元10在对第四行子像素充电时，此时第四级阵列基板行驱动单元10的栅极驱动信号G4为高电平，并且第四级时序信号Ck4为高电平。此时由于第六级子像素需要预充，第六级时序信号Ck6为高电平，而第四级时序信号Ck4为高电平，第五级阵列基板行驱动单元10在第三级阵列基板行驱动单元10的栅极驱动电压G3的作用下，第五级阵列基板行驱动单元10的上拉控制信号端保持高电平，从而驱动第五级辅助电路单元20工作，并输出低电平的栅极驱动信号G5至第五行子像素。第五行子像素在第四行子像素充电时，由于第四行子像素充的数据电压由正准位向正准位跳转为正准位的数据电压，第五行子像素停止预充电，从而避免充入极性相反的数据电压，而增加第五行子像素充电的爬坡时间。
在第五级阵列基板行驱动单元10在对第五行子像素充电时，此时第五级阵列基板行驱动单元10接收的G3仍保持高电平，并且第五级时序信号Ck5为高电平，从而输出高电平的栅极驱动信号G5至第五行子像素，此时第四级时序信号Ck4为低电平，第六级时序信号Ck6为高电平，第五级辅助电路单元20不工作，由第五级阵列基板行驱动单元10驱动第五行子像素进行充电。在这个过程中，由于在对第三级子像素进行充电时，已经对第五行子像素进行预充电，因此第五行子像素无需经历由正电压向负电压跳转的爬坡时间，从而使得第五行子像素可以充电保护。
可以理解的是，本实施例以第五级阵列基板行驱动单元10的工作为例进行说明，在其他级阵列基板行驱动单元10中，均可以以此类推，获得该级阵列基板行驱动单元10的工作状态，此处不再一一列举。此外，在由正极性转正极性的子像素中，由于子像素的储能电容容量是一定的，在进行预充电和充电的总和即等于其容量总和，因此当充至其电容容量值的最大值，即充满时子像素的储能电容两端的电压将维持稳定，保持不变。也即，预充电可以对于极性反转的子像素，可以补偿其爬坡的充电电压，并提高子像素的充电速率，而在极性无需反转的子像素，预充电可以提高子像素的充电速率。
本申请阵列基板行驱动电路100通过设置N个级联设置的阵列基板行驱动单元10，以及对应每一所述阵列基板行驱动单元10设置的辅助电路单元20，并在第N级所述阵列基板行驱动单元10的其信号输入端接收到第N-2级所述阵列基板行驱动单元10输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电时，通过第N级所述辅助电路单元20在其第一时序信号输入端Ck（n-1)接入的第N-1级时序控制信号及第二时序信号输入端Ck（n+1)接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元10不进行预充电。本申请通过预充电而对第N级子像素进行预充电，以补偿第N行子像素在进行像素充电时，由于需要进行爬坡而导致充电不饱和的电压部分，并通过第N级辅助电路单元20对由于第N-1行子像素充的数据电压由正准位向正准位跳转为正准位的数据电压，第N行子像素停止预充电，从而避免充入极性相反的数据电压，而增加第N行子像素充电的爬坡时间。本申请通过第N级阵列基板行驱动单元10和第N级辅助电路单元20设计栅极驱动信号的波形，以保证第N行子像素充电饱和，有利于数据信号的电压从正极性切换至负极性，或者从负极性切换至正极性时，保证每一子像素的充电效果相同，且亮度一致。本申请解决了数据信号电压在极性反转时，由于跨压比较大，导致共用一数据线的两相邻子像素之间的充电饱和程度存在差异而出现低灰阶亮暗线的现象，本申请提高了显示装置的画面品质。
参照图1至图7每一所述辅助电路单元20包括第一主动开关T1、第二主动开关T2及第三主动开关T3，所述第一主动开关T1的受控端为所述辅助电路单元20的第一时序信号输入端Ck（n-1)，所述第一主动开关T1的输入端为所述辅助电路单元20的第二时序信号输入端Ck（n+1)，所述第一主动开关T1的输出端与所述第二主动开关T2的输入端连接，所述第二主动开关T2的受控端为所述辅助电路单元20的第一受控端Q（n)，所述第二主动开关T2的输出端与所述第三主动开关T3的受控端连接，所述第三主动开关T3的输入端接入栅关闭信号，所述第三主动开关T3的输出端为所述辅助电路单元20的输出端。
本实施例中，第一主动开关T1、第二主动开关T2及第三主动开关T3至少一个为薄膜晶体管，本实施例可选为第一主动开关T1、第二主动开关T2及第三主动开关T3均设置为N型薄膜晶体管，也即均为高电平导通。本实施例中，第一主动开关T1基于第N-1级时序信号Ck（n+1）控制，第二主动开关T2基于上拉点控制端的上拉信号Q（n）控制，并且三者均为高电平时，第三主动开关T3基于第N+1级时序信号Ck（N+1）控制，当第一主动开关T1在第N+1级时序信号Ck（n+1）为高电平时导通，并输出第N-1级时序信号Ck（n-1），第二主动开关T2在上拉信号Q（n）为高电平使导通，第三主动开关T3在第一主动开关T1和第二主动开关T2导通时，并在第一主动开关T1输入端输入的第N-1级时序信号Ck（n-1）为高电平时工作，以将第N级阵列基板行驱动单元10的栅极驱动信号输出端的电压拉低，从而第N-1级阵列基板行驱动单元10输出栅极驱动信号，并驱动第N-1行子像素充电时。控制第N级阵列基板行驱动单元10停止预充电，如此可以避免充入极性相反的数据电压，而增加第五行子像素充电的爬坡时间。
参照图1至图7，每一所述阵列基板行驱动单元10包括充电单元11、复位单元12及输出单元13，充电单元11、输出单元13以及复位单元12具体为薄膜晶体管实现的电路结构。所述充电单元11的输入端为所述阵列基板行驱动单元10的信号输入端，所述充电单元11的输出端为所述阵列基板行驱动单元10的上拉控制信号端，并与所述与所述输出单元13的受控端连接，所述输出单元13的输入端接入当前级时序信号，所述输出单元13的输出端为所述阵列基板行驱动单元10的栅极驱动信号输出端。
本实施例中，每个第一阵列基板行驱动单元10均包括充电单元11、输出单元13以及复位单元12，充电单元11主要设置为输出上拉控制信号。输出单元13的输入端与充电单元11所输出的上拉控制信号输出端Q（n）相连接，主要设置为根据该上拉控制信号Q（n）输出栅极驱动信号G（n）。复位单元12分别与充电单元11的输出单元13的受控端以及输出单元13的栅极驱动信号输出端相连接，在完成对当前行像素单元的扫描后，将上拉控制信号Q（n）以及行扫描信号G（n）下拉至低电平。还可以设置有自举电容，自举电容的第一极连接上拉控制信号输出端Q（n），其第二极连接当前级阵列基板行驱动单元10的栅极驱动信号输出端G（n）。自举电容C设置为维持输出单元13之间的电压，稳定输出单元13的输出。
当第N-2级的栅极驱动信号的输出信号来临之前，Ck（n）为低电平，此时上拉控制信号输出端Q（n）的电平为低电平，此时输出单元13无信号输出。当第N-2级的栅极驱动信号的输出信号来临时，Ck（n）为低电平，此时上拉控制信号输出端Q（n）的电平为高电平，输出单元13的栅极驱动信号输出端G（n）输出的信号为低电平信号。
当第N-2级的栅极驱动信号的输出信号来临时，Ck（n）为高电平，此时上拉控制信号输出端Q（n）的电平为高电平，输出单元13的栅极驱动信号输出端G（n）输出高电平的栅极驱动信号，以打开第N行子像素对应的薄膜晶体管，从而驱动第N行子像素充电或者预充电。
由于第N级的栅极驱动信号是第N-2级阵列基板行驱动单元10的输出信号，因此，第N-2级阵列基板行驱动单元10在第N级阵列基板行驱动单元10驱动第N行子像素进行充电时，第N+2级阵列基板行驱动单元10也在驱动第N+2子像素进行预充电，而在第N+2行子像素进行充电时，第Ｎ+2级阵列基板行驱动单元10输出的栅极驱动信号输出至第N-2级阵列基板行驱动单元10的复位单元12的受控端，从而控制复位单元12工作，并输出栅关闭信号至输出单元13，以控制输出单元13输停止工作，进而关断第N行子像素对应的薄膜晶体管。
参照图1至图7，在一实施例中，所述充电单元11包括第四主动开关T4，所述第四主动开关T4的输入端和受控端为所述充电单元11的输入端，所述第四主动开关T4的输出端为所述充电单元11的输出端。
可选地，所述复位单元12包括第五主动开关T5和第六主动开关T6，所述第五主动开关T5和所述第六主动开关T6的受控端接入第N+4级阵列基板行驱动单元10输出的栅极驱动信号，所述第五主动开关T5和第六主动开关T6的输入端分别接入栅关闭信号；所述第五主动开关T5的输出端与所述上拉控制信号端连接，所述第六主动开关T6的输出端与所述栅极驱动信号输出端连接。
可选地，所述输出单元13包括第七主动开关T7和第八主动开关T8，所述第七主动开关T7的受控端为所述输出单元13的受控端，并与所述第八主动开关T8的受控端，所述第七主动开关T7的输入端为所述输出单元13的输入端，并与所述第八主动开关T8的输入端连接，所述第七主动开关T7的输出端为所述输出单元13的输出端，所述第八主动开关T8的输出端与第N+2级阵列基板行驱动单元10的信号输入端。上述实施例中，各主动开关可以采用薄膜晶体管来实现，具体可以采用高电平导通的N型薄膜晶体管来实现。各阵列基板行驱动单元10还包括下拉单元及下拉驱动单元，下拉单元被设置为输出复位信号至输出单元13的输出端及受控端，以控制输出单元13停止工作。
本申请还提出一种阵列基板行驱动电路，所述阵列基板行驱动电路100包括：
N个级联设置的阵列基板行驱动单元10，每一所述阵列基板行驱动单元10包括信号输入端，上拉控制信号端及栅极驱动信号输出端；
辅助电路单元20，对应每一所述阵列基板行驱动单元10设置，每一所述辅助电路单元20包括第一时序信号输入端Ck（n-1)、第二时序信号输入端Ck（n+1)、第一受控端Q（n)及输出端G(n)；其中，第N级所述辅助电路单元20的第一时序信号输入端Ck（n-1)接入第N-1级时序控制信号，第N级所述辅助电路单元20的第二时序信号输入端Ck（n+1)接入第N+1级时序控制信号，第N级所述辅助电路单元20的受控端与第N级所述阵列基板行驱动单元10的上拉控制信号端连接，第N级所述辅助电路单元20的输出端与第N级所述阵列基板行驱动单元10的栅极驱动信号输出端；其中，
第N级所述阵列基板行驱动单元10，设置为在其信号输入端接收到第N-2级所述阵列基板行驱动单元10输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电；
第N级所述辅助电路单元20，设置为在其第一时序信号输入端Ck（n-1)接入的第N-1级时序控制信号及第二时序信号输入端Ck（n+1)接入的第N+1级时序控制信号Ck（n+1)均为高电平时，控制所述第N级所述阵列基板行驱动单元10不进行预充电；
N 为大于等于2的正整数；
每一所述辅助电路单元20包括第一主动开关T1、第二主动开关T2及第三主动开关T3，所述第一主动开关T1、所述第二主动开关T2及所述第三主动开关T3至少一个为薄膜晶体管。
本申请阵列基板行驱动电路100通过设置N个级联设置的阵列基板行驱动单元10，以及对应每一所述阵列基板行驱动单元10设置的辅助电路单元20，并在第N级所述阵列基板行驱动单元10的其信号输入端接收到第N-2级所述阵列基板行驱动单元10输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电时，通过第N级所述辅助电路单元20在其第一时序信号输入端Ck（n-1)接入的第N-1级时序控制信号及第二时序信号输入端Ck（n+1)接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元10不进行预充电。本申请通过预充电而对第N级子像素进行预充电，以补偿第N行子像素在进行像素充电时，由于需要进行爬坡而导致充电不饱和的电压部分，并通过第N级辅助电路单元20对由于第N-1行子像素充的数据电压由正准位向正准位跳转为正准位的数据电压，第N行子像素停止预充电，从而避免充入极性相反的数据电压，而增加第N行子像素充电的爬坡时间。本申请通过第N级阵列基板行驱动单元10和第N级辅助电路单元20设计栅极驱动信号的波形，以保证第N行子像素充电饱和，有利于数据信号的电压从正极性切换至负极性，或者从负极性切换至正极性时，保证每一子像素的充电效果相同，且亮度一致。本申请解决了数据信号电压在极性反转时，由于跨压比较大，导致共用一数据线的两相邻子像素之间的充电饱和程度存在差异而出现低灰阶亮暗线的现象，本申请提高了显示装置的画面品质。
本申请还提出一种显示装置。参照图1至图7，所述显示装置包括：显示面板200，所述显示面板200具有相对设置的两侧，所述显示面板200包括像素阵列240；
以及如上所述的阵列基板行驱动电路100，所述阵列基板行驱动电路100包括N个级联设置的阵列基板行驱动单元10和对应每一所述阵列基板行驱动单元10设置的辅助电路单元20，N个级联设置的所述阵列基板行驱动单元10和辅助电路单元20对应设置于所述显示面板200的两侧。
本实施例中，显示面板200可以是有机发光二极管显示面板200，也可以是TFT-LCD显示面板200。显示面板200以栅极驱动器设计来分，可以分为SOC型和阵列基板行驱动型两种。阵列基板行驱动电路100由于其直接将栅极驱动电路制作在显示装置的阵列基板上，来代替由外接硅片制作的驱动芯片的一种工艺技术。该技术的应用可减少生产工艺程序，降低产品工艺成本，并且可以提高显示面板200的集成度。相对于SOC型显示面板200，阵列基板行驱动型显示面板200具有更窄的边框。随着科技进步以及人们对视觉效果的更高要求，显示面板200窄边框化是未来的主流趋势。因此，阵列基板行驱动型显示面板200相对于SOC型显示面板200是一种更为重要的应用。在阵列基板行驱动型显示面板200的范例性的架构中，其上下玻璃基板之间填充液晶分子且四周用密封材料密封；其中，液晶是一种高分子材料，因为其特殊的物理、化学、光学特性，被广泛应用在轻薄型的显示技术上。
本实施例中，显示面板200的像素阵列240由多个子像素构成，三个子像素（红、绿、蓝）构成一个像素，例如在同一横行上的子像素在分布于显示面板200上时，每一子像素的导通时间是一致的。在一些大尺寸的显示面板200中，由于面板远离栅极驱动的区域与靠近栅极驱动的区域的扫描线走线电阻是不均匀的，在同一行的子像素同时打通，而数据信号输出至各子像素的时间是相同的，这势必会出现原理栅极驱动和靠近栅极驱动充电不均匀的现象而导致显示面板200的亮度不均。因此，往往在显示面板200的左右两侧都设置有栅极驱动，并通过时序控制器输出帧起始信号、扫描时钟脉冲信号，时钟信号Ck1~Ckx、以及低频信号LC1&LC2等阵列基板行驱动驱动信号，传输到面板左右两侧的阵列基板行驱动电路100中，阵列基板行驱动单元10正常动作后再逐行开启显示面板200内的扫描线，以实现双边驱动。
在一些实施例中，显示装置还设置有源极驱动器500、时序控制器300及驱动电源400，源极驱动器500设置为输入数据信号的源极驱动器500，源极驱动器500安装与驱动板上，源极驱动器500与时序控制器连接，源极驱动器500的多个输出端分别与像素阵列240对应数据线连接，时序控制器接收外部控制电路，例如电视机的控制系统SOC输出的数据信号、控制信号以及时钟信号，并转换成适合于各阵列基板行驱动电路100、源极驱动器500的数据信号、控制信号以及时钟信号，源极驱动器500的将数据信号通过数据线输出至对应的像素，实现显示面板200的图像显示。源极驱动器500的数量为多个，具体可以根据显示面板200的尺寸进行设置，本实施例以两个为例进行说明。驱动电源400，所述驱动电源400的输出端与阵列基板行驱动电路100、源极驱动器500连接；驱动电源400集成了多个不同电路功能的直流-直流转换电路，每个转换电路输出不同的电压值。驱动电源40的输入端输入的电压一般为5V或12V，输出的电压包括给时序控制器11提供的工作电压DVDD，以及给栅极驱动器提供的栅极开启电压VGH和关断电压VGL。
参照图1至图7，在一实施例中，所述显示面板200包括：
像素阵列240；
第一基板210，具有显示区域与周边区域；所述像素阵列240设置于所述第一基板210上且位于所述显示区域；所述N个级联设置的所述阵列基板行驱动单元10和辅助电路单元20设置于所述第一基板210上且位于所述周边区域；
第二基板220，与所述第一基板210相对设置；
液晶层，设置于所述第一基板210与所述第二基板220之间，所述液晶层包括若干液晶分子，所述像素阵列240设置为控制所述若干液晶分子的动作。本实施例中，第一基板210与第二基板220通常均为玻璃基板或塑料基板等透光材料基板。第二基板220与第一基板210相对设置，在第一基板210与第二基板220之间可以设置对应的电路。像素阵列240设置于第一基板210上且位于显示区域AA，像素阵列240在阵列基板行驱动电路100的驱动控制下，可以产生控制信号控制显示面板200的显示。阵列基板行驱动电路100设置于第一基板210上且位于非显示区域BB，相应地，阵列基板行驱动电路100可以通过隔离结构来实现阵列基板行驱动电路100与液晶层23的隔离，从而阵列基板行驱动电路100分别与第二基板220之间形成无液晶区。
可以理解的是，上述实施例中，显示面板200还包括框胶250，设置于第一基板210与第二基板220之间的非显示区域BB内并环绕液晶层23设置，阵列基板行驱动电路100位于框胶250与显示区域AA之间。框胶250可以采用密封胶涂布在第一基板210上，或者第二基板220上，以连接第一基板210和第二基板220，从而实现对显示面板200的组装处理。具体地，所述像素阵列240为半源极驱动架构的像素阵列240。
参照图1至图7，在一可选实施例中，所述像素阵列240包括多个子像素，每一所述子像素均包括一主动开关（薄膜晶体管）及一像素电极，所述主动开关T的栅极与该子像素对应的扫描线电性连接，所述主动开关的源极与该像素单元对应的数据线电性连接，所述主动开关的漏极与该子像素的像素电极电性连接。像素阵列240还包括连接主动开关元件阵列的像素电极阵列。
显示面板200由多个像素组成，每个像素又由红绿蓝三个亚像素组成。每个亚像素电路结构一般设置有一个薄膜晶体管和一个电容，薄膜晶体管的栅极通过扫描线与栅极驱动器连接，薄膜晶体管的源极通过数据线与源极驱动器500连接，薄膜晶体管的漏极与电容的一端连接。其中，多个薄膜晶体管构成了本实施例的薄膜晶体管阵列（图未标示）。位于同一列的薄膜晶体管31通过一数据线与源极驱动器500连接，位于同一行的薄膜晶体管通过一扫描线与栅极驱动器连接，如此以构成薄膜晶体管阵列。阵列基板行驱动电路100对若干薄膜晶体管的栅极提供电压。这些薄膜晶体管可以是a-S薄膜晶体管或者多晶硅薄膜晶体管，其中Poly-Si薄膜晶体管可以采用LTPS 等技术加以形成。
在像素阵列240中，各行中奇数列的所述薄膜晶体管分别与偶数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与奇数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。各行中奇数列的所述薄膜晶体管分别与奇数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与偶数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。可选地，所述开关阵列的极性反转方式为1+2行画素行线信号反转。可选地，所述开关阵列的极性反转方式为2行画素行线信号反转。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (18)

  1. 一种阵列基板行驱动电路，其中，所述阵列基板行驱动电路包括：
    N个级联设置的阵列基板行驱动单元，每一所述阵列基板行驱动单元包括信号输入端，上拉控制信号端及栅极驱动信号输出端；
    辅助电路单元，对应每一所述阵列基板行驱动单元设置，每一所述辅助电路单元包括第一时序信号输入端、第二时序信号输入端、第一受控端及输出端；其中，第N级所述辅助电路单元的第一时序信号输入端接入第N-1级时序控制信号，第N级所述辅助电路单元的第二时序信号输入端接入第N+1级时序控制信号，第N级所述辅助电路单元的受控端与第N级所述阵列基板行驱动单元的上拉控制信号端连接，第N级所述辅助电路单元的输出端与第N级所述阵列基板行驱动单元的栅极驱动信号输出端；其中，
    第N级所述阵列基板行驱动单元，设置为在其信号输入端接收到第N-2级所述阵列基板行驱动单元输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电；
    第N级所述辅助电路单元，设置为在其第一时序信号输入端接入的第N-1级时序控制信号及第二时序信号输入端接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元不进行预充电；
    N 为大于等于2的正整数。
  2. 如权利要求1所述的阵列基板行驱动电路，其中，每一所述辅助电路单元包括第一主动开关、第二主动开关及第三主动开关，所述第一主动开关的受控端为所述辅助电路单元的第一时序信号输入端，所述第一主动开关的输入端为所述辅助电路单元的第二时序信号输入端，所述第一主动开关的输出端与所述第二主动开关的输入端连接，所述第二主动开关的受控端为所述辅助电路单元的第一受控端，所述第二主动开关的输出端与所述第三主动开关的受控端连接，所述第三主动开关的输入端接入栅关闭信号，所述第三主动开关的输出端为所述辅助电路单元的输出端。
  3. 如权利要求1所述的阵列基板行驱动电路，其中，每一所述阵列基板行驱动单元包括充电单元、复位单元及输出单元，所述充电单元的输入端为所述阵列基板行驱动单元的信号输入端，所述充电单元的输出端为所述阵列基板行驱动单元的上拉控制信号端，并与所述与所述输出单元的受控端连接，所述输出单元的输入端接入当前级时序信号，所述输出单元的输出端为所述阵列基板行驱动单元的栅极驱动信号输出端。
  4. 如权利要求3所述的阵列基板行驱动电路，其中，所述充电单元包括第四主动开关，所述第四主动开关的输入端和受控端为所述充电单元的输入端，所述第四主动开关的输出端为所述充电单元的输出端。
  5. 如权利要求3所述的阵列基板行驱动电路，其中，所述复位单元包括第五主动开关和第六主动开关，所述第五主动开关和所述第六主动开关的受控端接入第N+4级阵列基板行驱动单元输出的栅极驱动信号，所述第五主动开关和第六主动开关的输入端分别接入栅关闭信号；所述第五主动开关的输出端与所述上拉控制信号端连接，所述第六主动开关的输出端与所述栅极驱动信号输出端连接。
  6. 如权利要求3所述的阵列基板行驱动电路，其中，所述输出单元包括第七主动开关和第八主动开关，所述第七主动开关的受控端为所述输出单元的受控端，并与所述第八主动开关的受控端，所述第七主动开关的输入端为所述输出单元的输入端，并与所述第八主动开关的输入端连接；所述第七主动开关的输出端为所述输出单元的输出端，所述第八主动开关的输出端与第N+2级阵列基板行驱动单元的信号输入端。
  7. 一种阵列基板行驱动电路，其中，所述阵列基板行驱动电路包括：
    N个级联设置的阵列基板行驱动单元，每一所述阵列基板行驱动单元包括信号输入端，上拉控制信号端及栅极驱动信号输出端；
    辅助电路单元，对应每一所述阵列基板行驱动单元设置，每一所述辅助电路单元包括第一时序信号输入端、第二时序信号输入端、第一受控端及输出端；其中，第N级所述辅助电路单元的第一时序信号输入端接入第N-1级时序控制信号，第N级所述辅助电路单元的第二时序信号输入端接入第N+1级时序控制信号，第N级所述辅助电路单元的受控端与第N级所述阵列基板行驱动单元的上拉控制信号端连接，第N级所述辅助电路单元的输出端与第N级所述阵列基板行驱动单元的栅极驱动信号输出端；其中，
    第N级所述阵列基板行驱动单元，设置为在其信号输入端接收到第N-2级所述阵列基板行驱动单元输出的栅极驱动信号时，输出第N级栅极驱动信号，以进行第N级预充电和子像素充电；
    第N级所述辅助电路单元，设置为在其第一时序信号输入端接入的第N-1级时序控制信号及第二时序信号输入端接入的第N+1级时序控制信号均为高电平时，控制所述第N级所述阵列基板行驱动单元不进行预充电；
    N 为大于等于2的正整数；
    每一所述辅助电路单元包括第一主动开关、第二主动开关及第三主动开关，所述第一主动开关、所述第二主动开关及所述第三主动开关至少一个为薄膜晶体管。
  8. 一种显示装置，其中，所述显示装置包括：
    显示面板，所述显示面板具有相对设置的两侧，所述显示面板包括像素阵列；
    以及如权利要求1所述的阵列基板行驱动电路，所述阵列基板行驱动电路包括N个级联设置的阵列基板行驱动单元和对应每一所述阵列基板行驱动单元设置的辅助电路单元，N个级联设置的所述阵列基板行驱动单元和辅助电路单元对应设置于所述显示面板的两侧。
  9. 如权利要求8所述的显示装置，其中，所述显示面板包括：
    像素阵列；
    第一基板，具有显示区域与周边区域；所述像素阵列设置于所述第一基板上且位于所述显示区域；所述N个级联设置的所述阵列基板行驱动单元和辅助电路单元设置于所述第一基板上且位于所述周边区域；
    第二基板，与所述第一基板相对设置；
    液晶层，设置于所述第一基板与所述第二基板之间，所述液晶层包括若干液晶分子，所述像素阵列设置为控制所述若干液晶分子的动作。
  10. 如权利要求9所述的显示装置，其中，所述像素阵列为半源极驱动架构的像素阵列。
  11. 如权利要求10所述的显示装置，其中，所述像素阵列包括多个薄膜晶体管，各行中奇数列的所述薄膜晶体管分别与偶数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与奇数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接；
    或者，各行中奇数列的所述薄膜晶体管分别与奇数行的所述扫描线的连接，各行中偶数列的所述薄膜晶体管分别与偶数行的所述扫描线的电连接连接，相邻的奇数列薄膜晶体管和偶数列薄膜晶体管与同一条所述数据线电连接。
  12. 如权利要求11所述的显示装置，其中，所述像素阵列的极性反转方式为1+2行画素行线信号反转。
  13. 如权利要求11所述的显示装置，其中，所述像素阵列的极性反转方式为2行画素行线信号反转。
  14. 如权利要求9所述的显示装置，其中，所述显示面板还包括框胶，设置于所述第一基板与所述第二基板之间的非显示区域内并环绕液晶层设置。
  15. 如权利要求9所述的显示装置，其中，所述显示装置还设置时序控制器，所述时序控制器与所述阵列基板行驱动电路连接，所述时序控制器，设置为接收外部电路的数据信号，并转换成驱动各所述阵列基板行驱动电路工作的时序控制信号。
  16. 如权利要求15所述的显示装置，其中，所述显示装置还设置有源极驱动器，所述源极驱动器与所述时序控制器连接，所述源极驱动器，接收所述时序控制器输出的数据信号，并通过数据线输出至对应的子像素。
  17. 如权利要求16所述的显示装置，其中，所述显示装置还设置有驱动电源，所述驱动电源的输出端与所述阵列基板行驱动电路及源极驱动器连接。
  18. 如权利要求8所述的显示装置，其中，每一所述辅助电路包括第一主动开关、第二主动开关及第三主动开关，所述第一主动开关的受控端为所述辅助电路的第一时序信号输入端，所述第一主动开关的输入端为所述辅助电路的第二时序信号输入端，所述第一主动开关的输出端与所述第二主动开关的输入端连接，所述第二主动开关的受控端为所述辅助电路的第一受控端，所述第二主动开关的输出端与所述第三主动开关的受控端连接，所述第三主动开关的输入端接入栅关闭信号，所述第三主动开关的输出端为所述辅助电路的输出端。
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JP2016061913A (ja) * 2014-09-17 2016-04-25 セイコーエプソン株式会社 電気光学装置、電気光学装置の制御方法、及び電子機器
CN108279539A (zh) * 2018-02-24 2018-07-13 惠科股份有限公司 一种阵列基板及显示装置
CN108877725A (zh) * 2018-08-31 2018-11-23 重庆惠科金渝光电科技有限公司 一种显示面板的驱动方法及装置

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