WO2020113516A1 - 一种eoa电路、显示面板及终端 - Google Patents

一种eoa电路、显示面板及终端 Download PDF

Info

Publication number
WO2020113516A1
WO2020113516A1 PCT/CN2018/119554 CN2018119554W WO2020113516A1 WO 2020113516 A1 WO2020113516 A1 WO 2020113516A1 CN 2018119554 W CN2018119554 W CN 2018119554W WO 2020113516 A1 WO2020113516 A1 WO 2020113516A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
signal
level
eoa circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/119554
Other languages
English (en)
French (fr)
Inventor
陈丹
金志河
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Royole Technologies Co Ltd
Original Assignee
Shenzhen Royole Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Royole Technologies Co Ltd filed Critical Shenzhen Royole Technologies Co Ltd
Priority to CN201880097640.5A priority Critical patent/CN113168811B/zh
Priority to PCT/CN2018/119554 priority patent/WO2020113516A1/zh
Publication of WO2020113516A1 publication Critical patent/WO2020113516A1/zh
Priority to US17/338,963 priority patent/US11367402B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technology, and more particularly, to an EOA circuit, display panel and terminal.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the display of the OLED display panel needs to be provided with a scanning driving signal by a scanning driving circuit.
  • the scanning driving circuit is mainly composed of GOA (Gate D-IC On Array, display panel scanning driver) circuit and EOA circuit are composed of two parts.
  • GOA Gate D-IC On Array, display panel scanning driver
  • EOA emission D-IC On Array, display panel light-emitting drive
  • the signal enters through the drive transistor to complete the input of the data signal.
  • the existing EOA circuit structure is generally composed of 8T1C (that is, 8 transistors and 1 capacitor), and requires 4 first clock signal (ECLK) and 2 second clock signal (ECLKB) signal lines, as shown in Figure 1
  • ECLK first clock signal
  • ECLKB second clock signal
  • FIG. 1 It is a circuit diagram of the existing 8T1C EOA circuit.
  • the EOA circuit mainly includes a pull-up control module, a pull-up output module, a pull-down control module, and a pull-down output module.
  • the circuit structure is in layout It requires a large amount of space, which is not conducive to narrow border design.
  • the technical problem to be solved by the present invention is that the above-mentioned circuit structure of the prior art is complicated, occupies a large space, and is not conducive to the defects of the narrow frame design, and provides an EOA circuit, a display panel, and a terminal.
  • the technical solution adopted by the present invention to solve its technical problems is to provide an EOA circuit, including:
  • the output module is used to generate an output signal according to the first scan signal and the clock signal; the output module is also used to convert the first scan signal to an active level and the clock signal to an inactive period. The output signal is reset from the high level signal to the low level signal;
  • the control module is configured to restore the output signal from the low-level signal to the high-level signal according to the second scan signal while the first scan signal is at an invalid level.
  • the output module is composed of an N-channel metal oxide semiconductor transistor.
  • control module is composed of an N-channel metal oxide semiconductor transistor and a P-channel metal oxide semiconductor transistor.
  • the output module includes:
  • a third transistor the first electrode of the third transistor is connected to the clock signal, the second electrode of the third transistor is connected to the output of the EOA circuit, and the third electrode of the third transistor is connected to the first Scan the signal.
  • control module includes:
  • a first transistor, a first electrode of the first transistor is connected to a high-level signal, a second electrode of the first transistor is connected to a second electrode of the third transistor, and a third electrode of the first transistor is connected to a The second scan signal is described.
  • control module further includes:
  • a second transistor the first electrode of the second transistor is connected to the second electrode of the first transistor, the second electrode of the second transistor is connected to a low-level signal, and the third electrode of the second transistor is connected to the The third electrode of the first transistor is short-circuited and connected to the second scan signal.
  • the first transistor is a P-channel metal oxide semiconductor transistor
  • the second transistor is an N-channel metal oxide semiconductor transistor.
  • the third transistor is turned on.
  • the first transistor when the second scan signal is at a high level, the first transistor is turned off, and the third transistor is turned on.
  • the size of the third transistor is larger than the size of the first transistor.
  • the first scan signal is at a low level and the second scan signal is at a high level; when a low-level first scan signal is applied to the third electrode of the third transistor, the The third transistor is turned off, and at the same time, a high-level second scan signal is applied to the third electrodes of the first transistor and the second transistor, the first transistor is turned off, and the second transistor is turned on;
  • the low-level signal pulls the first electrode of the second transistor low, and at the same time pulls the voltage of the output terminal of the EOA circuit low, so that the output terminal of the EOA circuit outputs a low-level signal.
  • the third transistor when the first scan signal of the high level is applied to the third electrode of the third transistor, the third transistor is turned on, and at the same time, the second scan signal of the low level is applied to Third electrodes of the first transistor and the second transistor, the first transistor is turned on, and the second transistor is turned off;
  • the high-level clock signal is transmitted from the first electrode of the third transistor to the second electrode of the third transistor and to the output of the EOA circuit, and at the same time, the high-level signal is transmitted from the first
  • the first electrode of the transistor is transferred to the second electrode of the first transistor and to the output of the EOA circuit, so that the output of the EOA circuit outputs a high-level signal.
  • the third transistor when a low-level second scan signal is applied to the third electrode of the first transistor and the third electrode of the third transistor, the first transistor is turned on, the The second transistor is turned off, and at the same time, a high-level first scan signal is applied to the third electrode of the third transistor, and the third transistor is turned on;
  • a high-level signal is transmitted from the first electrode of the first transistor to the second electrode of the first transistor and to the output of the EOA circuit, and at the same time, a low-level clock signal passes through the third
  • the first electrode of the transistor is transferred to the second electrode of the third transistor and to the output terminal of the EOA circuit, so that the output terminal of the EOA circuit outputs a low-level signal.
  • the EOA circuit is a CMOS EOA circuit.
  • the present invention also provides a display panel including an EOA circuit provided in a boundary area, the EOA circuit being the EOA circuit described above.
  • the display panel is a liquid crystal display panel.
  • the display panel is an OLED display panel.
  • the display panel is an AMOLED display panel.
  • the present invention also provides a terminal including the above-mentioned display panel.
  • the implementation of the EOA circuit of the present invention can greatly reduce the layout size of the EOA circuit due to the simple circuit structure adopted, and the layout takes up less space, which greatly facilitates the design of narrow borders and can be widely used in display panels with narrow border design requirements.
  • Figure 1 is a circuit diagram of an existing 8T1C EOA circuit
  • FIG. 2 is a circuit diagram of the EOA circuit provided by the present invention.
  • FIG. 3 is a timing diagram of a single-stage EOA circuit provided by the present invention.
  • FIG. 5 is a diagram of a simulation result of clock signal timing of a multi-level EOA circuit provided by the present invention.
  • FIG. 6 is a comparison diagram of the layout size of the EOA circuit provided by the present invention and the existing 8T1C EOA circuit;
  • FIG. 7 is a schematic diagram of the location of the EOA circuit provided by the present invention.
  • the EOA circuit can be used in a display panel, wherein the display panel includes but is not limited to a liquid crystal display panel (such as TFT-LCD panel), OLED display panel, AMOLED display panel, flexible Display panel, etc.
  • a liquid crystal display panel such as TFT-LCD panel
  • OLED display panel such as OLED display panel
  • AMOLED display panel such as AMOLED display panel
  • flexible Display panel etc.
  • the EOA circuit can be set in the non-display area of the display panel, and generally can be set in the boundary area of the display panel, such as the left and right sides of the display panel.
  • the EOA circuit of the present invention may be a CMOS EOA circuit.
  • the EOA circuit includes an output module 10 and a control module 20.
  • the output module 10 is used for generating the output signal by the first scan signal (Gn) and the clock signal (ECKB); the output module 10 is also used for the clock signal (ECKB) while the first scan signal (Gn) is at an effective level During the inactive level, the output signal (Eout) is reset from the high level signal to the low level signal.
  • the control module 20 is configured to restore the output signal (Eout) from the low-level signal to the high-level signal according to the second scan signal (Gn-2) while the first scan signal (Gn) is at an invalid level.
  • the effective level period of the first scan signal (Gn) is a high level period
  • the invalid level period of the first scan signal (Gn) is a low level period
  • the active level period of the clock signal (ECKB) is a high level period
  • the inactive level period of the clock signal (ECKB) is a low level period.
  • the output module 10 may be composed of an N-channel metal oxide semiconductor transistor.
  • the output module 10 includes an output terminal (Eout) of the EOA circuit and a third transistor T3.
  • the first electrode of the third transistor T3 is connected to the clock signal (ECKB), the second electrode of the third transistor T3 is connected to the output terminal (Eout) of the EOA circuit, and the third electrode of the third transistor T3 is connected to the first scan signal (Gn).
  • the third transistor T3 may be an N-channel metal oxide semiconductor transistor, such as an N-type MOS transistor.
  • the first electrode of the third transistor T3 is the drain of the N-type MOS tube, the second electrode of the third transistor T3 is the source of the N-type MOS tube, and the third electrode of the third transistor T3 is the N-type MOS tube Grid.
  • the third transistor T3 when the first scan signal (Gn) is at a high level, the third transistor T3 is turned on; when the first scan signal (Gn) is at a low level, the third transistor T3 is turned off.
  • the size of the third transistor of the embodiment of the present invention is much larger than the size of the first transistor.
  • the first scan signal is low and the second scan signal is high.
  • the third transistor T3 is turned off, and at the same time, the second scan signal of the high level is applied to the first transistor T1 and the second transistor T2.
  • the third electrode, the first transistor T1 and the second transistor T2 are turned on; the low-level signal pulls the first electrode of the second transistor T2 low, and at the same time pulls the voltage of the output terminal (Eout) of the EOA circuit low, making the EOA circuit
  • the output (Eout) outputs a low-level signal.
  • the third transistor T3 when the high-level first scan signal (Gn) is applied to the third electrode of the third transistor T3, the third transistor T3 is turned on, and at the same time, the low-level second scan signal (Gn) Gn-2) applied to the third electrodes of the first transistor T1 and the second transistor T2, the first transistor T1 is turned on, the second transistor T2 is turned off; the high-level clock signal (ECKB) is from the third transistor T3
  • One electrode is transmitted to the second electrode of the third transistor T3 and to the output terminal (Eout) of the EOA circuit, and at the same time, a high-level signal (EGH) is transmitted from the first electrode of the first transistor T1 to the first transistor T1
  • the second electrode is transmitted to the output terminal (Eout) of the EOA circuit, so that the output terminal (Eout) of the EOA circuit outputs a high-level signal.
  • control module 20 may be composed of an N-channel metal oxide semiconductor transistor and a P-channel metal oxide semiconductor transistor.
  • control module 20 includes a first transistor T1.
  • the first electrode of the first transistor T1 is connected to the high-level signal (EGH), the second electrode of the first transistor T1 is connected to the second electrode of the third transistor T3, and the third electrode of the first transistor T1 is connected to the second scan signal ( Gn-2).
  • the first transistor T1 may be a P-channel metal oxide semiconductor transistor, such as a P-type MOS transistor.
  • the first electrode of the first transistor T1 is the drain of the P-type MOS tube, the second electrode of the first transistor T1 is the source of the P-type MOS tube, and the third electrode of the first transistor T1 is the P-type MOS tube Grid.
  • the second scan signal (Gn-2) when the second scan signal (Gn-2) is at a low level, the first transistor T1 is turned on; when the second scan signal (Gn-2) is at a high level, the first transistor T1 is turned off.
  • control module 20 further includes a second transistor T2.
  • the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2 is connected to the low-level signal (EGL), the third electrode of the second transistor T2 and the first transistor T1
  • the third electrode is short-circuited and connected to the second scan signal (Gn-2).
  • the second transistor T2 may be an N-channel metal oxide semiconductor transistor, such as an N-type MOS transistor.
  • the first electrode of the second transistor T2 is the source of the N-type MOS tube, the second electrode of the second transistor T2 is the drain of the N-type MOS tube, and the third electrode of the second transistor T2 is the N-type MOS tube Grid.
  • the second scan signal (Gn-2) when the second scan signal (Gn-2) is at a low level, the second transistor T2 is turned off; when the second scan signal (Gn-2) is at a high level, the second transistor T2 is turned on.
  • the first transistor T1 is a P-type MOS tube
  • the second transistor T2 is an N-type MOS tube
  • the gate of the first transistor T1 and the gate of the second transistor T2 are short-circuited.
  • the second scan signal (Gn-2) is low
  • the first transistor T1 is turned on
  • the second transistor T2 is turned off
  • the second scan signal (Gn-2) is high
  • the first transistor T1 is turned off
  • the first The two transistors T2 are turned on.
  • the high-level signal (EGH) is transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1 and to the output terminal (Eout) of the EOA circuit, and at the same time, the low-level clock signal (ECKB)
  • the first electrode of the third transistor T3 is transferred to the second electrode of the third transistor T3 and to the output terminal (Eout) of the EOA circuit. Since the size of the third transistor T3 is much larger than the size of the first transistor T1, the EOA The output terminal (Eout) of the circuit is kept at a low level, and then the output terminal (Eout) of the EOA circuit outputs a low-level signal.
  • FIG. 3 shows a timing simulation result diagram of a single clock signal (ECKB) of the EOA circuit of the present invention.
  • the second scan signal (Gn-2) is high level
  • the first scan signal (Gn) is low level
  • the clock signal (ECKB) is high level
  • the first The three transistors T3 are turned off, the first transistor T1 is turned off, the second transistor T2 is turned on, the low level signal (EGL) is output to the point P through the second transistor T2, and the output terminal (Eout) of the EOA circuit is pulled down to a low level Level, so that the output (Eout) of the EOA circuit outputs a low level.
  • the second scan signal (Gn-2) is low level, the first scan signal (Gn) is high level, and the clock signal (ECKB) is high level
  • the third transistor T3 is turned on, The first transistor T1 is turned on and the second transistor T2 is turned off; a high-level clock signal (ECKB) is input from the first electrode of the third transistor T3 and transmitted to the output terminal of the EOA circuit through the second electrode of the third transistor T3 (Eout), the high-level signal (EGH) is output to the point P through the first transistor T1, so that the output terminal (Eout) of the EOA circuit outputs a high-level signal (EGH) to the display area of the display panel.
  • the second scan signal (Gn-2) is low level, the first scan signal (Gn) is high level, and the clock signal (ECKB) is low level
  • the third transistor T3 is turned on, The first transistor T1 is turned on, and the second transistor T2 is turned off; a low-level clock signal (ECKB) is applied to the first electrode of the third transistor T3, and output to the point P through the third transistor T3, while a high-level signal (EGH) Output to point P through the first transistor T1.
  • the voltage at point P is maintained at a low level, which in turn outputs the output of the EOA circuit
  • the terminal (Eout) is pulled down to a low level to reset the high-level signal (EGH) of the output terminal (Eout) of the EOA circuit to a low-level signal (EGL).
  • the second scan signal (Gn-2) is low, the first scan signal (Gn) is low, and the clock signal (ECKB) is high
  • the third transistor T3 is turned off, The first transistor T1 is turned on, and the second transistor T2 is turned off; the high level signal (EGH) is transmitted from the first electrode input of the first transistor T1 to the second electrode of the first transistor T1, and the second transistor T1
  • the electrode transmits the high-level signal (EGH) to the output terminal (Eout) of the EOA circuit, and restores the output terminal (Eout) of the EOA circuit from the low-level signal to the high-level signal.
  • FIG. 4 it is a simulation result diagram of a single-stage EOA circuit provided by an embodiment of the present invention.
  • FIG. 5 is a simulation result of the present invention using the aforementioned EOA circuit and 4 clock signals (ECKB). It can be seen from FIG. 5 that the present invention can complete the output of the light-emitting signal of the driving TFT tube in the display panel using only the aforementioned EOA circuit and four clock signal (ECKB) lines.
  • the EOA circuit of the present invention only needs 3 transistors and 4 clock signal (ECKB) lines to complete the control of the output signal of the EOA circuit, compared with the existing 8T1C, 4
  • Two CLK signal lines and two ECLKB signal lines have better stability, and the number of transistors is greatly reduced, and the number of signal lines is also greatly reduced, which greatly simplifies the circuit structure of the EOA circuit.
  • the layout size of the EOA circuit of the present invention is compared with the layout size of the existing 8T1C EOA circuit. As can be seen from FIG.
  • the layout size of each stage of the EOA circuit of the present invention can be reduced to 0.75mm, which can be reduced by 50% compared to the existing one, and the overall EOA circuit layout size can be reduced by 20%. Therefore, the EOA circuit of the present invention can effectively reduce the space occupied by the layout, and can be applied to designs with narrow border requirements.
  • the present invention also provides a display panel including an EOA circuit disposed in a boundary area, and the EOA circuit disposed in a boundary area of the display panel is the aforementioned EOA circuit.
  • the boundary area is a non-display area of the display panel.
  • FIG. 7 shows a location diagram of a specific embodiment of an EOA circuit provided by an embodiment of the present invention.
  • the display panel displays area AA and two EOA circuits.
  • the display area AA is located in the middle of the display panel, and the area between the periphery of the display area AA and the edge of the display panel forms a boundary area.
  • the two EOA circuits are respectively disposed in the boundary areas on opposite sides of the display area AA.
  • the display panel provided by the embodiment of the present invention may be a liquid crystal display panel (such as TFT-LCD, etc.), or the display panel provided by the embodiment of the present invention may be an OLED display panel; or, the display panel provided by the embodiment of the present invention
  • the display panel may be an AMOLED display panel.
  • the display panel provided by the embodiment of the present invention may also be another type of display panel, such as a flexible display panel, etc., which is not specifically described in the present invention. limited.
  • the present invention also provides a terminal including the aforementioned display panel.
  • terminals include but are not limited to smart phones, tablet computers, smart watches, smart wearable devices, smart homes, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种EOA电路、显示面板及终端，该EOA电路包括：输出模块（10），用于根据第一扫描信号（Gn）和时钟信号（ECKB）生成输出信号（Eout）；输出模块（10）还用于在第一扫描信号（Gn）为有效电平期间且时钟信号（ECKB）为无效电平期间，将输出信号（Eout）由高电平信号重置为低电平信号；控制模块（20），用于在第一扫描信号（Gn）为无效电平期间，根据第二扫描信号（Gn-2），将输出信号（Eout）由低电平信号恢复至高电平信号。该EOA电路结构简单，占用空间小，有利于窄边框设计。

Description

一种EOA电路、显示面板及终端 技术领域
本发明涉及显示技术领域，更具体地说，涉及一种EOA电路、显示面板及终端。
 背景技术
OLED（Organic Light-Emitting Diode，有机发光二极管）作为一种电流型发光器件，具有自发光、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点，被广泛应用于显示技术领域。
OLED显示面板的显示需要由扫描驱动电路提供扫描驱动信号，扫描驱动电路主要由GOA(Gate D-IC On Array，显示面板扫描驱动)电路和EOA电路两部分组成。其中， EOA（Emission D-IC On Array，显示面板发光驱动）电路，其仅在数据输入阶段为低电平，在其它阶段均为高电平，即在数据输入阶段，EOA电路处于截止状态，不输出信号，驱动IC输出的数据信号经由驱动晶体管进入，完成数据信号的输入。
现有的EOA电路结构一般由8T1C（即8个晶体管和1个电容）组成，同时需要4条第一时钟信号（ECLK）和2条第二时钟信号（ECLKB）信号线，如图1所示为现有的8T1C的EOA电路的电路图，该EOA电路主要包括上拉控制模块、上拉输出模块、下拉控制模块和下拉输出模块，由图1中可以看出，该电路结构在布局（layout）时需要占用的空间较大，不利于窄边框设计。
 技术问题
本发明要解决的技术问题在于，针对现有技术的上述电路结构复杂，占用空间大，不利于窄边框设计的缺陷，提供一种EOA电路、显示面板及终端。
 技术解决方案
本发明解决其技术问题所采用的技术方案是：提供一种EOA电路，包括：
输出模块，用于根据第一扫描信号和时钟信号生成输出信号；所述输出模块还用于在所述第一扫描信号为有效电平期间且所述时钟信号为无效电平期间，将所述输出信号由高电平信号重置为低电平信号；
控制模块，用于在所述第一扫描信号为无效电平期间，根据第二扫描信号，将所述输出信号由低电平信号恢复至高电平信号。
优选地，所述输出模块由N沟道金属氧化物半导体晶体管构成。
优选地，所述控制模块由N沟道金属氧化物半导体晶体管和P沟道金属氧化物半导体晶体管构成。
优选地，所述输出模块包括：
EOA电路的输出端；
第三晶体管，所述第三晶体管的第一电极连接所述时钟信号，所述第三晶体管第二电极连接所述EOA电路的输出端，所述第三晶体管的第三电极连接所述第一扫描信号。
优选地，所述控制模块包括：
第一晶体管，所述第一晶体管的第一电极连接高电平信号，所述第一晶体管的第二电极连接所述第三晶体管的第二电极，所述第一晶体管的第三电极连接所述第二扫描信号。
优选地，所述控制模块还包括：
第二晶体管，所述第二晶体管的第一电极连接所述第一晶体管的第二电极，所述第二晶体管的第二电极连接低电平信号，所述第二晶体管的第三电极与所述第一晶体管的第三电极短接并连接所述第二扫描信号。
优选地，所述第一晶体管为P沟道金属氧化物半导体晶体管，所述第二晶体管为N沟道金属氧化物半导体晶体管。
优选地，所述第一扫描信号为高电平时，所述第三晶体管导通。
优选地，所述第二扫描信号为高电平时，所述第一晶体管关断，所述第三晶体管导通。
优选地，所述第三晶体管的尺寸大于所述第一晶体管的尺寸。
优选地，在第一时段，第一扫描信号为低电平，第二扫描信号为高电平；当低电平的第一扫描信号施加至所述第三晶体管的第三电极时，所述第三晶体管关断，同时，高电平的第二扫描信号施加至所述第一晶体管和第二晶体管的第三电极，所述第一晶体管关断，第二晶体管导通；
低电平信号将第二晶体管的第一电极拉低，同时将所述EOA电路的输出端电压拉低，使所述EOA电路的输出端输出低电平信号。
优选地，在第二时段，当高电平的第一扫描信号施加至所述第三晶体管的第三电极时，所述第三晶体管导通，同时，低电平的第二扫描信号施加至所述第一晶体管和所述第二晶体管的第三电极，所述第一晶体管导通，所述第二晶体管关断；
高电平的时钟信号从所述第三晶体管的第一电极传送至所述第三晶体管的第二电极，并传送至所述EOA电路的输出端，同时，高电平信号从所述第一晶体管的第一电极传送至所述第一晶体管的第二电极，并传送至所述EOA电路的输出端，使所述EOA电路的输出端输出高电平信号。
优选地，在第三时段，当低电平的第二扫描信号施加至所述第一晶体管的第三电极和所述第三晶体管的第三电极时，所述第一晶体管导通，所述第二晶体管关断，同时，高电平的第一扫描信号施加至所述第三晶体管的第三电极，第三晶体管导通；
高电平信号从所述第一晶体管的第一电极传送至所述第一晶体管的第二电极，并传送至所述EOA电路的输出端，同时，低电平的时钟信号通过所述第三晶体管的第一电极传送至所述第三晶体管的第二电极并传送至所述EOA电路的输出端，使所述EOA电路的输出端输出低电平信号。
优选地，所述EOA电路为CMOS EOA电路。
本发明还提供一种显示面板，包括设置在边界区域的EOA电路，所述EOA电路为以上所述的EOA电路。
优选地，所述显示面板为液晶显示面板。
优选地，所述显示面板为OLED显示面板。
优选地，所述显示面板为AMOLED显示面板。
本发明还提供一种终端，包括以上所述的显示面板。
 有益效果
实施本发明的EOA电路，由于所采用的电路结构简单，可以大大缩小EOA电路的layout尺寸，layout占用空间小，大大有利于窄边框设计，可广泛应用于窄边框设计需求的显示面板。
 附图说明
为了更清楚地说明本发明实施例，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。附图中：
图1是现有的8T1C的EOA电路的电路图；
图2是本发明提供的EOA电路的电路图；
图3是本发明提供的单级EOA电路的时序图；
图4是本发明提供的单级EOA电路的仿真结果图；
图5是本发明提供的多级EOA电路的时钟信号时序仿真结果图；
图6是本发明提供的EOA电路与现有的8T1C的EOA电路的layout尺寸对比图；
图7为本发明提供的EOA电路的位置示意图。
 本发明的最佳实施方式
在此处键入本发明的最佳实施方式描述段落。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2是本发明提供的一种EOA电路的电路图，该EOA电路可用于显示面板，其中，显示面板包括但不限于液晶显示面板（如TFT-LCD面板）、OLED显示面板、AMOLED显示面板、柔性显示面板等。
其中，该EOA电路可设置在显示面板的非显示区域，一般可设置在显示面板的边界区域，如可以设置显示面板的左右两侧。本发明的EOA电路可以为CMOS EOA电路。
如图2所示，本实施例中，该EOA电路包括输出模块10和控制模块20。其中，输出模块10用于第一扫描信号（Gn）和时钟信号（ECKB）生成输出信号；该输出模块10还用于在第一扫描信号（Gn）为有效电平期间且时钟信号（ECKB）为无效电平期间，将输出信号（Eout）由高电平信号重置为低电平信号。控制模块20，用于在第一扫描信号（Gn）为无效电平期间，根据第二扫描信号（Gn-2），将输出信号（Eout）由低电平信号恢复至高电平信号。
这里，第一扫描信号（Gn）的有效电平期间为高电平期间，第一扫描信号（Gn）的无效电平期间为低电平期间。时钟信号（ECKB）的有效电平期间为高电平期间，时钟信号（ECKB）的无效电平期间为低电平期间。
可选的，本发明实施例中，输出模块10可以由N沟道金属氧化物半导体晶体管构成。
进一步地，在该实施例中，该输出模块10包括EOA电路的输出端（Eout）和第三晶体管T3。
该第三晶体管T3的第一电极连接时钟信号（ECKB），第三晶体管T3第二电极连接EOA电路的输出端（Eout），第三晶体管T3的第三电极连接第一扫描信号（Gn）。可以理解地，该第三晶体管T3可以为N沟道金属氧化物半导体晶体管，如N型MOS管。其中，第三晶体管T3的第一电极为N型MOS管的漏极，第三晶体管T3的第二电极为N型MOS管的源极，第三晶体管T3的第三电极为N型MOS管的栅极。本实施例中，当第一扫描信号（Gn）为高电平时，第三晶体管T3导通；当第一扫描信号（Gn）为低电平时，第三晶体管T3关断。其中，本发明实施例的第三晶体管的尺寸远大于第一晶体管的尺寸。
如图3所示，在第一时段（①），第一扫描信号为低电平，第二扫描信号为高电平。当低电平的第一扫描信号施加至第三晶体管T3的第三电极时，第三晶体管T3关断，同时，高电平的第二扫描信号施加至第一晶体管T1和第二晶体管T2的第三电极，第一晶体管T1和第二晶体管T2导通；低电平信号将第二晶体管T2的第一电极拉低，同时将EOA电路的输出端（Eout）电压拉低，使EOA电路的输出端（Eout）输出低电平信号。
在第二时段（②），当高电平的第一扫描信号（Gn）施加至第三晶体管T3的第三电极时，第三晶体管T3导通，同时，低电平的第二扫描信号（Gn-2）施加至第一晶体管T1和第二晶体管T2的第三电极，第一晶体管T1导通，第二晶体管T2关断；高电平的时钟信号（ECKB）从第三晶体管T3的第一电极传送至第三晶体管T3的第二电极，并传送至EOA电路的输出端（Eout），同时，高电平信号（EGH）从第一晶体管T1的第一电极传送至第一晶体管T1的第二电极，并传送至EOA电路的输出端（Eout），使EOA电路的输出端（Eout）输出高电平信号。
可选的，本发明实施例中，控制模块20可以由N沟道金属氧化物半导体晶体管和P沟道金属氧化物半导体晶体管构成。
进一步地，在该实施例中，该控制模块20包括第一晶体管T1。
该第一晶体管T1的第一电极连接高电平信号（EGH），第一晶体管T1的第二电极连接第三晶体管T3的第二电极，第一晶体管T1的第三电极连接第二扫描信号（Gn-2）。可以理解地，该第一晶体管T1可以为P沟道金属氧化物半导体晶体管，如P型MOS管。其中，第一晶体管T1的第一电极为P型MOS管的漏极，第一晶体管T1的第二电极为P型MOS管的源极，第一晶体管T1的第三电极为P型MOS管的栅极。本实施例中，当第二扫描信号（Gn-2）为低电平时，第一晶体管T1导通；当第二扫描信号（Gn-2）为高电平时，第一晶体管T1关断。
进一步地，该控制模块20还包括第二晶体管T2。
该第二晶体管T2的第一电极连接第一晶体管T1的第二电极，第二晶体管T2的第二电极连接低电平信号（EGL），第二晶体管T2的第三电极与第一晶体管T1的第三电极短接并连接第二扫描信号（Gn-2）。可以理解地，该第二晶体管T2可以为N沟道金属氧化物半导体晶体管，如N型MOS管。其中，第二晶体管T2的第一电极为N型MOS管的源极，第二晶体管T2的第二电极为N型MOS管的漏极，第二晶体管T2的第三电极为N型MOS管的栅极。本实施例中，当第二扫描信号（Gn-2）为低电平时，第二晶体管T2关断；当第二扫描信号（Gn-2）为高电平时，第二晶体管T2导通。
即如图2所示，第一晶体管T1为P型MOS管，第二晶体管T2为N型MOS管，且第一晶体管T1的栅极与第二晶体管T2的栅极短接，所以，当第二扫描信号（Gn-2）为低电平时，第一晶体管T1导通，第二晶体管T2关断；当第二扫描信号（Gn-2）为高电平时，第一晶体管T1关断，第二晶体管T2导通。
如图3所示，在第三时段（③），当低电平的第二扫描信号（Gn-2）施加至第一晶体管T1的第三电极和第二晶体管T2的第三电极时，第一晶体管T1导通，第二晶体管T2关断，同时，高电平的第一扫描信号（Gn）施加至第三晶体管T3的第三电极，第三晶体管T3导通。
高电平信号（EGH）从第一晶体管T1的第一电极传送至第一晶体管T1的第二电极，并传送至EOA电路的输出端（Eout），同时，低电平的时钟信号（ECKB）通过第三晶体管T3的第一电极传送至第三晶体管T3的第二电极并传送至EOA电路的输出端（Eout），由于，第三晶体管T3的尺寸远大于第一晶体管T1的尺寸，所以EOA电路的输出端（Eout）保持在低电平，进而EOA电路的输出端（Eout）输出低电平信号。
进一步地，图3示出了本发明的EOA电路的单个时钟信号（ECKB）的时序仿真结果图。
如图3所示：在①时段：第二扫描信号（Gn-2）为高电平，第一扫描信号（Gn）为低电平，时钟信号（ECKB）为高电平，此时，第三晶体管T3关断，第一晶体管T1关断，第二晶体管T2导通，低电平信号（EGL）通过第二晶体管T2输出到P点，将EOA电路的输出端（Eout）下拉到低电平，，使EOA电路的输出端（Eout）输出低电平。
在②时段：第二扫描信号（Gn-2）为低电平，第一扫描信号（Gn）为高电平，时钟信号（ECKB）为高电平，此时，第三晶体管T3导通，第一晶体管T1导通，第二晶体管T2关断；高电平的时钟信号（ECKB）从第三晶体管T3的第一电极输入并通过第三晶体管T3的第二电极传送至EOA电路的输出端（Eout），高电平信号（EGH）通过第一晶体管T1输出到P点，使EOA电路的输出端（Eout）输出高电平信号（EGH）至显示面板的显示区域。
在③时段：第二扫描信号（Gn-2）为低电平，第一扫描信号（Gn）为高电平，时钟信号（ECKB）为低电平，此时，第三晶体管T3导通，第一晶体管T1导通，第二晶体管T2关断；低电平的时钟信号（ECKB）施加在第三晶体管T3的第一电极上，通过第三晶体管T3输出到P点，同时高电平信号（EGH）通过第一晶体管T1输出到P点，此时，由于第三晶体管T3的尺寸远大于第一晶体管T1的尺寸，所以，P点的电压维持在低电平，进而将EOA电路的输出端（Eout）拉低至低电平，将EOA电路的输出端（Eout）的高电平信号（EGH）重置为低电平信号（EGL）。
在④时段：第二扫描信号（Gn-2）为低电平，第一扫描信号（Gn）为低电平，时钟信号（ECKB）为高电平，此时，第三晶体管T3关断，第一晶体管T1导通，第二晶体管T2关断；高电平信号（EGH）从第一晶体管T1的第一电极输入传送至第一晶体管T1的第二电极，由第一晶体管T1的第二电极将高电平信号（EGH）传送至EOA电路的输出端（Eout），将EOA电路的输出端（Eout）由低电平信号恢复至高电平信号。
参考图4，为本发明实施例提供的单级EOA电路的仿真结果图。
对比图3和图4可以看出，仿真结果图与时序图结果相当。
结合图5，图5为本发明采用前述EOA电路及4条时钟信号（ECKB）的仿真结果。由图5中可以看出，本发明只采用前述的EOA电路及4条时钟信号（ECKB）线即可完成对显示面板中驱动TFT管的发光信号的输出。
综上，如图1和图5所示，本发明的EOA电路只需3个晶体管和4条时钟信号（ECKB）线即可完成EOA电路的输出信号的控制，相比现有的8T1C、4条CLK信号线和2条ECLKB信号线，稳定性更好，而且，晶体管的数量大大减小，而且信号线的数量也大大减小，进而大大简化了EOA电路的电路结构，在进行layout时可以有效缩小EOA电路占用的空间。如图6所示，为本发明的EOA电路的layout尺寸和现有8T1C的EOA电路的layout尺寸对比图，由图6中可以看出，本发明的每一级EOA电路的layout尺寸可以缩小到0.75mm，相比现有可以缩小达到50%，整体的EOA电路的layout尺寸可以缩小达到20%，因此，本发明的EOA电路可以有效缩小layout占用的空间，可应用于窄边框需求的设计。
本发明还提供了一种显示面板，该显示面板包括设置在边界区域的EOA电路，设置在该显示面板的边界区域的EOA电路为前述的EOA电路。其中，边界区域为显示面板的非显示区域。
参考图7，图7示出了本发明实施例提供的EOA电路一个具体实施例的位置图。
如图7所示，在该实施例中，该显示面板显示区域AA和两个EOA电路。显示区域AA位于显示面板的中部位置，显示区域AA外围与显示面板的边缘之间的区域形成边界区域。该两个EOA电路分别设置在显示区域AA的相对两侧的边界区域内。
在具体实施时，本发明实施例提供的显示面板可以为液晶显示面板（如TFT-LCD等）、或者，本发明实施例提供的显示面板可以为OLED显示面板；或者，本发明实施例提供的显示面板可以为AMOLED显示面板，当然，可以理解地，在其他一些实施例中，本发明实施例提供的显示面板还可以是其他类型的显示面板，如柔性显示面板等，本发明对此不作具体限定。
本发明还提供一种终端，该终端包括前述的显示面板。其中，终端包括但不限于智能手机、平板电脑、智能手表、智能可穿戴设备、智能家居等。
以上实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据此实施，并不能限制本发明的保护范围。凡跟本发明权利要求范围所做的均等变化与修饰，均应属于本发明权利要求的涵盖范围。
应当理解的是，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，而所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (19)

  1. 一种EOA电路，其特征在于，包括：
    输出模块，用于根据第一扫描信号和时钟信号生成输出信号；所述输出模块还用于在所述第一扫描信号为有效电平期间且所述时钟信号为无效电平期间，将所述输出信号由高电平信号重置为低电平信号；
    控制模块，用于在所述第一扫描信号为无效电平期间，根据第二扫描信号，将所述输出信号由低电平信号恢复至高电平信号。
  2. 根据权利要求1所述的EOA电路，其特征在于，所述输出模块由N沟道金属氧化物半导体晶体管构成。
  3. 根据权利要求1所述的EOA电路，其特征在于，所述控制模块由N沟道金属氧化物半导体晶体管和P沟道金属氧化物半导体晶体管构成。
  4. 根据权利要求2所述的EOA电路，其特征在于，所述输出模块包括：
    EOA电路的输出端；
    第三晶体管，所述第三晶体管的第一电极连接所述时钟信号，所述第三晶体管第二电极连接所述EOA电路的输出端，所述第三晶体管的第三电极连接所述第一扫描信号。
  5. 根据权利要求4所述的EOA电路，其特征在于，所述控制模块包括：
    第一晶体管，所述第一晶体管的第一电极连接高电平信号，所述第一晶体管的第二电极连接所述第三晶体管的第二电极，所述第一晶体管的第三电极连接所述第二扫描信号。
  6. 根据权利要求5所述的EOA电路，其特征在于，所述控制模块还包括：
    第二晶体管，所述第二晶体管的第一电极连接所述第一晶体管的第二电极，所述第二晶体管的第二电极连接低电平信号，所述第二晶体管的第三电极与所述第一晶体管的第三电极短接并连接所述第二扫描信号。
  7. 根据权利要求6所述的EOA电路，其特征在于，所述第一晶体管为P沟道金属氧化物半导体晶体管，所述第二晶体管为N沟道金属氧化物半导体晶体管。
  8. 根据权利要求6所述的EOA电路，其特征在于，所述第一扫描信号为高电平时，所述第三晶体管导通。
  9. 根据权利要求6所述的EOA电路，其特征在于，所述第二扫描信号为高电平时，所述第一晶体管关断，所述第二晶体管导通。
  10. 根据权利要求5所述的EOA电路，其特征在于，所述第三晶体管的尺寸大于所述第一晶体管的尺寸。
  11. 根据权利要求6所述的EOA电路，其特征在于，在第一时段，第一扫描信号为低电平，第二扫描信号为高电平；当低电平的第一扫描信号施加至所述第三晶体管的第三电极时，所述第三晶体管关断，同时，高电平的第二扫描信号施加至所述第一晶体管和第二晶体管的第三电极，所述第一晶体管和第二晶体管导通；
    低电平信号将第二晶体管的第一电极拉低，同时将所述EOA电路的输出端电压拉低，使所述EOA电路的输出端输出低电平信号。
  12. 根据权利要求6所述的EOA电路，其特征在于，在第二时段，当高电平的第一扫描信号施加至所述第三晶体管的第三电极时，所述第三晶体管导通，同时，低电平的第二扫描信号施加至所述第一晶体管和所述第二晶体管的第三电极，所述第一晶体管导通，所述第二晶体管关断；
    高电平的时钟信号从所述第三晶体管的第一电极传送至所述第三晶体管的第二电极，并传送至所述EOA电路的输出端，同时，高电平信号从所述第一晶体管的第一电极传送至所述第一晶体管的第二电极，并传送至所述EOA电路的输出端，使所述EOA电路的输出端输出高电平信号。
  13. 根据权利要求6所述的EOA电路，其特征在于，在第三时段，当低电平的第二扫描信号施加至所述第一晶体管的第三电极和所述第二晶体管的第三电极时，所述第一晶体管导通，所述第二晶体管关断，同时，高电平的第一扫描信号施加至所述第三晶体管的第三电极，第三晶体管导通；
    高电平信号从所述第一晶体管的第一电极传送至所述第一晶体管的第二电极，并传送至所述EOA电路的输出端，同时，低电平的时钟信号通过所述第三晶体管的第一电极传送至所述第三晶体管的第二电极并传送至所述EOA电路的输出端，使所述EOA电路的输出端输出低电平信号。
  14. 根据权利要求1所述的EOA电路，其特征在于，所述EOA电路为CMOS EOA电路。
  15. 一种显示面板，包括设置在边界区域的EOA电路，其特征在于，所述EOA电路为权利要求1-14任一项所述的EOA电路。
  16. 根据权利要求15所述的显示面板，其特征在于，所述显示面板为液晶显示面板。
  17. 根据权利要求15所述的显示面板，其特征在于，所述显示面板为OLED显示面板。
  18. 根据权利要求15所述的显示面板，其特征在于，所述显示面板为AMOLED显示面板。
  19. 一种终端，其特征在于，包括权利要求15-18任一项所述的显示面板。
PCT/CN2018/119554 2018-12-06 2018-12-06 一种eoa电路、显示面板及终端 Ceased WO2020113516A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201880097640.5A CN113168811B (zh) 2018-12-06 2018-12-06 一种eoa电路、显示面板及终端
PCT/CN2018/119554 WO2020113516A1 (zh) 2018-12-06 2018-12-06 一种eoa电路、显示面板及终端
US17/338,963 US11367402B2 (en) 2018-12-06 2021-06-04 EOA circuit, display panel, and terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/119554 WO2020113516A1 (zh) 2018-12-06 2018-12-06 一种eoa电路、显示面板及终端

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/338,963 Continuation US11367402B2 (en) 2018-12-06 2021-06-04 EOA circuit, display panel, and terminal

Publications (1)

Publication Number Publication Date
WO2020113516A1 true WO2020113516A1 (zh) 2020-06-11

Family

ID=70974485

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/119554 Ceased WO2020113516A1 (zh) 2018-12-06 2018-12-06 一种eoa电路、显示面板及终端

Country Status (3)

Country Link
US (1) US11367402B2 (zh)
CN (1) CN113168811B (zh)
WO (1) WO2020113516A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114141182A (zh) * 2020-09-03 2022-03-04 深圳市柔宇科技股份有限公司 Eoa电路、阵列基板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120062608A1 (en) * 2010-09-14 2012-03-15 Dong-Hwi Kim Emission control driver and organic light emitting display using the same
CN104376814A (zh) * 2014-11-25 2015-02-25 上海天马微电子有限公司 一种驱动电路及驱动方法、显示面板、显示装置
CN104851386A (zh) * 2014-02-14 2015-08-19 三星显示有限公司 驱动电路及包括该驱动电路的显示装置
CN107331339A (zh) * 2016-04-29 2017-11-07 上海和辉光电有限公司 显示装置及其控制方法
CN108230982A (zh) * 2018-01-19 2018-06-29 京东方科技集团股份有限公司 像素驱动电路及方法、显示面板
CN108538336A (zh) * 2018-04-19 2018-09-14 上海天马有机发光显示技术有限公司 发光移位寄存器及发光控制方法、驱动电路及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102708795B (zh) * 2012-02-29 2014-11-12 京东方科技集团股份有限公司 阵列基板行驱动单元、阵列基板行驱动电路以及显示装置
US9454935B2 (en) * 2013-11-21 2016-09-27 Lg Display Co., Ltd. Organic light emitting diode display device
KR102330860B1 (ko) * 2015-10-05 2021-11-25 엘지디스플레이 주식회사 유기발광 표시장치와 그 구동방법
KR102373693B1 (ko) * 2015-10-23 2022-03-17 엘지디스플레이 주식회사 스캔 구동부, 표시장치 및 이의 구동방법
KR102408900B1 (ko) * 2015-10-23 2022-06-16 엘지디스플레이 주식회사 스캔 구동부, 표시장치 및 이의 구동방법
KR102597752B1 (ko) * 2015-12-01 2023-11-07 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN105609058B (zh) * 2016-01-04 2018-09-04 京东方科技集团股份有限公司 背光源及显示装置
KR102566782B1 (ko) * 2016-03-09 2023-08-16 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120062608A1 (en) * 2010-09-14 2012-03-15 Dong-Hwi Kim Emission control driver and organic light emitting display using the same
CN104851386A (zh) * 2014-02-14 2015-08-19 三星显示有限公司 驱动电路及包括该驱动电路的显示装置
CN104376814A (zh) * 2014-11-25 2015-02-25 上海天马微电子有限公司 一种驱动电路及驱动方法、显示面板、显示装置
CN107331339A (zh) * 2016-04-29 2017-11-07 上海和辉光电有限公司 显示装置及其控制方法
CN108230982A (zh) * 2018-01-19 2018-06-29 京东方科技集团股份有限公司 像素驱动电路及方法、显示面板
CN108538336A (zh) * 2018-04-19 2018-09-14 上海天马有机发光显示技术有限公司 发光移位寄存器及发光控制方法、驱动电路及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114141182A (zh) * 2020-09-03 2022-03-04 深圳市柔宇科技股份有限公司 Eoa电路、阵列基板及显示装置

Also Published As

Publication number Publication date
CN113168811B (zh) 2022-11-25
CN113168811A (zh) 2021-07-23
US20210312870A1 (en) 2021-10-07
US11367402B2 (en) 2022-06-21

Similar Documents

Publication Publication Date Title
US10593416B2 (en) Shift register, driving method, gate driving circuit and display device
WO2020010852A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
EP4290507B1 (en) Shift register, gate driver circuit, display panel, and electronic device
CN105632446B (zh) Goa单元及其驱动方法、goa电路、显示装置
KR102668997B1 (ko) 표시 장치
CN104900210B (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN103915074B (zh) 一种移位寄存器单元、栅极驱动装置和显示面板
US11307707B2 (en) Scan shift circuit, touch shift circuit, driving method and related apparatus
CN113056783B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN113327537B (zh) 移位寄存器、栅极驱动电路及显示装置
WO2022120576A1 (zh) 显示基板及显示面板
CN107919101B (zh) 像素电路及其驱动方法、显示面板及显示装置
US11710443B2 (en) Shift register, gate drive circuit and display panel
CN113421518B (zh) 移位寄存器单元、驱动方法、驱动电路和显示装置
CN104575433A (zh) Goa复位电路及驱动方法、阵列基板、显示面板和装置
CN107578751A (zh) 数据电压存储电路、驱动方法、液晶显示面板及显示装置
CN107799070A (zh) 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法
CN111610676A (zh) 一种显示面板、其驱动方法及显示装置
WO2019140943A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路
WO2020151439A1 (zh) 像素电路及其驱动方法、显示面板及显示装置
US20200105175A1 (en) Pixel circuit, method for driving method, display panel, and display device
CN113168811B (zh) 一种eoa电路、显示面板及终端
CN113409874A (zh) 移位寄存器、显示面板及显示装置
WO2021258888A1 (zh) 一种移位寄存器、栅极驱动电路及显示面板
CN108511025B (zh) 一种移位寄存器单元、栅极驱动电路及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18942142

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18942142

Country of ref document: EP

Kind code of ref document: A1