WO2020107980A1 - 显示面板及其制作方法、像素发光补偿方法以及显示装置 - Google Patents

显示面板及其制作方法、像素发光补偿方法以及显示装置 Download PDF

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Publication number
WO2020107980A1
WO2020107980A1 PCT/CN2019/103714 CN2019103714W WO2020107980A1 WO 2020107980 A1 WO2020107980 A1 WO 2020107980A1 CN 2019103714 W CN2019103714 W CN 2019103714W WO 2020107980 A1 WO2020107980 A1 WO 2020107980A1
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Prior art keywords
pixel
light
photoelectric
emitting unit
light emitting
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PCT/CN2019/103714
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English (en)
French (fr)
Inventor
闫华杰
黄清雨
李晓虎
刘暾
康亮亮
张娟
焦志强
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/641,072 priority Critical patent/US11257425B2/en
Publication of WO2020107980A1 publication Critical patent/WO2020107980A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/841—Self-supporting sealing arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G09G2360/147—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel
    • G09G2360/148—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel the light being detected by light detection means within each pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display, and in particular to a display panel, a method for manufacturing the same, a pixel light emission compensation method, and a display device.
  • AMOLED active matrix organic light emitting display
  • a display panel includes a plurality of pixel units arranged in an array.
  • Each pixel unit includes: an array substrate including a pixel driving circuit; a pixel defining layer disposed on the first surface of the array substrate away from the substrate, the pixel defining layer having a through hole; a light emitting unit disposed on the In the through hole, the light emitting unit is electrically connected to the output end of the pixel driving circuit, so that the driving current output by the pixel driving circuit drives the light emitting unit to emit light; and the photoelectric converter is configured to receive the Light emitted by the light emitting unit.
  • the pixel defining layer includes a light-transmitting portion that forms a light-transmitting region of the sidewall of the through-hole, wherein the photoelectric converter is configured to pass at least the light-transmitting region The part receives the light emitted by the light emitting unit.
  • the orthographic projection of the photoelectric converter on the array substrate and the orthographic projection of the light-transmitting portion on the array substrate at least partially overlap.
  • the orthographic projection of the photoelectric converter on the array substrate and the orthographic projection of the light emitting unit on the array substrate do not overlap.
  • the display panel further includes a photoelectric reading circuit electrically connected to the photoelectric converter to read the photoelectric signal generated by the photoelectric converter.
  • the photoelectric converter and the photoelectric reading circuit are provided in the array substrate.
  • the pixel driving circuit includes a driving transistor, one of the source or the drain of the driving transistor is electrically connected to the output terminal of the pixel driving circuit, for generating a driving current and providing the driving current to An output end of the pixel driving circuit.
  • the photoelectric reading circuit includes a reading control transistor, one of the source or drain of the reading control transistor is electrically connected to the photoelectric converter, and the other of the source or drain of the reading control transistor One is electrically connected with the signal reading line and is used to control the reading of the photoelectric signal generated by the photoelectric converter through the signal reading line.
  • the drive transistor and the read control transistor are formed by the same process.
  • the photoelectric converter is located between the pixel defining layer and the photoelectric reading circuit in a direction perpendicular to the array substrate.
  • the display panel further includes: an upper cover plate covering the pixel defining layer.
  • the photoelectric converter and the photoelectric reading circuit are provided in the upper cover.
  • the light emitting unit is an organic light emitting diode
  • the organic light emitting diode includes an anode layer, an organic layer, and a cathode layer sequentially stacked on the first surface, the anode layer and the pixel driving circuit
  • the output terminal is electrically connected.
  • the display panel further includes a compensation processor, the compensation processor is electrically connected to the photoelectric reading circuit via a signal reading line, and is configured to: receive a signal from the photoelectric reading circuit The photoelectric signal; and calculating a brightness compensation value based on the photoelectric signal.
  • the compensation processor is electrically connected to the photoelectric reading circuit via a signal reading line, and is configured to: receive a signal from the photoelectric reading circuit The photoelectric signal; and calculating a brightness compensation value based on the photoelectric signal.
  • a method for manufacturing a display panel including a plurality of pixel units arranged in an array.
  • the manufacturing method for each pixel unit includes the following steps: forming an array substrate, the array substrate including a pixel driving circuit, a photoelectric reading circuit, and a photoelectric converter, wherein the photoelectric reading circuit and the photoelectric The converter is electrically connected; a pixel defining layer is formed on the first surface of the array substrate away from the substrate; a through hole is formed in the pixel defining layer; a light emitting unit is formed in the through hole, so that the light emitting unit Electrically connected to the output end of the pixel drive circuit, the photoelectric converter and the light emitting unit are formed such that light emitted by the light emitting unit is received by the photoelectric converter.
  • the step of forming the pixel defining layer further includes: forming a light transmitting portion in the pixel defining layer, the light transmitting portion forming a light transmitting area of the sidewall of the through hole.
  • the photoelectric converter is formed to receive light emitted by the light-emitting unit at least via the light-transmitting portion.
  • the photoelectric converter and the light transmitting portion are formed such that an orthographic projection of the photoelectric converter on the array substrate and an orthographic projection of the light transmitting portion on the array substrate At least partially overlap.
  • the photoelectric converter and the light emitting unit are formed such that the orthographic projection of the photoelectric converter on the array substrate and the orthographic projection of the light emitting unit on the array substrate do not overlap .
  • the pixel driving circuit includes a driving transistor, one of the source or the drain of the driving transistor is electrically connected to the output terminal of the pixel driving circuit, for generating a driving current and providing the driving current to An output end of the pixel driving circuit.
  • the photoelectric reading circuit includes a reading control transistor, one of the source or drain of the reading control transistor is electrically connected to the photoelectric converter, and the other of the source or drain of the reading control transistor One is electrically connected to the signal reading line for controlling the reading of the photoelectric signal generated by the photoelectric converter through the signal reading line, and the driving transistor and the reading control transistor are formed by the same process.
  • the photoelectric converter is formed between the pixel defining layer and the photoelectric reading circuit in a direction perpendicular to the array substrate.
  • the light emitting unit is an organic light emitting diode.
  • the step of forming the light-emitting unit includes: sequentially forming an anode layer, an organic layer, and a cathode layer on the first surface.
  • the anode layer is formed to be electrically connected to the output terminal of the pixel driving circuit.
  • a method for manufacturing a display panel including a plurality of pixel units arranged in an array.
  • the manufacturing method includes the following steps: forming an array substrate, the array substrate including a pixel driving circuit; forming a pixel defining layer on a first surface of the array substrate remote from the substrate; A through hole is formed in the pixel defining layer; a light emitting unit is formed in the through hole so that the light emitting unit is electrically connected to the output end of the pixel driving circuit; an upper cover plate is formed, and the upper cover plate includes a photoelectric readout A circuit and a photoelectric converter, wherein the photoelectric reading circuit is electrically connected to the photoelectric converter; the upper cover plate is aligned with the pixel defining layer so that the light emitted by the light emitting unit is emitted by the Photoelectric converter receiving.
  • the step of forming a pixel defining layer further includes: forming a light transmitting portion in the pixel defining layer, wherein the light transmitting portion forms a light transmitting area of the sidewall of the through hole.
  • the step of mating the upper cover plate with the pixel defining layer causes the photoelectric converter to receive light emitted by the light emitting unit at least via the light-transmitting portion.
  • the step of aligning the upper cover plate with the pixel defining layer makes the orthographic projection of the photoelectric converter on the array substrate and the translucent portion on the array substrate The orthographic projections overlap at least partially.
  • the step of mating the upper cover plate with the pixel defining layer makes the orthographic projection of the photoelectric converter on the array substrate and the orthographic projection of the light emitting unit on the array substrate The projections do not overlap.
  • the step of mating the upper cover plate with the pixel defining layer causes the photoelectric converter to be located between the pixel defining layer and the photoelectric reading in a direction perpendicular to the array substrate Between circuits.
  • the light-emitting unit is an organic light-emitting diode
  • the step of forming the light-emitting unit includes: sequentially forming an anode layer, an organic layer, and a cathode layer on the first surface.
  • the anode layer is formed to be electrically connected to the output end of the pixel driving circuit.
  • a pixel light emission compensation method for the display panel described in the above embodiments includes: providing a first data voltage to the pixel driving circuit through a data driving circuit, so that the pixel driving circuit drives the light emitting unit to emit light at an initial brightness; and receiving the light of the initial brightness through the photoelectric converter And generate a photoelectric signal; read the photoelectric signal to a compensation processor through the photoelectric reading circuit; calculate a brightness compensation value through the compensation processor, and provide the brightness compensation value to the data driving circuit;
  • the pixel driving circuit is supplied with a second data voltage through the data driving circuit, so that the pixel driving circuit drives the light emitting unit to compensate for luminance light emission.
  • a display device including the display panel according to the above-mentioned embodiment.
  • FIG. 1 shows a schematic circuit diagram of a pixel driving circuit for a pixel unit of an AMOLED panel.
  • FIG. 2 shows a structural diagram of a display panel including the pixel driving circuit shown in FIG. 1 and an OLED light emitting unit.
  • FIG. 3 shows a structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 shows a structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 5 shows a circuit structure diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 6 shows a flowchart of a method of manufacturing a display panel according to an embodiment of the present disclosure.
  • FIG. 7 shows a flowchart of a method of manufacturing a display panel according to another embodiment of the present disclosure.
  • FIG. 8 shows a flowchart of a pixel light emission compensation method for a display panel according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the transistor mentioned in the present disclosure may be a thin film transistor (TFT).
  • the transistor can be an N-type or P-type transistor. By changing the level, the two transistors can be used interchangeably.
  • an N-type transistor is taken as an example, which is turned on when the gate inputs a high level, and is turned off when a low level is input.
  • the transistor is described as including a gate, a first electrode, and a second electrode. It should be understood that the first electrode is one of the source electrode and the drain electrode, and the second electrode is the other of the source electrode and the drain electrode.
  • FIG. 1 shows a schematic circuit diagram of a pixel driving circuit 100 for a pixel unit of an AMOLED panel.
  • FIG. 2 shows a structural diagram of a display panel including the pixel driving circuit 100 shown in FIG. 1 and an OLED light emitting unit. For convenience of description, only one pixel unit is shown in FIG. 2.
  • the circuit structure of the pixel driving circuit 100 schematically has a 2T1C structure, including a driving transistor T1, a light emission control transistor T2, and a storage capacitor Cs.
  • the pixel driving circuit 100 is used to drive the OLED light emitting unit.
  • the OLED light-emitting unit is current-driven and requires a stable current to control light emission.
  • the structure in FIG. 2 includes a substrate 110, a buffer layer 120, an interlayer dielectric layer 130, a passivation layer 140, a resin layer 150, and a pixel defining layer 160 that are sequentially stacked, and these layers constitute a display substrate of a display panel.
  • the display panel further includes an upper cover 170, and the upper cover 170 is mated with the display substrate to form a display panel.
  • the driving transistor T1 is formed in the interlayer dielectric layer 130 and is covered by the passivation layer 140. Therefore, the substrate 110, the buffer layer 120, the interlayer dielectric layer 130, the passivation layer 140, and the resin layer 150 may be collectively referred to as an array substrate.
  • the OLED light emitting unit is formed in the pixel defining layer 160 and is electrically connected to the driving transistor T1 in the interlayer dielectric layer 130 through the through hole. It should be understood that in other embodiments, some layers in the structure shown in FIG. 2 may be removed, or new layers are added, which is not limited in the present disclosure.
  • the specific structure of the driving transistor T1 of the pixel driving circuit 100 includes an active layer formed on the buffer layer 120.
  • the active layer includes a channel region 131 and doped regions 132 located on both sides of the channel region 131.
  • a gate insulating layer 133 is formed on the active region, and a gate 134 is formed on the gate insulating layer 133, both of which are covered on the active layer by the interlayer dielectric layer 130.
  • the orthographic projection of the channel region 131 of the active layer on the substrate 110 corresponds to the position of the orthographic projection of the gate electrode 134 on the substrate 110.
  • the interlayer dielectric layer 130 also has a through hole at a position above the doped region 132, and a source electrode 135 and a drain electrode 136 are formed in the through hole.
  • the source electrode 135 and the drain electrode 136 are electrically connected to the doped regions 132 on both sides of the channel region 131, respectively.
  • the driving transistor T1 is exemplified as having a top-gate structure, but it should be understood that in other embodiments, the driving transistor T1 may also have a bottom-gate structure or other suitable structures. None will affect the implementation of the embodiments of the present disclosure. It should also be understood that in other embodiments, the positions of the source electrode 135 and the drain electrode 136 may be interchanged.
  • the specific structure of the OLED light emitting unit includes an anode layer 161, an organic layer 162, and a cathode layer 163 formed on the resin layer 150.
  • a through hole is first formed in the resin layer 150 and the passivation layer 140 at a position above the drain 136, so that the material of the anode layer 161 fills the through hole and is thereby electrically connected to the drain 136.
  • the organic layer 162 is a light-emitting layer, and when the anode layer 161 and the cathode layer 163 are connected to respective voltages, the neutralization of electrons and holes emits light of a specific color.
  • the cathode layer 163 covers the organic layer and covers the pixel defining layer 160.
  • the light emission of OLED can be divided into top emission and bottom emission.
  • top emission the light emitted by the OLED light emitting unit is emitted from the upper cover 170.
  • bottom emission the light emitted by the OLED light emitting unit is emitted from the substrate 110.
  • the scan signal Vscan when a scan line scans a row of pixel cells, the scan signal Vscan is at a high level, and for each pixel cell in the row of pixel cells, T2 is turned on, and the data line writes a data signal Vdata to the storage capacitor Cs .
  • the scanning signal Vscan of the scanning signal line turns to a low level, so that T2 is turned off.
  • the voltage stored on the storage capacitor Cs drives T1 to generate a current to drive the OLED light-emitting unit to ensure that the OLED light-emitting unit continues to emit light (for example, within a frame of display).
  • Vth can be removed from the driving current formula by performing appropriate structure and timing design on the above pixel driving circuit, so that the panel will not cause mura due to the difference of driving transistors, which is internal compensation.
  • This compensation method can only compensate for the Vth factor, and it is difficult to compensate for all factors that cause mura, which has a relatively large limitation.
  • External compensation includes optical external compensation methods (ie Demura method) and electrical external compensation methods.
  • the brightness signal of the panel is extracted through optical CCD photography and the like, and the mura data is identified according to the relevant algorithm, thereby generating Demura data according to the corresponding algorithm, and burning the Demura data Go to the FLASH of the panel to realize the compensation effect.
  • this compensation method is only suitable for initial compensation before the panel leaves the factory, and it is difficult to achieve real-time compensation of the panel.
  • the embodiments of the present disclosure based on the display panel shown in FIG. 2 for example, set the photoelectric converter in the display panel to collect the luminous intensity of the OLED light emitting unit in real time and based The intensity adjustment to the data voltage provided by the pixel realizes a real-time comprehensive compensation scheme.
  • FIG. 3 shows a structural diagram of a display panel according to an embodiment of the present disclosure. For convenience of description, only one pixel unit 30 is shown in FIG. 3.
  • the pixel unit includes an array substrate 300, a pixel defining layer 360, a light emitting unit 360A, and a photoelectric converter 365A.
  • the array substrate 300 includes a substrate 310, a buffer layer 320, an interlayer dielectric layer 330, a passivation layer 340, and a resin layer 350.
  • a pixel driving circuit is formed in the array substrate 300.
  • the driving transistor T1 in the pixel driving circuit is shown in FIG. 3.
  • the driving transistor T1 is formed in the interlayer dielectric layer 330 and is covered by the passivation layer 340.
  • the driving transistor T1 is used to generate a driving current and provide the driving current to the output terminal of the pixel driving circuit. It should be understood that in other embodiments, some layers (such as the buffer layer 320 and the resin layer 350) in the structure shown in the array substrate may be removed, or new layers are added, which is not limited in the present disclosure.
  • the pixel defining layer 360 is disposed on the first surface of the array substrate 300 (ie, the surface away from the substrate 310).
  • the pixel defining layer 360 has a through hole for accommodating the light emitting unit 360A.
  • the pixel defining layer 360 includes a light-transmitting portion 365 that forms a part of the sidewall of the through hole, that is, the light-transmitting region 366 on the sidewall of the through hole.
  • the light-transmitting portion 365 is shown in FIG. 3 as being located on the opposite side of the through hole from the driving transistor T1, and it should be understood that this is only exemplary. In other embodiments, the light-transmitting portion 365 may be located in any orientation of the through hole, and thus may be used to form any area of the side wall of the through hole.
  • the OLED light emitting unit shown in FIG. 3 is provided in the through hole and covers the bottom surface and the side wall of the through hole.
  • the OLED light emitting unit includes an anode layer 361, an organic layer 362, and a cathode layer 363.
  • a through hole is first formed in the array substrate 300 so that the material of the anode layer 361 fills the through hole and thus is connected to the output end of the pixel driving circuit (for example, as shown in FIG. Drain) electrically connected.
  • the organic layer 362 emits light.
  • FIG. 3 is a case of top emission, so the figure also shows an upper cover plate, which covers the pixel defining layer 360, and the light emitted by the OLED light emitting unit is emitted from the upper cover plate.
  • the upper cover plate is shown in FIG. 3 as including a cover plate substrate 372 and an intermediate layer 371. It should be understood that the upper cover plate shown in FIG. 3 is inverted because the structure of the upper cover plate on the display substrate is composed of the array substrate 300 and the pixel defining layer 360 after the fabrication is completed.
  • the photoelectric converter 365A is disposed adjacent to the light-transmitting portion 365 so that the light emitted by the OLED light-emitting unit can at least pass through the light-transmitting portion 365 to reach the photoelectric converter 365A (it should be understood that according to the positional relationship between the photoelectric converter and the OLED light-emitting unit In some embodiments, the light emitted by the OLED light emitting unit can also directly illuminate the photoelectric converter). In some embodiments, the orthographic projection of the photoelectric converter 360A on the array substrate 300 and the orthographic projection of the light transmitting portion 365 on the array substrate 300 at least partially overlap to promote the photoelectric converter 365A to the light from the OLED light emitting unit receive. In some embodiments, the orthographic projection of the photoelectric converter 365A on the array substrate 300 does not overlap with the orthographic projection of the OLED light emitting unit on the array substrate 300, so as to avoid affecting the normal light emission of the OLED display panel.
  • the photoelectric converter 365A is exemplified as a PIN photodiode, and the PIN photodiode is exemplarily placed in the upper cover plate.
  • the photoelectric converter 365A may be implemented as any photoresistor, phototransistor, photodiode, or photocoupler with photoelectric conversion capabilities.
  • the PIN photodiode is shown as being placed on the cathode layer 363 of the OLED light emitting unit. It should be understood that, in other embodiments of the present disclosure, the PIN photodiode may be separated from the OLED light emitting unit and the pixel defining layer 360 by a certain distance.
  • the pixel defining layer 360 having the light transmitting portion 365 of a specific size is shown.
  • the light-transmitting portion 365 is for facilitating the PIN photodiode to receive the light emitted by the OLED light emitting unit, and thus can more flexibly set the position of the PIN photodiode.
  • the size of the light-transmitting portion 365 should be appropriately set.
  • the pixel defining layer 360 may not have the light-transmitting portion 365.
  • the position of the photoelectric converter 365A needs to be properly set so that it can directly receive the light emitted by the OLED light emitting unit, rather than being completely blocked by the pixel defining layer.
  • the display panel further includes a photoelectric reading circuit electrically connected to the PIN photodiode to read the photoelectric signal generated by the PIN photodiode.
  • a photoelectric reading circuit electrically connected to the PIN photodiode to read the photoelectric signal generated by the PIN photodiode.
  • the source 381 of the read control transistor M1 is connected to the PIN photodiode, and the drain 382 is connected to the signal reading line in the display panel, and the photoelectric signal generated by the PIN photodiode is controlled to be read via the signal by changing the level of the gate of M1. Take the line and transfer it to an external circuit for compensation calculation.
  • the photoelectric reading circuit is also located in the upper cover.
  • the specific layered structure of the intermediate layer 371 in the upper cover plate is not exemplarily described.
  • the intermediate layer in the upper cover plate can be realized by any layered structure, as long as the light emitted by the light-emitting unit 360A can be transmitted therethrough, and the circuit structure in which the photoelectric reading circuit can be formed That's it.
  • the photoelectric converter 365A is located between the pixel defining layer 360 and the photoelectric reading circuit in a direction perpendicular to the array substrate 300.
  • FIG. 4 shows a structural diagram of a display panel according to another embodiment of the present disclosure. For ease of explanation, only one pixel unit 40 is shown in FIG. 4.
  • the pixel unit 40 includes an array substrate 400, a pixel defining layer 460, a light emitting unit 460A, and a photoelectric converter 465A.
  • the array substrate 400 includes a substrate 410, a buffer layer 420, an interlayer dielectric layer 430, a passivation layer 440, and a resin layer 450.
  • a pixel driving circuit is formed in the array substrate 400.
  • the driving transistor T1 is formed in the interlayer dielectric layer 430 and is covered by the passivation layer 440.
  • the driving transistor T1 is used to generate a driving current and provide the driving current to the output terminal of the pixel driving circuit. It should be understood that in other embodiments, some layers (such as the buffer layer 420 and the resin layer 450) in the structure shown in the array substrate may be removed, or new layers are added, which is not limited in the present disclosure.
  • the pixel defining layer 460 is disposed on the first surface of the array substrate (ie, the surface away from the substrate 410).
  • the pixel defining layer 460 has a through hole for accommodating the light emitting unit 460A.
  • the pixel defining layer 460 includes a light-transmitting portion 465 that forms a part of the sidewall of the through hole, that is, the light-transmitting region 466 on the sidewall of the through hole.
  • the light-transmitting portion 465 is shown in FIG. 4 as being located on the opposite side of the through-hole from the driving transistor T1, and it should be understood that this is only exemplary. In other embodiments, the light-transmitting portion 465 may have any orientation of the through hole, and thus may be used to form any area of the side wall of the through hole.
  • the OLED light emitting unit shown in FIG. 4 is provided in the through hole, and covers the bottom surface and the side wall of the through hole.
  • the OLED light emitting unit includes an anode layer 461, an organic layer 462, and a cathode layer 463.
  • a through hole is first formed in the array substrate 400, so that the material of the anode layer 461 fills the through hole, and thus is connected to the output end of the pixel driving circuit (for example, as shown in FIG. Drain) electrically connected.
  • the organic layer 462 emits light.
  • the embodiment shown in FIG. 4 is a bottom emission case, so the upper cover plate structure in FIG. 3 is omitted in FIG. 4.
  • the light emitted by the OLED light emitting unit is emitted from the substrate 410.
  • the photoelectric converter 465A is disposed adjacent to the light-transmitting portion 465 so that the light emitted by the OLED light-emitting unit can at least pass through the light-transmitting portion 465 to reach the photoelectric converter 465A (it should be understood that according to the positional relationship between the photoelectric converter and the OLED light-emitting unit In some embodiments, the light emitted by the OLED light emitting unit can also directly illuminate the photoelectric converter). In some embodiments, the orthographic projection of the photoelectric converter 465A on the array substrate 400 and the orthographic projection of the light transmitting portion 465 on the array substrate at least partially overlap to facilitate the photoelectric converter 465A to receive light from the OLED light emitting unit . In some embodiments, the orthographic projection of the photoelectric converter 465A on the array substrate 400 does not overlap with the orthographic projection of the OLED light emitting unit on the array substrate, so as to avoid affecting the normal light emission of the OLED display panel.
  • the photoelectric converter 465A is exemplified as a PIN photodiode, and the PIN photodiode is exemplarily placed in the array substrate 400.
  • the PIN photodiode is formed in the passivation layer 440 and the resin layer 450.
  • the bottom-emitting OLED shown in FIG. 4 emits light
  • the PIN photodiode placed in the array substrate 400 is irradiated with light to generate a photoelectric signal.
  • a pixel defining layer 460 having a light transmission part 465 of a specific size is shown.
  • the light-transmitting portion 465 is for facilitating the PIN photodiode to receive the light emitted by the OLED light emitting unit, so that the position of the PIN photodiode can be set more flexibly.
  • the size of the light transmitting portion 465 should be appropriately set.
  • the pixel defining layer 460 may not have the light-transmitting portion 465. In these embodiments, the position of the photoelectric converter 465A needs to be properly set so that it can directly receive the light emitted by the OLED light emitting unit, rather than being completely blocked by the pixel defining layer 460.
  • the display panel further includes a photoelectric reading circuit electrically connected to the PIN photodiode to read the photoelectric signal generated by the PIN photodiode.
  • a photoelectric reading circuit electrically connected to the PIN photodiode to read the photoelectric signal generated by the PIN photodiode.
  • the photoelectric signal generated by the PIN photodiode is controlled to be read via the signal by changing the level of the gate of M1. Take the line and transfer it to an external circuit for compensation calculation.
  • the photoelectric reading circuit is also formed in the array substrate 400.
  • the read control transistor M1 and the drive transistor T1 may have the same or similar structure, and both may be formed simultaneously by the same process, thereby simplifying the process of forming the display panel 400.
  • the photoelectric converter is located between the pixel defining layer 460 and the photoelectric reading circuit in a direction perpendicular to the array substrate.
  • FIG. 5 shows a circuit structure diagram of a display panel 500 according to an embodiment of the present disclosure.
  • the display panel 500 includes an effective display area 510 and a non-display area 520.
  • the effective display area includes a plurality of pixel units 530 arranged in an array.
  • Each pixel unit 530 in the display panel 500 may have the structure of the pixel unit shown in FIG. 3 or FIG. 4.
  • the non-display area 520 includes a compensation processor 540 and a data driving circuit 550. It should be understood that, in other embodiments of the present disclosure, the compensation processor 540 may also be located outside the display panel 500.
  • Each pixel unit 530 includes a pixel driving circuit 531 and a photoelectric reading circuit 532, a light emitting unit 533, and a photoelectric converter 534.
  • the pixel unit 530 further includes a plurality of gate lines GATE (eg, GATE1, GATE2, ...), a plurality of data lines DATA (eg, DATA1, DATA2, ...), and a plurality of signal reading lines READ (eg, READ1 , READ2, ...) and multiple read control lines CON (for example, CON1, CON2, ).
  • the pixel driving circuit 531 includes a driving transistor T1, an emission control transistor T2, and a storage capacitor Cs.
  • Each pixel driving circuit 531 receives a data signal from the data driving circuit 550 via the data line DATA under the control of the corresponding gate line GATE, and generates a driving current related to the level of the data signal DATA to drive the light emitting unit 533 (eg, OLED The light emitting unit) emits light.
  • the light emitting unit 533 eg, OLED The light emitting unit
  • the photoelectric reading circuit 532 includes a reading control transistor M1 for receiving a photoelectric signal from a photo sensor 534 (for example, a PIN photodiode) under the control of the reading control line CON, and passing the received photoelectric signal via the reading signal line READ Transfer to the compensation processor 540.
  • a photo sensor 534 for example, a PIN photodiode
  • the photoelectric signal received by the photosensor 534 is caused by the light emitted by the light emitting unit 533.
  • the compensation processor 540 After receiving the photoelectric signal, the compensation processor 540 calculates a compensated brightness value based on the photoelectric signal. Then, the compensation processor 540 sends the calculated compensation brightness value to the data driving circuit 550, so that it changes the light-emission brightness of the corresponding pixel unit by changing the data voltage supplied to the data line DATA, thereby implementing pixel-specific comprehensive compensation.
  • FIG. 6 shows a flowchart of a method 600 for manufacturing a display panel according to an embodiment of the present disclosure.
  • the method 600 can be used to fabricate the display panel shown in FIG. 3, so the explanations and descriptions made above with reference to FIG. 3 are equally applicable here, and will not be repeated here.
  • step S610 an array substrate is formed.
  • the array substrate includes a pixel driving circuit.
  • step S620 a pixel defining layer is formed on the first surface of the array substrate away from the substrate.
  • step S620 further includes: forming a light transmitting portion in the pixel defining layer.
  • step S630 a through hole is formed in the pixel defining layer.
  • the pixel defining layer has a light-transmitting portion, so that the through-hole formed in step S630 makes the light-transmitting portion constitute a part of the side wall of the through-hole, that is, the light-transmitting region on the side wall.
  • step S640 a light emitting unit is formed in the through hole so that the light emitting unit is electrically connected to the output terminal of the pixel driving circuit.
  • step S640 includes sequentially forming an anode layer, an organic layer, and a cathode layer on the first surface of the array substrate away from the substrate.
  • the anode layer is formed to be electrically connected to the output end of the pixel driving circuit.
  • step S650 an upper cover is formed.
  • the upper cover plate includes a photoelectric reading circuit and a photoelectric converter, and the photoelectric reading circuit is electrically connected to the photoelectric converter.
  • step S660 the upper cover plate is aligned with the pixel defining layer so that the light emitted by the light emitting unit can be received by the photoelectric converter.
  • the pixel defining layer has a light-transmitting portion, so that step S660 enables the photoelectric converter to receive at least the light emitted by the light-emitting unit via the light-transmitting portion.
  • the orthographic projection of the photoelectric converter on the array substrate and the orthographic projection of the light transmitting portion on the array substrate at least partially overlap, the orthographic projection of the photoelectric converter on the array substrate and the light emitting unit
  • the orthographic projection on the array substrate does not overlap, and the photoelectric converter is located between the pixel defining layer and the photoelectric reading circuit in a direction perpendicular to the array substrate.
  • FIG. 7 shows a flowchart of a method 700 for manufacturing a display panel according to an embodiment of the present disclosure.
  • the method 700 can be used to fabricate the display panel shown in FIG. 4, so the explanations and explanations made above with reference to FIG. 4 are equally applicable here and will not be repeated here.
  • step S710 an array substrate is formed.
  • the array substrate includes a pixel driving circuit, a photoelectric reading circuit and a photoelectric converter, and the photoelectric reading circuit is electrically connected to the photoelectric converter.
  • the pixel driving circuit includes a driving transistor, and the photoelectric reading circuit includes a reading control transistor.
  • the driving transistor and the read control transistor are formed by the same process.
  • step S720 a pixel defining layer is formed on the first surface of the array substrate away from the substrate.
  • step S720 further includes: forming a light transmitting portion in the pixel defining layer.
  • step S730 a through hole is formed in the pixel defining layer.
  • the pixel defining layer has a light-transmitting portion, so that the through-hole formed in step S730 makes the light-transmitting portion constitute a part of the sidewall of the through-hole, that is, the light-transmitting region on the sidewall.
  • step S740 a light emitting unit is formed in the through hole so that the light emitting unit is electrically connected to the output terminal of the pixel driving circuit.
  • the photoelectric converter and the light emitting unit are formed so that light emitted by the light emitting unit can be received by the photoelectric converter.
  • the pixel defining layer has a light-transmitting portion, so that step S740 enables the photoelectric converter to receive at least the light emitted by the light-emitting unit via the light-transmitting portion.
  • step S740 includes: sequentially forming an anode layer, an organic layer, and a cathode layer on the first surface of the array substrate away from the substrate. Among them, the anode layer is formed to be electrically connected to the output end of the pixel driving circuit.
  • the photoelectric converter, the light transmitting portion, and the light emitting unit are formed such that the orthographic projection of the photoelectric converter on the array substrate and the orthographic projection of the light transmitting portion on the array substrate at least partially overlap, The orthographic projection on the array substrate and the orthographic projection of the light emitting unit on the array substrate do not overlap, and the photoelectric converter is located between the pixel defining layer and the photoelectric reading circuit in a direction perpendicular to the array substrate.
  • FIG. 8 shows a flowchart of a pixel emission compensation method 800 for a display panel according to an embodiment of the present disclosure.
  • the method 800 may be implemented by the display panel shown in FIG. 5, so the explanations and descriptions made above with reference to FIG. 5 are also adaptively applied here, and will not be repeated here.
  • step S810 the pixel driving circuit (eg, pixel driving circuit 531) is supplied with the first data voltage through the data driving circuit (eg, data driving circuit 550), so that the pixel driving circuit drives the light emitting unit (eg, light emitting unit 533) to initialize Brightness glows.
  • the data driving circuit eg, data driving circuit 550
  • step S820 the light of the initial brightness is received by the photoelectric converter (for example, the photoelectric converter 534), and a photoelectric signal is generated.
  • the photoelectric converter for example, the photoelectric converter 534.
  • step S830 the photoelectric signal is read to the compensation processor (eg, compensation processor 540) by the photoelectric reading circuit (eg, photoelectric reading circuit 532).
  • the compensation processor eg, compensation processor 540
  • the photoelectric reading circuit eg, photoelectric reading circuit 5302.
  • step S840 the brightness compensation value is calculated by the compensation processor, and the brightness compensation value is provided to the data driving circuit.
  • step S850 the pixel driving circuit is supplied with the second data voltage through the data driving circuit, so that the pixel driving circuit drives the light emitting unit to compensate for luminance light emission.
  • the display device 900 may include the display panel 910 according to the above-described embodiments of the present disclosure.
  • the display panel 910 may be implemented by the display panels shown in FIGS. 3, 4, and 5.
  • the display device 900 according to the embodiment of the present disclosure may be any product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

本公开提供了一种显示面板及其制作方法以及像素发光补偿方法和显示装置。所述显示面板包括阵列布置的多个像素单元，每个像素单元包括：阵列基板，包括像素驱动电路；像素界定层，设置在所述阵列基板的远离衬底的第一表面上，所述像素界定层中具有通孔；发光单元，设置在所述通孔中，所述发光单元与所述像素驱动电路的输出端电连接，以使得所述像素驱动电路输出的驱动电流驱动所述发光单元发光；以及光电转换器，被配置为接收所述发光单元发出的光。

Description

显示面板及其制作方法、像素发光补偿方法以及显示装置
相关申请的交叉引用
本申请要求于2018年11月30日递交的中国专利申请CN201811453407.4的优先权，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示领域，具体地涉及一种显示面板及其制作方法以及像素发光补偿方法和显示装置。
背景技术
有源矩阵有机发光显示器(AMOLED)的显示由于IR-Drop、阈值电压偏移、OLED材料本身的劣化等因素会造成亮度和颜色随着使用时间变长而发生偏差，因此需要对AMOLED的亮度和颜色进行补偿。
发明内容
根据本公开的一个方面，提出了一种显示面板。所述显示面板包括阵列布置的多个像素单元。每个像素单元包括：阵列基板，包括像素驱动电路；像素界定层，设置在所述阵列基板的远离衬底的第一表面上，所述像素界定层中具有通孔；发光单元，设置在所述通孔中，所述发光单元与所述像素驱动电路的输出端电连接，以使得所述像素驱动电路输出的驱动电流驱动所述发光单元发光；以及光电转换器，被配置为接收所述发光单元发出的光。
在一些实施例中，所述像素界定层包括透光部，所述透光部形成所述通孔的侧壁的透光区域，其中，所述光电转换器被配置为至少经由所述透光部接收所述发光单元发出的光。
在一些实施例中，所述光电转换器在所述阵列基板上的正投影与所述透光部在所述阵列基板上的正投影至少部分地重叠。
在一些实施例中，所述光电转换器在所述阵列基板上的正投影与所述发光单元在所述阵列基板上的正投影不重叠。
在一些实施例中，所述显示面板还包括：光电读取电路，与所述光电转换器电连接，以读取光电转换器产生的光电信号。
在一些实施例中，所述光电转换器和所述光电读取电路设置在所述阵列基板中。
在一些实施例中，所述像素驱动电路包括驱动晶体管，所述驱动晶体管的源极或漏极之一与所述像素驱动电路的输出端电连接，用于产生驱动电流并将驱动电流提供到所述像素驱动电路的输出端。所述光电读取电路包括读取控制晶体管，所述读取控制晶体管的源极或漏极之一与所述光电转换器电连接，所述读取控制晶体管的源极或漏极中的另一个与信号读取线电连接，用于控制通过信号读取线读取光电转换器产生的光电信号。所述驱动晶体管和所述读取控制晶体管是通过相同工艺形成的。
在一些实施例中，所述光电转换器在垂直于所述阵列基板的方向上位于所述像素界定层与所述光电读取电路之间。
在一些实施例中，所述显示面板还包括：上盖板，覆盖所述像素界定层。所述光电转换器和所述光电读取电路设置在所述上盖板中。
在一些实施例中，所述发光单元为有机发光二极管，所述有机发光二极管包括依次堆叠在所述第一表面上的阳极层、有机层和阴极层，所述阳极层与所述像素驱动电路的输出端电连接。
在一些实施例中，所述显示面板还包括补偿处理器，所述补偿处理器经由信号读取线与所述光电读取电路电连接，并且被配置为：从所述光电读取电路接收所述光电信号；以及基于所述光电信号计算亮度补偿值。
根据本公开的另一方面，提出了一种显示面板的制作方法，所述显示面板包括阵列布置的多个像素单元。对于每个像素单元所述制作方法所述方法包括以下步骤：形成阵列基板，所述阵列基板包括像素驱动电路、光电读取电路和光电转换器，其中，所述光电读取电路与所述光电转换器电连接；在所述阵列基板的远离衬底的第一表面上形成像素界定层；在所述像素界定层中形成通孔；在所述通孔中形成发光 单元，使得所述发光单元与所述像素驱动电路的输出端电连接，所述光电转换器和所述发光单元被形成为使得所述发光单元发出的光被所述光电转换器接收。
在一些实施例中，形成像素界定层的步骤还包括：在所述像素界定层中形成透光部，所述透光部形成所述通孔的侧壁的透光区域。
在一些实施例中，所述光电转换器被形成为至少经由所述透光部接收所述发光单元发出的光。
在一些实施例中，所述光电转换器和所述透光部被形成为使得所述光电转换器在所述阵列基板上的正投影与所述透光部在所述阵列基板上的正投影至少部分地重叠。
在一些实施例中，所述光电转换器和所述发光单元被形成为使得所述光电转换器在所述阵列基板上的正投影与所述发光单元在所述阵列基板上的正投影不重叠。
在一些实施例中，所述像素驱动电路包括驱动晶体管，所述驱动晶体管的源极或漏极之一与所述像素驱动电路的输出端电连接，用于产生驱动电流并将驱动电流提供到所述像素驱动电路的输出端。所述光电读取电路包括读取控制晶体管，所述读取控制晶体管的源极或漏极之一与所述光电转换器电连接，所述读取控制晶体管的源极或漏极中的另一个与信号读取线电连接，用于控制将通过信号读取线读取光电转换器产生的光电信号，所述驱动晶体管和所述读取控制晶体管是通过相同工艺形成的。
在一些实施例中，所述光电转换器被形成为在垂直于所述阵列基板的方向上位于所述像素界定层与所述光电读取电路之间。
在一些实施例中，所述发光单元为有机发光二极管。形成所述发光单元的步骤包括：在所述第一表面上依次形成阳极层、有机层和阴极层。所述阳极层被形成为与所述像素驱动电路的输出端电连接。
根据本公开的又一方面，提供了一种显示面板的制作方法，所述显示面板包括阵列布置的多个像素单元。对于每个像素单元所述制作方法，所述方法包括以下步骤：形成阵列基板，所述阵列基板包括像素驱动电路；在所述阵列基板的远离衬底的第一表面上形成像素界定层；在所述像素界定层中形成通孔；在所述通孔中形成 发光单元，使得所述发光单元与所述像素驱动电路的输出端电连接；形成上盖板，所述上盖板包括光电读取电路和光电转换器，其中，所述光电读取电路与所述光电转换器电连接；将所述上盖板与所述像素界定层对合，使得所述发光单元发出的光被所述光电转换器接收。
在一些实施例中，形成像素界定层的步骤还包括：在所述像素界定层中形成透光部，其中，所述透光部形成所述通孔的侧壁的透光区域。
在一些实施例中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器至少经由所述透光部接收所述发光单元发出的光。
在一些实施例中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器在所述阵列基板上的正投影与所述透光部在所述阵列基板上的正投影至少部分地重叠。
在一些实施例中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器在所述阵列基板上的正投影与所述发光单元在所述阵列基板上的正投影不重叠。
在一些实施例中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器在垂直于所述阵列基板的方向上位于所述像素界定层与所述光电读取电路之间。
在一些实施例中，所述发光单元为有机发光二极管，形成所述发光单元的步骤包括：在所述第一表面上依次形成阳极层、有机层和阴极层。其中，所述阳极层被形成为与所述像素驱动电路的输出端电连接。
根据本公开的又一方面，提供了一种针对上述实施例所述的显示面板的像素发光补偿方法。所述方法包括：通过数据驱动电路向所述像素驱动电路提供第一数据电压，使得所述像素驱动电路驱动所述发光单元以初始亮度发光；通过所述光电转换器接收所述初始亮度的光，并产生光电信号；通过所述光电读取电路将所述光电信号读取到补偿处理器；通过所述补偿处理器计算亮度补偿值，并向所述数据驱动电路提供所述亮度补偿值；通过所述数据驱动电路向所述像素驱动电路提供第二数据电压，使得所述像素驱动电路驱动所述发光单元以补偿亮度发光。
根据本公开的又一方面，提供了一种显示装置，包括根据上述实施例所述的显示面板。
附图说明
图1示出了针对AMOLED面板的像素单元的像素驱动电路的示意电路图。
图2示出了包括图1所示的像素驱动电路和OLED发光单元的显示面板的结构图。
图3示出了根据本公开实施例的显示面板的结构图。
图4示出了根据本公开另一实施例的显示面板的结构图。
图5示出了根据本公开实施例的显示面板的电路结构图。
图6示出了根据本公开实施例的显示面板的制作方法的流程图。
图7示出了根据本公开另一实施例的显示面板的制作方法的流程图。
图8示出了针对根据本公开实施例的显示面板的像素发光补偿方法的流程图。
图9示出了根据本公开实施例的显示装置的示意方框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
在本文中，本公开中所提及的晶体管可以是薄膜晶体管(TFT)。晶体管可以为N型或P型晶体管，通过改变电平的高低，两种晶体管是可以互换使用。在下文中以N型晶体管为例进行描述，其在栅极输入高电平时导通，输入低电平时截止。下文将晶体管描述为包括栅极、第一极和第二极，应该理解的是，第一极是源极和漏 极之一，第二极是源极和漏极中的另一个。
以下参照附图描述本公开的各实施例。
图1示出了针对AMOLED面板的像素单元的像素驱动电路100的示意电路图。图2示出了包括图1所示的像素驱动电路100和OLED发光单元的显示面板的结构图，为了便于说明，图2中只示出了一个像素单元。
如图1所示，像素驱动电路100的电路结构示意性地具有2T1C结构，包括驱动晶体管T1、发光控制晶体管T2和存储电容器Cs。像素驱动电路100用于对OLED发光单元进行驱动。OLED发光单元属于电流驱动，需要稳定的电流来控制发光。
如图2所示，显示面板的层叠结构中只示意性地示出了像素驱动电路100中的驱动晶体管T1(图中的矩形虚线框)和OLED发光单元(图中的椭圆虚线框)。具体地，图2中的结构包括依次堆叠的衬底110、缓冲层120、层间介质层130、钝化层140、树脂层150和像素界定层160，这些层构成显示面板的显示基板。此外，显示面板还包括上盖板170，上盖板170与显示基板对合，形成显示面板。驱动晶体管T1形成在层间介质层130中，并被钝化层140覆盖。因此，可以将衬底110、缓冲层120、层间介质层130、钝化层140和树脂层150统称为阵列基板。OLED发光单元形成在像素界定层160中，并通过通孔与层间介质层130中的驱动晶体管T1电连接。应该理解的是，在其他实施例中，可以去除图2中所示结构中的某些层，或增加新的层，本公开对此不加以限制。
像素驱动电路100的驱动晶体管T1的具体结构包括形成在缓冲层120上的有源层，有源层包括沟道区131和位于沟道区131两侧的掺杂区132。在有源区上形成有栅极绝缘层133，在栅极绝缘层133上形成有栅极134，二者都被层间介质层130覆盖于有源层上。有源层的沟道区131在衬底110上的正投影与栅极134在衬底110上的正投影的位置相对应。层间介质层130还在掺杂区132上方的位置处具有通孔，在通孔中形成有源极135和漏极136。源极135和漏极136分别与沟道区131两侧的掺杂区132电连接。如图1所示，在本实施例中，驱动晶体管T1被示例为具有顶栅结构，但应该理解的是，在其他实施例中，驱动晶体管T1也可以具有底栅结构或 其他适当的结构，都不会影响本公开实施例的实现。还应理解的是，在其他实施例中，源极135和漏极136的位置可以互换。
OLED发光单元的具体结构包括形成于树脂层150上的阳极层161、有机层162和阴极层163。在制作阳极层161之前，首先在树脂层150和钝化层140中位于漏极136上方的位置处形成通孔，使得阳极层161的材料填充通孔，并由此与漏极136电连接。有机层162是发光层，其在阳极层161和阴极层163分别接入相应电压时会利用电子与空穴的中和发出特定颜色的光。阴极层163覆盖有机层并覆盖像素界定层160。OLED的发光可以分为顶发射和底发射两种情况。在顶发射情况中，OLED发光单元发出的光从上盖板170中射出。在底发射情况中，OLED发光单元发出的光从衬底110中射出。应该理解的是，为了使光能够顺利射出，需要对光路径上的层的材料或结构进行适应性改动，本公开在这里不进行具体说明。
在图1中，当扫描线扫描某一行像素单元时，扫描信号Vscan为高电平，针对该行像素单元中的每一个像素单元，T2导通，数据线向存储电容器Cs写入数据信号Vdata。当该行扫描结束后，扫描信号线的扫描信号Vscan转为低电平，使得T2截止。此时，存储在存储电容器Cs上的电压驱动T1，使其产生电流来驱动OLED发光单元，保证OLED发光单元持续发光(例如在一帧的显示内)。OLED发光单元的发光电流的公式为Ids＝K(Vdata-Vth) 2，其中，K为与工艺、设计和材料相关的参数，Vth为T1的阈值电压。可见Ids的大小至少受到K、Vdata和Vth这三个参量的影响。具体地，当OLED材料本身发生劣化时，参数K会发生变化；由于像素单元离数据线的距离不同，其所接收的数据信号会受到不同的电压降，这将影响每个像素单元的Vdata；各像素单元的驱动晶体管的阈值可能是不均匀分布的或可能发生漂移，这将导致各像素单元的驱动晶体管具有不同的Vth。这些因素都将导致显示面板的亮度不均匀(即mura)。因此，需要进行设计对这种不均匀的现象进行亮度补偿。
一般地，补偿分为内部补偿和外部补偿。例如，在相关技术中，可以通过对上述像素驱动电路进行适当的结构和时序设计来在驱动电流公式中去除Vth，以使得面板不会因驱动晶体管的差异而造成mura，此为内部补偿。这一补偿方式只能针对 Vth因素进行补偿，而难以针对所有导致mura的因素进行补偿，具有较大的局限性。
外部补偿包括光学外部补偿方法(即Demura方法)和电学外部补偿方法。在一种相关技术的光学外部补偿方法中，通过光学CCD照相等方法将面板的亮度信号抽取出来，并根据相关算法识别出mura数据，从而根据相应的算法产生Demura数据，并将Demura数据烧录到面板的FLASH ROM中，以实现补偿效果。然而，这一补偿方式只适合用于面板出厂前的初始补偿，很难实现面板的实时补偿。
为了至少部分地解决现有补偿方案中的问题，本公开实施例在例如图2所示的显示面板的基础上，通过在显示面板中设置光电转换器实时采集OLED发光单元的发光强度并基于检测到的强度调节为像素提供的数据电压，实现了一种实时的全面补偿方案。
具体地，本公开提供了一种显示面板，该显示面板包括阵列布置的多个像素单元。图3示出了根据本公开的一个实施例的显示面板的结构图，为了便于说明，图3中只示出了一个像素单元30。
如图3所示，像素单元中包括阵列基板300、像素界定层360、发光单元360A和光电转换器365A。
阵列基板300包括衬底310、缓冲层320、层间介质层330、钝化层340和树脂层350。阵列基板300中形成有像素驱动电路，为了便于描述，图3中只示出了像素驱动电路中的驱动晶体管T1，驱动晶体管T1形成在层间介质层330中，并被钝化层340覆盖。驱动晶体管T1用于产生驱动电流并将驱动电流提供到像素驱动电路的输出端。应该理解的是，在其他实施例中，可以去除阵列基板中所示结构中的某些层(例如缓冲层320和树脂层350)，或增加新的层，本公开对此不加以限制。
像素界定层360设置在所述阵列基板300的第一表面(即远离衬底310的表面)上。像素界定层360中具有通孔，用于容纳发光单元360A。在本公开的一些实施例中，像素界定层360包括透光部365，透光部365形成通孔的侧壁的一部分，即通孔侧壁上的透光区域366。图3中将透光部365示为与驱动晶体管T1位于通孔的相对侧，应该理解的是，这仅是示例性的。在其他实施例中，透光部365可以位于通 孔的任何方位，从而可以用于形成通孔的侧壁的任何区域。
作为发光单元360A的示例，图3所示的OLED发光单元设置在通孔中，并且覆盖所述通孔的底面和侧壁。具体地，OLED发光单元包括阳极层361、有机层362和阴极层363。在制作阳极层361之前，首先在阵列基板300中形成通孔，使得阳极层361的材料填充通孔，并由此与像素驱动电路的输出端(例如，如图3所示与驱动晶体管T1的漏极)电连接。从而，在来自驱动晶体管T1的驱动电流的驱动下，有机层362发光。图3中示出的实施例为顶发射情况，因此图中还示出了上盖板，该上盖板覆盖像素界定层360，OLED发光单元发出的光从上盖板中射出。上盖板在图3中被示为包括盖板衬底372和中间层371。应该理解的是，由于上盖板在其上的结构制作完成后与由阵列基板300和像素界定层360组成的显示基板对合，因此，图3中示出的上盖板是倒置的。
光电转换器365A邻近透光部365设置，使得OLED发光单元发出的光至少能够穿过透光部365到达光电转换器365A(应该理解的是，根据光电转换器与OLED发光单元之间的位置关系，在一些实施例中，OLED发光单元发出的光也能直接照射到光电转换器)。在一些实施例中，光电转换器360A在阵列基板300上的正投影与透光部365在阵列基板300上的正投影至少部分地重叠，以促进光电转换器365A对来自OLED发光单元的光的接收。在一些实施例中，光电转换器365A在阵列基板300上的正投影还与OLED发光单元在阵列基板300上的正投影不重叠，从而避免对OLED显示面板的正常发光造成影响。
在图3中，将光电转换器365A示例为PIN光电二极管，并且将PIN光电二极管示例性地置于上盖板中。在图3所示的顶发射OLED发光单元发光时，会有光照射到置于上盖板中的PIN光电二极管，使其产生光电信号。应该理解的是，在本公开的其他实施例中，光电转换器365A可以实现为具有光电转换能力的任何光敏电阻、光电三极管、光电二极管或者光电耦合器件。
在图3的实施例中，将PIN光电二极管示为置于OLED发光单元的阴极层363上。应该理解的是，在本公开的其他实施例中，PIN光电二极管可以与OLED发光单元以及像素界定层360间隔开一定的距离。
在图3的实施例中，示出了具有特定尺寸的透光部365的像素界定层360。应该理解的是，透光部365是为了便于PIN光电二极管接收OLED发光单元发出的光，并从而能够更加灵活地设置PIN光电二极管的位置。然而，如果透光部365的尺寸过大则会对显示面板的正常显示造成影响(例如，不同像素之间的漏光造成混像)，因此，应该适当地设置透光部365的大小。在本公开的另一些实施例中，像素界定层360中可以不具有透光部365。在这些实施例中，需要适当地设置光电转换器365A的位置，使其能够直接接收到OLED发光单元发出的光，而不是被像素界定层完全阻挡。
在一些实施例中，显示面板还包括光电读取电路，光电读取电路与PIN光电二极管电连接，以读取PIN光电二极管产生的光电信号。为了便于说明，在图3的实施例中只示出了光电读取电路中的读取控制晶体管M1。读取控制晶体管M1的源极381连接到PIN光电二极管，漏极382连接显示面板中的信号读取线，通过改变M1的栅极的电平来控制将PIN光电二极管产生的光电信号经由信号读取线传递到外部电路进行补偿计算。图3中，光电读取电路同样位于上盖板中。
在图3所述的实施例中，为了简明，没有对上盖板中的中间层371的具体分层结构进行示例性说明。本领域技术人员应该理解的是，可以通过任意的分层结构来实现上盖板中的中间层，只要能够允许发光单元360A发出的光从中透射，并且能够在其中形成光电读取电路的电路结构即可。此外，在上盖板的盖板衬底372和中间层371之间还可以具有其他层结构，本公开对此不再赘述。
在一些实施例中，光电转换器365A在垂直于阵列基板300的方向上位于像素界定层360与光电读取电路之间。
图4示出了根据本公开另一实施例的显示面板的结构图，为了便于说明，图4中只示出了一个像素单元40。
如图4所示，像素单元40包括阵列基板400、像素界定层460、发光单元460A和光电转换器465A。
阵列基板400包括衬底410、缓冲层420、层间介质层430、钝化层440和树脂层450。阵列基板400中形成有像素驱动电路，为了便于描述，图4中只示出了像 素驱动电路中的驱动晶体管T1，驱动晶体管T1形成在层间介质层430中，并被钝化层440覆盖。驱动晶体管T1用于产生驱动电流并将驱动电流提供到像素驱动电路的输出端。应该理解的是，在其他实施例中，可以去除阵列基板中所示结构中的某些层(例如缓冲层420和树脂层450)，或增加新的层，本公开对此不加以限制。
像素界定层460设置在所述阵列基板的第一表面(即远离衬底410的表面)上。像素界定层460中具有通孔，用于容纳发光单元460A。在本公开的一些实施例中，像素界定层460包括透光部465，透光部465形成通孔的侧壁的一部分，即通孔侧壁上的透光区域466。图4中将透光部465示为与驱动晶体管T1位于通孔的相对侧，应该理解的是，这仅是示例性的。在其他实施例中，透光部465可以通孔的任何方位，从而可以用于形成通孔的侧壁的任何区域。
作为发光单元460A的示例，图4所示的OLED发光单元设置在通孔中，并且覆盖所述通孔的底面和侧壁。具体地，OLED发光单元包括阳极层461、有机层462和阴极层463。在制作阳极层461之前，首先在阵列基板400中形成通孔，使得阳极层461的材料填充通孔，并由此与像素驱动电路的输出端(例如，如图4所示与驱动晶体管T1的漏极)电连接。从而，在来自驱动晶体管T1的驱动电流的驱动下，有机层462发光。图4中示出的实施例为底发射情况，因此图4中省略了图3中的上盖板结构。OLED发光单元发出的光从衬底410射出。
光电转换器465A邻近透光部465设置，使得OLED发光单元发出的光至少能够穿过透光部465到达光电转换器465A(应该理解的是，根据光电转换器与OLED发光单元之间的位置关系，在一些实施例中，OLED发光单元发出的光也能直接照射到光电转换器)。在一些实施例中，光电转换器465A在阵列基板400上的正投影与透光部465在阵列基板上的正投影至少部分地重叠，以促进光电转换器465A对来自OLED发光单元的光的接收。在一些实施例中，光电转换器465A在阵列基板400上的正投影还与OLED发光单元在阵列基板上的正投影不重叠，从而避免对OLED显示面板的正常发光造成影响。
在图4中，将光电转换器465A示例为PIN光电二极管，并且将PIN光电二极管示例性地置于阵列基板400中。图4中PIN光电二极管形成在钝化层440和树脂 层450中。在图4所示的底发射OLED发光时，会有光照射到置于阵列基板400中的PIN光电二极管，使其产生光电信号。
在图4的实施例中，示出了具有特定尺寸的透光部465的像素界定层460。应该理解的是，透光部465是为了便于PIN光电二极管接收OLED发光单元发出的光，从而能够更加灵活地设置PIN光电二极管的位置。然而，如果透光部465的尺寸过大则会对显示面板的正常显示造成影响，因此，应该适当地设置透光部465的大小。在本公开的另一些实施例中，像素界定层460中可以不具有透光部465。在这些实施例中，需要适当地设置光电转换器465A的位置，使其能够直接接收到OLED发光单元发出的光，而不是被像素界定层460完全阻挡。
在一些实施例中，显示面板还包括光电读取电路，光电读取电路与PIN光电二极管电连接，以读取PIN光电二极管产生的光电信号。为了便于说明，在图4的实施例中只示出了光电读取电路中的读取控制晶体管M1。读取控制晶体管M1的源极481连接到PIN光电二极管，漏极482连接显示面板中的信号读取线，通过改变M1的栅极的电平来控制将PIN光电二极管产生的光电信号经由信号读取线传递到外部电路进行补偿计算。在底发射的情况中，光电读取电路同样形成于阵列基板400中。具体地，如图4所示，读取控制晶体管M1与驱动晶体管T1可以具有相同或相似的结构，二者可以是通过相同的工艺同时形成的，从而能够简化形成显示面板400的工序。
在一些实施例中，光电转换器在垂直于阵列基板的方向上位于像素界定层460与光电读取电路之间。
图5示出了根据本公开实施例的显示面板500的电路结构图。显示面板500包括有效显示区域510和非显示区域520。有效显示区域包括阵列布置的多个像素单元530。显示面板500中的各个像素单元530可以具有图3或图4中示出的像素单元的结构。
非显示区域520包括补偿处理器540和数据驱动电路550。应该理解的是，在本公开的其他实施例中，补偿处理器540还可以位于显示面板500的外部。
每个像素单元530包括像素驱动电路531和光电读取电路532、发光单元533和光电转换器534。此外，像素单元530还包括多条栅线GATE(例如GATE1、GATE2、...)、多条数据线DATA(例如DATA1、DATA2、...)、多条信号读取线READ(例如，READ1、READ2、...)和多条读取控制线CON(例如，CON1、CON2、...)。
像素驱动电路531包括驱动晶体管T1、发光控制晶体管T2以及存储电容器Cs。像素驱动电路531的连接关系以及驱动原理可参见上文结合图1进行的描述，在此不再赘述。每个像素驱动电路531在相应的栅线GATE的控制下经由数据线DATA从数据驱动电路550接收数据信号，并产生与数据信号DATA的电平有关的驱动电流，驱动发光单元533(例如，OLED发光单元)发光。
光电读取电路532包括读取控制晶体管M1，用于在读取控制线CON的控制下从光电传感器534(例如PIN光电二极管)接收光电信号，并将所接收的光电信号经由读取信号线READ传送到补偿处理器540。其中，光电传感器534接收的光电信号是由发光单元533发出的光引起的。
补偿处理器540在接收光电信号后，基于所述光电信号计算补偿亮度值。然后，补偿处理器540将计算出的补偿亮度值发送给数据驱动电路550，使其通过改变提供给数据线DATA的数据电压来改变相应像素单元的发光亮度，从而实现像素特定的全面补偿。
图6示出了根据本公开实施例的显示面板的制作方法600的流程图。所述方法600可以用于制作图3所示的显示面板，因此上文中参照图3进行的解释和说明，在这里同样适应性地适用，在此不再赘述。
在步骤S610中，形成阵列基板。其中，阵列基板包括像素驱动电路。
在步骤S620中，在阵列基板的远离衬底的第一表面上形成像素界定层。
在一些实施例中，步骤S620还包括：在像素界定层中形成透光部。
在步骤S630中，在像素界定层中形成通孔。
在一些实施例中，像素界定层中具有透光部，从而步骤S630中形成的通孔使得所述透光部构成所述通孔的侧壁的一部分，即侧壁上的透光区域。
在步骤S640中，在通孔中形成发光单元，使得发光单元与像素驱动电路的输出端电连接。
在一些实施例中，发光单元为有机发光二极管。从而，步骤S640包括：在阵列基板的远离衬底的第一表面上依次形成阳极层、有机层和阴极层。其中，阳极层被形成为与像素驱动电路的输出端电连接。
在步骤S650中，形成上盖板。其中，上盖板包括光电读取电路和光电转换器，光电读取电路与光电转换器电连接。
在步骤S660中，将上盖板与像素界定层对合，使得发光单元发出的光能够被光电转换器接收。
在一些实施例中，像素界定层中具有透光部，从而步骤S660使得光电转换器至少能够经由所述透光部接收所述发光单元发出的光。
在一些实施例中，在对合后，光电转换器在阵列基板上的正投影与透光部在阵列基板上的正投影至少部分地重叠，光电转换器在阵列基板上的正投影与发光单元在阵列基板上的正投影不重叠，并且光电转换器在垂直于阵列基板的方向上位于像素界定层与光电读取电路之间。
图7示出了根据本公开实施例的显示面板的制作方法700的流程图。所述方法700可以用于制作图4所示的显示面板，因此上文中参照图4进行的解释和说明，在这里同样适应性地适用，在此不再赘述。
在步骤S710中，形成阵列基板。其中，阵列基板包括像素驱动电路、光电读取电路和光电转换器，光电读取电路与光电转换器电连接。
像素驱动电路包括驱动晶体管，以及光电读取电路包括读取控制晶体管。在一些实施例中驱动晶体管和读取控制晶体管是通过相同工艺形成的。
在步骤S720中，在阵列基板的远离衬底的第一表面上形成像素界定层。
在一些实施例中，步骤S720还包括：在像素界定层中形成透光部。
在步骤S730中，在像素界定层中形成通孔。
在一些实施例中，像素界定层中具有透光部，从而步骤S730中形成的通孔使得所述透光部构成所述通孔的侧壁的一部分，即侧壁上的透光区域。
在步骤S740中，在通孔中形成发光单元，使得发光单元与像素驱动电路的输出端电连接。光电转换器和发光单元被形成为使得发光单元发出的光能够被光电转换器接收。
在一些实施例中，像素界定层中具有透光部，从而步骤S740使得光电转换器至少能够经由透光部接收发光单元发出的光。
在一些实施例中，发光单元为有机发光二极管。从而，步骤S740包括：在阵列基板的远离衬底的第一表面上依次形成阳极层、有机层和阴极层。其中，阳极层被形成为与像素驱动电路的输出端电连接。
在一些实施例中，光电转换器、透光部和发光单元被形成为使得：光电转换器在阵列基板上的正投影与透光部在阵列基板上的正投影至少部分地重叠，光电转换器在阵列基板上的正投影与发光单元在阵列基板上的正投影不重叠，以及光电转换器在垂直于阵列基板的方向上位于像素界定层与光电读取电路之间。
图8示出了针对根据本公开实施例的显示面板的像素发光补偿方法800的流程图。方法800可通过图5所示的显示面板来实现，因此上文中参照图5进行的解释和说明，在这里同样适应性地适用，在此不再赘述。
在步骤S810中，通过数据驱动电路(例如，数据驱动电路550)向像素驱动电路(例如像素驱动电路531)提供第一数据电压，使得像素驱动电路驱动发光单元(例如，发光单元533)以初始亮度发光。
在步骤S820中，通过光电转换器(例如，光电转换器534)接收初始亮度的光，并产生光电信号。
在步骤S830中，通过光电读取电路(例如光电读取电路532)将光电信号读取到补偿处理器(例如补偿处理器540)。
在步骤S840中，通过补偿处理器计算亮度补偿值，并向数据驱动电路提供亮度补偿值。
在步骤S850中，通过数据驱动电路向像素驱动电路提供第二数据电压，使得像素驱动电路驱动发光单元以补偿亮度发光。
图9示出了根据本公开实施例的显示装置900的示意方框图。如图9所示，显示装置900可以包括根据本公开上述实施例的显示面板910。显示面板910可以通过图3、图4、图5所示的显示面板来实现。根据本公开实施例的显示装置900可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (29)

  1. 一种显示面板，包括阵列布置的多个像素单元，每个像素单元包括：
    阵列基板，包括像素驱动电路；
    像素界定层，设置在所述阵列基板的远离衬底的第一表面上，所述像素界定层中具有通孔；
    发光单元，设置在所述通孔中，所述发光单元与所述像素驱动电路的输出端电连接，以使得所述像素驱动电路输出的驱动电流驱动所述发光单元发光；以及
    光电转换器，被配置为接收所述发光单元发出的光。
  2. 根据权利要求1所述的显示面板，其中，所述像素界定层包括透光部，所述透光部形成所述通孔的侧壁的透光区域，以及
    其中，所述光电转换器被配置为至少经由所述透光部接收所述发光单元发出的光。
  3. 根据权利要求2所述的显示面板，其中，所述光电转换器在所述阵列基板上的正投影与所述透光部在所述阵列基板上的正投影至少部分地重叠。
  4. 根据权利要求1所述的显示面板，其中，所述光电转换器在所述阵列基板上的正投影与所述发光单元在所述阵列基板上的正投影不重叠。
  5. 根据权利要求1-4中的任一项所述的显示面板，还包括：光电读取电路，与所述光电转换器电连接，以读取光电转换器产生的光电信号。
  6. 根据权利要求5所述的显示面板，其中，所述光电转换器和所述光电读取电路设置在所述阵列基板中。
  7. 根据权利要求6所述的显示面板，其中，所述像素驱动电路包括驱动晶体管，所述驱动晶体管的源极或漏极之一与所述像素驱动电路的输出端电连接，用于产生驱动电流并将驱动电流提供到所述像素驱动电路的输出端，
    所述光电读取电路包括读取控制晶体管，所述读取控制晶体管的源极或漏极之一与所述光电转换器电连接，所述读取控制晶体管的源极或漏极中的另一个与信号读取线电连接，用于控制通过信号读取线读取光电转换器产生的光电信号，
    其中，所述驱动晶体管和所述读取控制晶体管是通过相同工艺形成的。
  8. 根据权利要求7所述的显示面板，其中，所述光电转换器在垂直于所述阵列基板的方向上位于所述像素界定层与所述光电读取电路之间。
  9. 根据权利要求5所述的显示面板，还包括：上盖板，覆盖所述像素界定层，
    其中，所述光电转换器和所述光电读取电路设置在所述上盖板中。
  10. 根据权利要求9所述的显示面板，其中，所述光电转换器在垂直于所述阵列基板的方向上位于所述像素界定层与所述光电读取电路之间。
  11. 根据权利要求5所述的显示面板，还包括补偿处理器，所述补偿处理器经由信号读取线与所述光电读取电路电连接，并且被配置为：
    从所述光电读取电路接收所述光电信号；以及
    基于所述光电信号计算亮度补偿值。
  12. 根据权利要求1所述的显示面板，其中，所述发光单元为有机发光二极管，所述有机发光二极管包括依次堆叠在所述第一表面上的阳极层、有机层和阴极层，
    其中，所述阳极层与所述像素驱动电路的输出端电连接。
  13. 一种显示面板的制作方法，所述显示面板包括阵列布置的多个像素单元，针对每个像素单元所述制作方法包括以下步骤：
    形成阵列基板，所述阵列基板包括像素驱动电路、光电读取电路和光电转换器，其中，所述光电读取电路与所述光电转换器电连接；
    在所述阵列基板的远离衬底的第一表面上形成像素界定层；
    在所述像素界定层中形成通孔；以及
    在所述通孔中形成发光单元，使得所述发光单元与所述像素驱动电路的输出端电连接，
    其中，所述光电转换器和所述发光单元被形成为使得所述发光单元发出的光被所述光电转换器接收。
  14. 根据权利要求13所述的方法，其中，形成像素界定层的步骤还包括：在所述像素界定层中形成透光部，
    其中，所述透光部形成所述通孔的侧壁的透光区域。
  15. 根据权利要求14所述的方法，其中，所述光电转换器被形成为至少经由所述透光部接收所述发光单元发出的光。
  16. 根据权利要求15所述的方法，其中，所述光电转换器和所述透光部被形成为使得所述光电转换器在所述阵列基板上的正投影与所述透光部在所述阵列基板上的正投影至少部分地重叠。
  17. 根据权利要求13所述的方法，其中，所述光电转换器和所述发光单元被形成为使得所述光电转换器在所述阵列基板上的正投影与所述发光单元在所述阵列基板上的正投影不重叠。
  18. 根据权利要求13所述的方法，其中，所述像素驱动电路包括驱动晶体管，所述驱动晶体管的源极或漏极之一与所述像素驱动电路的输出端电连接，用于产生驱动电流并将驱动电流提供到所述像素驱动电路的输出端，
    所述光电读取电路包括读取控制晶体管，所述读取控制晶体管的源极或漏极之一与所述光电转换器电连接，所述读取控制晶体管的源极或漏极中的另一个与信号读取线电连接，用于控制将通过信号读取线读取光电转换器产生的光电信号，
    其中，所述驱动晶体管和所述读取控制晶体管是通过相同工艺形成的。
  19. 根据权利要求18所述的方法，其中，所述光电转换器被形成为在垂直于所述阵列基板的方向上位于所述像素界定层与所述光电读取电路之间。
  20. 根据权利要求13所述的方法，其中，所述发光单元为有机发光二极管，形成所述发光单元的步骤包括：
    在所述第一表面上依次形成阳极层、有机层和阴极层，
    其中，所述阳极层被形成为与所述像素驱动电路的输出端电连接。
  21. 一种显示面板的制作方法，所述显示面板包括阵列布置的多个像素单元，对于每个像素单元所述制作方法包括以下步骤：
    形成阵列基板，所述阵列基板包括像素驱动电路；
    在所述阵列基板的远离衬底的第一表面上形成像素界定层；
    在所述像素界定层中形成通孔；
    在所述通孔中形成发光单元，使得所述发光单元与所述像素驱动电路的输出端 电连接；
    形成上盖板，所述上盖板包括光电读取电路和光电转换器，其中，所述光电读取电路与所述光电转换器电连接；以及
    将所述上盖板与所述像素界定层对合，使得所述发光单元发出的光被所述光电转换器接收。
  22. 根据权利要求21所述的方法，其中，形成像素界定层的步骤还包括：在所述像素界定层中形成透光部，
    其中，所述透光部形成所述通孔的侧壁的透光区域。
  23. 根据权利要求22所述的方法，其中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器至少经由所述透光部接收所述发光单元发出的光。
  24. 根据权利要求23所述的方法，其中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器在所述阵列基板上的正投影与所述透光部在所述阵列基板上的正投影至少部分地重叠。
  25. 根据权利要求21所述的方法，其中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器在所述阵列基板上的正投影与所述发光单元在所述阵列基板上的正投影不重叠。
  26. 根据权利要求21所述的方法，其中，将所述上盖板与所述像素界定层对合的步骤使得所述光电转换器在垂直于所述阵列基板的方向上位于所述像素界定层与所述光电读取电路之间。
  27. 根据权利要求21所述的方法，其中，所述发光单元为有机发光二极管，形成所述发光单元的步骤包括：
    在所述第一表面上依次形成阳极层、有机层和阴极层，
    其中，所述阳极层被形成为与所述像素驱动电路的输出端电连接。
  28. 一种针对根据权利要求11所述的显示面板的像素发光补偿方法，包括：
    通过数据驱动电路向所述像素驱动电路提供第一数据电压，使得所述像素驱动电路驱动所述发光单元以初始亮度发光；
    通过所述光电转换器接收所述初始亮度的光，并产生光电信号；
    通过所述光电读取电路将所述光电信号读取到补偿处理器；
    通过所述补偿处理器计算亮度补偿值，并向所述数据驱动电路提供所述亮度补偿值；以及
    通过所述数据驱动电路向所述像素驱动电路提供第二数据电压，使得所述像素驱动电路驱动所述发光单元以补偿亮度发光。
  29. 一种显示装置，包括根据权利要求1-12任一项所述的显示面板。
PCT/CN2019/103714 2018-11-30 2019-08-30 显示面板及其制作方法、像素发光补偿方法以及显示装置 WO2020107980A1 (zh)

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