WO2020103744A1 - 芯片的封装结构以及封装方法 - Google Patents

芯片的封装结构以及封装方法

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Publication number
WO2020103744A1
WO2020103744A1 PCT/CN2019/118162 CN2019118162W WO2020103744A1 WO 2020103744 A1 WO2020103744 A1 WO 2020103744A1 CN 2019118162 W CN2019118162 W CN 2019118162W WO 2020103744 A1 WO2020103744 A1 WO 2020103744A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
packaging
adhesive layer
substrate
electrical contact
Prior art date
Application number
PCT/CN2019/118162
Other languages
English (en)
French (fr)
Inventor
王之奇
胡津津
吴明轩
Original Assignee
苏州晶方半导体科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Publication of WO2020103744A1 publication Critical patent/WO2020103744A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Definitions

  • the present application relates to the field of chip packaging technology, for example, to a chip packaging method and a packaging method.
  • the main component of the electronic device to realize the preset function is the chip.
  • the integration of the chip is getting higher and higher, the function of the chip is getting stronger, and the size of the chip is getting smaller and smaller, so the chip needs
  • a packaging structure is formed, so that the chip is electrically connected to an external circuit.
  • the chip When the chip is packaged to form a package structure, the chip is generally electrically connected to the package substrate directly, and the chip is electrically connected to the external circuit through the package substrate. In the related art, the heat dissipation performance of the chip packaging structure is poor.
  • the application provides a chip packaging structure and a packaging method, which can improve the heat dissipation performance of the packaging structure.
  • a packaging structure of a chip includes:
  • a packaging substrate including opposite first and second surfaces, a through hole penetrating the first surface and the second surface, the first surface is provided with an electrical contact protrusion, the electrical contact The protrusion is used for electrical connection with an external circuit board;
  • a chip fixed on the first surface, the chip covering the through hole, the chip is electrically connected to the electrical contact protrusion; covering a side surface of the chip facing away from the packaging substrate and the first An adhesive layer on the surface, the adhesive layer exposes the end of the electrical contact protrusion facing away from the packaging substrate, so that the end is electrically connected to the external circuit board.
  • This application also provides a chip packaging method, including:
  • a base is provided, the base includes a plurality of package substrates arranged in an array, and a cutting channel is provided between adjacent package substrates, the package substrate includes opposite first surfaces and second surfaces, and penetrates the first surfaces and A through hole in the second surface, the first surface is provided with an electrical contact protrusion, and the electrical contact protrusion is used for electrical connection with an external circuit board;
  • a chip is fixed on the first surface, the chip covers the through hole, and the chip is electrically connected to the electrical contact protrusion;
  • An adhesive layer is formed on the surface of the base on which the chip is fixed, the adhesive layer covers the side surface of the chip facing away from the packaging substrate and the first surface, and the adhesive layer exposes the electrical contacts The protrusion faces away from the end of the packaging substrate, so that the end is electrically connected to the external circuit board;
  • the substrate is divided based on the cutting channel to form a plurality of single-particle packaging structures.
  • Figure 1 is a schematic diagram of a conventional chip packaging structure
  • FIG. 2 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of yet another chip packaging structure provided by an embodiment of the present application.
  • 5 to 13 are schematic flowcharts of a chip packaging method provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a package structure of a conventional chip.
  • the package structure shown in FIG. 1 includes: a package substrate 11, a chip 12 and a cover 13.
  • the package substrate 11 includes opposite first and second surfaces, and has a through hole 16 penetrating the first and second surfaces.
  • the cover plate 13 is fixed on the second surface and covers the through hole 16, and the chip 12 is fixed on the first surface and covers the through hole 16.
  • the first surface has solder bumps 14 and the chip 12 is electrically connected to the solder bumps 14.
  • the solder bump 14 is used for electrical connection with an external circuit.
  • An adhesive layer 15 is provided on the first surface, and the adhesive layer 15 surrounds the sidewall of the chip 12.
  • the height of the chip 12 is smaller than the height of the solder bump 14. Therefore, there are two main heat dissipation paths for the heat generated by the chip 12, one is through the back surface of the chip 12 to the air, this method directly dissipates heat through the back of the chip 12, because the chip 12 is generally a semiconductor material substrate, the thermal conductivity is poor, It is inconvenient for the heat to be quickly dissipated from the chip 12, and the other is to conduct heat to the solder bump 14 through the circuit, and dissipate heat through the solder bump 14, which dissipates heat through the metal circuit.
  • the metal circuit has good thermal conductivity, the heat needs to pass through
  • the area where the front surface of the chip 12 is electrically connected to the package substrate 11 is transferred to the solder bump 14 through the metal line.
  • the area is small, and it is not convenient for the heat to be quickly radiated from the front surface of the chip 12, Longer, it is not convenient for rapid heat dissipation. It can be seen that the existing chip packaging structure has poor heat dissipation performance.
  • the technical solution of the present application provides a chip packaging structure and a packaging method, by providing an adhesive layer on the back of the chip, so that the heat of the chip can be transferred to the adhesive layer and then dissipated through the adhesive layer, so that the heat is quickly transferred Go out to avoid heat accumulation in the chip and improve heat dissipation performance.
  • FIG. 2 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application.
  • the packaging structure includes: a packaging substrate 21, and the packaging substrate 21 includes opposite first surfaces and second surfaces, which extend through the A through hole T on the first surface and the second surface, the first surface is provided with an electrical contact protrusion 24 for electrically connecting with an external circuit board; fixed on the first surface Chip 22, the chip 22 covers the through hole T, the chip 22 is electrically connected to the electrical contact protrusion 24; covers the side surface of the chip 22 facing away from the packaging substrate 21 and the first An adhesive layer 25 on the surface, the adhesive layer 25 exposes the end of the electrical contact protrusion 24 facing away from the packaging substrate 21, so that the end is electrically connected to the external circuit board.
  • the external circuit board is not shown in FIG. 2.
  • the chip 22 has opposite back and front sides, and the front side faces the first surface.
  • the gap between the side wall of the chip 22 and the electrical contact bump 24 is filled through the adhesive layer 25, so that heat is directly transmitted to the electrical contact bump 24 through the adhesive layer 25 through the side wall of the chip 22, the heat dissipation path is short, and passes through the entire chip
  • the side wall of 22 conducts heat and the heat dissipation area is large, which can greatly improve the heat dissipation speed.
  • the adhesive layer 25 covers the chip 22 and covers the first surface. Compared with the back surface of the chip 22, the surface of the side of the back package substrate 21 of the adhesive layer 25 has a larger area, which can increase the heat dissipation speed. Therefore, the packaging structure described in the embodiments of the present application has better heat dissipation performance.
  • the adhesive layer 25 is made of thermally conductive adhesive, so that the heat of the chip 22 can be quickly transferred to the adhesive layer 25 through the back of the chip, and dissipated through the adhesive layer 25 to increase the speed of heat transfer out of the chip 22 and avoid heat accumulation in the chip 22 .
  • the thermal conductivity of the adhesive layer 25 is greater than the thermal conductivity of the substrate of the chip 22. If the silicon substrate is used to prepare the chip 21, the thermal conductivity of the adhesive layer 25 is greater than that of the silicon substrate.
  • the height of the electrical contact protrusion 24 is greater than the height of the chip 22; wherein, the first direction is directed from the second surface to the first surface.
  • the height of the electrical contact protrusion 24 may be the height of the chip 22, in which case the external circuit board needs to have a soldering protrusion matching the electrical contact protrusion 24 for The contact protrusion 24 is soldered and fixed, so that the package structure is electrically connected to the external circuit board.
  • the height of the electrical contact protrusion 24 is greater than the maximum distance of the adhesive layer 25 from the surface of the packaging substrate 21 to the packaging substrate 21; wherein, the first A direction is directed from the second surface to the first surface. In this way, the package structure can be directly electrically connected to the external circuit board through the exposed end of the electrical contact protrusion 24.
  • the height of the electrical contact protrusion 24 may also be set to be less than the maximum distance from the surface of the adhesive layer 25 away from the surface of the packaging substrate 21 to the packaging substrate 21, at this time, in order to facilitate electrical connection with an external circuit board
  • the adhesive layer 25 needs to be provided with an opening exposing the electrical contact protrusion 24, and the external circuit board needs to have a soldering protrusion matching the electrical contact protrusion 24 for welding and fixing with the electrical contact protrusion 24, so as to facilitate the packaging structure and The external circuit board is electrically connected.
  • the electrical contact protrusion 24 is soldered and fixed to the external circuit board, and the adhesive layer 25 on the surface of the chip 22 facing away from the packaging substrate 21 is in contact with and fixed to the external circuit board.
  • the heat of the adhesive layer 25 can be directly transmitted to the external circuit board, and the heat is radiated through the external circuit board.
  • the heat dissipation rate is faster.
  • the adhesive layer 25 is a hot-melt adhesive.
  • the adhesive layer 25 is heated and melted when the electrical contact protrusion 24 is welded to the external circuit board to fix the chip 22 and the external circuit board.
  • the hot-melt adhesive with good thermal conductivity is used as the adhesive layer 25, which can be melted by heat when the electrical contact protrusion 24 is welded and fixed to the external circuit board. Due to the contact with the external circuit board due to gravity, on the one hand, it can improve the packaging structure and the external circuit.
  • Fixing stability performance can also make the adhesive layer 25 directly contact with the external circuit board, so that the heat causes the heat of the chip 22 to be transmitted to the external circuit board through the adhesive layer 25, and dissipates heat through the external circuit board to improve the heat dissipation performance.
  • the packaging substrate 11 is any one of a PCB board, an organic substrate, and a glass substrate.
  • the first surface has a pad electrically connected to the line, and the chip 22 fixed on the first surface is electrically connected to the pad.
  • the pad is electrically connected to the electrical contact bump 24 through a metal line.
  • the metal circuit may be provided on the first surface or inside the packaging substrate 21.
  • the electrical contact protrusion 24 is a solder ball.
  • the illustrated packaging structure further includes a light-transmitting cover plate 23 fixed on the second surface, and the light-transmitting cover plate 23 covers the through hole T.
  • the light-transmitting cover plate 23 can be fixed to the packaging substrate 21 by adhesive.
  • the 22-bit photosensitive chip of the chip may be, for example, an optical fingerprint chip.
  • FIG. 3 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application.
  • the adhesive layer 25 also fills the gap 26.
  • the chip 22 and the package substrate 21 are directly soldered and fixed, and the two are electrically connected by soldering and fixing.
  • soldering is bound to make the chip 22 and the first surface of the package substrate 21 completely contactless.
  • the gap can be filled through the adhesive layer 25.
  • the fixing stability of the chip 22 and the first surface can be improved.
  • the gap can be filled, the contact area of the chip 22 and the first surface can be increased, and the front surface of the chip 22 can be increased. The area of heat dissipation area improves heat dissipation performance.
  • FIG. 4 is a schematic diagram of yet another chip packaging structure provided by an embodiment of the present application.
  • the adhesive layer 25 further covers the through hole T Side wall 27 to reduce light reflection.
  • the reflective layer of the through-hole T sidewall 27 can be reduced by an adhesive layer to avoid the influence of the reflected light of the through-hole T sidewall 27 on the detection result of the chip 22 and improve the detection accuracy of the chip 22.
  • the packaging structure in the packaging structure described in the embodiments of the present application, the packaging structure is simple and the manufacturing cost is low. Moreover, the heat dissipation performance of the packaging structure can be improved by the adhesive layer 25 provided on the back of the chip 22.
  • FIG. 5 to FIG. 11 is a chip package provided by an embodiment of the present application. Schematic diagram of the method.
  • the packaging method includes:
  • Step S11 As shown in FIGS. 5 and 6, a substrate 20 is provided.
  • the base 20 includes a plurality of package substrates 21 arranged in an array, with a cutting channel 10 between adjacent package substrates 21, the package substrate 21 includes opposite first surfaces and second surfaces, and penetrates the first surface And the through hole T of the second surface, the first surface is provided with an electrical contact protrusion 24, and the electrical contact protrusion is used for electrical connection with an external circuit board.
  • 5 is a plan view of the base 20 toward the first surface of each package substrate 21, and FIG. 6 is a cross-sectional view of FIG. 5 in the P-P 'direction.
  • the packaging substrate 21 is any one of a PCB board, an organic substrate, and a glass substrate.
  • the electrical contact protrusion 24 is a solder ball.
  • a frame 30 of a predetermined height is fixed on the periphery of the base 20, the substrate 20 is placed horizontally, and the frame 30 is located above.
  • the adhesive layer 25 can be formed in subsequent steps .
  • a carrier board 31 may be fixed on the second surface of the base 20.
  • Step S12 As shown in FIGS. 6 and 7, a chip 22 is fixed on the first surface, the chip 22 covers the through hole T, and the chip 22 is electrically connected to the electrical contact protrusion 24.
  • Step S13 As shown in FIG. 8, an adhesive layer 25 is formed on the surface of the substrate 20 on which the chip 22 is fixed.
  • the adhesive layer 25 covers a side surface of the chip 22 facing away from the packaging substrate 21 and the first surface, and the adhesive layer 25 exposes an end of the electrical contact protrusion 24 facing away from the packaging substrate 21, In order to facilitate the electrical connection between the end and the external circuit board.
  • the height of the electrical contact bump 24 is greater than the height of the chip 22, and the height of the electrical contact bump 24 is greater than the surface of the adhesive layer 25 facing away from the surface of the packaging substrate 21 to the package
  • the electrical contact protrusion 24 is soldered and fixed to the external circuit board, and the adhesive layer 25 on the surface of the chip 22 facing away from the packaging substrate 21 is in contact with and fixed to the external circuit board.
  • the adhesive layer 25 is a hot-melt adhesive. In this way, the adhesive layer 25 is heated and melted when the electrical contact protrusion 24 is welded to the external circuit board to fix the chip 22 and the external circuit board.
  • forming the glue layer 25 on the surface of the substrate 20 on which the chip 22 is fixed includes: injecting liquid glue into the frame 30, and after the liquid glue is cured, the glue layer 25 is formed.
  • the side wall of the frame 30 may be provided with at least one opening through which liquid glue is injected into the frame 30.
  • an opening may be provided at each of the four top corners of the frame 30 for injecting liquid glue.
  • the packaging method further includes: after the liquid glue is cured, before the substrate 20 is divided, removing the frame 30.
  • the packaging method further includes: after forming the adhesive layer 25 and before dividing the substrate 20, fixing the light-transmitting cover plate 23 on the second surface, the light-transmitting cover plate 23 covering the ⁇ ⁇ ⁇ T ⁇ Said through hole T.
  • the carrier plate 31 If the carrier plate 31 is used, the carrier plate 31 can be removed, the substrate 20 can be placed horizontally, and the second surface of each package substrate 21 can be set upward, covering and fixing the transparent cover plate 23 on each through hole T.
  • Each of the through holes T is provided with a transparent cover plate 23 respectively.
  • the chip 22 is a photosensitive chip, and light signals can be collected through the through hole T and the transparent cover plate 23.
  • Step S14 As shown in FIG. 11, the substrate 20 is divided based on the cutting channel 10 to form a plurality of single-particle packaging structures.
  • the method shown in FIGS. 5-11 can be used to manufacture the package structure shown in FIG. 2.
  • the method has simple process, low manufacturing cost, simple package structure and good heat dissipation performance.
  • the difference from the above method is that, as shown in FIG. 12, after the chip 22 is fixed to the first surface, there is a gap 26 between the chip 22 and the first surface When the liquid glue is injected, the liquid glue fills the gap 26, so that after curing, the glue layer 25 also fills the gap 26.
  • the size parameter of the gap can be adjusted by setting the bonding pad on the front surface of the chip 22 and the pad bonding the first surface with the bonding pad, so that the glue can completely fill the gap.
  • the liquid glue covers the side wall 27 of the through hole T through the gap 26, so that after curing,
  • the adhesive layer 25 also covers the sidewall 27 of the through hole T to reduce light reflection.
  • the packaging method described in the embodiment of the present application can produce the packaging structure described in the above embodiments.
  • the process is simple, the manufacturing cost is low, the manufactured packaging structure is simple, and the heat dissipation performance is good.
  • the chip is packaged through a packaging substrate having through holes.
  • the package substrate has a through hole, fixes the chip to the first surface of the repackage substrate, and covers the through hole, the chip is electrically connected to the electrical contact protrusions provided on the first surface, so as to facilitate electrical connection with an external circuit connection.
  • An adhesive layer is provided on a surface of the chip facing away from the packaging substrate, and the heat of the chip can be conducted to the adhesive layer, which accelerates the heat dissipation of the chip and improves the heat dissipation performance of the packaging structure.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本申请公开了一种芯片的封装结构以及封装方法，本申请技术方案通过具有通孔的封装基板对芯片进行封装。封装基板具有通孔，将芯片固定再封装基板的第一表面，且覆盖所述通孔，所述芯片与设置在所述第一表面的电接触凸起电连接，以便于实现与外部电路电连接。在所述芯片背离所述封装基板的一侧表面设置有胶层，所述芯片的热量可以传导至所述胶层，通过所述胶层加快所述芯片的散热，提高封装结构的散热性能。

Description

芯片的封装结构以及封装方法
本公开要求在2018年11月20日提交中国专利局、申请号为201811382449.3的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请涉及芯片封装技术领域，例如涉及一种芯片的封装方法以及封装方法。
背景技术
随着科学技术的不断发展，越来越多的电子设备被广泛的应用于人们的日常生活以及工作当中，为人们的日常生活以及工作带来了巨大的便利，成为当今人们不可或缺的重要工具。
电子设备实现预设功能的主要部件是芯片，随着集成电路技术的不断进步，芯片的集成度越来越高，芯片的功能越来越强大，而芯片的尺寸越来越小，故芯片需要通过封装，形成封装结构，以便于芯片与外部电路电连接。
对芯片进行封装形成封装结构时，一般是直接在芯片与封装基板电连接，芯片通过封装基板与外部电路电连接。相关技术中，芯片的封装结构散热性能较差。
发明内容
本申请提供一种芯片的封装结构以及封装方法，可以提高封装结构的散热性能。
本申请提供如下技术方案：
一种芯片的封装结构，所述封装结构包括：
封装基板，所述封装基板包括相反的第一表面以及第二表面，贯穿所述第一表面以及所述第二表面的通孔，所述第一表面设置有电接触凸起，所述电接触凸起用于与外部电路板电连接；
固定在所述第一表面的芯片，所述芯片覆盖所述通孔，所述芯片与所述电接触凸起电连接；覆盖所述芯片背离所述封装基板的一侧表面以及所述第一表面 的胶层，所述胶层露出所述电接触凸起背离所述封装基板的端部，以便于所述端部与所述外部电路板电连接。本申请还提供一种芯片的封装方法，包括：
提供一基底，所述基底包括多个阵列排布的封装基板，相邻封装基板之间具有切割沟道，所述封装基板包括相反的第一表面以及第二表面，贯穿所述第一表面以及所述第二表面的通孔，所述第一表面设置有电接触凸起，所述电接触凸起用于与外部电路板电连接；
在所述第一表面固定芯片，所述芯片覆盖所述通孔，所述芯片与所述电接触凸起电连接；
在所述基底固定有所述芯片的一侧表面形成胶层，所述胶层覆盖所述芯片背离所述封装基板的一侧表面以及所述第一表面，所述胶层露出所述电接触凸起背离所述封装基板的端部，以便于所述端部与所述外部电路板电连接；
基于所述切割沟道分割所述基板，形成多个单粒封装结构。
附图说明
图1为常规芯片的封装结构的示意图；
图2为本申请实施例提供的一种芯片的封装结构的示意图；
图3为本申请实施例提供的另一种芯片的封装结构的示意图；
图4为本申请实施例提供的又一种芯片的封装结构的示意图；
图5-图13为本申请实施例提供的一种芯片的封装方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。参考图1，图1为常规芯片的封装结构的示意图，图1所示封装结构包括：封装基板11、芯片12以及盖板13。封装基板11包括相反的第一表面以及第二表面，且具有贯穿所述第一表面以及所述第二表面的通孔16。盖板13固定在第二表面，且覆盖通孔16，芯片12固定在第一表面，且覆盖通孔16。第一表面具有焊接凸起14，芯片12与焊接凸起14电连接。焊接凸起14用于与外部电路电连接。第一表面设置有胶层15，胶层15包围芯片12的侧壁。
由图1所示封装结构可知，为了便于焊接凸起14与外部电路电连接，以所 述封装基板11的第一表面为参考，芯片12的高度的小于焊接凸起14的高度。因此，芯片12产生的热量散热路径主要有两种，一种是通过其背面散发到空气中散发，该方式直接通过芯片12的背面散热，由于芯片12一般半导体材料衬底，导热性能较差，不便于热量快速由芯片12散发出去，另一种是是通过电路传导至焊接凸起14，通过焊接凸起14散热，该方式通过金属线路散热，虽然金属线路导热性能较好，但是热量需要通过该芯片12正面与封装基板11电连接的区域传递，再通过金属线路传导至焊接凸起14，一方面，该区域面积较小，不便于热量快速从芯片12正面散发出去，另一方面，路径较长，不便于热量的快速散发。可见，现有芯片的封装结构，散热性能较差。
为了解决上述问题，本申请技术方案提供了一种芯片的封装结构以及封装方法，通过在芯片的背面设置胶层，使得芯片的热量可以传导至胶层后，通过胶层散发，使得热量快速传递出去，避免芯片内的热量积累，提高了散热性能。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
参考图2，图2为本申请实施例提供的一种芯片的封装结构的示意图，该封装结构包括：封装基板21，所述封装基板21包括相反的第一表面以及第二表面，贯穿所述第一表面以及所述第二表面的通孔T，所述第一表面设置有电接触凸起24，所述电接触凸起24用于与外部电路板电连接；固定在所述第一表面的芯片22，所述芯片22覆盖所述通孔T，所述芯片22与所述电接触凸起24电连接；覆盖所述芯片22背离所述封装基板21的一侧表面以及所述第一表面的胶层25，所述胶层25露出所述电接触凸起24背离所述封装基板21的端部，以便于所述端部与所述外部电路板电连接。图2中未示出所述外部电路板。
本申请实施例所述结构，芯片22具有相反的背面和正面，且正面朝向第一表面。通过在所述芯片22的背面设置胶层25，可以使得热量由芯片22的背面传递至胶层25，使得热量快速传导出芯片22，避免热量在芯片22内积累，提高散热速度。而且，通过胶层25填充芯片22侧壁与电接触凸起24之间的间隙，使得热量直接通过芯片22侧壁通过胶层25传导至电接触凸起24，该散热路径短，通过整个芯片22的侧壁传导热量，散热区域大，可以大大提高散热速度。同时，胶层25覆盖芯片22，且覆盖第一表面，相对于芯片22的背面，胶层25的背面封装基板21的一侧表面的面积更大，可以提高散热速度。因此，本申请 实施例所述封装结构具有较好的散热性能。
所述胶层25为导热胶制备，以便于使得芯片22的热量快速通过其背面传递至胶层25，通过胶层25散发出去，提高热量传递出芯片22的速度，避免热量在芯片22内积累。所述胶层25导热系数大于芯片22的衬底的导热系数。如采用硅衬底制备芯片21，则胶层25的导热系数大于硅衬底的导热系数。
如图2所示，在第一方向上，所述电接触凸起24的高度大于所述芯片22的高度；其中，所述第一方向由所述第二表面指向所述第一表面。其他方式中，在第一方向上，所述电接触凸起24的高度可以所述芯片22的高度，此时需要外部电路板具有与电接触凸起24匹配的焊接凸起，用于与电接触凸起24焊接固定，以便于封装结构与外部电路板电连接。
如图2所示，在第一方向上，所述电接触凸起24的高度大于所述胶层25背离所述封装基板21的表面到所述封装基板21的最大距离；其中，所述第一方向由所述第二表面指向所述第一表面。这样，封装结构可以直接通过电接触凸起24露出的端部与外部电路板电连接。其他方式中，还可以设置所述电接触凸起24的高度小于所述胶层25背离所述封装基板21的表面到所述封装基板21的最大距离，此时，为了便于与外部电路板电连接，需要设置胶层25具有露出电接触凸起24的开口，需要外部电路板具有与电接触凸起24匹配的焊接凸起，用于与电接触凸起24焊接固定，以便于封装结构与外部电路板电连接。
所述电接触凸起24与所述外部电路板焊接固定，所述芯片22背离所述封装基板21一侧表面的所述胶层25与所述外部电路板接触固定。这样，当与外部电路板绑定时，胶层25的热量可以直接传导至外部电路板，通过外部电路板散热，相对于胶层25与外部电路板具有间隙的方式，散热速率更快。
所述胶层25为热熔胶，所述胶层25在所述电接触凸起24与所述外部电路板焊接固定时受热融化，以固定所述芯片22与所述外部电路板。采用导热性能良好的热熔胶作为胶层25，可以在电接触凸起24与外部电路板焊接固定时，受热融化，由于重力与外部电路板接触，一方面，可以提高封装结构与外部电路的固定稳定性能，另一方，还可以使得胶层25直接与外部电路板接触，使得热量使得芯片22热量通过胶层25传导至外部电路板，通过外部电路板散热，提高散热性能。
本申请实施例中，所述封装基板11为PCB板、有机基板以及玻璃基板中的任一种。第一表面具有与该线路电连接的焊盘，固定在第一表面的芯片22与该焊盘电连接。焊盘通过金属线路与电接触凸起24电连接。该金属线路可以设置在第一表面，或是设置在封装基板21的内部。所述电接触凸起24为锡球。
如图2所示，所示封装结构还包括：固定在所述第二表面的透光盖板23，所述透光盖板23覆盖所述通孔T。透光盖板23可以通过黏胶与封装基板21固定。所述芯片22位感光芯片，例如可以为光学指纹芯片。
参考图3，图3为本申请实施例提供的另一种芯片的封装结构的示意图，基于图2所示方式，图3所示方式中，所述芯片22与所述第一表面固定后，所述芯片22与所述第一表面之间具有间隙26；所述胶层25还填充所述间隙26。一般的，芯片22与封装基板21直接焊接固定，通过焊接固定方式实现二者电连接。而焊接势必无法使得芯片22和封装基板21的第一表面完全无间隙接触。该方式可以通过胶层25填充所述间隙，一方面，提高芯片22与第一表面的固定稳定性，另一方面，可以填充间隙，提高芯片22与第一表面的接触面积，提高芯片22正面散热区域面积，提高散热性能。
参考图4，图4为本申请实施例提供的又一种芯片的封装结构的示意图，基于图3所示方式，图4所示方式中，所述胶层25还覆盖所述通孔T的侧壁27，以降低光的反射。如当所述芯片22为感光芯片时，可以通过胶层降低通孔T侧壁27的反光，避免通孔T侧壁27反射光对芯片22检测结果的影响，提高芯片22的检测准确性。
通过上述描述可知，本申请实施例所述封装结构中，封装结构简单，制作成本低。而且可以通过设置在芯片22背面的胶层25提高封装结构的散热性能。
基于上述封装结构实施例，本申请另一实施例还提供了一种封装方法，该封装方法如图5-图11所示，图5-图11为本申请实施例提供的一种芯片的封装方法的流程示意图，该封装方法包括：
步骤S11：如图5和图6所示，提供一基底20。
所述基底20包括多个阵列排布的封装基板21，相邻封装基板21之间具有切割沟道10，所述封装基板21包括相反的第一表面以及第二表面，贯穿所述第一表面以及所述第二表面的通孔T，所述第一表面设置有电接触凸起24，所述 电接触凸起用于与外部电路板电连接。其中，图5为基底20朝向各个封装基板21第一表面的俯视图，图6为图5在P-P’方向的切面图。
所述封装基板21为PCB板、有机基板以及玻璃基板中的任一种。所述电接触凸起24为锡球。
在所述基底20的周缘固定预设高度的框架30，所述基板20水平放置，且所述框架30位于上方，通过在所述基底20上设置框架30，可以便于后续步骤中形成胶层25。可以在基底20的第二表面固定一承载板31。
步骤S12：如图6和图7所示，在所述第一表面固定芯片22，所述芯片22覆盖所述通孔T，所述芯片22与所述电接触凸起24电连接。
步骤S13：如图8所示，在所述基底20固定有所述芯片22的一侧表面形成胶层25。
所述胶层25覆盖所述芯片22背离所述封装基板21的一侧表面以及所述第一表面，所述胶层25露出所述电接触凸起24背离所述封装基板21的端部，以便于所述端部与所述外部电路板电连接。
在第一方向上，所述电接触凸起24的高度大于所述芯片22的高度，所述电接触凸起24的高度大于所述胶层25背离所述封装基板21的表面到所述封装基板21的最大距离；其中，所述第一方向由所述第二表面指向所述第一表面。所述电接触凸起24与所述外部电路板焊接固定，所述芯片22背离所述封装基板21一侧表面的所述胶层25与所述外部电路板接触固定。
所述胶层25为热熔胶，这样，所述胶层25在所述电接触凸起24与所述外部电路板焊接固定时受热融化，以固定所述芯片22与所述外部电路板。
该步骤中，所述在所述基底20固定有所述芯片22的一侧表面形成胶层25包括：在所述框架30内注入液态胶，液态胶固化后，形成所述胶层25。可以设置框架30侧壁具有至少一个开口，通过所述开口向所述框架30内注入液态胶。如可以在框架30的四个顶角分别设置一个开口用于注入液态胶。
如图9所示，在进行下一步骤的切割工艺之前，所述封装方法还包括：在所述液态胶固化后，在分割所述基板20之前，去除所述框架30。
如图10所示，所述封装方法还包括：形成所述胶层25之后，分割所述基 底20之前，在所述第二表面固定透光盖板23，所述透光盖板23覆盖所述通孔T。如采用承载板31，可以去除该承载板31，将基板20水平放置，且各个封装基板21的第二表面朝上设置，在各个通孔T上覆盖固定透光盖板23。每个所述通孔T分别设置一个透光盖板23。所述芯片22为感光芯片，可以通过所述通孔T以及所述透光盖板23采集光信号。
步骤S14：如图11所示，基于所述切割沟道10分割所述基板20，形成多个单粒封装结构。
通过图5-图11所示方法，可以用于制作如图2所示的封装结构，该方法工艺简单，制作成本低，制作的封装结构简单，散热性能好。
如果制作如图3所示封装结构，与上述方法不同在于，如图12所示，所述芯片22与所述第一表面固定后，所述芯片22与所述第一表面之间具有间隙26；在注入所述液态胶时，所述液态胶填充所述间隙26，以使得固化后，所述胶层25还填充所述间隙26。可以通过设置芯片22正面的焊垫以及第一表面与所述焊垫焊接的焊盘位置，调节所述间隙的尺寸参数，以使得胶液可以完全填充所述间隙。
如果只做如图4所示封装结构，与上述方法不同在于，在注入所述液态胶时，所述液态胶通过所述间隙26覆盖所述通孔T的侧壁27，以使得固化后，所述胶层25还覆盖所述通孔T的侧壁27，以降低光的反射。
本申请实施例所述封装方法可以制作上述实施例所述封装结构，工艺简单，制作成本低，制作的封装结构简单，散热性能好。
本发明技术方案提供的芯片的封装结构以及封装方法中，通过具有通孔的封装基板对芯片进行封装。封装基板具有通孔，将芯片固定再封装基板的第一表面，且覆盖所述通孔，所述芯片与设置在所述第一表面的电接触凸起电连接，以便于实现与外部电路电连接。在所述芯片背离所述封装基板的一侧表面设置有胶层，所述芯片的热量可以传导至所述胶层，通过所述胶层加快所述芯片的散热，提高封装结构的散热性能。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较 简单，相关之处参见方法部分说明即可。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。

Claims (23)

  1. 一种芯片的封装结构，包括：
    封装基板，所述封装基板包括相反的第一表面以及第二表面，贯穿所述第一表面以及所述第二表面的通孔，所述第一表面设置有电接触凸起，所述电接触凸起用于与外部电路板电连接；
    固定在所述第一表面的芯片，所述芯片覆盖所述通孔，所述芯片与所述电接触凸起电连接；覆盖所述芯片背离所述封装基板的一侧表面以及所述第一表面的胶层，所述胶层露出所述电接触凸起背离所述封装基板的端部，以便于所述端部与所述外部电路板电连接。
  2. 根据权利要求1所述的封装结构，其中，在第一方向上，所述电接触凸起的高度大于所述芯片的高度；
    其中，所述第一方向由所述第二表面指向所述第一表面。
  3. 根据权利要求1所述的封装结构，其中，在第一方向上，所述电接触凸起的高度大于所述胶层背离所述封装基板的表面到所述封装基板的最大距离；
    其中，所述第一方向由所述第二表面指向所述第一表面。
  4. 根据权利要求1所述的封装结构，其中，所述电接触凸起与所述外部电路板焊接固定，所述芯片背离所述封装基板一侧表面的所述胶层与所述外部电路板接触固定。
  5. 根据权利要求4所述的封装结构，其中，所述胶层为热熔胶，所述胶层在所述电接触凸起与所述外部电路板焊接固定时受热融化，以固定所述芯片与所述外部电路板。
  6. 根据权利要求1所述的封装结构，其中，所述芯片与所述第一表面固定后，所述芯片与所述第一表面之间具有间隙；
    所述胶层还填充所述间隙。
  7. 根据权利要求6所述的封装结构，其中，所述胶层还覆盖所述通孔的侧壁，以降低光的反射。
  8. 根据权利要求1所述的封装结构，其中，所述封装基板为PCB板、有机基板以及玻璃基板中的任一种。
  9. 根据权利要求1所述的封装结构，还包括：固定在所述第二表面的透光盖板，所述透光盖板覆盖所述通孔。
  10. 根据权利要求1所述的封装结构，其中，所述电接触凸起为锡球。
  11. 根据权利要求1所述的封装结构，其中，所述芯片为感光芯片。
  12. 一种芯片的封装方法，包括：
    提供一基底，所述基底包括多个阵列排布的封装基板，相邻封装基板之间具有切割沟道，所述封装基板包括相反的第一表面以及第二表面，贯穿所述第一表面以及所述第二表面的通孔，所述第一表面设置有电接触凸起，所述电接触凸起用于与外部电路板电连接；
    在所述第一表面固定芯片，所述芯片覆盖所述通孔，所述芯片与所述电接触凸起电连接；
    在所述基底固定有所述芯片的一侧表面形成胶层，所述胶层覆盖所述芯片背离所述封装基板的一侧表面以及所述第一表面，所述胶层露出所述电接触凸起背离所述封装基板的端部，以便于所述端部与所述外部电路板电连接；
    基于所述切割沟道分割所述基板，形成多个单粒封装结构。
  13. 根据权利要求12所述的芯片的封装方法，其中，在所述基底的周缘固定预设高度的框架，所述基板水平放置，且所述框架位于上方，所述在所述基底固定有所述芯片的一侧表面形成胶层包括：
    在所述框架内注入液态胶，液态胶固化后，形成所述胶层。
  14. 根据权利要求13所述的芯片的封装方法，其中，在所述液态胶固化后，在分割所述基板之前，去除所述框架。
  15. 根据权利要求12所述的芯片的封装方法，其中，在第一方向上，所述电接触凸起的高度大于所述芯片的高度，所述电接触凸起的高度大于所述胶层背离所述封装基板的表面到所述封装基板的最大距离；
    其中，所述第一方向由所述第二表面指向所述第一表面。
  16. 根据权利要求12所述的芯片的封装方法，其中，所述电接触凸起与所述外部电路板焊接固定，所述芯片背离所述封装基板一侧表面的所述胶层与所述外部电路板接触固定。
  17. 根据权利要求16所述的芯片的封装方法，其中，所述胶层为热熔胶，所述胶层在所述电接触凸起与所述外部电路板焊接固定时受热融化，以固定所述芯片与所述外部电路板。
  18. 根据权利要求12所述的芯片的封装方法，其中，所述芯片与所述第一表面固定后，所述芯片与所述第一表面之间具有间隙；
    在注入所述液态胶时，所述液态胶填充所述间隙，以使得固化后，所述胶层还填充所述间隙。
  19. 根据权利要求18所述的芯片的封装方法，其中，在注入所述液态胶时，所述液态胶通过所述间隙覆盖所述通孔的侧壁，以使得固化后，所述胶层还覆盖所述通孔的侧壁，以降低光的反射。
  20. 根据权利要求12所述的芯片的封装方法，其中，所述封装基板为PCB板、有机基板以及玻璃基板中的任一种。
  21. 根据权利要求12所述的芯片的封装方法，还包括：
    形成所述胶层之后，分割所述基底之前，在所述第二表面固定透光盖板，所述透光盖板覆盖所述通孔。
  22. 根据权利要求12所述的芯片的封装方法，其中，所述电接触凸起为锡球。
  23. 根据权利要求12所述的芯片的封装方法，其中，所述芯片为感光芯片。
PCT/CN2019/118162 2018-11-20 2019-11-13 芯片的封装结构以及封装方法 WO2020103744A1 (zh)

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CN109524382B (zh) * 2018-11-20 2021-05-18 苏州晶方半导体科技股份有限公司 芯片的封装结构以及封装方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075624A (zh) * 2006-05-18 2007-11-21 大瀚光电股份有限公司 覆晶式取像模块封装结构及其封装方法
US20090039455A1 (en) * 2007-08-08 2009-02-12 Xintec Inc. Image sensor package with trench insulator and fabrication method thereof
CN203895457U (zh) * 2014-05-20 2014-10-22 苏州晶方半导体科技股份有限公司 一种影像传感器模组
CN106935606A (zh) * 2017-05-11 2017-07-07 北京工业大学 一种影像传感器的封装结构
CN107968077A (zh) * 2017-11-29 2018-04-27 信利光电股份有限公司 一种倒装芯片封装结构及工艺和摄像模组封装结构
CN109524382A (zh) * 2018-11-20 2019-03-26 苏州晶方半导体科技股份有限公司 芯片的封装结构以及封装方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623471B (zh) * 2012-03-27 2015-09-09 格科微电子（上海）有限公司 图像传感器的封装方法
CN103956369A (zh) * 2014-05-20 2014-07-30 苏州晶方半导体科技股份有限公司 影像传感器模组及其形成方法
CN103985723B (zh) * 2014-05-20 2017-06-20 苏州晶方半导体科技股份有限公司 封装方法以及封装结构
CN108321134A (zh) * 2018-04-09 2018-07-24 黄山宝霓二维新材科技有限公司 高功率密度塑封式ipm模块的封装结构及加工工艺
CN108364970A (zh) * 2018-04-20 2018-08-03 苏州晶方半导体科技股份有限公司 一种影像传感芯片的封装结构及其封装方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075624A (zh) * 2006-05-18 2007-11-21 大瀚光电股份有限公司 覆晶式取像模块封装结构及其封装方法
US20090039455A1 (en) * 2007-08-08 2009-02-12 Xintec Inc. Image sensor package with trench insulator and fabrication method thereof
CN203895457U (zh) * 2014-05-20 2014-10-22 苏州晶方半导体科技股份有限公司 一种影像传感器模组
CN106935606A (zh) * 2017-05-11 2017-07-07 北京工业大学 一种影像传感器的封装结构
CN107968077A (zh) * 2017-11-29 2018-04-27 信利光电股份有限公司 一种倒装芯片封装结构及工艺和摄像模组封装结构
CN109524382A (zh) * 2018-11-20 2019-03-26 苏州晶方半导体科技股份有限公司 芯片的封装结构以及封装方法

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