WO2020103615A1 - 光电计算单元、光电计算阵列及光电计算方法 - Google Patents

光电计算单元、光电计算阵列及光电计算方法

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Publication number
WO2020103615A1
WO2020103615A1 PCT/CN2019/111513 CN2019111513W WO2020103615A1 WO 2020103615 A1 WO2020103615 A1 WO 2020103615A1 CN 2019111513 W CN2019111513 W CN 2019111513W WO 2020103615 A1 WO2020103615 A1 WO 2020103615A1
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Prior art keywords
area
input
data
output
readout
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PCT/CN2019/111513
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English (en)
French (fr)
Inventor
闫锋
潘红兵
马浩文
石东海
李张南
王宇宣
王晨曦
陈轩
岳涛
朱棣
罗元勇
王子豪
娄胜
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南京大学
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Priority to KR1020217012261A priority Critical patent/KR102608628B1/ko
Priority to JP2021540360A priority patent/JP7224065B2/ja
Priority to EP19887726.8A priority patent/EP3839694A4/en
Priority to US17/278,567 priority patent/US20210382516A1/en
Publication of WO2020103615A1 publication Critical patent/WO2020103615A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E3/00—Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data
    • G06E3/001—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements
    • G06E3/005—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements using electro-optical or opto-electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/067—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using optical means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7896—Modular architectures, e.g. assembled from a number of identical packages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1057—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices [CCD] or charge injection devices [CID]

Definitions

  • the invention relates to a photoelectric calculation unit, a photoelectric calculation array and a photoelectric calculation method. More specifically, the present invention combines some technologies in the computing field and the semiconductor device field, and the technical solutions of the present invention can perform calculations independently or in combination with current electronic computing technologies.
  • Typical storage and computing integrated devices are mainly RRAM (memristor) and FLASH (flash memory).
  • RRAM can save the resistance value affected by the input amount of its electrical input terminal for a long time after power off, but RRAM does not support
  • the production of standard CMOS process the yield and uniformity of the device can not be guaranteed, which is unacceptable in the neural network algorithm that must use a large number of memory-calculation integrated devices to form a network to accelerate.
  • FLASH as a memory-calculation integrated device, it means that a single floating gate tube must store more than one bit of data, that is, multi-value storage. This is for traditional FLASH that can only use two methods of erasing and programming to change the threshold. Difficult to do.
  • the known optical calculation methods are mostly pure optical calculations that use light propagation rules to interact between light and optical devices.
  • an optoelectronic computing device that uses the optoelectronic properties of semiconductor materials and uses external input optical signals to modulate electrical signals transmitted in the semiconductor materials to implement adders, multipliers, and some advanced operations .
  • the device can realize a high-precision storage-calculation integrated function, and a single device can store the optical signal of the optical input end and store it for a long time after the light is cut off.
  • a new photoelectric calculation method which uses the photoelectric properties of semiconductor materials and uses input optical signals to modulate the electrical signals transmitted in the semiconductor materials to implement basic operations such as adders and multipliers. New mechanism.
  • the invention uses the photoelectric performance of semiconductor materials to design a photoelectric computing device, and discloses various adders, multipliers and algorithm accelerators composed of the photoelectric computing device, and their corresponding photoelectric calculation methods. It can be seen that the present invention utilizes the optoelectronic characteristics of semiconductor materials and the extended application of the technology that has been commonly used in the traditional optical field in the field of computing, and proposes a brand new optoelectronic computing device and a class of optoelectronic computing methods that can achieve high precision
  • the integrated memory-calculation function a single device can both store the optical signal at the optical input and save it for a long time after the light is cut off, and can achieve a single device to complete the multiplication operation, which is very suitable for accelerating a class of needs represented by neural network algorithms. Store parameters "algorithm.
  • FIG. 1 is a schematic diagram showing the basic structure of a multifunctional area of a photoelectric computing unit according to the present invention.
  • FIG. 2 is a front view showing the photoelectric calculation unit according to the first embodiment of the present invention.
  • FIG. 3 is a schematic perspective view showing the photoelectric calculation unit according to the first embodiment of the present invention.
  • FIG. 4 is a configuration diagram showing a multi-function area of the photoelectric calculation unit according to the first embodiment of the present invention.
  • FIG. 5 is an electrical model showing the photoelectric calculation unit according to the first embodiment of the present invention.
  • FIG. 6 is a front view showing a photoelectric calculation unit according to a second embodiment of the present invention.
  • FIG. 7 is a 3D schematic diagram showing an optoelectronic calculation unit according to a second embodiment of the present invention.
  • FIG. 8 is a configuration diagram showing a multi-function area of a photoelectric calculation unit according to a second embodiment of the present invention.
  • FIG. 9 is a front view showing a photoelectric calculation unit according to a third embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing the photoelectric calculation unit 3D according to the third embodiment of the present invention.
  • FIG. 11 is a configuration diagram showing the multi-function area of the photoelectric calculation unit according to the third embodiment of the present invention.
  • FIG. 12 is an electrical model showing a photoelectric calculation unit according to a third embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing the structure of a photoelectric calculation unit according to a fourth embodiment of the present invention.
  • FIG. 14 is a schematic diagram showing the structure of the multifunctional area of the photoelectric calculation unit according to the fourth embodiment of the present invention.
  • 15 is a schematic diagram showing a direct projection scheme according to the present invention.
  • 16 is a schematic diagram showing the integration of the light emitting unit and the photoelectric calculation unit according to the present invention.
  • FIG. 17 is a schematic diagram showing a lens light input scheme according to the present invention.
  • FIG. 18 is a schematic diagram showing an optical fiber cone light input scheme according to the present invention.
  • FIG. 19 is a schematic diagram showing a funnel-shaped optical fiber cone scheme according to the present invention.
  • FIG. 20 is a structural diagram showing an example of a multi-control gate structure using a photoelectric calculation unit according to the present invention.
  • FIG. 21 is a structural diagram showing an example of a multi-control gate structure using a photoelectric calculation unit according to the present invention.
  • FIG. 22 is a structural diagram showing an example of a multi-control gate structure using a photoelectric calculation unit according to the present invention.
  • FIG. 23 is a diagram showing an example of one of the adders according to the present invention.
  • 24 is a diagram showing an example of one of the multipliers according to the present invention.
  • FIG. 25 is a diagram showing an example of one of the multipliers according to the present invention.
  • FIG. 26 is a diagram showing an example of one of the multipliers according to the present invention.
  • FIG. 27 is a diagram showing an example of a vector adder according to the present invention.
  • FIG. 28 is a diagram showing an example of a high-bit width multiplier according to the present invention.
  • FIG. 29 is a schematic diagram showing a serial matrix vector multiplier according to the present invention.
  • FIG. 30 is a schematic diagram showing the calculation of the parallel matrix vector multiplier according to the present invention.
  • FIG. 31 is a schematic diagram showing a parallel matrix vector multiplier according to the present invention.
  • FIG. 32 is a schematic diagram showing the convolution operation according to the present invention.
  • FIG. 33 is a schematic diagram showing an array of convolution operation units according to the present invention, in which a 3 * 3 convolution kernel is targeted.
  • Fig. 34 is a schematic diagram showing an ALEXnet network according to the present invention.
  • FIG. 35 is a schematic diagram showing RELU function images according to the present invention.
  • 36 is a schematic diagram showing an X-ray imaging method and a CT imaging method according to the present invention.
  • FIG. 37 is a schematic diagram showing a CT algorithm according to the present invention, in which the ith ray passes through the jth pixel.
  • Fig. 38 is a schematic diagram showing a CT algorithm according to the present invention.
  • 39 is a schematic diagram showing an array of serial CT algorithm accelerators according to the present invention.
  • FIG. 40 is a schematic diagram showing digital control logic according to the present invention.
  • FIG. 41 is a graph showing the light response curve of the photoelectric calculation unit according to the first embodiment of the present invention.
  • FIG. 42 is a schematic diagram showing an AlexNet-like network for simulation according to the present invention.
  • the optoelectronic computing device unit according to the present invention includes a semiconductor multifunctional region structure, wherein the semiconductor multifunctional region structure includes a carrier control region, a coupling region, and a photogenerated carrier collection and reading Out of the zone, and the multifunctional zone can be a multi-layer structure, or any layer or zone structure that achieves the same photoelectric effect and control through the arrangement and transformation of multiple spaces.
  • the photoelectric optoelectronic calculation unit according to the present invention will be described in detail with reference to the accompanying drawings.
  • the photoelectric optoelectronic calculation unit according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 5.
  • the photoelectric optoelectronic computing unit of FIGS. 2 and 3 there is a P-type semiconductor substrate as the photogenerated carrier collection area and readout area divided into a left side collection area and a right side reading The output area, wherein the left-side collection area is used to apply a pulse with a negative voltage range on the substrate, or a pulse with a positive voltage range on the control gate, so that The depletion layer collected by the photoelectrons, and the number of collected photoelectrons is read out through the right reading area as the input amount of the light input terminal.
  • the right readout area includes shallow trench isolation, N-type drain and N-type source.
  • the shallow trench isolation is located in the middle of the collection region and the readout region in the middle of the semiconductor substrate.
  • the shallow trench isolation is formed by etching and filling with silicon dioxide to isolate the electrical signals of the collection region and the readout region .
  • the N-type source terminal is located on the side near the bottom dielectric layer in the readout area, and is formed by doping by ion implantation.
  • the N-type drain end is located on the other side of the semiconductor substrate close to the bottom dielectric layer opposite to the N-type source end, and is also formed by the doping method by ion implantation.
  • a positive voltage is applied to the control gate to form a conductive channel between the N-type source terminal and the N-type drain terminal of the collection region, and then a bias pulse is applied between the N-type source terminal and the N-type drain terminal.
  • the voltage accelerates the electrons in the conductive channel to form a current between the source and drain.
  • Carriers that form a current in the channel between the source and drain are subjected to the control gate voltage, the voltage between the source and drain, and the number of photoelectrons collected in the collection area to act as electrons that are combined by the light input and the electric input.
  • the output is in the form of current, where the control gate voltage and the source-drain voltage can be used as the electrical input of the device, and the number of photoelectrons is the optical input of the device.
  • the coupling region to connect the collection region and the read-out region, so that the depletion region in the collection region substrate begins to collect photoelectrons, and the surface potential of the substrate in the collection region will be collected Quantity influence;
  • the surface potential of the semiconductor substrate in the readout area is affected by the surface potential of the semiconductor substrate in the collection area, which in turn affects the current between the source and drain in the readout area, so that To read the number of photoelectrons collected in the collection area;
  • control gate as the carrier control region for applying a pulse voltage thereon, so that a depletion region for exciting photoelectrons is generated in the read-out region of the P-type semiconductor substrate.
  • the photoelectric calculation unit includes a control gate as the carrier control region, a charge-coupled layer as the coupling region, and the photogeneration A P-type substrate for carrier collection and readout regions, and a bottom dielectric layer for isolation are provided between the P-type semiconductor substrate and the charge-coupled layer, and a top dielectric layer for isolation , Is disposed between the charge-coupled layer and the control gate.
  • left side, right side, upper side, and lower side mentioned in this article only represent that the relative position observed under the viewing angle shown in the figure changes with the viewing angle, and is not to be understood as a limitation on the specific structure.
  • FIG. 5 is an electrical model of the photoelectric calculation unit according to the first embodiment of the present invention, and the principle of the photoelectric calculation unit is described in detail based on the electrical model shown in FIG. 5.
  • the left collecting area is equivalent to a capacitor of MOS capacitor
  • the right readout area is equivalent to a standard floating gate MOS tube. Due to the design, the capacitance C2 is much smaller than C1, so the effect of the readout area on the photosensitive area when the device is working is negligible.
  • the electric potential in a MOS-capacitor Si can be obtained by solving the following Poisson equation:
  • ⁇ SI is the dielectric constant of silicon and ⁇ is the bulk charge density of the P-type substrate.
  • the x direction is perpendicular to the downward direction of the underlying dielectric layer
  • x d is the depth of the depletion region
  • q is the amount of electron charge
  • V is the potential at the depth x.
  • E S is the surface electric field strength, assuming that the substrate voltage is set to 0V, so that the control gate potential during the photosensitive process is:
  • V G is the electric potential of the control gate
  • the available depletion region depth x d is:
  • the total amount of charge on the control gate Q CG N A + Q, Q is the amount of signal charge (e- / cm2), because this signal charge is collected in the collection area under the action of the electric field between the control gate and the P-type substrate, and because the recombination of carriers in the semiconductor substrate requires a certain time, plus The presence of thermally excited carriers in the upper depletion zone, therefore, this signal charge will still be stored in the arithmetic unit for a long time after the light is cut off, realizing the integrated function of storage and calculation.
  • V Q is the sum of the potentials generated by the signal charge:
  • the channel current I d can be expressed as:
  • V DS is the source-drain voltage
  • V FG is the charge-coupled layer potential
  • its size is affected by the control gate potential V G and the surface potential V s of the P-type substrate, which can be expressed as :
  • equation (1-6) can be simplified as:
  • Formula (1-11) brings into (1-3), that is, the surface potential V S of the P-type substrate and the control gate potential V G and the sum of the potentials generated by the signal charge V Q are approximately equal, that is:
  • t is the exposure time
  • X photon is the number of photons incident per unit time
  • ⁇ is the device quantum efficiency
  • the most basic structure of the photoelectric calculation unit contains only one output terminal, but if the MOSFET on the right side is divided into multiple parallel small MOSFETs with independent source and drain, and the device parameters are equal, then Expanding the number of output terminals, if the same V DS is given to the plurality of small MOSFETs, multiple identical output quantities of the photoelectric calculation unit can be obtained.
  • the photoelectric calculation unit based on the solution described in the first embodiment described above will also be described later.
  • the photoelectric calculation unit according to the second embodiment of the present invention will be described with reference to FIGS. 6 to 8.
  • an N-type semiconductor substrate as a photogenerated carrier collection and readout area, which is divided into a left-side collection area and a right-side readout area.
  • the left readout region is used to apply a pulse with a positive voltage range on the substrate, or a pulse with a negative voltage range on the control gate, so that a light hole is generated in the collection region substrate
  • the depletion layer is collected, and the collected amount of photohole charge is read through the right readout region;
  • the right readout region includes shallow trench isolation, a P-type drain terminal, and a P-type source terminal.
  • the shallow trench isolation is located in the middle of the semiconductor substrate in the middle of the collection area and the readout area, and is formed by etching and filling with silicon dioxide to isolate the electrical signals of the collection area and the readout area.
  • the P-type source terminal is located on the side near the bottom dielectric layer in the readout area, and is formed by doping by ion implantation.
  • the P-type drain end is located on the other side of the semiconductor substrate near the bottom dielectric layer opposite to the P-type source end, and is also formed by an ion implantation method using a doping method.
  • a negative pulse voltage is applied to the control gate to form a conductive channel between the P-type source and the P-type drain, and then a bias pulse voltage is applied between the P-type source and the P-type drain , So that the holes in the conductive channel accelerate to form a current between the source and drain.
  • Carriers that form a current in the channel between the source and drain are subjected to the control gate pulse voltage, the voltage between the source and drain, and the number of light holes collected in the collection area, as a combined effect of the light input and the electrical input Carriers are output in the form of current, where the control gate voltage and the source-drain voltage can be used as the electrical input of the device, and the number of light holes is the optical input of the device.
  • a charge-coupled layer as a coupling region to connect the collection region and the readout region, so that the depletion region in the collection region substrate begins to collect light holes, the surface potential of the collection region substrate will be affected by the collection region The influence of the number of light holes; through the connection of the charge-coupled layer, the surface potential of the semiconductor substrate in the readout area is affected by the surface potential of the semiconductor substrate in the readout area, which in turn affects the source-drain current in the readout area, thereby determining the readout area The current between source and drain is used to read the number of light holes collected in the collection area.
  • control gate as a carrier control region for applying a negative pulse voltage thereon, so that a depletion region for exciting light holes is generated in the readout region of the N-type semiconductor substrate. It can be used as an electrical input terminal to input one bit of calculation.
  • the photoelectric calculation unit includes a control gate as the carrier control region, a charge-coupled layer as the coupling region, and as the photogenerated An N-type substrate for carrier collection and readout regions, and a bottom dielectric layer for isolation are provided between the N-type semiconductor substrate and the charge-coupled layer, and a top dielectric layer for isolation , Is disposed between the charge-coupled layer and the control gate.
  • this second embodiment differs in that the P-type substrate used in the device unit is replaced with an N-type, and the N-type source and drain terminals of the readout MOSFET are replaced by The P-type and other structures are unchanged. Therefore, the principle-based derivation process is similar to the process described in the first embodiment, and the similar parts are not described in detail.
  • formula (1-7) points out that when the voltage difference between the control gate and the substrate is unchanged, the higher the doping concentration of the substrate before the photon is incident, the shallower the depth of the depletion region , And too shallow depletion region will cause the computing device to receive light input, the maximum number of photons that can be received is too small, the input range of the optical input terminal becomes smaller, which affects the performance of the computing unit; and, according to related theory, it is too high
  • the doping concentration of the substrate will cause the thermal excitation of the carrier to become larger, which will affect the storage time of the data at the optical input end in the integrated device.
  • the wafer is born with a low concentration of P-type doping, this doping can be used directly as a substrate condition for the production of P-type substrate devices; and if an N-type substrate device needs to be produced, ion implantation is required
  • the first way is to make an N-well, and then make an N-type substrate device in the N-well. Therefore, compared to the N-type substrate device, the P-type substrate device is easier to obtain lower substrate doping, so in the above two embodiments, the solution described in the first embodiment is often compared to the second implementation
  • the example solution has more advantages.
  • the most basic structure of the photoelectric calculation unit in the second embodiment includes only one output terminal, but if the MOSFET on the right readout area is divided into a plurality of parallel independent sources and drains, In addition, the number of small MOSFETs with equal device parameters can expand the number of output terminals. If the same V DS is given to the multiple small MOSFETs, the same output of multiple channels of the photoelectric calculation unit can be obtained.
  • the photoelectric calculation unit based on the solution described in the second embodiment described above will also be described later.
  • the photoelectric calculation unit according to the third embodiment of the present invention will be described with reference to FIGS. 9 to 12.
  • a P-type semiconductor substrate as the photogenerated carrier collection and readout area, which can undertake both photoreception and readout work, including An N-type drain and an N-type source.
  • the N-type source terminal is located on the side near the bottom dielectric layer in the readout area, and is formed by doping by ion implantation.
  • the N-type drain end is located on the other side of the semiconductor substrate close to the bottom dielectric layer opposite to the N-type source end, and is also formed by the doping method by ion implantation.
  • a pulse with a negative voltage range is applied to the P-type semiconductor substrate, and a pulse with a positive voltage range is applied to the control gate as the carrier control region, so that A depletion layer for photoelectron collection is generated in the substrate, and the electrons generated in the depletion region are accelerated by the electric field between the control gate and the P-type substrate, and sufficient energy is obtained upon arrival.
  • the control gate When receiving light, a pulse with a negative voltage range is applied to the P-type semiconductor substrate, and a pulse with a positive voltage range is applied to the control gate as the carrier control region, so that A depletion layer for photoelectron collection is generated in the substrate, and the electrons generated in the depletion region are accelerated by the electric field between the control gate and the P-type substrate, and sufficient energy is obtained upon arrival.
  • the control gate Through the barrier of the underlying dielectric layer between the P-type substrate and the charge-coupled layer, it enters the charge-coupled layer and is stored there. The amount of charge in the charge-
  • a pulse voltage accelerates the electrons in the conductive channel to form a current between the source and drain.
  • the current between the source and drain is controlled by the pulse voltage of the control gate, the voltage between the source and drain, and the number of electrons stored in the charge-coupled layer. As the electrons that are combined by the light input and the electric input, the current takes the form of current.
  • the output where the control gate voltage and the source-drain voltage can be used as the electrical input of the device, and the number of photoelectrons stored in the charge-coupled layer is the optical input of the device.
  • a charge-coupled layer as the coupling region for storing photoelectrons entering it, and changing the threshold value of the device during reading, thereby affecting the current between the source and drain of the readout region, thereby determining the source-drain between the readout region
  • the current is used to read out the number of photoelectrons generated when light is received and enters the charge-coupled layer.
  • control gate as the carrier control region for applying a pulse voltage thereon, so that a depletion region for exciting photoelectrons is generated in the read-out region of the P-type semiconductor substrate.
  • an electrical input terminal input one of the operation quantities.
  • the photoelectric calculation unit includes a control gate as the carrier control region, a charge-coupled layer as the coupling region, and as the photogenerated P-type substrate for carrier collection and readout area, wherein a bottom dielectric layer for isolation is provided between the P-type semiconductor substrate and the charge-coupled layer, and a top dielectric layer for isolation , Is disposed between the charge-coupled layer and the control gate.
  • FIG. 12 is an electrical model of the photoelectric calculation unit according to the third embodiment of the present invention, and the principle of the photoelectric calculation unit is described in detail based on the electrical model shown in FIG. 5.
  • the structure of the photoelectric computing unit unit is roughly equivalent to the floating gate device.
  • the topmost gate is the control gate, which is completely separated from the middle charge-coupled layer.
  • Floating gate is the capacitance between the floating gate and the control gate, the source terminal, the substrate, and the drain terminal, respectively.
  • V FG is the electric potential on the floating gate
  • V CG is the electric potential on the control gate
  • V S , V D , V B are the electric potential of the source end, drain end and substrate respectively.
  • the coupling coefficient of the electrode J can be any one of the control gate G, the drain terminal D, the source terminal S, and the substrate B, and then the potential V FG of the floating gate can be expressed by the coupling coefficient as:
  • V FG ⁇ G V GS + ⁇ D V DS + ⁇ S V S + ⁇ B V B (2-2)
  • V GS and V DS are the gate-source voltage and source-drain voltage, respectively
  • ⁇ G , ⁇ S , ⁇ D , and ⁇ B are the coupling coefficients of the gate, source, drain, and substrate, respectively. It can be seen that the potential of the floating gate is not only related to the control gate, but also related to the potential of the source, drain and substrate. If both the source and the substrate are grounded,
  • the threshold voltage V T and the conduction coefficient ⁇ can be derived from the formula of a common MOS device:
  • the floating gate potential when the device reaches the threshold is For the control gate potential when the device reaches the threshold, ⁇ CG is the body conduction coefficient for the control gate, and ⁇ FG is the body conduction coefficient for the floating gate.
  • Formulas (2-3), (2-5), (2-7) are:
  • V T is the same as Are directly related, while the formula of V T may be to change ⁇ V T can be expressed as:
  • V T0 is the threshold when there is no charge in the floating gate.
  • a gate voltage pulse is applied to the control gate of the photoelectric calculation unit shown in FIGS. 9 and 10, and a negative pulse voltage is applied to the substrate to form a depletion layer in the substrate semiconductor.
  • photons representing the amount of light input enter the depletion region of the semiconductor substrate, and the Si semiconductor substrate absorbs a photon and excites an electron-hole pair.
  • the photoelectron accelerates to the channel and obtains sufficiently high energy. If the energy is high enough, it can enter the charge-coupled layer under the action of the gate oxygen electric field to complete charge storage. After storing photoelectrons in the charge-coupled layer, the drain current and threshold voltage of the floating gate MOSFET will change during reading.
  • ⁇ V T is the change in threshold voltage
  • Q e is the amount of single electron charge
  • C CG is the capacitance from the control gate to the floating gate
  • N elec is the number of photoelectrons in the storage layer.
  • the number of photoelectrons in the optoelectronic storage layer can be estimated by measuring the change in threshold voltage before and after exposure.
  • the formula is as follows:
  • W and L respectively represent the gate width and gate length of the floating gate device
  • H is the thickness of the floating gate
  • t IPD is the thickness between the floating gate and the gate in the device unit
  • ⁇ 0 is the vacuum dielectric constant
  • ⁇ 0x is Relative permittivity
  • ⁇ I DS can be expressed as follows:
  • the storage number of photoelectrons can also be obtained by measuring the change of the drain current in the linear region.
  • drain-source current I d in the final readout area is:
  • the drain-source current I d in the readout area as the readout is simultaneously affected by N as the optical input, V G and V DS as the electrical input, and naturally contains multiplication
  • the operation relationship described above can be used to design an operation device that can realize various functions.
  • the biggest difference of the third embodiment lies in: because the storage carrier photoelectron in the device unit of the optical input of this solution is stored in the isolated charge-coupled layer, it has Very long holding time, up to 10 years, and the optical input signals of the solutions described in the first and second embodiments above can only be maintained for seconds, so as an integrated storage and computing device, it has a greater Advantage.
  • the most basic structure of the photoelectric calculation unit includes only one output terminal, but if the substrate under the charge-coupled layer is divided into a plurality of parallel independent sources and drains, In addition, the number of small MOSFETs with equal device parameters can expand the number of output terminals. If the same V DS is given to the multiple small MOSFETs, the same output of multiple channels of the photoelectric calculation unit can be obtained.
  • the photoelectric calculation unit based on the solution described in the second embodiment described above will also be described later.
  • the photoelectric calculation unit according to the fourth embodiment of the present invention will be described with reference to FIGS. 13 and 14.
  • FIG. 13 there is a photodiode and readout tube as the photogenerated carrier collection and readout area, where the photodiode is formed by ion doping and is responsible for light sensitivity.
  • the N area of the photodiode is connected to the control gate of the readout tube and the source end of the reset tube through the optoelectronic coupling lead as the coupling area, and a positive voltage pulse is applied to the drain end of the readout tube as the readout current Driving voltage; before exposure, the reset tube is opened, and the drain voltage of the reset tube is applied to the photodiode, so that the photodiode as the collection area is in a reverse bias state, and a depletion layer is generated; during exposure, the reset tube is turned off, The photodiode is electrically isolated.
  • the control gate potential begins to decrease, which in turn affects the electron concentration in the channel of the readout tube.
  • the read tube is responsible for reading, and a positive pulse voltage is applied to its drain end, and the source end is connected to the drain end of the address tube. During reading, the address tube is opened, and a current is generated in the read tube.
  • the drain voltage of the reset tube, the drain voltage of the read tube and the number of incident photons affect the electrons in the channel of the read tube as the electrons that are combined by the light input and the electric input, and are output in the form of current, in which reset
  • the tube drain voltage and the read tube drain voltage can be used as the electrical input of the device, and the number of incident photons is the optical input of the device.
  • an optoelectronic coupling lead as a coupling region for connecting the photodiode as a collection region in the photogenerated carrier collection and readout region and the readout tube as a readout region, applying the photodiode N region potential to the readout Tube control grid.
  • a reset tube as the so-called carrier control area.
  • a positive voltage is applied to the photodiode through its drain terminal.
  • the reset tube When the reset tube is turned on, the positive voltage will act on the photodiode, causing the photodiode to generate
  • the depletion area is sensitive and can also be used as an electrical input terminal to input one bit of calculation.
  • the addressing tube is used to control the output of the entire arithmetic device as the output current of the output.
  • the photoelectric calculation unit includes a reset tube as the carrier control area, an optoelectronic coupling lead as the coupling area, and as the photogenerated load
  • the photodiode and the readout tube in the flow collection and readout area in addition, also include an addressing tube, which is used to select the rows and columns when the photoelectric computing units are arrayed.
  • the drain end of the reset tube is connected to the power supply, and the power supply voltage V d1 .
  • a high voltage is applied to the gate of the reset tube to turn on the reset tube, and the power supply voltage V d1 is applied to the photodiode.
  • the anode of the photodiode is grounded, and the voltage V PD across the photodiode is:
  • V PD V d1 (3-1)
  • K is a constant related to the diode parameters
  • V bi is the built-in electric field
  • m j depends on whether the diode type is abrupt junction or slow bias junction.
  • R ph is the sensitivity of the photodiode
  • L 0 is the cross-sectional area
  • A is the light intensity. Because the photodiode is isolated, the photoelectrons will accumulate in the depletion region, which has the following ordinary differential equation:
  • m j is a constant. It can be seen that the voltage across the photodiode gradually decreases with the increase in the number of incident photons. When the conventional parameters of the photodiode are brought into it, the curve of the voltage drop between the two ends with time has good linearity. Simplify the above formula to:
  • V (t) (V d1 ) -K * X photo (3-5)
  • X photo is the number of incident photons representing the amount of light input
  • K is the slope of the fitted straight line.
  • V ′ T is the threshold of the read tube itself
  • V d2 is the voltage between the drain and the source of the read tube
  • ⁇ is the channel mobility
  • W and L are the gate width and gate length, respectively.
  • the source leakage current I d of the readout area as the readout amount is simultaneously affected by X photo as the light input amount and V d1 and V d2 as the electric input amount, and is naturally generated
  • the operation relationship including multiplication and addition can be used to design an operation device that can realize various functions.
  • the biggest difference of the optoelectronic operation device unit described in the fourth embodiment is that the unit area is larger, and it needs one photodiode and three MOS tubes to achieve it, and the integration level is low.
  • the most basic structure of the optoelectronic computing unit contains only one output terminal, but if one readout tube is expanded to multiple readouts with multiple gates connected, all device parameters are equal
  • the number of output tubes can be expanded by adding the same number of addressing tubes. If the same V DS is given to the multiple readout tubes, the same output of multiple channels of the photoelectric calculation unit can be obtained.
  • the photoelectric calculation unit based on the solution described in the second embodiment described above will also be described later.
  • the photons entering the photoelectric calculation unit may come from the light emitting unit optically corresponding to the photoelectric calculation unit, or may come from other light sources, such as natural light sources or scenes of objects.
  • the photons entering the photoelectric calculation unit may come from the light emitting unit optically corresponding to the photoelectric calculation unit, or may come from other light sources, such as natural light sources or scenes of objects.
  • a combination scheme of a light-emitting unit array and an optoelectronic computing unit array which includes one or more light-emitting units and one or more optoelectronic computing units.
  • the optoelectronic computing unit and the light-emitting unit are optically One-to-one correspondence to achieve accurate light input to a single optoelectronic computing unit in the array.
  • the light-emitting unit array can be implemented using a high-density small pixel LED array.
  • the light-emitting unit and the calculation unit correspond optically, that is, the light emitted by the light-emitting unit is accurately irradiated to the calculation unit corresponding to the light-emitting unit.
  • the light emitted by the light emitting unit is irradiated to the calculation unit. If a light emitting unit such as 10 * 10 is used to form a light emitting array and the same number of calculation units are used to form a calculation array, the light emitted by each light emitting unit in the light emitting array needs to be calculated according to specific calculations According to the demand, the corresponding one or more calculation units are accurately irradiated. If the calculation function realized by this array is matrix vector multiplication, the light emitted by each light-emitting unit is required to be accurately irradiated to each calculation unit. This precise light input can be achieved through the following four preferred embodiments:
  • one method is to directly make the light-emitting unit array close to the surface of the device array.
  • the light-emitting array uses a small pixel LED screen, as shown in FIG. 15.
  • the ideal light-emitting unit emits a spherical wave.
  • the distance is close enough, it can be considered that the light emitted by the light-emitting unit is only transmitted to the surface of the device directly below it, thus achieving a one-to-one correspondence between the light source and the device.
  • the optical structure between the luminous array and the computing array that realizes the focusing function can be a lens.
  • the most common solution is to use a lens.
  • the optical one-to-one correspondence between the light-emitting unit and the photoelectric calculation unit can also be achieved in this way, as shown in FIG. 17.
  • the optical structure that realizes the focusing function between the light-emitting array and the computing array may also be an optical fiber cone.
  • the fiber cone is a microstructure that can realize one-to-one correspondence between the light-emitting unit and the photoelectric calculation unit, and its function is similar to that of optical fiber.
  • the optical fiber can be understood as an optical fiber array formed by multiple strands of dense light. If a fiber cone array is used to link the light emitting unit and the optoelectronic computing unit, a one-to-one correspondence between the light emitting unit and the optoelectronic computing unit can be well achieved.
  • the general structure is shown in the figure. 18.
  • the transfer function is high, and the one-to-one correspondence of the fiber cone can effectively suppress the optical crosstalk.
  • the size of a single photoelectric calculation unit will be as small as possible while taking into account other indicators, while the size of the LED pixel is currently only about 8um.
  • a funnel-shaped optical fiber cone can be used to connect the two units. The general structure is shown in FIG. 19.
  • the driving of the light-emitting unit is controlled by the light input control part in the digital control system.
  • the light-emitting unit is driven by a constant current sent by the driver, keeping the light intensity unchanged, and adjusting the light-emitting time to realize the input of different amounts of light input. If there is only one calculation unit and one light-emitting unit, the light input control part converts the data required to be input into the calculation unit through the light input into the pulse width of the light-emitting unit's light-emitting time, depending on the type of calculation unit used, for example, if Using the specific calculation unit as described in the first embodiment above, the larger the light input amount, the shorter the light emission duration of the driven light emitting unit should be.
  • a single photoelectric calculation unit can implement addition or multiplication operations. If multiple photoelectric calculations are combined into an array, the above light-emitting units corresponding to the photoelectric calculation unit are also formed into an array , You can complete one or more sets of addition or multiplication operations. At the same time, through the connection of the leads, if the output ends of the two photoelectric calculation units are connected to make the output current converge into a current, it is equivalent to the realization of one addition .
  • the connection of the lead and the arrangement of the photoelectric calculation unit can be changed to create a calculation array that implements specific operations.
  • the present invention proposes a variety of specific embodiments of photoelectric calculation devices and photoelectric calculation methods.
  • the light-emitting unit and the photoelectric calculation unit described above including the preferred first to fourth embodiments
  • two Addition of bit addends are used.
  • the biggest advantage of the adder according to the present invention is that it only needs a single photoelectric calculation unit and a light-emitting unit to realize the addition operation of two addends, and the integration is relatively high.
  • the number of output terminals of this adder depends on the number of output terminals of the photoelectric calculation unit used, for example, if the photoelectric calculation unit with two output terminals described above is used, the adder also has two output terminals As an example, the photoelectric calculation unit with one output terminal is adopted by default in the four schemes described in detail below.
  • V G is the voltage on the control gate representing the carrier control region
  • t is the voltage on the control gate representing the carrier control region
  • ⁇ is the voltage on the control gate representing the carrier control region
  • q is the relationship between X photo and V G .
  • X photo represents the input quantity of the optical input terminal, which is the first addend
  • V G represents the input quantity of the electrical input terminal, which is the second addend
  • the output current I d in the readout area of the carrier collection and readout area is the result of the addition operation, which is equivalent to the calculation described in (3-1-2):
  • a, b, k and c are constants.
  • the biggest difference of the solution 2 based on the photoelectric calculation unit of the second embodiment is that the P-substrate device is replaced by an N-substrate device, so it serves as the control gate of the carrier control region
  • the applied voltage on the pole changed from positive to negative.
  • the voltage applied to the N-type substrate as the carrier collection and readout area during exposure changed from negative to positive, but the control gate voltage and incidence
  • the number of photons is still a pair of addition and subtraction. Therefore, it is only necessary to make a few changes when modulating the optical input signal and the electrical input signal, and an addition operation that is substantially similar to the solution of the first embodiment can still be achieved.
  • N elec is the number of electrons entering the charge-coupled layer as the coupling region
  • V G is the voltage on the control gate as the carrier control region
  • N elec represents the input quantity at the optical input terminal, which is the first addend
  • V G represents the input quantity at the electrical input terminal, which is the second addend
  • the voltage between the drain and the source in the readout area of the carrier collection and readout area V DS to be a constant value, the carrier-collection area and the read area is read out of the output current I D is the result of the addition operation, i.e., were calculated as equal to (3-3-2) according to the formula:
  • a, b, k and c are constants.
  • V d1 is the drain voltage of the reset tube as the carrier control area
  • K is the slope of the fitted straight line
  • V d2 is the source drain of the read tube Time voltage.
  • X photo represents the input quantity of the optical input terminal, which is the first addend;
  • V d1 represents the input quantity of the electrical input terminal, which is the second addend; at the same time, it serves as a readout tube in the readout area of the carrier collection and readout area If the drain terminal voltage V DS is added to a constant value, then the output current I d in the readout area of the carrier collection and readout area is the result of the addition operation, which is equal to the process described in (3-4-2) The calculation:
  • a, b, k and c are constants.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes a variety of specific implementation schemes of photoelectric calculation devices and photoelectric calculation methods.
  • a light-emitting unit and a multi-control area photoelectric calculation unit By using a light-emitting unit and a multi-control area photoelectric calculation unit, at least two-digit addition operation is realized.
  • the biggest advantage of this adder is that it not only needs a single photoelectric calculation unit to realize the addition operation, and the number of input addends is not limited to two, but it needs the support of the process, especially the use of the above first, second,
  • the multi-control gate parameters must have high uniformity.
  • the number of output terminals of this adder depends on the number of output terminals of the photoelectric calculation unit used. For example, if the above photoelectric calculation unit with two output terminals is used, the adder also has two output terminals. Among the four schemes described, the photoelectric calculation unit with one output terminal is taken by default as an example.
  • V G1 to V Gn represent the input voltages on the n control gates respectively, which are the electrical input quantities of multiple electrical input terminals, and k 1 to k n are the multi-gate input weights related to the area of the n control gates, respectively. It is not difficult to see from (4-1-2) that the voltage on each control gate and the amount of light input X photo are naturally a relationship of addition and subtraction, so the modulation of X photo and V G1 to V Gn can be used Addition.
  • X photo represents the input quantity of the optical input terminal, which is the first addend;
  • V G1 to V Gn represent the multiple input quantities of the electrical input terminal, which is the second to nth addend; at the same time, the carrier collection and readout area If the voltage V DS between the drain and the source of the readout area is given a constant value, the output current I d of the carrier collection and readout area in the readout area is the result of the addition operation, which is equal to (3-1-2 )
  • a, b, k and c are constants.
  • Option 2 the biggest difference between Option 2 is that the P substrate device is replaced by an N substrate device, so the voltage applied to the multi-gate control gate as the carrier control region changes from a positive voltage For negative pressure, the voltage applied to the N-type substrate as the carrier collection and readout area during exposure changes from negative pressure to positive pressure, but the multiple voltages of the multi-gate and the number of incident photons are still one
  • it is only necessary to make some changes in the modulation of the optical input signal and the electrical input signal and it is still possible to implement the addition operation of multiple addends that are generally similar to Scheme 1.
  • V G1 to V Gn represent the input voltages on the n control gates respectively, which are the electrical input quantities of multiple electrical input terminals, and k 1 to k n are the multi-gate input weights related to the area of the n control gates, respectively. It is not difficult to see from (4-2-1) that the voltage on each control gate and the amount of charge N that the photoelectrons enter into the charge coupling layer representing the coupling region are inherently a relationship of addition and subtraction. For the modulation of G1 to V Gn , the above relationship is used for addition.
  • N represents the input quantity of the optical input terminal, which is the first addend
  • V G1 to V Gn represent the multiple input quantities of the electrical input terminal, which is the second to nth addend;
  • the carrier collection and reading area read be a constant value of the voltage V DS between the drain-source region, the carrier collection region and a readout output current I D read-out zone is the result of operation, as carried out it is equal to (4-3-2)
  • a, b, k and c are constants.
  • V d1 to V dn represent the voltages of the drain terminals of n reset tubes, respectively, and are the electrical input quantities of multiple electrical input terminals
  • k 1 to k n are the multi-gate input weights related to the channel resistance of the n reset tubes, respectively. It is not difficult to see from (4-4-1) that the voltage at the drain end of each reset tube and the light input amount X photo are naturally in the relationship of addition and subtraction, so the modulation of X photo and V d1 to V dn can be used to Addition.
  • X photo represents the input quantity of the optical input terminal, which is the first addend;
  • V d1 to V dn represent the multiple input quantities of the electrical input terminal, which is the second to nth addend;
  • the carrier collection and readout area drain-source region of the read-out value to be a constant voltage V DS, and the results of the read-collection region of the read-out zone is the output current I D then adding the carrier, i.e. made equal to (4-4-2 )
  • a, b, k and c are constants.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off. There is no need to re-enter the optical input for the next calculation.
  • the present invention proposes a variety of specific implementation schemes of photoelectric calculation devices and photoelectric calculation methods.
  • the addition of at least two digits is realized Operation.
  • the biggest advantage of the scheme of this adder is that it uses the characteristics of high optical input accuracy.
  • An optoelectronic computing unit only undertakes the input of one optical signal, and the electrical signal is only given a constant value, which is conducive to the improvement of the calculation uniformity; in addition, if there is Fixed calculation errors similar to fixed image noise or device uniformity can also be corrected by changing the constant value at the electrical input.
  • the number of output terminals of this adder depends on the number of output terminals of the photoelectric calculation unit used. For example, if the photoelectric calculation unit with two output terminals described above is used, the adder also has two output terminals. In the following detailed description, a photoelectric calculation unit with an output terminal is taken as an example by default.
  • X photon is the number of effective photons incident on the photoelectric calculation unit. If the output ends of two units with the same parameters are connected in parallel, the output current is converged and the two photoelectric calculation units are given different light input amounts X photo , But given the same electrical input terminals V G and V DS , the above formula is changed to:
  • X photo1 and X photo2 are the input quantities of the optical input terminals of the two units whose output terminals are connected in parallel. It is not difficult to see from (5-1-2) that the data of the optical input terminals of the two units is naturally a relationship of addition and subtraction. Therefore, by modulating X photo1 and X photo2 , addition can be performed using the above relationship.
  • X photo1 and X photo2 represent the first and second digit addends of the optical input terminal, respectively, while the control grid V G of the two cell units as the carrier control region and the carrier collection and readout region be the drain-source voltage of the read-out zone V DS constant value, then the total output current I D through the aggregated total, and then after the AD conversion, into the control system, to obtain the result of the addition, carried out as equal to (5 -1-3)
  • control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the biggest difference compared to the above scheme 1 is that the P substrate device is replaced by an N substrate device, so the voltage applied to the control gate of the carrier control region is changed from positive pressure It becomes a negative pressure, and the voltage applied to the N-type substrate as the carrier collection and readout area during exposure changes from a negative pressure to a positive pressure, but the data of the optical input terminals of multiple units connected in parallel is still.
  • the relationship of a pair of addition and subtraction so only need to make some changes when the optical input signal and the electrical input constant value modulation, can still achieve the addition operation of multiple addends that are generally similar to Scheme 1.
  • two photoelectric calculation units and light-emitting units are used, as shown in FIG. 23, where a box unit marked with a V character represents a photoelectric calculation unit adopting this scheme 3. .
  • N is the photoelectron that enters the charge-coupled layer as the coupling region.
  • N 1 and N 2 are the input quantities of the optical input terminals of the two output terminals connected in parallel. It is not difficult to see from (5-3-2) that the data of the optical input terminals of the two units is naturally a relationship of addition and subtraction. Therefore, by modulating N 1 and N 2 , addition can be performed using the above relationship.
  • N 1 and N 2 respectively represent the first and second addends of the optical input terminal, and at the same time, the two cells of the control gate V G as the carrier control area and the carrier collection and readout area be the drain-source voltage of the read-out zone V DS constant value, then the total output current I D through the aggregated total, and then after the AD conversion, into the control system, to obtain the result of the addition, carried out as equal to (5 -3-3)
  • control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • X photo is the photoelectrons collected in the photodiode as the readout area in the carrier collection and readout area, if the output ends of two units with the same various parameters are connected in parallel, the output current will converge , And give two photoelectric computing units different light input X photo , but given the same electrical input terminal input V d1 and V d2 , the above formula is changed to:
  • X photo1 and X photo2 represent the first and second digit addends of the optical input terminal, respectively, and the drain voltage V d1 of the reset tube as the carrier control area of the two units, and as the carrier collection and reading drain voltage V d2 is read out of the tube in the region of the read-out zone to be constant, then the total output current I D through the aggregated total, and then after AD conversion, into the control system, to obtain the result of the addition, It is equal to the calculation as described in (5-4-3):
  • control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the number of addends can be freely selected.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and the optical input does not need to be re-entered in the next calculation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a light-emitting unit and the photoelectric calculation unit described in the above embodiment a multiplication operation of a two-digit multiplier is realized.
  • the biggest advantage of the solution of this multiplier is its high degree of integration.
  • a single device can achieve multiplication, but it only supports multiplication of two inputs, and dual analog inputs have limited calculation accuracy.
  • the number of output terminals of this multiplier depends on the number of output terminals of the photoelectric calculation unit used, for example, if the photoelectric calculation unit described in the above embodiment having two output terminals is used, the multiplier also has two outputs In the detailed description below, the photoelectric calculation unit with an output terminal is adopted by default.
  • the source-drain output current meets the formula:
  • V DS is the drain voltage of the P-type substrate representing the carrier collection and output regions, because the relationship between them is inherently multiplicative Therefore, by modulating X photo and V DS , the relationship between the two can be used to perform multiplication:
  • X photo represents the input quantity of the light input terminal, which is the first multiplier
  • V DS represents the input quantity of the electrical input terminal, which is the second multiplier
  • the control gate voltage V G of the carrier control region is given a constant value
  • I is the output current carrier collection results and a readout of the read-out zone in the region D of the multiplication, i.e. equivalent was calculated as (6-1-2) according to the formula:
  • a, b, and k are constants.
  • the second scheme the biggest difference compared to the first scheme is that the P substrate device is replaced by an N substrate device, so the voltage applied to the control gate of the carrier control region is changed from positive pressure Becomes a negative pressure, the voltage applied to the N-type substrate as the carrier collection and readout area during exposure changes from a negative pressure to a positive pressure, but the drain voltage of the carrier readout area and the number of incident photons It is still a relationship of a pair of multiplications, so you only need to change the control gate voltage and the N-type substrate voltage, and you can still achieve a multiplication operation that is similar to the first scheme.
  • the source-drain output current meets the formula:
  • N elec is the photoelectron collected in the charge-coupled layer as the coupling region
  • V DS is the drain voltage of the P-type substrate representing the carrier collection and output regions
  • N elec represents the input quantity of the optical input terminal, which is the first multiplier
  • V DS represents the input quantity of the electrical input terminal, which is the second multiplier
  • the control gate voltage V G of the carrier control region is given a constant value, then I is the output current carrier collection results and a readout of the read-out zone in the region D of the multiplication, i.e. equivalent was calculated as (6-3-2) according to the formula:
  • a, b, and k are constants.
  • the source-drain output current meets the formula:
  • X photo represents the input quantity of the optical input terminal, which is the first multiplier
  • V d2 represents the input quantity of the electrical input terminal, which is the second multiplier
  • the reset terminal drain voltage V d1 of the carrier control area is constant
  • output current I D is the result of the multiplication of the carrier collection region and read out read-out zone, i.e., were calculated as equal to (6-4-3) according to the formula:
  • a, b, and k are constants.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a light-emitting unit and the photoelectric calculation unit described in the above embodiment a multiplication operation of a two-digit multiplier is realized.
  • the biggest advantage of this multiplier solution is that the electrical input is changed to a digital serial input, which has a high calculation accuracy.
  • the disadvantage is that the serial input and output of data affect the calculation speed, and the control system needs to participate in auxiliary operations.
  • the number of output terminals of this multiplier depends on the number of output terminals of the photoelectric calculation unit used, for example, if the photoelectric calculation unit described in the above embodiment having two output terminals is used, the multiplier also has two outputs In the detailed description below, the photoelectric calculation unit with an output terminal is adopted by default.
  • FIG. 24 the calculation diagram is shown in Figure 24.
  • the box unit marked with the V character in the figure represents the photoelectric calculation unit using the first scheme, where A is input through the electrical input terminal and W is through the light Input input.
  • A A 0 A 1 A 2 ?? A m-1 (7-1-1)
  • m depends on the bit width of the electrical input data.
  • the binary data of A is bit-wise, and the n binary data are serially input into the control gate as the carrier control region in the form of a modulated voltage.
  • the source-drain output current meets the formula:
  • X photo represents the input quantity of the optical input terminal, which is the first multiplier;
  • the serial input V G represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it is collected and read out as a carrier
  • the source-drain voltage V DS of the P-type substrate in the region is given a constant value.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the second scheme the biggest difference compared to the first scheme is that the P substrate device is replaced by an N substrate device, so the voltage applied to the control gate of the carrier control region is changed from positive pressure Becomes a negative pressure, the voltage applied to the N-type substrate as the carrier collection and readout area during exposure changes from a negative pressure to a positive pressure, but on the control gate of the carrier control area
  • the output binarization voltage and the number of incident photons are still a pair of multiplications. Therefore, only a slight change is needed to the control gate voltage and the N-type substrate voltage, and the multiplication operation similar to the first scheme can still be achieved.
  • FIG. 24 The box unit marked with the V character in the figure represents the photoelectric calculation unit adopting the third scheme, where A is input through the electrical input terminal and W is through the optical Input input.
  • A A 0 A 1 A 2 ?? A m-1 (7-3-1)
  • m depends on the bit width of the electrical input data.
  • the binary data of A is bit-wise, and the n binary data are serially input into the control gate as the carrier control region in the form of a modulated voltage.
  • the source-drain output current meets the formula:
  • N elec is the number of photoelectrons in the charge-coupled layer
  • V G is the voltage representing the control gate.
  • N elec represents the input quantity of the optical input terminal, which is the first multiplier;
  • the serial input V G represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it is collected and read out as a carrier
  • the source-drain voltage V DS of the P-type substrate in the region is given a constant value.
  • R kW (A 0 * 2 0 + A 1 * 2 1 + A 2 * 2 2 +... + A m * 2 m-1 + a) (7-3-3)
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the box unit marked with the V character in the figure represents the photoelectric calculation unit adopting the fourth scheme, in which A is input through the electrical input terminal, W is through the light Input input.
  • A A 0 A 1 A 2 ?? A m-1 (7-4-1)
  • m depends on the bit width of the electrical input data.
  • the binary data of A is bitwise, and the n binary data are serially input in the form of a modulated voltage to the drain end of the reset tube as the carrier control area .
  • the source-drain output current meets the formula:
  • V d1 is the voltage representing the control gate, when the control gate input binarization data is 0, it is equal to whether such that the input data X photo optical input terminal is equal to the number, it is sufficient such that the output current I D 0 is equal to the voltage value; when the control gate input binary data is 1, i.e. equal to the input voltage of the constant control gate.
  • V d1 Because when V d1 is 0, there is no conductive channel in the readout tube, the current is 0, and the output result is 0, which is consistent with the multiplication result of the electrical input data 0 and the optical input data X photo ; when V d1 is equal to a When the voltage of the channel generated in the output tube, if V d2 is also given a constant value, the output result only depends on the optical input data X photo , and the output result still conforms to the constant value 1 and the result of the optical input input X photo multiplication.
  • X photo represents the input quantity of the optical input terminal, which is the first multiplier;
  • the serial input V d1 represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it is collected and read out as a carrier drain voltage V d2 readout tube area reading zone given a constant value, as the serial input V d1, carrier collection region and a serial read output of the read output current I D through the region
  • AD conversion it is sent to the control system, and the shift and accumulation operations are performed according to the bits input from the electrical input terminal in the control system, and the operation result of multiplication A * W can be obtained. That is equal to the calculation as described in (7-4-3):
  • R kW (A 0 * 2 0 + A 1 * 2 1 + A 2 * 2 2 +... + A m * 2 m-1 + a) (7-4-3)
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a multiplication operation of a two-digit multiplier is realized.
  • the biggest advantage of this multiplier solution is that the electrical input is changed to a digital parallel input, which has a higher calculation accuracy and a higher calculation speed than the second multiplier mentioned above; the disadvantage is that the parallel input of data needs more There are many photoelectric calculation units, and the control system needs to participate in auxiliary operations.
  • the number of output terminals of this multiplier depends on the number of output terminals of the photoelectric calculation unit used, for example, if the photoelectric calculation unit described in the above embodiment having two output terminals is used, the multiplier also has two outputs In the detailed description below, the photoelectric calculation unit with an output terminal is adopted by default.
  • a box unit marked with a V character in the figure represents a photoelectric calculation unit adopting the first scheme, in which A is input through an electrical input terminal, W is input through the optical input terminal.
  • A A 0 A 1 A 2 ?? A m-1 (8-1-1)
  • m is equivalent to the number of units used, depending on the bit width of the data at the electrical input.
  • the source-drain output current meets the formula:
  • X photo represents the input quantity of the optical input terminal, which is the first multiplier;
  • V G represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it is used as the carrier collection and reading area
  • the source-drain voltage V DS of the P-type substrate is given a constant value.
  • the parallel output carrier collection and the output current I D in the read-out area of the read-out area undergo AD conversion before sending.
  • the control system in the control system according to the bit input at the electrical input terminal to shift and accumulate operations, you can get the multiplication A * W operation results. That is equal to the calculation as described in (8-1-3):
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the second scheme the biggest difference compared to the first scheme is that the P substrate device is replaced by an N substrate device, so the voltage applied to the control gate of the carrier control region is changed from positive pressure Becomes a negative pressure, the voltage applied to the N-type substrate as the carrier collection and readout area during exposure changes from a negative pressure to a positive pressure, but on the control gate of the carrier control area
  • the output binarization voltage and the number of incident photons are still a pair of multiplications. Therefore, only a slight change is needed to the control gate voltage and the N-type substrate voltage, and the multiplication operation similar to the first scheme can still be achieved.
  • a box unit marked with a V character in the figure represents an optoelectronic calculation unit adopting the third scheme, where A is input through the electrical input terminal. W is input through the optical input terminal.
  • A A 0 A 1 A 2 ?? A m-1 (8-3-1)
  • m is equivalent to the number of units used, depending on the bit width of the data at the electrical input.
  • the source-drain output current meets the formula:
  • N elec is the number of photoelectrons in the charge-coupled layer
  • V G is the voltage representing the control gate.
  • N elec represents the input quantity of the optical input terminal, which is the first multiplier
  • the parallel input V G represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it is used as the carrier collection and reading area
  • the source-drain voltage V DS of the P-type substrate is given a constant value.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • a box unit marked with a V character in the figure represents a photoelectric calculation unit using the fourth scheme, where A is input through the electrical input terminal. W is input through the optical input terminal.
  • A A 0 A 1 A 2 ?? A m-1 (8-4-1)
  • m is equivalent to the number of units used, depending on the bit width of the data at the electrical input.
  • the source-drain output current meets the formula:
  • V d1 is the voltage representing the control gate, when the control gate input binarization data is 0, it is equal to whether such that the input data X photo optical input terminal is equal to the number, it is sufficient such that the output current I D 0 is equal to the voltage value; when the control gate input binary data is 1, i.e. equal to the input voltage of the constant control gate.
  • V d1 Because when V d1 is 0, there is no conductive channel in the readout tube, the current is 0, and the output result is 0, which is consistent with the multiplication result of the electrical input data 0 and the optical input data X photo ; when V d1 is equal to a When the voltage of the channel generated in the output tube, if V d2 is also given a constant value, the output result only depends on the optical input data X photo , and the output result still conforms to the constant value 1 and the result of the optical input input X photo multiplication.
  • X photo represents the input quantity of the optical input terminal, which is the first multiplier;
  • the parallel input V d1 represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it serves as the carrier collection and readout area
  • the drain voltage V d2 of the read tube in the middle read zone is given a constant value.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a multiplication operation of a two-digit multiplier is realized.
  • the biggest advantage of this multiplier solution is that it implements the bit weight participation operation.
  • the disadvantage is that it is essentially the multiplication of two analog inputs. The accuracy will be lower than the above second and third multiplier solutions.
  • the number of output terminals of this multiplier depends on the number of output terminals of the photoelectric calculation unit used, for example, if the photoelectric calculation unit described in the above embodiment having two output terminals is used, the multiplier also has two outputs In the detailed description below, the photoelectric calculation unit with an output terminal is adopted by default.
  • FIG. 26 A box unit marked with a V character in the figure represents a photoelectric calculation unit adopting the first scheme, in which A is input through an electrical input terminal, W is input through the optical input terminal.
  • A A 0 A 1 A 2 ?? A m-1 (9-1-1)
  • m is equivalent to the number of units used, depending on the bit width of the data at the electrical input.
  • the source-drain output current meets the formula:
  • V G is the voltage representing the control gate
  • V DS is the source-drain voltage of the P-type substrate as the carrier control and output region.
  • V DS and V G and X photo are inherently multiplied. Therefore, the binarized data on the control gate of the P-type substrate between the source and drain input and the parallel input corresponds to
  • the bit weights corresponding to the bits 2 0 , 2 1 , 2 2 ... 2 m-1 are equivalent to the shift operation, and then the accumulation operation is completed directly by the current convergence method, without the need to control the system operation. Complete a complete multiplication operation.
  • X photo represents the input quantity of the optical input terminal, which is the first multiplier
  • the parallel input V G represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it is used as the carrier collection and reading area
  • the source-drain voltage V DS of the P-type substrate gives a modulated voltage equivalent to the corresponding bit weight of the binarized data.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the second scheme the biggest difference compared to the first scheme is that the P substrate device is replaced by an N substrate device, so the voltage applied to the control gate of the carrier control region is changed from positive pressure Becomes a negative pressure, the voltage applied to the N-type substrate as the carrier collection and readout area during exposure changes from a negative pressure to a positive pressure, but on the control gate of the carrier control area
  • the output binarization voltage and the number of incident photons are still a pair of multiplications. Therefore, only a slight change is needed to the control gate voltage and the N-type substrate voltage, and the multiplication operation similar to the first scheme can still be achieved.
  • a box unit marked with a V character in the figure represents an optoelectronic calculation unit adopting the third scheme, where A is input through the electrical input terminal, W is input through the optical input terminal.
  • m is equivalent to the number of units used, depending on the bit width of the data at the electrical input.
  • the source-drain output current meets the formula:
  • N elec is the number of photoelectrons in the charge-coupled layer
  • V G is the voltage representing the control gate.
  • V DS and V G and N elec are inherently multiplied. Therefore, the binarized data on the control gate of the P-type substrate between the source and drain input and the parallel input corresponds to
  • the bit weights corresponding to the bits 2 0 , 2 1 , 2 2 ... 2 m-1 are equivalent to the shift operation, and then the accumulation operation is completed directly by the current convergence method, without the need to control the system operation. Complete a complete multiplication operation.
  • N elec represents the input quantity of the optical input terminal, which is the first multiplier
  • the parallel input V G represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it is used as the carrier collection and reading area
  • the source-drain voltage V DS of the P-type substrate gives a modulated voltage equivalent to the corresponding bit weight of the binarized data.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • FIG. 26 A box unit marked with a V character in the figure represents a photoelectric calculation unit adopting the fourth scheme, in which A is input through an electrical input terminal, W is input through the optical input terminal.
  • m is equivalent to the number of units used, depending on the bit width of the data at the electrical input.
  • the source-drain output current meets the formula:
  • V d1 is the voltage representing the control gate, when the control gate input binarization data is 0, it is equal to whether such that the input data X photo optical input terminal is equal to the number, it is sufficient such that the output current I D 0 is equal to the voltage value; when the control gate input binary data is 1, i.e. equal to the input voltage of the constant control gate.
  • V d1 Because when V d1 is 0, there is no conductive channel in the readout tube, the current is 0, and the output result is 0, which is consistent with the multiplication result of the electrical input data 0 and the optical input data X photo ; when V d1 is equal to a When the voltage of the channel generated in the output tube, if V d2 is also given a constant value, the output result only depends on the optical input data X photo , and the output result still conforms to the constant value 1 and the result of the optical input input X photo multiplication.
  • V DS and V G and X photo are naturally multiplied, so the bit corresponding to the binarized data on the control gate of the drain input of the readout tube and the parallel input Bit weight 2 0 , 2 1 , 2 2 ... 2 m-1 corresponding to the bit, which is equivalent to performing a shift operation, and then the accumulation operation is completed directly by current convergence, which can be completed without the control system operation.
  • a complete multiplication operation
  • X photo represents the input quantity of the optical input terminal, which is the first multiplier;
  • V d1 represents the input quantity of the electrical input terminal, which is the binarized data of the second multiplier; at the same time, it serves as the carrier collection and readout area
  • the drain voltage V d2 of the read tube in the middle read area gives a modulated voltage equivalent to the corresponding bit weight of the binarized data.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a plurality of photoelectric calculation adders described in one of the first, second, and third adders at least two dimensions are at least Vector addition of two vectors.
  • R is the addition operation result
  • X photo is the input quantity of the light input end
  • Y is the input quantity of the electrical input end
  • d, a, b and c are constants related to the unit parameters.
  • Vector addition that is, adding elements corresponding to the serial number of two to-be-added vectors with the same dimension one by one to obtain a result vector with the same dimension as the to-be-added vector.
  • the vector addition operation can be split into k separate addition operations with two two-bit inputs, so using k above-mentioned first adders can form a vector adder, as shown in Figure 27 As shown, where each box with "V adder" written in the middle represents a single first adder as described above.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • R is the addition operation result
  • X photo optical input terminal input Y 1 to Y n is the multi-carrier control area electrical input terminal input
  • b, a, c and k 1 to k n are sum adders Constants related to unit parameters.
  • Vector addition that is, adding elements corresponding to the sequence numbers of two to-be-added vectors of the same dimension one by one to obtain a result vector with the same dimension as the to-be-added vector, and the addition operation of n to-be-added vectors of dimension m is A 1 + A 2 ... + A n as an example:
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • R is the result of the addition operation
  • X 1 to X n are the input quantities of the optical input terminals of multiple individual photoelectric calculation units
  • n is equal to the number of parallel photoelectric calculation units used
  • a, c and k are the parameters of the adder unit Related constants.
  • the above-mentioned third adder is the same as the above-mentioned second adder, and can perform addition operation with an addend greater than 2, so the vector adder composed of the above-mentioned third adder and the vector composed of the above-mentioned second adder are used.
  • the adder scheme is similar and will not be repeated.
  • the input data has storage characteristics, and can be stored in the device for a long time after the light is cut off. There is no need to re-enter the light input during the next calculation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a vector dot product operation of two vectors with at least two dimensions is realized .
  • R is the result of multiplication operation
  • X is the input quantity of the optical input end
  • Y is the input quantity of the electrical input end
  • c, a, b are constants related to the unit parameters.
  • Vector dot multiplication that is, multiplying the elements of the corresponding serial numbers of two to-be-multiplied vectors with the same dimension to obtain a result vector with the same dimension as the to-be-multiplied vector, and the multiplication operation of the to-be-multiplied vector with two dimensions of k B as an example:
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the above-mentioned second, third and fourth multipliers are similar to the above-mentioned first multiplier, support multiplication operation of two-digit multiplier input, use the above three multipliers to form a vector dot multiplier scheme and use the first multiplier
  • the composition of the vector dot multiplier is similar, and will not be repeated again.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • the photoelectric calculation multiplier described in one of the above-mentioned various multipliers the multiplication of two high-bit width multipliers is realized.
  • R is the result of multiplication operation
  • X is the input quantity of the optical input end
  • Y is the input quantity of the electrical input end
  • c, a, b are constants related to the unit parameters.
  • High-bit width multiplication means splitting the two high-bit width multipliers into bits first, and then multiplying them in sequence according to the high and low bits, and then shifting and adding the results to complete the complete high-bit width multiplication operation. Take the two high-bit width multipliers A * B as an example, split the high-bit width multiplier into multiple low-bit width multipliers of bit width k, and then multiply the high and low bits:
  • each box with "V multiplier" in the figure represents one of the above-mentioned first multipliers, and the number of shifts that the output of this multiplier needs to complete in the control system.
  • the solid line represents the data Input, dashed line indicates data accumulation.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the above-mentioned second, third and fourth multipliers are similar to the above-mentioned first multiplier, and support multiplication operation of two-digit multiplier input.
  • the above three multipliers are used to form a high-bit width multiplier and the first multiplication is used.
  • the composition of the high-bit width multiplier is similar and will not be repeated again.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a matrix and a vector whose dimensions conform to the matrix vector multiplication rule are realized Multiplication.
  • this matrix-vector multiplier depends on the number of outputs of the photoelectric calculation unit used. For example, if the photoelectric calculation unit described in the above embodiment with two outputs is used, the matrix vector multiplier also With two output terminals, the photoelectric calculation unit with one output terminal is adopted by default in the detailed description below.
  • the number of photoelectric calculation units to be used in the present invention should be equal to the number of elements in the matrix to be multiplied by default.
  • the matrix contains vectors, that is, if the matrix is 3 rows and 1 column, the number of photoelectric calculation units used is 3, but if The number of photoelectric calculation units is greater than the number of elements in the matrix. If six photoelectric calculation units are arranged in 3 rows and 2 columns, the operation is not affected.
  • the calculation diagram is shown in Figure 29.
  • the box unit marked with the V character represents the photoelectric calculation unit adopting the first scheme, in which the elements in the vector A are input through the electrical input terminal, and the elements in the matrix W are input through the optical input terminal.
  • each element of A is binary converted in the control system:
  • k depends on the bit width of a single element in the vector.
  • the photoelectric calculation units according to the first embodiment described above will be arranged in an array as shown in FIG. 29, where the number of rows of the array is n and the number of columns is m, and the photoelectric calculation of all the same rows of the array
  • the control gates of the cell as the carrier control area are all connected and input the same electrical input data; all the photoelectric calculation units of the same column of the array are used as P of the carrier collection and readout area
  • the output terminals of the type substrate are connected, so that the output currents are concentrated and added.
  • m * n data in the matrix are sequentially input into m * n photoelectric calculation units through the optical input terminal; the elements in the vector are serially input from the control gate connected to the peer unit, the same element is different
  • the binary data of the bits is input sequentially in time-sharing.
  • the binary data of the lowest bit of the element in the matrix and the element of the vector is multiplied by the corresponding bit, which is equal to Performed an operation (13-1-3):
  • the calculation result (13-1-5) is AD converted, it is input to the control system. Because it is the lowest bit, it is shifted to the left by 0 bits, and then the second lower bit of the vector is used as the electrical input data input to the control gate to obtain The second lowest bit of the vector and the matrix vector multiplication result of the matrix are shifted to the left by 1 bit after input into the control system, and vector addition is performed with the lowest bit of the vector and the matrix multiplication result described above, and so on. After the binary data of all bits are sequentially shifted and accumulated after the control system, the final matrix vector operation result is obtained, which is equivalent to the following operations:
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the second, third, and fourth schemes are similar to the first scheme.
  • the multiplication of two multiplier inputs can also be completed through serial input, as described in the second multiplier above, so the previous
  • the matrix vector multiplier composed of the photoelectric calculation unit of the first scheme is used instead of the matrix vector multiplier composed of the photoelectric calculation units of the second, third and fourth schemes.
  • the only difference is that:
  • the collection of the P-type substrate becomes the collection of the charge-coupled layer due to the change of the light input mode, so the light input quantity needs to be re-modulated.
  • the parallel carrier control area is no longer the control gate, but the drain end of the reset tube.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a matrix and a vector whose dimensions conform to the matrix vector multiplication rule are realized Multiplication.
  • the difference between the implementation scheme proposed by the present invention and the above-mentioned serial matrix vector multiplier is that more photoelectric calculation units and light-emitting units are used to form an array, and the binary data of the elements in the vector is input through the parallel input mode, and the operation speed is higher. But more units are needed.
  • this matrix-vector multiplier depends on the number of outputs of the photoelectric calculation unit used. For example, if the photoelectric calculation unit described in the above embodiment with two outputs is used, the matrix vector multiplier also With two output terminals, the photoelectric calculation unit with one output terminal is adopted by default in the detailed description below.
  • the number of photoelectric calculation units to be used in the present invention should be equal to the result of multiplying the number of elements in the matrix to be multiplied by the bit width of a single element by default.
  • the matrix contains vectors, but if the number of photoelectric calculation units is greater than the number of elements in the matrix , Does not affect the operation.
  • each element of A is binary converted in the control system:
  • k depends on the bit width of a single element in the vector.
  • the photoelectric calculation unit according to the above first embodiment will be used, and a total of k * m * n units will be used.
  • the above units will be divided into k groups, with m * n units in each group, and the units in each group will be arranged as
  • the above serial matrix vector multiplier array is the same array, that is, arranged in an array according to the form shown in FIG.
  • each array has n rows and m columns, and all the groups All the photoelectric calculation units in the same row of all the arrays are connected to the control gate as the carrier control area, input the same electrical input data; all the same column photoelectric calculation units of all the arrays of all groups The output ends of the P-type substrate as the carrier collection and readout regions are connected, so that the output currents are converged and added.
  • the other 1st to k-1th arrays input the binarized data from the 1st bit to the k-1th bit of the vector from the control gate of each row, and output them separately.
  • the corresponding matrix vector multiplication result is output from the output terminal, and then the k group of calculation results are AD converted into the control system, and all elements of the i-th array result vector are shifted left by i bits, and then the shift will be completed in the control system.
  • the output results of all subsequent groups are accumulated according to the rule of vector addition, that is, the final matrix vector operation result is obtained, which is equivalent to the following operation:
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the second, third, and fourth schemes are similar to the first scheme, and the multiplication operation of the two multiplier inputs can also be completed through parallel input, as described in the third multiplier above, so the use described above In the first scheme, the matrix vector multiplier composed of the photoelectric calculation unit is changed to use the matrix vector multiplier composed of the photoelectric calculation unit in the second, third, and fourth schemes.
  • the only difference is that:
  • the collection of the P-type substrate becomes the collection of the charge-coupled layer due to the change of the light input mode, so the light input quantity needs to be re-modulated.
  • the parallel carrier control area is no longer the control gate, but the drain end of the reset tube.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • a vector dot multiplier and one of the photoelectric matrix vector multipliers described in 12 an average pooling operation is realized.
  • A is the vector input terminal, that is, the vector data input from the electrical input terminal, is input in a serial manner
  • W is the matrix input terminal, that is, the data input from the electrical input terminal
  • the output result is a vector of m * 1 dimension.
  • Pooling operations include many types of operations, such as average pooling and maximum pooling.
  • the pooling operator described in the present invention is only for average pooling operations.
  • Average pooling that is, averaging, for example (15-1-2)
  • a vector dot multiplier as described above suitable for an input matrix with a data dimension of n columns and 1 row matrix (vector) and n * 1 photoelectric calculation units can be used to complete the above calculation.
  • control system determines the number of elements in the matrix to be pooled, and then in the control system, all the elements of the matrix to be pooled are disassembled, and then recombined into a one-dimensional vector, input from the vector input of the matrix vector multiplier , And then input the same optical input data equivalent to the reciprocal of the number of elements in the matrix to all the elements in the matrix vector multiplier through the optical input end, an output of the output of the matrix vector multiplier is the matrix to be pooled Average pooling operation result.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the above high-bit width multiplier is similar to the above vector dot multiplier, the only difference is that the data at the vector input is parallel input, the operation speed is faster but more photoelectric calculation units are needed. If the above high-bit width multiplier is used to calculate the formula (15-1-3), 4 * K photoelectric calculation units are needed, K is the bit width of the elements in the matrix A to be pooled, and using the above vector dot multiplier to calculate requires only 4 photoelectric calculation units.
  • the optical input data has storage characteristics, and can be stored in the device for a long time after the light is cut off. There is no need to re-enter the optical input during the next operation. It is particularly advantageous for the pooling operation to calculate the average pooling denominator unchanged for multiple operations.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods. By using multiple light-emitting units and the photoelectric calculation units described in the above embodiments, the convolution operation of the matrix is realized.
  • the number of output terminals of this convolution operator depends on the number of output terminals of the photoelectric calculation unit used, for example, if the photoelectric calculation unit described in the above embodiment having two output terminals is used, the convolution operator also With two output terminals, the photoelectric calculation unit with one output terminal is adopted by default in the detailed description below.
  • the rule of the convolution operation is that the to-be-convolved matrix plays one by one under the mapping of the convolution kernel and the elements in the convolution kernel, and then moves the convolution kernel in accordance with the corresponding step size for the next mapping, as shown in FIG.
  • the following steps are required:
  • the initial position of the convolution kernel coincides with the upper left corner of the matrix A, that is, the 3 rows and 3 columns of the convolution kernel a correspond to the 0 , 1, 2 rows, and 0, 1, 2 columns of the matrix A 0 , and then
  • the elements in the product kernel and the elements in the matrix A 0 corresponding to the convolution kernel are multiplied one by one, as in the formula (16-1-3), it becomes 9 multiplication results, and then all the 9 multiplication results Accumulate to get the result of the convolution operation at the current position of the convolution kernel, called R 00 , which is to complete the operation described in (16-1-4):
  • the above-mentioned matrix R which is the convolution matrix A, is the result of a convolution operation with a step size of 1 under the action of the convolution kernel a.
  • the convolution operation is an operation of multiplying and accumulating the corresponding elements of two matrices multiple times, wherein the two matrices of the elements are multiplied two by one, and one of the matrices is
  • the convolution kernel is an amount that is constant in multiple operations
  • the other matrix is an element with a convolution matrix corresponding to the position of the convolution kernel, which is an amount that changes in multiple operations, so the invention described in invention 1 can be used
  • the photoelectric calculation unit adopting the first type of photoelectric calculation unit scheme takes advantage of the advantage that the optical input storage can store data.
  • the optical input terminal is used to input convolution kernel data, and the electrical input terminal is input with convolution matrix data for convolution operation. , Which can greatly improve the energy efficiency ratio and calculation speed. Therefore, the electrical input terminal of the unit is the data input terminal of the convolution matrix to be convolved, and the optical input terminal is the input terminal of the convolution kernel.
  • the convolution operator can also be divided into serial input and parallel input.
  • the main difference is the number of units used and the data input method of the electrical input terminal.
  • the serial input scheme is as follows:
  • the photoelectric calculation unit of the first scheme is used in an amount equal to the number of elements in the convolution kernel, the units are arranged in an array with the same dimension as the convolution kernel, and the carriers are collected and read out.
  • the output terminals of the middle readout area are all connected, and the addition is completed by aggregation.
  • FIG. 33 it is a cell array with a convolution kernel dimension of 3 * 3.
  • a box with V in the middle in Fig. 33 represents an optoelectronic computing unit using the first scheme.
  • the convolution kernel data is input into the unit one by one through the optical input terminal, and then the data corresponding to the position of the current convolution kernel in the matrix is converted into binary, and then serially from the carrier control area
  • the control grid is input into the array, and the output results are aggregated and added to the control system after AD conversion, and then shifted and accumulated, that is, the convolution operation result of the current convolution kernel position is obtained, and then the convolution kernel is moved, Input the pre-stored convolution kernel data using the previous light, and directly re-enter the electrical input data to obtain the convolution operation result corresponding to the next convolution kernel position, and so on, until the convolution kernel facilitates the entire convolution matrix, Then the output convolution results are recombined into a result matrix, that is, all convolution operations are completed.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the second, third, and fourth schemes are similar to the first scheme, and the convolution operation can also be completed by serial or parallel line input. Therefore, the convolution composed of the first scheme photoelectric calculation unit is used as described above.
  • the arithmetic unit instead of using the matrix vector multiplier composed of the photoelectric calculation units described in the second, third, and fourth schemes, can also perform calculations. The only difference is that:
  • the collection of the P-type substrate becomes the collection of the charge-coupled layer due to the change of the light input mode, so the light input quantity needs to be re-modulated.
  • the optical input data has storage characteristics, and can be stored in the device for a long time after the light is cut off. There is no need to re-enter the optical input during the next operation. It is particularly advantageous for the convolution operation to be performed multiple times in the convolution operation.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • serial and parallel matrix vector multipliers By using the above-mentioned serial and parallel matrix vector multipliers, pooling operators and convolution operators, together with corresponding control systems, Speed up the work of neural network algorithm inference.
  • the reasoning of the neural network algorithm is composed of a convolution layer and a fully connected layer, and can perform tasks such as face recognition.
  • the detailed structure of the network is shown in Figure 34, where the convolution layer contains The operations include convolution operations, pooling operations, and nonlinear function operations; the operations included in the fully connected layer include matrix vector multiplication operations, pooling operations, and nonlinear function operations. You can see that in addition to nonlinear function operations, other operations are in The corresponding optoelectronic operation accelerator solutions have been mentioned in the present invention. There are many ways to operate non-linear functions. The most common one is the RELU function. Its function image is shown in Figure 35.
  • the biggest advantage of using optoelectronic computing units for neural network acceleration is the storage characteristics of the optical input.
  • the ALEXnet network is still used as an example.
  • the dimensions of the output data of each layer are fixed values, such as the above-mentioned convolution operator
  • the storage advantage of the optical input data can be used to complete multiple or even a single light All the convolution operations work, which greatly reduces the time and energy consumption required for data exchange between the storage unit and the optoelectronic calculation unit.
  • the existence of a large number of matrix vector multiplications is the most powerless part of the traditional calculation method.
  • the matrix data are fixed weights obtained through training. Once training is completed, the weights The value will not change anymore, so when performing inference operation, the weight value is also input into the photoelectric calculation unit through the light input method, which can greatly improve the operation efficiency.
  • the input data of the ALEXnet network is 227 * 227 * 3 three-dimensional matrix data, which first passes through the convolution layer 1, as described in FIG. 34.
  • convolution layer 1 the size of the convolution kernel is 11 * 11, the number is 96, and the step size is 4 for the convolution operation.
  • the convolution operator scheme as described above, a minimum of 96 convolutions as above Convolution operator with kernel size 11 * 11.
  • the pooling operation in convolutional layer 1 uses average pooling, because the kernel size is 3 * 3, so the number of 9 is an average of 1, so at least one of the 3 * 3 for the pooling operator described above is required. Pooling operator for matrix input.
  • convolutional layer 2 At least 256 convolution operators with a convolution kernel size of 5 * 5 as described above are required, and at least one of the 3 * 3 matrix inputs as described in the pooling operator described above is required. Pooling operator.
  • convolutional layer 5 a minimum of 256 convolution operators as described above for the convolution kernel size of 3 * 3, and at least one pooling operator as described above for the 3 * 3 matrix input .
  • a matrix vector multiplier supporting 4096 * 9216 scale matrix and 1 * 9216 scale vector as described in the above serial and parallel matrix vector multiplier is required at least.
  • a matrix vector multiplier supporting 4096 * 4096 scale matrix and 1 * 4096 scale vector as described in the above serial and parallel matrix vector multiplier is required at least.
  • a matrix vector multiplier supporting a matrix of 1000 * 4096 scale and a vector of 1 * 4096 scale as described in the above serial and parallel matrix vector multiplier is required at least.
  • ALEXnet network accelerator a complete ALEXnet network accelerator can be formed. If you need to increase the calculation speed, you can consider using parallel The input method consumes more calculators and obtains higher calculation speed.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the input of the above calculation amount by optical input can be used The storage characteristics of the optical input are maximized.
  • the present invention proposes specific implementation solutions of various photoelectric calculation devices and photoelectric calculation methods.
  • the acceleration work of the CT algorithm is realized.
  • the number of output terminals of the CT algorithm accelerator depends on the number of output terminals of the photoelectric calculation unit used. For example, if the photoelectric calculation unit described in the above embodiment having two output terminals is used, the CT algorithm accelerator also has two One output terminal, the photoelectric calculation unit with one output terminal is adopted by default in the detailed description below.
  • CT that is, electronic computer tomography, which uses precise collimated X-ray beams, gamma rays, ultrasound, etc., together with a highly sensitive calculator, to make one after another around a part of the human body
  • Cross-section scanning has the characteristics of fast scanning time and clear image.
  • the CT shooting mode and X-ray shooting mode are quite different. As shown in FIG. 36, the X-ray and CT shooting modes for an object are respectively from top to bottom.
  • CT photography that is, the method of judging the internal material division of the fault through the received X-ray intensity that passes through a fault of the object to be observed from different angles, and the received one-dimension of multiple sets of different faults along different angles
  • the algorithm that converts the incident X-ray intensity into two-dimensional multiple sets of two-dimensional material division pictures of different faults is the CT algorithm.
  • the general content of the CT algorithm is as follows. As shown in Figure 37, the cross-sectional view of this tomographic image of an irregularly shaped object in the figure, multiple X-rays pass through it from different angles, of which the ith article passes through it The ray is the ray incident at the angle shown in the figure, and the cross-sectional view of the object is the tomogram that is to be restored by CT shooting and the CT algorithm.
  • This tomogram is divided into pixels, from the first row to the first column. At the beginning of the count, the first pixel in the first row is the first pixel, a total of N pixels, and the j-th pixel is just passed by the i-th X-ray.
  • X-rays are absorbed when passing through objects, and the amount of absorption varies according to the type of substance (water, cell tissue, bones, etc.). By determining the amount of absorption, you can indirectly determine what the object is.
  • different pixel positions correspond to different types of substances, so X-rays will be absorbed to varying degrees after passing through these pixels, and X-rays incident along different angles will pass through different substances , The energy remaining after it exits the object is also different. Definition, the gray value of each pixel in the cross section of the object shown in FIG.
  • Equation (18-1-2) is a multivariate equation system
  • x is the grayscale value of the tomographic pixel to be reconstructed, that is, the amount to be solved, and the others are all known quantities.
  • L is greater than or equal to N . Then this equation has a unique solution, that is, the tomographic image can be restored.
  • equation (18-1-2) is not an equation system composed of L equations with N unknowns, but an equation system composed of 2 equations with 2 unknowns, then these two equations can be expressed as two The two lines in the dimensional plane, because the equation has a solution, the two lines must have an intersection point, and the coordinates of the intersection point is the solution of the system of equations.
  • the method to quickly solve the solution of the system of equations is:
  • the actual physical meaning of is whether the ray passes through the pixel, if it passes, it is 1, and if it does not pass, it is 0, and the emission angle of the CT machine ray is mostly a fixed angle. Therefore, for multiple CT shooting ,
  • the system matrix ⁇ is mostly a fixed value, therefore, by using the storage characteristics of the optical input end of the photoelectric calculation unit described in the first scheme of invention 1 to input the data in the system matrix, the energy efficiency ratio and the operation speed will be greatly improved .
  • the core of formula (18-1-3) is vector-vector multiplication Therefore, using the cell array as shown in FIG. 39 can speed up the calculation of this part.
  • Each box with V in the middle of the figure represents an optoelectronic computing unit using the first scheme, with a system matrix size of N * L, CT algorithm with the number of X-rays as an example, assuming that the electrical input terminal data is serial input, the number of photoelectric calculation units to be used is N * L, and the number of photoelectric calculation units are arranged in N rows Column L, and the output ends of the P-type substrates as the carrier collection and readout area of all cells in the same column are connected together, so that the operation results are aggregated and added;
  • the control gates of the zones are independent of each other.
  • the control system may be a digital circuit, or various logic control units such as a computer, a single-chip microcomputer, and an FPGA.
  • the second, third, and fourth schemes are similar to the first scheme.
  • the CT algorithm can also be accelerated by serial or parallel line input. Therefore, the first scheme uses the photoelectric calculation unit composed of the first scheme.
  • the CT algorithm accelerator is changed to use the matrix vector multiplier composed of the photoelectric calculation units described in the second, third, and fourth schemes. The only difference is that:
  • the collection of the P-type substrate becomes the collection of the charge-coupled layer due to the change of the light input mode, so the light input quantity needs to be re-modulated.
  • the present invention proposes specific implementation schemes of various photoelectric calculation devices and photoelectric calculation methods.
  • the above-mentioned high-bit width multiplier and the photoelectric adder described in one of the first, second, and third adders two Multiplication of single precision floating point numbers.
  • Single-precision floating-point number that is, to express a real number with a fractional part in a manner similar to scientific notation
  • a single-precision floating-point number has a bit width of 32 bits, of which 1 sign bit is expressed by a binary number; 8-bit exponent Digits, the size of the part on the left of the decimal point is expressed by 8-bit binary numbers; the 23-bit mantissa, the size of the number of the right part of the decimal point is expressed by 23 binary numbers, as in formula (19-1-1):
  • A (A) sign bit (A) exponent bit (A) mantissa bit
  • the optoelectronic single-precision floating-point multiplier described above requires three operations of sign bit multiplication, exponent bit addition, and mantissa bit multiplication.
  • the sign bit only needs to be judged by the general logic, and the addition of the exponent 8-bit wide addend is subtracted by 01111111, and only the first, second, and three adder operations as above are required; and the mantissa bit
  • the multiplication of the two 23-bit wide multipliers because the multiplier bit width is large, it is necessary to use the above high-bit width multiplier for operation.
  • the photoelectric calculation multiplier described in one of the above multipliers is usually applicable At the optical input terminal, the input precision is about 8 bits, and the multiplier of the multiplier input with a maximum of 16 bits is not exceeded.
  • the control system divides the two single-precision floating-point numbers to be multiplied into a sign bit, an exponent bit, and a mantissa bit, and the sign bit is judged by the control system to be positive and negative.
  • the mantissa is input to the two addend input ends of the photoelectric adder.
  • the results of the three parts are returned to the control system, and recombined into a single-precision floating-point number in the control system, that is, a complete single-precision floating-point multiplication is completed.
  • the invention utilizes the photoelectric characteristics of semiconductor materials, and discloses a basic photoelectric hybrid operation method and operation device. Since the semiconductor material can have a higher sensitivity to incident photons, a longer optical signal storage time, and itself is easier to improve the integration, the present invention has a substantial improvement in computing technology.
  • the optical input data has storage characteristics, which can be stored in the device for a long time after the light is cut off, and there is no need to re-enter the optical input during the next operation.
  • the invention provides a digital logic control system of a photoelectric calculation module, which is used to control the state and data input and output of the photoelectric calculation module.
  • bit width of each element in the matrix W is 8 bits
  • at least 8 groups of n columns and m rows of photoelectric computing arrays are required to form a parallel input matrix vector multiplication module capable of computing A * W.
  • the digital control array of the optoelectronic calculation module is divided into the following parts: data input part, optical input control part, light receiving control part, electric input receiving control part, output control part and self-check control part.
  • the controlled objects are: Eight groups of n * m photoelectric operation arrays and power modules that supply power to these arrays, and drivers that drive the light-emitting arrays.
  • the power supply module can provide various voltages required by each functional area of the optoelectronic arithmetic array in various states such as receiving optical signals, receiving electrical signals, arithmetic and output, and resetting optical signals.
  • -3V needs to be added to the P-type substrate when receiving optical signals
  • 4V or 0V needs to be added to the control gate when receiving electrical signals
  • P-type substrate when outputting
  • the read-out area MOSFET needs to add 0.5V between the source and drain, and the substrate needs to add 1V during reset, then the power supply module that supplies it needs to provide at least -3V, 0V, 1V, 4V voltage, and in Under the control of digital control logic, the voltage is given to the corresponding parts of the cells in the array at the required moment.
  • the matrix data W and the vector data A are input to the data input section, and the data input section is sent to the optical input control section and the electrical input reception control section and pre-stored in the register.
  • Each element in the matrix data W in the register of the light input control part is converted into the time for the light emitting unit in the light emitting array to emit light through the light input control part, and sent to the driver of the light emitting array, the driver is converted into a pulse to drive the light emitting array Illuminate to realize light input.
  • the light receiving control part sends a status signal corresponding to the received light signal to the power supply module.
  • the power supply module changes the power supply voltage to put the cells in the computing array into the light receiving state.
  • the power module gives the P-type substrate -3V, the source and drain of the readout area are floating, and the control gate is 0V, so that a depletion layer is generated in the P-type substrate When a photon is incident again, it will absorb the photon to generate photo-generated carriers to complete the light input.
  • the driver is controlled by the light input control part to stop the light; then the electric input receiving part sends the state signal of the electric input to the power supply module, so that the units in the computing array enter the electric input state, and the Vector data A is input into the carrier control area of the computing array in parallel.
  • the power module needs to give the control gate a voltage of 0V or 3V at this time. The specific value of 0V or 3V is controlled by the electrical input receiving control section.
  • the input amount should be 0, then 0V voltage is applied to the control gate; if the electrical input amount is 1, then 3V voltage is applied to the control gate, at the same time, the P-type substrate remains applied -3V unchanged, the source and drain of the readout area are still Floating.
  • the output control section sends a status signal that outputs the calculation result to the power module, so that the photoelectric calculation unit enters the output state.
  • the power module needs to give The voltage difference between the source and drain of the readout region is 0.5V, and the voltage of 0V / 3V on the P-type substrate -3V and the control gate is maintained. After the output current as the operation result is converged, it first enters AD conversion, and the output control part sends a signal to start AD conversion to the AD converter.
  • the power module After the AD converter completes the conversion, the converted result and the conversion end signal are output from the output terminal to the output control Part, after receiving the conversion end signal, the output control part sends the received conversion result to the shifter and accumulator for shifting and accumulating to obtain the final A * W operation result vector and store the result in the register , And send the status signal of the end of the operation to the power module, the power module ends the operation.
  • the power module needs to cancel the 0.5V voltage difference between the source and drain of the readout area and the 0V / 3V electrical input on the control gate at the end of the operation. Value signal, but keep the -3V of the P-type substrate unchanged to maintain the "storage" of the optical input signal, waiting for the next operation.
  • the optical input data reset signal is sent to the power module through the output control section, and the power module performs light on the cells in the computing array Input data reset.
  • the power module needs to give the P-type substrate 1V at this time and control the gate at 0V, while keeping the source and drain of the readout area floating.
  • the output control part sends a reset completion signal to the power supply module. The power supply module stops supplying power and waits for the next light input.
  • the self-checking process occurs before the operation of the computing module, and is used to check whether the cells in the computing array are damaged.
  • the self-test control part sends a status signal to the power module.
  • the power module starts self-test on the first row of all columns of all groups. For example, if the photoelectric device of the first embodiment of invention 1 is used For the calculation unit, the power module needs to first give the control gate a voltage of 3V, a voltage of 0.5V between the source and drain in the readout area, and the output current is output to the self-test control part through the output terminal of each column.
  • the first cell of this column is judged to be damaged; after that, the voltage of 3V on the control gate is removed, and the source and drain of the readout area remain at 0.5V, and the output of each column is judged by the self-test control part For the current, if it is found that there is still a current after the 3V voltage of the control gate is cut off at the output end of the column, the first cell in the column is judged to be damaged.
  • the self-check control part controls the line feed, and starts the self-check on the second line.
  • the self-check conditions are the same until the self-check of all lines is completed, that is, all the self-checks are completed.
  • digital control logic can be a variety of digital circuits, microcontrollers, FPGAs and so on.
  • This embodiment provides a single measured photoresponse curve using the photoelectric calculation unit according to the first embodiment described above, and with the aid of the photoresponse curve measured on the machine as a model of a single photoelectric calculation unit, built as described above
  • the model of the parallel input matrix vector multiplier and the model of the convolution operator as described above, and with the aid of the built model components, become a complete neural network accelerator built using the optoelectronic calculation unit according to the first embodiment described above.
  • use simulation software to try to simulate a complete AlexNet-like network (different from the standard AlexNet network mentioned in the above neural network accelerator solution) to classify and predict the pictures in the CIFAR-10 data set. And evaluate the accuracy of the operation results.
  • a single photoelectric computing unit measured results and network simulation analysis
  • the measured light response curve of the photoelectric calculation unit according to the first embodiment used is shown in FIG. 41, where the abscissa is the number of incident photons X characterized by the exposure time, and the ordinate is the carrier collection and In the P-type substrate of the readout area, the operation result size of the output end of the MOSFET in the readout area is output in the form of current.
  • the control gate of the carrier control area that is, V G plus 3V voltage, P-type substrate plus -3V voltage, and give the appropriate output voltage when the source-drain voltage corresponds to the output result.
  • the structure included in the simulated AlexNet-like network model is shown in FIG. 42.
  • This type of AlexNet network model is composed of six convolutional layers, five pooling layers, and two fully connected layers, and uses ReLU as the activation function.
  • the pooling layer does not use the above pooling operator, but directly assumes that general logic is used to perform the pooling operation.
  • the function realized by this network is target recognition, and the picture data set used is the CIFAR-10 data set.
  • the data set has a total of 60,000 color images, and the size of these images is 32 * 32 * 3, which is divided into 10 categories, each with 6000 images.
  • the accuracy is high or low. Obviously, there are two factors that lead to the inaccuracy of the final recognition result.
  • a network itself, and the recognition errors caused by the imperfect weights obtained through training are not related to the accuracy of inference calculation; the other is because
  • the neural network accelerator model built by the single-tube model of the computing device has a calculation error and
  • the parallel matrix vector multiplier shown in FIG. 31 there are k arrays of size m * n in total, assuming that each array has one additional array under each column AD, and the input value range of the optical input terminal is (-127,127), and the positive optical input value and the negative optical input value are respectively input into different matrices, the AD bit width is nbit, the matrix vector is multiplied by the row of the matrix If the number is m lines, the AD conversion accuracy is:
  • 127 represents the maximum output value of a single photoelectric calculation unit, that is, the result of multiplying the maximum value 127 of the optical input terminal and the binarized maximum value 1 of the electrical input terminal.
  • the smallest unit that can be recognized after AD conversion is 508, and outputs smaller than this value will be truncated, resulting in a certain decrease in accuracy.
  • the convolution operator will also suffer from similar accuracy degradation caused by AD, and will not be repeated.
  • the weight is the matrix data, and the source of the weight is the training of the network.
  • the accuracy of the weight can be customized during training.
  • the accuracy of the weight is considered in equation (21-2) It is 8bit, that is, the range is (-127,127).
  • the results of the weight accuracy on the ideal network without calculation errors are as follows. The result is the accuracy of the target classification when performing inference:
  • the classification accuracy of the neural network accelerator model is 85.4%, which is only 3% less than the ideal accuracy result of 88% without any calculation error, which is less than 3%, which is a higher
  • the precision is enough to accelerate the work of neural network.
  • the delay of a single AD is 20ns
  • the operation delay of each layer of the network is 0.164ms
  • the time required to complete a complete network inference is 1.312ms, which is a few seconds less than the optical input data.
  • the retention time of many years (using the photoelectric calculation unit according to the third embodiment above) is already a fairly short time, even a few seconds of retention time is enough to operate within the time window of one light input Thousands of complete network reasoning.
  • the inference time of the complete network of 1.312ms can easily meet the real-time video surveillance of hundreds of frames, and to achieve this index, regardless of the peripheral logic circuit, at least a total of only Need to use about 2 million photoelectric calculation units, assuming that the area of a photoelectric calculation unit is 3um * 3um, the chip size is less than 5mm * 5mm; according to the actual measurement results of a single photoelectric calculation unit, each photoelectric calculation unit is in the read state
  • the power is only 0.1uW level, the entire network inference takes 1.312ms, each unit only needs to run at most one-eighth time, the leakage current when not running is negligible, so the total power of the chip operation is only To 0.05W. Regardless of power consumption or chip area, with the same computing power, this is unmatched by using GPU to accelerate neural network inference.
  • the following table is a comparison chart of the estimated power consumption, chip area, computing power and manufacturing process of the integrated photoelectric storage and integrated chip and Google's TPU chip.
  • the parameters and performance indicators of the photoelectric storage and integrated chip are derived from theoretical reasoning and Simulation results.
  • the number of operations per second is still much higher than that of the TPU chip, which is mainly due to the computing array in the optoelectronic storage and computing integrated chip
  • the multiplication operation can be completed, and the current collection has completed an addition operation, so a single unit can contribute two operands in a mechanical cycle, which is far superior to the TPU chip, but also leads to the chip
  • the area is also smaller than that of the TPU chip; and another major advantage of the integrated photoelectric storage and calculation chip: the storage characteristics of the optical input, which leads to the photoelectric storage and calculation integrated chip will be much lower in power consumption than the TPU chip; in addition, the above parameters are Based on the 65nm process, Google TPU is the product of the 28nm process, which in turn creates the possibility for the optoelectronic storage and computing core to improve the performance of the device through the reduction of process nodes in the future; finally, it can be

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Abstract

一种光电计算单元、光电计算阵列及光电计算方法，光电计算单元包括一个半导体多功能区结构，半导体多功能区结构，包括至少一个载流子控制区，至少一个耦合区，以及至少一个光生载流子收集区和读出区。

Description

光电计算单元、光电计算阵列及光电计算方法
本申请要求于2018年11月22日递交的中国专利申请第201811398206.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明涉及一种光电计算单元、光电计算阵列及光电计算方法。更具体地，本发明结合了计算领域和半导体器件领域的一些技术，本发明的技术方案可以独立地，或与目前的电子计算技术相结合来进行运算。
背景技术
现有的电子计算机在原理上，根据半导体材料可以对特定的电信号进行传递、加减和倒相等特性，经过统和与集成，可以完成极其复杂的运算。这一计算，事实上已构成现代文明的一个重要基础。
传统的计算机大多采取冯诺依曼架构，然而，冯诺依曼架构存储单元和运算单元的分立，在处理以神经网络算法为代表的一类算法时，因为网络的权值需要被反复调用，存储单元和运算单元的分立就导致了在数据传输上产生了极大的能量消耗，并且影响运算速度。同时，以神经网络算法、CT算法为代表的一系列算法中，需要大量运算矩阵向量乘法，而传统乘法器的规模动辄上万晶体管，这也极大的影响了传统计算在处理此类算法时的能效比和集成度。
为了克服这种限制，人们提出了存-算一体器件。典型的存算一体器件主要为RRAM(忆阻器)和FLASH(闪存)两类，RRAM可以在断电后较长时间内保存受其电输入端输入量影响的电阻值，然而RRAM并不支持标准CMOS工艺生产，其器件的良率和均匀性都得不到保证，这在必须大量使用存-算一体器件组成网络才能加速的神经网络算法中，是不可接受的。而如果要使用FLASH作为存-算一体器件，就意味着单个浮栅管必须存储超过一位的数据，即多值存储，这对于只能使用擦除和编程两种方式改变阈值的传统FLASH是难以做到的。
并且，已知的光运算方法，多为利用光的传播规律来进行光与光学器件相互作用的纯粹光运算。
发明内容
根据本发明的一个方面，提供一种光电计算装置，其采用半导体材料的光电性能，用外界的输入光信号来调制半导体材料中所传输的电信号，以实现加法器、乘法器以及一些高级运算。并且，本装置可以实现高精度的存-算一体功能，单个器件即可以存储光输入端的光信号并在断光后长时间保存。
根据本发明的另一方面，提供一种新的光电计算方法，采用半导体材料的光电性能，用输入光信号来调制半导体材料中所传输的电信号，以实现加法器、乘法器等基本运算的新的机制。
本发明采用半导体材料的光电性能，设计了一种光电计算器件，并公开了由所述光电计算器件组成的多种加法器、乘法器和算法加速器，及其相应的光电运算方法。由此可见，本发明利用半导体材料的光电特性，以及传统光学领域已经普遍使用的技术在计算领域的扩展应用，提出了一种全新的光电计算器件和一类光电计算方法，其可以实现高精度的存-算一体功能，单个器件既可以存储光输入端的光信号并在断光后长时间保存，并且可以实现单个器件即完成乘法运算，非常适合加速以神经网络算法为代表的一类需要“存储参数”的算法。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用于提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对发明的限制，在附图中：
图1是示出根据本发明的光电计算单元的多功能区的基本结构的示意图。
图2是示出根据本发明第一实施例的光电计算单元的正视图。
图3是示出根据本发明第一实施例的光电计算单元的立体示意图。
图4是示出根据本发明第一实施例的光电计算单元的多功能区的配置图。
图5是示出根据本发明第一实施例的光电计算单元的电学模型。
图6是示出根据本发明第二实施例的光电计算单元的正视图。
图7是示出根据本发明第二实施例的光电计算单元的3D示意图。
图8是示出根据本发明第二实施例的光电计算单元的多功能区的配置图。
图9是示出根据本发明第三实施例的光电计算单元的正视图。
图10是示出根据本发明第三实施例的光电计算单元3D的示意图。
图11是示出根据本发明第三实施例的光电计算单元的多功能区的配置图。
图12是示出根据本发明第三实施例的光电计算单元的电学模型。
图13是示出根据本发明第四实施例的光电计算单元的结构示意图。
图14是示出根据本发明第四实施例的所述光电计算单元的多功能区结构示意图。
图15是示出根据本发明的直接投影方案的示意图。
图16是示出根据本发明的发光单元和光电计算单元的集成的示意图。
图17是示出根据本发明的镜头光输入方案的示意图。
图18是示出根据本发明的光纤锥光输入方案的示意图。
图19是示出根据本发明的漏斗状光纤锥方案的示意图。
图20是示出根据本发明的采用光电计算单元的多控制栅极结构的示例之一结构图。
图21是示出根据本发明的采用光电计算单元的多控制栅极结构的示例之一结构图。
图22是示出根据本发明的采用光电计算单元的多控制栅极结构的示例之一结构图。
图23是示出根据本发明的加法器之一的示例的图。
图24是示出根据本发明的乘法器之一的示例的图。
图25是示出根据本发明的乘法器之一的示例的图。
图26是示出根据本发明的乘法器之一的示例的图。
图27是示出根据本发明的向量加法器的示例的图。
图28是示出根据本发明的高位宽乘法器的示例的图。
图29是示出根据本发明的串行矩阵向量乘法器的示意图。
图30是示出根据本发明的并行矩阵向量乘法器计算的示意图。
图31是示出根据本发明的并行矩阵向量乘法器的示意图。
图32是示出根据本发明的卷积运算的示意图。
图33是示出根据本发明的卷积运算单元阵列示意图，其中针对3*3的卷积核。
图34是示出根据本发明的ALEXnet网络的示意图。
图35是示出根据本发明的RELU函数图像的示意图。
图36是示出根据本发明的X光的拍摄方式和CT的拍摄方式的示意图。
图37是示出根据本发明的CT算法的示意图，其中第i条射线穿过第j个像素。
图38是示出根据本发明的CT算法的示意图。
图39是示出根据本发明的串行CT算法加速器阵列示意图。
图40是示出根据本发明的数字控制逻辑的示意图。
图41是示出根据本发明的采用本发明第一实施例的光电计算单元的光响应曲线。
图42是示出根据本发明的仿真用的类AlexNet网络的示意图。
具体实施方式
为了使得本发明实施例的目的、技术方案和优点更为明显，下面将参照附图详细描述根据本发明的各个实施例，在本说明书和附图中，具有基本上相同步骤和元素用相同的附图标记来表示，且对这些步骤和元素的重复解释将被省略。
应理解，所描述的实施例仅仅是本发明的一部分实施例，而不是本发明的全部实施例。基于本发明中描述的实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本发明的保护范围之内。而且，为了使说明书更加清楚简洁，将省略对本领域熟知功能和构造的详细描述。
首先，将参照图1描述根据本发明的光电光电计算单元的多功能区的基本结构的示意图。大体上，根据本发明的光电计算器件单元，包括一个半导体多功能区结构，其中所述半导体多功能区结构，包括一个载流子控制区，一个耦合区，以及一个光生载流子收集和读出区，并且该多功能区可以是多层结 构，也可以是通过多种空间的布置和变换实现同样的光电作用和控制的任何层或区的结构。下文将参照附图详细描述根据本发明的光电光电计算单元的四个优选实施例。
光电运算单元方案
第一实施例
参照图2至5描述根据本发明第一实施例的光电光电计算单元。
如图2和图3的光电光电计算单元的正视图和立体图所示，存在一个作为所述光生载流子收集区和读出区的P型半导体衬底分为左侧收集区和右侧读出区，其中所述左侧收集区用以在衬底上施加一个电压范围为负压的脉冲，或在控制栅上施加一个电压范围为正压的脉冲，使得收集区衬底中产生用于光电子收集的耗尽层，并通过右侧读出区读出收集的光电子数量，作为光输入端的输入量。所述右侧读出区，包含浅槽隔离、N型漏端和N型源端。所述浅槽隔离，位于半导体衬底中部收集区和读出区的中间，所述浅槽隔离通过刻蚀并填充入二氧化硅来形成，以用于隔离收集区和读出区的电信号。所述N型源端，位于读出区内靠近底层介质层的一侧，通过离子注入法掺杂而形成。所述N型漏端，位于半导体衬底中靠近底层介质层与所述N型源端相对的另一侧，同样通过离子注入法进行掺杂法形成。读出时，在控制栅极上施加一正电压，使N型源端和收集区N型漏端间形成导电沟道，再通过在N型源端和N型漏端间施加一个偏置脉冲电压，使得导电沟道内的电子加速形成源漏之间的电流。所述源漏之间沟道内形成电流的载流子，受到控制栅电压、源漏间电压和收集区收集的光电子数量共同作用，作为被光输入量和电输入量共同作用后的电子，以电流的形式进行输出，其中控制栅电压、源漏间电压可以作为器件的电输入量，光电子数量则为器件的光输入量。
此外，存在一个作为所述耦合区的电荷耦合层，用以连接收集区和读出区，使收集区衬底内耗尽区开始收集光电子以后，收集区衬底表面势就会受到收集的光电子数量影响；通过电荷耦合层的连接，使得读出区半导体衬底表面势受到收集区半导体衬底表面势影响，进而影响读出区源漏间电流大小，从而通过判断读出区源漏间电流来读出收集区收集的光电子数量；
此外，存在一个作为所述载流子控制区的控制栅，用以在其上施加一个脉 冲电压，使得在P型半导体衬底读出区中产生用于激发光电子的耗尽区，同时也可以作为电输入端，输入其中一位运算量；
此外，所述P型半导体衬底和所述电荷耦合层之间存在用于隔离的底层介质层；所述电荷耦合层和所述控制栅之间亦存在用于隔离的顶层介质层。
进一步参照图4所示的光电光电计算单元的多功能区的配置图，光电计算单元包括作为所述载流子控制区的控制栅极、作为所述耦合区的电荷耦合层、作为所述光生载流子收集和读出区的P型衬底，并且用于隔离的底层介质层，被设置在所述P型半导体衬底和所述电荷耦合层之间，以及用于隔离的顶层介质层，被设置在电荷耦合层和所述控制栅之间。
应理解，本文中提及的左侧、右侧、上方以及下方只代表在通过图中所示视角观察下的相对位置随观察视角变化而变化，并不理解为对具体结构的限制。
另外，图5是根据本发明第一实施例的光电计算单元的电学模型，根据图5所示的电学模型详细描述该光电计算单元的原理。
如图5所示，左侧收集区等效于一个电容为
Figure PCTCN2019111513-appb-000001
的MOS电容，右侧读出区等效于一个标准的浮栅MOS管。由于设计时，电容C2远小于C1，因此器件工作时读出区对感光区产生的影响忽略不计。
对于一个MOS-电容Si中的电势可以通过解如下泊松方程得到：
Figure PCTCN2019111513-appb-000002
其中，ε SI为硅的介电常数，ρ为P型衬底的体电荷密度。
当作为载流子收集和读出区的P衬底施加一负脉冲，或作为载流子控制区的控制栅上施加一正脉冲时，衬底将处在耗尽状态，开始收集作为光输入信号的光子并产生光电子，对于耗尽区而言ρ＝qN A，其中N A为掺杂浓度。
求解上述泊松方程可以得到：
Figure PCTCN2019111513-appb-000003
其中，x方向为垂直于底层介质层向下的方向，x d为耗尽区深度，q为电子电荷量，V为深度为x处的电势。对于MOS而言，P型衬底表面电势V S即 为x＝0时电势V的值
因此可得：
Figure PCTCN2019111513-appb-000004
求导该式即可得：
Figure PCTCN2019111513-appb-000005
其中E S为表面电场强度，假设衬底电压设为0V，这样感光过程中的控制栅极电势为：
Figure PCTCN2019111513-appb-000006
其中，V G为控制栅电势，解可得耗尽区深度x d为：
Figure PCTCN2019111513-appb-000007
当有光子入射器件时，在耗尽区内产生光电子并且在栅极电场的作用下收集于收集区沟道内，控制栅上的总电荷量Q CG＝N A+Q，Q即为信号电荷量(e-/cm2)，因为此信号电荷在控制栅和P型衬底之间电场的作用下被收集于收集区中，并且因为半导体衬底中载流子的复合需要一定的时间，再加上耗尽区内热激发载流子的存在，因此，此信号电荷将在断光后较长的时间内依旧存储于运算单元当中，实现存-算一体功能。
此时，
Figure PCTCN2019111513-appb-000008
其中，V Q为信号电荷产生的电势总和：
Figure PCTCN2019111513-appb-000009
由上式可以看到随着信号电荷量Q的增大，x d逐渐减小，当Q的值使得V Q＝0时x d即为0，此时表面电势V s＝0，沟道电势不再变化，此时器件到达满阱。
对于右侧的读出区浮栅MOSFET，其沟道电流I d可以表示为：
Figure PCTCN2019111513-appb-000010
其中W和L分别为栅宽栅长，V DS为源漏间电压，V FG为电荷耦合层电势，其大小受到控制栅电势V G和P型衬底表面势V s的影响，可表示为：
Figure PCTCN2019111513-appb-000011
当P型衬底掺杂浓度较低时(如2E15每立方厘米)，耗尽区的分压远大于电容C 1和C 3的分压，因此公式(1-6)可以简化为：
Figure PCTCN2019111513-appb-000012
公式(1-11)带入(1-3)，即得到P型衬底表面电势V S和控制栅电势V G以及信号电荷产生的电势总和V Q为近似相等，即：
V S≈V Q     (1-12)
将公式(1-12)、(1-8)带入(1-10)，再带入(1-9)，即可得：
Figure PCTCN2019111513-appb-000013
并用入射光子数X photon来表示信号电荷Q的大小：
Q＝X photontη    (1-14)
其中t为曝光时间，X photon为单位时间入射的光子个数，η为器件量子效率。
从而就得到器件可以作为乘法器工作的表达式：
Figure PCTCN2019111513-appb-000014
从公式(1-15)中不难看出，作为输出量的读出区源漏电流I d同时受到作为光输入量的X photon、作为电输入量的V G和V DS作用，并且天生包含乘法和加法的运算关系，利用这样的作用关系，本发明可以实现各种不同功能的运算装置。
所述光电计算单元的最基本结构只包含一个输出端，但是如果将右侧读出区的MOSFET分割为多个并列的各自有独立源漏，并且各项器件参数都相等的小MOSFET，则可扩展输出端的数量，如果给予所述多个小MOSFET相 同的V DS，则可获得光电计算单元的多路相同的输出量。也将在后文中描述基于上述第一实施例所述方案的光电计算单元。
第二实施例
参照图6至8描述根据本发明第二实施例的光电计算单元。
如图6和图7的光电计算单元的正视图和立体图所示，存在一个作为光生载流子收集及读出区的N型半导体衬底，分为左侧收集区和右侧读出区。所述左侧读出区用以在衬底上施加一个电压范围为正压的脉冲，或在控制栅上施加一个电压范围为负压的脉冲，使得收集区衬底中产生用于光空穴收集的耗尽层，并通过右侧读出区读出收集的光空穴电荷量；所述右侧读出区，包含浅槽隔离、P型漏端和P型源端。所述浅槽隔离，位于半导体衬底中部收集区和读出区中间，通过刻蚀并填充入二氧化硅来形成，用于隔离收集区和读出区的电信号。所述P型源端，位于读出区内靠近底层介质层的一侧，通过离子注入法掺杂而形成。所述P型漏端，位于半导体衬底中靠近底层介质层与所述P型源端相对的另一侧，同样通过离子注入法进行掺杂法形成。读出时，在控制栅极上施加一负脉冲电压，使P型源端和P型漏端间形成导电沟道，再通过在P型源端和P型漏端间施加一个偏置脉冲电压，使得导电沟道内的空穴加速形成源漏之间的电流。所述源漏之间沟道内形成电流的载流子，受到控制栅脉冲电压、源漏间电压和收集区收集的光空穴数量共同作用，作为被光输入量和电输入量共同作用后的载流子，以电流的形式进行输出，其中控制栅电压、源漏间电压可以作为器件的电输入量，光空穴数量则为器件的光输入量。
此外，存在一个作为耦合区的电荷耦合层，用以连接收集区和读出区，使收集区衬底内耗尽区开始收集光空穴以后，收集区衬底表面势就会受到收集区的光空穴数量影响；通过电荷耦合层的连接，使得读出区半导体衬底表面势再受到读出区半导体衬底表面势影响，进而影响读出区源漏间电流，从而通过判断读出区源漏间电流来读出收集区收集的光空穴数量。
此外，存在一个作为载流子控制区的控制栅，用以在其上施加一个负脉冲电压，使得在N型半导体衬底读出区中产生用于激发光空穴的耗尽区，同时也可以作为电输入端，输入其中一位运算量。
此外，所述N型半导体衬底和所述电荷耦合层之间存在一层用于隔离的底层介质层；所述电荷耦合层和所述控制栅之间亦存在一层用于隔离的顶层介质层。
进一步参照图8所示的光电计算单元的多功能区的配置图，光电计算单元包括作为所述载流子控制区的控制栅极、作为所述耦合区的电荷耦合层，以及作为所述光生载流子收集和读出区的N型衬底，并且用于隔离的底层介质层，被设置在所述N型半导体衬底和所述电荷耦合层之间，以及用于隔离的顶层介质层，被设置在电荷耦合层和所述控制栅之间。
与上述的本发明的第一实施例相比，该第二实施例的区别在于将器件单元使用的P型衬底更换为N型，将读出区MOSFET的N型源端和漏端更换为了P型，其他结构均无改动，因此基于原理的推导过程与第一实施例所述的过程相似，相似部分不再赘述。
根据之前的推导，公式(1-7)指出，当控制栅和衬底之间的压差不变时，光子入射前，衬底的掺杂浓度越高，耗尽区的深度也就越浅，而过浅的耗尽区将导致运算器件在接收光输入时，可接收的最大光子数过少，光输入端的可输入范围变小，影响运算单元的性能；并且，根据相关理论，过高的衬底掺杂浓度会导致载流子的热激发变大，这将影响光输入端数据在存算一体器件中的存储时间。
在半导体工艺中，因为晶圆天生就是低浓度的P型掺杂，制作P型衬底器件可以直接使用此掺杂作为衬底条件；而如需制作N型衬底器件，则需要通过离子注入的方式来先制作一个N井，再在N井中制作N型衬底器件。因此相对于N型衬底器件而言，P型衬底器件较容易获得更低的衬底掺杂，因此上述两种实施例中，第一实施例所述的方案往往相较于第二实施例的方案有更多的优势。
同第一实施例的方案一样，第二实施例中的光电计算单元的最基本结构只包含一个输出端，但是如果将右侧读出区的MOSFET分割为多个并列的各自有独立源漏，并且各项器件参数都相等的小MOSFET，则可扩展输出端的数量，如果给予所述多个小MOSFET相同的V DS，则可获得光电计算单元的多路相同的输出量。也将在后文中描述基于上述第二实施例所述方案的光电计算单元。
第三实施例
参照图9至12描述根据本发明第三实施例的光电计算单元。
如图9和图10的光电计算单元的正视图和立体图所示，存在一个作为所述光生载流子收集及读出区的P型半导体衬底，可以同时承担感光和读出的工作，包含一个N型漏端和一个N型源端。所述N型源端，位于读出区内靠近底层介质层的一侧，通过离子注入法掺杂而形成。所述N型漏端，位于半导体衬底中靠近底层介质层与所述N型源端相对的另一侧，同样通过离子注入法进行掺杂法形成。感光时，在所述P型半导体衬底上施加一个电压范围为负压的脉冲，同时在所述作为载流子控制区的控制栅极上施加一个电压范围为正压的脉冲，使得P型衬底中产生用于光电子收集的耗尽层，产生在耗尽区内的电子在控制栅极和P型衬底两端之间的电场作用下被加速，并在到达获得足够高的能量，穿过P型衬底和电荷耦合层之间的底层介质层势垒，进入电荷耦合层并储存于此，电荷耦合层中的电荷数量，会影响器件开启时的阈值，进而影响读出时的源漏间电流大小；读出时，在控制栅极上施加一脉冲电压，使N型源端和N型漏端间形成导电沟道，再通过在N型源端和N型漏端间施加一个脉冲电压，使得导电沟道内的电子加速形成源漏之间的电流。所述源漏之间的电流受到控制栅脉冲电压、源漏间电压和电荷耦合层中存储的电子数量共同作用，作为被光输入量和电输入量共同作用后的电子，以电流的形式进行输出，其中控制栅电压、源漏间电压可以作为器件的电输入量，电荷耦合层中存储的光电子数量则为器件的光输入量。
此外，存在一个作为所述耦合区的电荷耦合层，用以储存进入其中的光电子，并改变读出时器件阈值大小，进而影响读出区源漏间电流，从而通过判断读出区源漏间电流来读出感光时产生并且进入电荷耦合层中的光电子数量。
此外，存在一个作为所述载流子控制区的控制栅，用以在其上施加一个脉冲电压，使得在P型半导体衬底读出区中产生用于激发光电子的耗尽区，同时也可以作为电输入端，输入其中一位运算量。
此外，所述P型半导体衬底和所述电荷耦合层之间存在一层用于隔离的底层介质层；所述电荷耦合层和所述控制栅之间亦存在一层用于隔离的顶层介质层。
进一步参照图11所示的光电计算单元的多功能区的配置图，光电计算单 元包括作为所述载流子控制区的控制栅极、作为所述耦合区的电荷耦合层，以及作为所述光生载流子收集和读出区的P型衬底，其中用于隔离的底层介质层，被设置在所述P型半导体衬底和所述电荷耦合层之间，以及用于隔离的顶层介质层，被设置在所述电荷耦合层和所述控制栅之间。
另外，图12是根据本发明第三实施例的光电计算单元的电学模型，根据图5所示的电学模型详细描述该光电计算单元的原理。
如图12所示，光电计算单元单元的结构和浮栅器件大致相当，最顶端的栅是控制栅极，与中间的电荷耦合层是完全隔开的，电荷耦合层即相当于浮栅器件中的浮栅。其中，C FC、C S、C B、C D分别是浮栅与控制栅、源端、衬底、漏端之间的电容。
当浮栅中不存电荷时，即
Figure PCTCN2019111513-appb-000015
可得到：
Figure PCTCN2019111513-appb-000016
其中，V FG是浮栅上的电势，V CG是控制栅上的电势，V S、V D、V B分别为源端、漏端和衬底的电势。
如果定义浮栅的总电容C T为C T＝C FC+C S+C D+C B，同时定义电极J的耦合系数
Figure PCTCN2019111513-appb-000017
为
Figure PCTCN2019111513-appb-000018
其中电极J可以为控制栅G、漏端D、源端S、衬底B中的任意一个，然后浮栅的电势V FG就可以由耦合系数表示为：
V FG＝α GV GS+α DV DS+α SV S+α BV B  (2-2)
其中，V GS、V DS分别为栅源电压和源漏电压，α G、α S、α D、α B分别为栅、源、漏和衬底的耦合系数。可以看到浮栅的电势不仅与控制栅极相关，同时与源端、漏端和衬底的电势相关，如果源和衬底都接地，则：
Figure PCTCN2019111513-appb-000019
其中，
Figure PCTCN2019111513-appb-000020
对于浮栅器件，阈值电压V T和传导系数β可由普通MOS器件的公式推导得到：
Figure PCTCN2019111513-appb-000021
Figure PCTCN2019111513-appb-000022
其中，
Figure PCTCN2019111513-appb-000023
器件达到阈值时的浮栅电势为，
Figure PCTCN2019111513-appb-000024
为器件达到阈值时的控制栅电势，β CG为针对控制栅的体传导系数，β FG为针对浮栅的体传导系数。
由此，对于线性区
Figure PCTCN2019111513-appb-000025
而言，漏端电流I DS为：
Figure PCTCN2019111513-appb-000026
当浮栅中存储有电荷时，
Figure PCTCN2019111513-appb-000027
公式(2-3)，(2-5)，(2-7)即为：
Figure PCTCN2019111513-appb-000028
Figure PCTCN2019111513-appb-000029
Figure PCTCN2019111513-appb-000030
从公式(2-9)可以看到V T是与
Figure PCTCN2019111513-appb-000031
是直接相关的，同时，由该式可以的到V T的改变ΔV T可以表示为：
Figure PCTCN2019111513-appb-000032
其中，V T0为浮栅中不存在电荷时的阈值。在图9、图10所示的光电计算单元的控制栅极加上栅压脉冲，衬底上加负脉冲电压后，在衬底半导体中形成耗尽层。光输入时，代表光输入量的光子入射到半导体衬底耗尽区内，Si半导体衬底吸收一个光子并激发一个电子空穴对。光电子在栅极电压的驱使下加速移动到沟道，并获得足够高的能量，如果能量足够高，即可在栅氧电场的作用下进入电荷耦合层中，完成电荷存储。电荷耦合层在存入光电子后，读出时浮栅MOSFET的漏端电流和阈值电压将发生变化。
由式(2-11)可以知道光电子进入电荷耦合层后引起的器件阈值电压的变 化可表示为：
Figure PCTCN2019111513-appb-000033
其中△V T为阈值电压的变化，Q e为单个电子电荷量电荷量，C CG为控制栅到浮栅的电容，N elec为存储层中的光电子数目。该公式表明阈值电压变化与光电荷量呈线性关系。
通过对曝光前后阈值电压的变化量测量可推定光电子存储层中光电子数目，公式如下：
Figure PCTCN2019111513-appb-000034
将控制栅到浮栅的电容C CG表达式代入上式，得到：
Figure PCTCN2019111513-appb-000035
其中W、L分别代表浮栅器件的栅宽和栅长，H为浮栅厚度，t IPD为所述器件单元中浮栅与栅之间的厚度，ε 0为真空介电常数，ε 0x为相对介电常数。
由式(2-10)可以知道阈值电压变化对应于线性区漏端电流变化△I DS可以表示为如下：
Figure PCTCN2019111513-appb-000036
因而光电子的存储数目还可以通过测量线性区漏端电流的变化得到。
综上，最终读出区的漏源电流I d为：
Figure PCTCN2019111513-appb-000037
从公式(2-15)中不难看出，作为读出量的读出区漏源电流I d同时受到作为光输入量的N、作为电输入量的V G和V DS作用，并且天生包含乘法和加法的运算关系，利用所述的作用关系，即可设计出可以实现各种不同功能的运算装置。
与上述第一实施例以及第二实施例相比，第三实施例最大的区别在于：因为本方案光输入量在器件单元中的存储载体光电子是存储在隔离的电荷耦合层之中，因此具有非常长的保持时间，最多可以达到10年，而上述第一实施 例以及第二实施例所述的方案的光输入信号只能维持秒级的时间，因而作为存算一体器件，具有更大的优势。
同上述第一实施例以及第二实施例一样，所述光电计算单元的最基本结构只包含一个输出端，但是如果将电荷耦合层下的衬底分割为多个并列的各自有独立源漏，并且各项器件参数都相等的小MOSFET，则可扩展输出端的数量，如果给予所述多个小MOSFET相同的V DS，则可获得光电计算单元的多路相同的输出量。也将在后文中描述基于上述第二实施例所述方案的光电计算单元。
第四实施例
参照图13和图14描述根据本发明第四实施例的光电计算单元。
如图13所示，存在一个作为所述光生载流子收集和读出区的光电二极管和读出管，其中，光电二极管通过离子掺杂形成，负责感光。所述光电二极管的N区通过作为耦合区的所述光电子耦合引线连接到读出管的控制栅和复位管的源端上，读出管的漏端施加一正电压脉冲，作为读出电流的驱动电压；曝光前，复位管打开，复位管漏端电压施加到光电二极管上，使所述作为收集区的光电二极管处于反偏状态，产生耗尽层；曝光时，复位管关断，所述光电二极管被电学上隔离，光子入射光电二极管耗尽区后产生光电子，并在二极管中积累，二极管的N区和在电学上通过作为耦合区的所述光电子耦合引线和N区连接的读出管控制栅电势开始下降，进而影响读出管沟道内的电子浓度。所述读出管负责读出，其漏端施加一正脉冲电压，源端和选址管漏端连接，读出时，打开选址管，读出管中产生电流电流,所述电流大小受到复位管漏端电压、读出管漏端电压和入射光子数共同影响，读出管沟道内的电子，作为被光输入量和电输入量共同作用后的电子，以电流的形式输出，其中复位管漏端电压、读出管漏端电压可以作为器件的电输入量，电入射光子数则为器件的光输入量。
此外，存在一个作为耦合区的光电子耦合引线用于连接作为光生载流子收集和读出区中收集区的光电二极管和作为读出区的读出管，将光电二极管N区电势施加到读出管控制栅上。
此外，存在一个作为所谓载流子控制区的复位管，通过其漏端输入一个正 电压作用于光电二极管，当复位管打开时，所述正电压即会作用在光电二极管上，使光电二极管产生耗尽区并感光，同时也可以作为电输入端，输入其中一位运算量。
此外，所述选址管，用于控制整个运算器件作为输出量的输出电流的输出。
进一步参照图14所示的光电计算单元的多功能区的配置图，光电计算单元包括作为所述载流子控制区的复位管、作为所述耦合区的光电子耦合引线，以及作为所述光生载流子收集和读出区的光电二极管和读出管，此外，还包括选址管，用于将所述光电计算单元组成阵列时行列选址使用。
另外，如图13所示，复位管的漏端和电源相连，电源电压V d1，曝光前，在复位管的栅极上加一高电压，使复位管开启，电源电压V d1施加到光电二极管的负极，光电二极管正极接地，此时光电二极管两端电压V PD为：
V PD＝V d1   (3-1)
此时光电二极管内产生耗尽区，耗尽区宽度W为：
Figure PCTCN2019111513-appb-000038
其中，K为和所述二极管参数有关的常数，V bi为内建电场，m j的值取决于二极管的类型为突变结还是缓偏结。
此时，关断复位管，光电二极管在电学上被隔离，代表光输入量的光子入射光电二极管耗尽区，并在耗尽区内形成光电子，单位时间内产生的光电子数I ph为：
I ph＝R phL 0A   (3-3)
其中R ph为光电二极管的敏感度，L 0为其截面积，A为光强。因为光电二极管被隔离，光电子会在耗尽区内积累，有如下常微分方程：
Figure PCTCN2019111513-appb-000039
其中I d为反偏电流，解上述微分方程，得到：
Figure PCTCN2019111513-appb-000040
m j为常数，可以看到，光电二极管两端电压随着入射光子数的增加逐渐降低，将光电二极管的常规参数带入会发现两端电压随时间下降的曲线有较 好的线性度，因此，将上式简化为：
V(t)＝(V d1)-K*X photo   (3-5)
X photo即代表光输入量的入射光子数，K为拟合出的直线斜率。因为作为载流子读出区的读出管和作为载流子收集区的光电二极管，通过作为耦合区的光电子耦合引线相连，因此光电二极管两端电压即读出管控制栅极电压，读出时，将MOSFET线性区沟道电流公式带入：
Figure PCTCN2019111513-appb-000041
其中，V′ T为读出管本身的阈值，V d2为读出管漏源间电压，μ为沟道迁移率，W和L分别为栅宽栅长。
从公式(3-6)中不难看出，作为读出量的读出区管源漏电流I d同时受到作为光输入量的X photo、作为电输入量的V d1和V d2作用，并且天生包含乘法和加法的运算关系，利用所述的作用关系，即可设计出可以实现各种不同功能的运算装置。
第四实施例所述的光电运算器件单元，相对于上述另外上述三种方案而言，最大的区别在于单元面积更大，需要一个光电二极管和三个MOS管才可实现，集成度较低。
同另外上述三种方案一样，所述光电计算单元的最基本结构只包含一个输出端，但是如果将一个读出管扩展为多个栅极都相连的多个各项器件参数都相等的读出管，并配以相同数量的选址管，则可扩展输出端的数量，如果给予所述多个读出管相同的V DS，则可获得光电计算单元的多路相同的输出量。也将在后文中描述基于上述第二实施例所述方案的光电计算单元。
另外，需要强调的是，入射所述光电计算单元的光子可以来自于光学上与光电计算单元对应的发光单元，也可以来自于其他光源，例如来自自然光源或物体的景象。下文将详细描述几种光输入的方案。
光输入的方案
根据本发明的一个方面，提出一种发光单元阵列和光电计算单元阵列的结合方案，其中包含一个或多个发光单元和一个或多个光电计算单元，所述光电计算单元和发光单元在光学上一一对应，以实现对阵列中单个光电计算单元精确的光输入，例如，所述发光单元阵列可以使用高密度小像素LED阵列 来实现。具体地，发光单元和计算单元在光学上的相对应，即发光单元发出的光，精确地照射到该发光单元所对应的计算单元上，如果只使用一个发光单元和计算单元，则需要让此发光单元发出的光照射到计算单元上，如果使用例如10*10的发光单元组成发光阵列和同样数量的计算单元组成计算阵列，则需要让该发光阵列中每一个发光单元发出的光根据具体计算需求，精确照射到其对应的一个或多个计算单元上，假如此阵列实现的计算功能为矩阵向量乘法，则要求每一个发光单元发出的光都精确地照射到每一个计算单元中，为了实现这种精准的光输入，可以通过以下四种优选实施例来实现：
直接投影
若需实现发光单元和器件的一一对应，一种方法是直接让发光单元阵列紧贴器件阵列表面，所述发光阵列使用小像素LED屏幕，如图15所示。
理想发光单元发出的是一球面波，当距离足够近的时候，可以认为发光单元发出的光，只传递到了其正下方器件的表面，这样即实现了光源和器件的一一对应。
发光单元和成像单元的集成
本方案类似于SOI技术，如果能实现发光单元和光电计算单元的三维集成，中间通过生长氧化物来进行隔离(做在一块硅片上)，则无论是阵列的集成度，还是LED到计算器件之间的距离，都会大大的优化，如图16所示，其中光电计算单元可以使用本发明上述的第一实施例中所述光电计算单元。
镜头光输入
发光阵列和计算阵列中间的实现对焦功能的光学结构，即可以是镜头。为了实现发光物体和成像芯片位置上的一一对应，最通用的方案就是使用镜头，发光单元和光电计算单元光学上的一一对应也可以通过这种途径来实现，如图17所示。
光纤维输入
发光阵列和计算阵列中间的实现对焦功能的光学结构，也可以是光纤锥。 光纤锥，为可以实现发光单元和光电计算单元一一对应的一种微结构，其功能类似光纤。
光纤可以被理解为多股密集光线排成的光纤阵列，如果使用光纤锥阵列来链接发光单元和光电计算单元，则可以很好的实现发光单元和光电计算单元的一一对应，大体结构如图18。
光纤锥的方案，相比于直接投影和使用镜头有明显的优势：
1、传递函数高，光纤锥实现的一一对应，可以将光学串扰有效抑制。
2、集成度高、良率高、可优化空间大。
上述直接投影的方案中提到，为了提高光电计算单元的集成度，单个光电计算单元的尺寸会在兼顾其他指标的情况下尽可能做小，而LED像素的尺寸目前只能在8um左右。为了实现尺寸不匹配的发光单元和光电计算单元的一一对应，例如，可以使用漏斗形的光纤锥来连接两个单元，大体结构如图19所示。
因此，光纤锥的使用，会使得所述的光电计算阵列在光输入问题上得到一个良好的解决方案。
发光单元的驱动方案
发光单元的驱动，受到数字控制系统中的光输入控制部分控制。
发光单元受到驱动器发出的恒定电流驱动，保持光强不变，通过调整发光时间来实现不同大小的光输入量的输入。若只存在一个计算单元和一个发光单元，光输入控制部分将所需通过光输入输入到计算单元中的数据转化为发光单元发光时长的脉宽，根据使用的计算单元的种类不同，例如，若使用如上述第一实施例所述的具体计算单元，则光输入量越大，被驱动的发光单元的发光时长就应越短。
计算阵列和发光阵列
如上述光电计算单元的实施例所述，单个光电计算单元可以实现加法或者乘法的运算，若将多个光电计算组合成阵列，并将上述的与光电计算单元相对应的发光单元同样也组成阵列，即可完成一组或多组加法或者乘法的运算，同时，通过引线的连接，如将两个光电计算单元的输出端相连，让输出电流汇 聚成一股电流，则又等同于实现了一次加法。通过上述方法，将光电计算单元根据具体的算法需要，改变引线的连接和光电计算单元的排布方式，就可以制作出实现特定运算的计算阵列。
并且，通过对光电计算单元和发光单元的相应排布组成阵列，可以实现矩阵向量乘法的运算、平均池化运算的阵列、以及卷积运算的阵列等。
第一种加法器
如上所述，本发明提出了多种光电计算装置和光电计算方法的具体实施方式，通过使用发光单元和上文所述光电计算单元(包括优选的第一至第四实施例)，可以实现两位加数的加法运算。
根据本发明的加法器最大的优点在于：只需要单一光电计算单元和发光单元就可实现两个加数的加法运算，集成度较高。
此加法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如，如果使用上文所述的具有两个输出端的光电计算单元，则加法器也具有两个输出端，下文详细描述的四种方案中默认采取有一个输出端的光电计算单元，作为示例。
方案1：基于上述第一实施例的光电计算单元
在本方案1中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000042
其中，X photo为入射到光电计算单元的有效光子数，V G为代表所述载流子控制区的控制栅上的电压，t为，η为，q为。因为X photo和V G公式中天生即为加减的关系，故而可以通过对X photo和V G的调制，用所述的二者关系来进行加法运算，其中：
X photo代表光输入端的输入量，为第一位加数；V G代表电输入端的输入量，为第二位加数；同时载流子收集和读出区中读出区的漏源间电压V DS加以恒定值，则载流子收集和读出区中读出区的输出电流I d即为加法运算的结果，即等于进行了如(3-1-2)式所述的计算：
R＝k(aX+bY+c)         (3-1-2)
其中，a、b、k和c都为常数。
方案2：基于上述第二实施例的光电计算单元
相比上述方案1而言，基于上述第二实施例的光电计算单元的方案2最大的区别在于：从P衬底器件更换为了N衬底器件，因此作为所述载流子控制区的控制栅极上加的电压从正压变为了负压，作为所述载流子收集和读出区的N型衬底在曝光时加的电压从负压变成了正压，但控制栅电压和入射光子数依旧是一对加减的关系，因此只需要在对光输入信号和电输入信号调制时进行些许变化，依旧可以实现与第一实施例的方案大体相似的加法运算。
方案3：基于上述第三实施例的光电计算单元
在基于上述第三实施例的光电计算单元的方案3中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000043
其中，N elec为进入到作为所述耦合区的电荷耦合层中的电子数，V G为作为所述载流子控制区的控制栅上的电压，
Figure PCTCN2019111513-appb-000044
为器件阈值。因为N elec和V G公式中天生即为加减的关系，故而可以通过对N elec和V G的调制，用所述的二者关系来进行加法运算：
N elec代表光输入端的输入量，为第一位加数；V G代表电输入端的输入量，为第二位加数；同时载流子收集和读出区中读出区的漏源间电压V DS加以恒定值，则载流子收集和读出区中读出区的输出电流I D即为加法运算的结果，即等于进行了如(3-3-2)式所述的计算：
R＝k(aX+bY+c)       (3-3-2)
其中，a、b、k和c都为常数。
方案4：基于上述第四实施例的光电计算单元
在基于上述第四实施例的光电计算单元的方案4中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000045
其中，X photo为入射到光电计算单元的有效光子数，V d1为作为所述载流子控制区的复位管漏端电压，K为拟合出的直线斜率，V d2为读出管源漏间电压。因为X photo和V d1公式中天生即为加减的关系，故而可以通过对X photo和V d1的调制，用所述的二者关系来进行加法运算：
X photo代表光输入端的输入量，为第一位加数；V d1代表电输入端的输入量，为第二位加数；同时作为载流子收集和读出区中读出区的读出管的漏端电压V DS加以恒定值，则载流子收集和读出区中读出区的输出电流I d即为加法运算的结果，即等于进行了如(3-4-2)式所述的计算：
R＝k(aX+bY+c)     (3-4-2)
其中，a、b、k和c都为常数。
采取本方案进行加法运算，相较于传统加法运算器有如下优势：
1、集成度高，单个光电计算单元就可实现运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
第二种加法器
如上所述，本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用一个发光单元和多控制区光电计算单元，来实现至少两位加数的加法运算。此加法器的最大优点是不光只需要单一光电计算单元即可实现加法运算，而且输入的加数数量也不仅仅局限于两个，但是需要工艺的支持，尤其是使用上述第一、第二、第三实施例中所述光电计算单元的方案时，多控制栅参数必须有较高的均匀性。
此加法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如，如果使用具有两个输出端的上述光电计算单元，则加法器也具有两个输出端，下文的详细描述的四个方案中默认采取有一个输出端的光电计算单元，作为示例。
方案1：基于上述第一实施例的光电计算单元
在本方案1中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000046
其中，X photo为入射到光电计算单元的有效光子数，V G为代表所述载流子控制区的控制栅上的电压，t为曝光时间，η为量子效率，q为电子电荷量。如果将控制栅改为多栅极结构，如图20，则上式改为：
Figure PCTCN2019111513-appb-000047
其中，V G1到V Gn分别代表n个控制栅上的输入的电压，为多个电输入端的电输入量，k 1到k n分别为和n个控制栅面积有关的多栅极输入权重。从(4-1-2)中不难看出，各个控制栅上的电压和光输入量X photo天生即为加减的关系，故而可以通过对X photo和V G1到V Gn的调制，用所述的关系来进行加法运算。
X photo代表光输入端的输入量，为第一位加数；V G1到V Gn代表电输入端的多个输入量，为第二到第n位加数；同时载流子收集和读出区中读出区的漏源间电压V DS加以恒定值，则载流子收集和读出区中读出区的输出电流I d即为加法运算的结果，即等于进行了如(3-1-2)式所述的计算：
R＝k(aX+k 1Y 1+k 2Y 2……k nY n+c)   (4-1-3)
其中，a、b、k和c都为常数。
方案2：基于上述第二实施例的光电计算单元
相比于方案1而言，方案2最大的区别在于从P衬底器件更换为了N衬底器件，因此作为所述载流子控制区的多栅极控制栅极上加的电压从正压变为了负压，作为所述载流子收集和读出区的N型衬底在曝光时加的电压从负压变成了正压，但多栅极的多个电压和入射光子数依旧是一对加减的关系，因此只需要在对光输入信号和电输入信号调制时进行些许变化，依旧可以实现和方案1大体相似的多个加数的加法运算。
方案3：基于上述第三实施例的光电计算单元
在本方案3中，如果代表所述载流子控制区的控制栅极采用多栅极结构，如图21所示，则源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000048
其中，V G1到V Gn分别代表n个控制栅上的输入的电压，为多个电输入端的电输入量，k 1到k n分别为和n个控制栅面积有关的多栅极输入权重。从(4-2-1)中不难看出，各个控制栅上的电压和光电子进入代表所述耦合区的电荷耦合层的电荷量N天生即为加减的关系，故而可以通过对N和V G1到V Gn的调制，用所述的关系来进行加法运算。
N代表光输入端的输入量，为第一位加数；V G1到V Gn代表电输入端的多个输入量，为第二到第n位加数；同时载流子收集和读出区中读出区的漏源间电压V DS加以恒定值，则载流子收集和读出区中读出区的输出电流I D即为加法运算的结果，即等于进行了如(4-3-2)式所述的计算：
R＝k(aX+k 1Y 1+k 2Y 2……k nY n+c)   (4-3-2)
其中，a、b、k和c都为常数。
方案4：基于上述第四实施例的光电计算单元
在本方案4中，如果代表所述载流子控制区的复位管采用多复位管并联的方式，如图22所示，则源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000049
其中，V d1到V dn分别代表n个复位管漏端的电压，为多个电输入端的电输入量，k 1到k n分别为和n个复位管沟道电阻有关的多栅极输入权重。从(4-4-1)中不难看出，各个复位管漏端的电压和光输入量X photo天生即为加减的关系，故而可以通过对X photo和V d1到V dn的调制，用所述的关系来进行加法运算。
X photo代表光输入端的输入量，为第一位加数；V d1到V dn代表电输入端的多个输入量，为第二到第n位加数；同时载流子收集和读出区中读出区的漏源间电压V DS加以恒定值，则载流子收集和读出区中读出区的输出电流I D即为加法运算的结果，即等于进行了如(4-4-2)式所述的计算：
R＝k(aX+k 1Y 1+k 2Y 2……k nY n+c)    (4-4-2)
其中，a、b、k和c都为常数。
采取本方案进行加法运算，相较于传统加法运算器有如下优势：
1、集成度高，单个光电计算单元就可实现多个加数的加法运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运 算时无需重新进行光输入。
第三种加法器
如上所述，本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用至少两个发光单元和至少两个上文中所述光电计算单元，来实现至少两位加数的加法运算。本加法器的方案最大的优点就是利用光输入精度较高的特点，一个光电计算单元只承担一路光信号的输入，电信号只给予恒定值，这有利于计算均匀性的提高；另外，如果存在类似于固定图像噪声或器件均匀性等固定不变的计算误差，也可以通过电输入端恒定值的改变加以修正。
此加法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用上述中所述的具有两个输出端的光电计算单元，则加法器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元，作为示例。
方案1：基于上述第一实施例的光电计算单元
在本方案1中，以两位加数的加法运算为例，使用两个光电计算单元和发光单元，如图23所示，其中，一个标有V字符的方框单元即代表一个采用本方案1的光电计算单元。
在本方案1中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000050
其中，X photon为入射到光电计算单元的有效光子数，如果将两个各种参数均相同单元的输出端并接，让输出电流汇聚，并给予两个光电计算单元不同的光输入量X photo，但给予相同的电输入端输入V G和V DS，则上式改为：
Figure PCTCN2019111513-appb-000051
其中，X photo1和X photo2分别为两个输出端并联的单元的光输入端输入量，从(5-1-2)中不难看出，两个单元光输入端数据天生即为加减的关系，故而可以通过对X photo1和X photo2的调制，用所述的关系来进行加法运算。
X photo1和X photo2分别代表光输入端的第一和第二位加数，同时两个单元的作为所述载流子控制区的控制栅极V G，和作为载流子收集和读出区中读出区的漏源间电压V DS加以恒定值，则经过汇聚后的总输出电流I D总，再经过AD转换，送入控制系统后，即可获得加法的结果，等于进行了如(5-1-3)式所述的计算：
R＝k(aX 1+aX 2+c)   (5-1-3)
其中a、c和k都为常数，如需进行加数大于2的加法运算，只需增加并接的光电计算单元和与之对应的发光单元即可。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
方案2：基于上述第二实施例的光电计算单元
在本方案2中，相比于上述方案1而言最大的区别在于从P衬底器件更换为了N衬底器件，因此作为所述载流子控制区的控制栅极上加的电压从正压变为了负压，作为所述载流子收集和读出区的N型衬底在曝光时加的电压从负压变成了正压，但并接的多个单元的光输入端数据依旧是一对加减的关系，因此只需要在对光输入信号和电输入恒定值调制时进行些许变化，依旧可以实现与方案1大体相似的多个加数的加法运算。
方案3：基于上述第三实施例的光电计算单元
以两位加数的加法运算为例，使用两个光电计算单元和发光单元，如图23所示连接，其中，一个标有V字符的方框单元即代表一个采用本方案3的光电计算单元。
在本方案3中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000052
其中，N为进入到作为所述耦合区的电荷耦合层中的光电子，如果将两个各种参数均相同单元的输出端并接，让输出电流汇聚，并给予两个光电计算单元不同的光输入量N，但给予相同的电输入端输入V G和V DS，则上式改为：
Figure PCTCN2019111513-appb-000053
其中，N 1和N 2分别为两个输出端并联的单元的光输入端输入量，从(5-3-2)中不难看出，两个单元光输入端数据天生即为加减的关系，故而可以通过对N 1和N 2的调制，用所述的关系来进行加法运算。
N 1和N 2分别代表光输入端的第一和第二位加数，同时两个单元的作为所述载流子控制区的控制栅极V G，和作为载流子收集和读出区中读出区的漏源间电压V DS加以恒定值，则经过汇聚后的总输出电流I D总，再经过AD转换，送入控制系统后，即可获得加法的结果，等于进行了如(5-3-3)式所述的计算：
R＝k(aX 1+aX 2+c)   (5-3-3)
其中a、c和k都为常数，如需进行加数大于2的加法运算，只需增加并接的光电计算单元和与之对应的发光单元即可。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
方案4：基于上述第四实施例的光电计算单元
以两位加数的加法运算为例，使用两个光电计算单元和发光单元，如图23所示，其中，一个标有V字符的方框单元即代表一个采用本方案4的光电计算单元。
在本方案4中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000054
其中，X photo为被收集在作为所述载流子收集和读出区中读出区的光电二极管中的光电子，如果将两个各种参数均相同单元的输出端并接，让输出电流汇聚，并给予两个光电计算单元不同的光输入量X photo，但给予相同的电输入端输入V d1和V d2，则上式改为：
Figure PCTCN2019111513-appb-000055
X photo1和X photo2分别代表光输入端的第一和第二位加数，同时两个单元的作为所述载流子控制区的复位管的漏端电压V d1，和作为载流子收集和读出区中读出区的读出管的漏端电压V d2加以恒定值，则经过汇聚后的总输出电流I D 总，再经过AD转换，送入控制系统后，即可获得加法的结果，等于进行了如(5-4-3)式所述的计算：
R＝k(aX 1+aX 2+c)     (5-4-3)
其中a、c和k都为常数，如需进行加数大于2的加法运算，只需增加并接的光电计算单元和与之对应的发光单元即可。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
采取本方案4进行加法运算，相较于传统加法运算器有如下优势：
1、集成度高，两个光电计算单元就可实现两位加数的加法运算。
2、可以自由选择加数的数量。
3、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
第一种乘法器
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用一个发光单元和上述实施例中所述的光电计算单元，来实现两位乘数的乘法运算。本乘法器的方案最大的优点就是集成度高，单一器件即可实现乘法运算，但是只支持两路输入的乘法运算，并且双路模拟输入，计算精度有限。
此乘法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则乘法器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
1)、采用上述光电计算单元的第一实施例的方案：
在第一种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000056
其中，X photo为入射到光电计算单元的有效光子数，V DS为代表所述载流子收集和输出区的P型衬底的漏端电压，因为其二者公式中天生即为乘法的关系，故而可以通过对X photo和V DS的调制，用所述的二者关系来进行乘法运算：
X photo代表光输入端的输入量，为第一位乘数；V DS代表电输入端的输入量，为第二位乘数；同时载流子控制区的控制栅极电压V G加以恒定值，则载流子收集和读出区中读出区的输出电流I D即为乘法运算的结果，即等于进 行了如(6-1-2)式所述的计算：
R＝k(aX+b)Y    (6-1-2)
a，b，k都为常数。
2)、采用上述光电计算单元的第二实施例的方案：
第二种方案，相比于第一种方案而言最大的区别在于从P衬底器件更换为了N衬底器件，因此作为所述载流子控制区的控制栅极上加的电压从正压变为了负压，作为所述载流子收集和读出区的N型衬底在曝光时加的电压从负压变成了正压，但载流子读出区漏端电压和入射光子数依旧是一对乘法的关系，因此只需要改变控制栅电压和N型衬底电压，依旧可以实现和第一种方案大体相似的乘法运算。
3)、采用上述光电计算单元的第三实施例的方案：
在第三种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000057
其中，N elec为作为耦合区的电荷耦合层中收集的光电子，V DS为代表所述载流子收集和输出区的P型衬底的漏端电压，因为其二者公式中天生即为乘法的关系，故而可以通过对N elec和V DS的调制，用所述的二者关系来进行乘法运算：
N elec代表光输入端的输入量，为第一位乘数；V DS代表电输入端的输入量，为第二位乘数；同时载流子控制区的控制栅极电压V G加以恒定值，则载流子收集和读出区中读出区的输出电流I D即为乘法运算的结果，即等于进行了如(6-3-2)式所述的计算：
R＝k(aX+b)Y     (6-3-2)
a，b，k都为常数。
4)、采用上述光电计算单元的第四实施例的方案：
在第四种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000058
其中，X photo为入射到光电计算单元的有效光子数，V d2为代表所述载流子收集和输出区的读出管的漏端电压，因为其二者公式中天生即为乘法的关系，故而可以通过对X photo和V d2的调制，用所述的二者关系来进行乘法运算：
X photo代表光输入端的输入量，为第一位乘数；V d2代表电输入端的输入量，为第二位乘数；同时载流子控制区的复位管漏端电压V d1加以恒定值，则载流子收集和读出区中读出区的输出电流I D即为乘法运算的结果，即等于进行了如(6-4-3)式所述的计算：
R＝k(aX+b)Y    (6-4-3)
a，b，k都为常数。
采取本方案进行乘法运算，相较于传统乘法运算器有如下优势：
1、集成度高，单个光电计算单元就可实现乘法运算，相较于传统乘法器动辄上万晶体管而言有巨大的优势。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
第二种乘法器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用一个发光单元和上述实施例中所述的光电计算单元，来实现两位乘数的乘法运算。本乘法器的方案最大的优点在于电输入端改为了数字量的串行输入，具有较高的计算精度，缺点在于数据的串行输入输出影响计算速度，并且需要控制系统参与辅助运算。
此乘法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则乘法器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
1)、采用上述光电计算单元的第一实施例的方案：
以计算乘法运算A*W为例，计算示意图如图24所示，图中标有V字符 的方框单元即代表采用第一种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1    (7-1-1)
m取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制数据按比特位，串行的将上述n个二值化的数据以调制过的电压的形式，输入到作为载流子控制区的控制栅上。
在第一种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000059
其中，X photo为入射到光电计算单元的有效光子数，V G为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据X photo等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V G为0时，读出区MOSFET内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据X photo的乘法结果；当V G等于一个足以使得读出区MOSFET内产生沟道的电压大小时，V DS假如也给予恒定值，输出结果只取决于光输入端数据X photo，其输出结果依旧符合恒定值1和光输入端输入量X photo乘法的结果。
X photo代表光输入端的输入量，为第一位乘数；串行输入的V G代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区的P型衬底的源漏间电压V DS给予恒定值，随着V G的串行输入，串行输出的载流子收集和读出区中读出区的输出电流I D经过AD转换后，再送入控制系统，在控制系统中按照电输入端输入的比特位进行移位和累加操作，即可获得乘法A*W的运算结果。即等于进行了如(7-1-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)  (7-1-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用上述光电计算单元的第二实施例的方案：
第二种方案，相比于第一种方案而言最大的区别在于从P衬底器件更换 为了N衬底器件，因此作为所述载流子控制区的控制栅极上加的电压从正压变为了负压，作为所述载流子收集和读出区的N型衬底在曝光时加的电压从负压变成了正压，但作为所述载流子控制区的控制栅极上输出的二值化电压和入射光子数依旧是一对乘法的关系，因此只需要对控制栅电压和N型衬底电压进行些许变化，依旧可以实现和第一种方案大体相似的乘法运算。
3)、采用上述光电计算单元的第三实施例的方案：
以计算乘法运算A*W为例，计算示意图如图24所示，图中标有V字符的方框单元即代表采用第三种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1   (7-3-1)
m取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制数据按比特位，串行的将上述n个二值化的数据以调制过的电压的形式，输入到作为载流子控制区的控制栅上。
在第三种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000060
其中，N elec为进行电荷耦合层中的光电子数量，V G为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据N elec等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V G为0时，浮栅MOSFET内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据N elec的乘法结果；当V G等于一个足以使得浮栅MOSFET内产生沟道的电压大小时，V DS假如也给予恒定值，输出结果只取决于光输入端数据N elec，其输出结果依旧符合恒定值1和光输入端输入量N elec乘法的结果。
N elec代表光输入端的输入量，为第一位乘数；串行输入的V G代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区的P型衬底的源漏间电压V DS给予恒定值，随着V G的串行输入，串行输出的载流子收集和读出区中读出区的输出电流I D经过AD转换后，再送入控制系统，在控制系统中按照电输入端输入的比特位进行移位和累加操作，即可获得乘 法A*W的运算结果。即等于进行了如(7-3-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)   (7-3-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
4)、采用上述光电计算单元的第四实施例的方案：
以计算乘法运算A*W为例，计算示意图如图24所示，图中标有V字符的方框单元即代表采用第四种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1   (7-4-1)
m取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制数据按比特位，串行的将上述n个二值化的数据以调制过的电压的形式，输入到作为载流子控制区的复位管漏端上。
在第四种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000061
其中，X photo为作为光电子收集和读出区的读出区的光电二极管中收集的光电子数，V d1为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据X photo等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V d1为0时，读出管内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据X photo的乘法结果；当V d1等于一个足以使得读出管内产生沟道的电压大小时，V d2假如也给予恒定值，输出结果只取决于光输入端数据X photo，其输出结果依旧符合恒定值1和光输入端输入量X photo乘法的结果。
X photo代表光输入端的输入量，为第一位乘数；串行输入的V d1代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区中读出区的读出管的漏端电压V d2给予恒定值，随着V d1的串行输入，串行输出的载流子收集和读出区中读出区的输出电流I D经过AD转换后，再送入控制系统，在控制系统中按照电输入端输入的比特位进行移位和累加操作，即可获 得乘法A*W的运算结果。即等于进行了如(7-4-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)   (7-4-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
采取本方案进行乘法运算，相较于传统乘法运算器有如下优势：
1、集成度高，单个光电计算单元就可实现乘法运算，相较于传统乘法器动辄上万晶体管而言有巨大的优势。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
第三种乘法器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用至少两个个发光单元和上述实施例中所述的光电计算单元，来实现两位乘数的乘法运算。本乘法器的方案最大的优点在于电输入端改为了数字量的并行输入，具有较高的计算精度，并且有着较上述第二种乘法器更高的运算速度；缺点在于数据的并行输入需要更多的光电计算单元，并且需要控制系统参与辅助运算。
此乘法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则乘法器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
1)、采用上述光电计算单元的第一实施例的方案：
以计算乘法运算A*W为例，计算示意图如图25所示，图中一个标有V字符的方框单元即代表一个采用第一种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1(8-1-1)
m和所使用的单元个数相当，取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制转化后的二值化数据，按比特位并 行的将上述m个二值化的数据以调制过的电压的形式，输入到m个单元的作为载流子控制区的控制栅上。
在第一种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000062
其中，X photo为入射到光电计算单元的有效光子数，V G为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据X photo等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V G为0时，读出区MOSFET内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据X photo的乘法结果；当V G等于一个足以使得读出区MOSFET内产生沟道的电压大小时，V DS假如也给予恒定值，输出结果只取决于光输入端数据X photo，其输出结果依旧符合恒定值1和光输入端输入量X photo乘法的结果。
X photo代表光输入端的输入量，为第一位乘数；并行输入的V G代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区的P型衬底的源漏间电压V DS给予恒定值，随着V G的并行输入，并行输出的载流子收集和读出区中读出区的输出电流I D经过AD转换后，再送入控制系统，在控制系统中按照电输入端输入的比特位进行移位和累加操作，即可获得乘法A*W的运算结果。即等于进行了如(8-1-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)  (8-1-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用上述光电计算单元的第二实施例的方案：
第二种方案，相比于第一种方案而言最大的区别在于从P衬底器件更换为了N衬底器件，因此作为所述载流子控制区的控制栅极上加的电压从正压变为了负压，作为所述载流子收集和读出区的N型衬底在曝光时加的电压从负压变成了正压，但作为所述载流子控制区的控制栅极上输出的二值化电压和入射光子数依旧是一对乘法的关系，因此只需要对控制栅电压和N型衬底电压进行些许变化，依旧可以实现和第一种方案大体相似的乘法运算。
3)、采用上述光电计算单元的第三实施例的方案：
以计算乘法运算A*W为例，计算示意图如图25所示，图中一个标有V字符的方框单元即代表一个采用第三种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1   (8-3-1)
m和所使用的单元个数相当，取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制转化后的二值化数据，按比特位并行的将上述m个二值化的数据以调制过的电压的形式，输入到m个单元的作为载流子控制区的控制栅上。
在第三种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000063
其中，N elec为进行电荷耦合层中的光电子数量，V G为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据N elec等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V G为0时，浮栅MOSFET内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据N elec的乘法结果；当V G等于一个足以使得浮栅MOSFET内产生沟道的电压大小时，V DS假如也给予恒定值，输出结果只取决于光输入端数据N elec，其输出结果依旧符合恒定值1和光输入端输入量N elec乘法的结果。
N elec代表光输入端的输入量，为第一位乘数；并行输入的V G代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区的P型衬底的源漏间电压V DS给予恒定值，随着V G的并行输入，并行输出的载流子收集和读出区中读出区的输出电流I D经过AD转换后，再送入控制系统，在控制系统中按照电输入端输入的比特位进行移位和累加操作，即可获得乘法A*W的运算结果。即等于进行了如(8-3-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)   (8-3-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
4)、采用上述光电计算单元的第四实施例的方案：
以计算乘法运算A*W为例，计算示意图如图25所示，图中一个标有V字符的方框单元即代表一个采用第四种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1   (8-4-1)
m和所使用的单元个数相当，取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制转化后的二值化数据，按比特位并行的将上述m个二值化的数据以调制过的电压的形式，输入到m个单元的作为载流子控制区的复位管漏端上。
在第四种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000064
其中，X photo为作为光电子收集和读出区的读出区的光电二极管中收集的光电子数，V d1为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据X photo等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V d1为0时，读出管内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据X photo的乘法结果；当V d1等于一个足以使得读出管内产生沟道的电压大小时，V d2假如也给予恒定值，输出结果只取决于光输入端数据X photo，其输出结果依旧符合恒定值1和光输入端输入量X photo乘法的结果。
X photo代表光输入端的输入量，为第一位乘数；并行输入的V d1代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区中读出区的读出管的漏端电压V d2给予恒定值，随着V d1的并行输入，并行输出的载流子收集和读出区中读出区的输出电流I D经过AD转换后，再送入控制系统，在控制系统中按照电输入端输入的比特位进行移位和累加操作，即可获得乘法A*W的运算结果。即等于进行了如(8-4-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)  (8-4-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
采取本方案进行乘法运算，相较于传统乘法运算器有如下优势：
1、集成度高，数个光电计算单元就可实现乘法运算，相较于传统乘法器动辄上万晶体管而言有巨大的优势。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
第四种乘法器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用至少两个个发光单元和上述实施例中所述的光电计算单元，来实现两位乘数的乘法运算。本乘法器的方案最大的优点在于实现了位权的参与运算，相较于上述第二、三种乘法器的方案，不需要控制系统辅助计算；缺点在于本质上还是两路模拟输入的乘法，精度会低于上述第二、三种乘法器的方案。
此乘法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则乘法器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
采用上述光电计算单元的第一实施例的方案：
以计算乘法运算A*W为例，计算示意图如图26所示，图中一个标有V字符的方框单元即代表一个采用第一种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1    (9-1-1)
m和所使用的单元个数相当，取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制转化后的二值化数据，按比特位并行的将上述m个二值化的数据以调制过的电压的形式，输入到m个单元的作为载流子控制区的控制栅上。
在第一种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000065
其中，X photo为入射到光电计算单元的有效光子数，V G为代表控制栅极的 电压，V DS为作为所述载流子控制和输出区的P型衬底源漏间电压。当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据X photo等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V G为0时，读出区MOSFET内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据X photo的乘法结果；当V G等于一个足以使得读出区MOSFET内产生沟道的电压大小时，V DS假如也给予恒定值，输出结果只取决于光输入端数据X photo，其输出结果依旧符合恒定值1和光输入端输入量X photo乘法的结果。
同时式(9-1-2)中，V DS和V G、X photo天生即为相乘的关系，因此在P型衬底源漏间输入和并行输入的控制栅上二值化数据对应的比特位相对应的位权2 0、2 1、2 2……2 m-1，即等同于进行了移位操作，之后直接通过电流汇聚的方式完成累加运算，即可无需控制系统操作，就可完成一个完整的乘法运算。
X photo代表光输入端的输入量，为第一位乘数；并行输入的V G代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区的P型衬底的源漏间电压V DS给予和二值化数据相应比特位位权相当的调制过的电压，随着V G的并行输入，并行输出的载流子收集和读出区中读出区的输出电流I D经汇聚完成相加操作，再通过AD转换后送入控制系统，即可获得乘法A*W的运算结果。即等于进行了如(9-1-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)   (9-1-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用上述光电计算单元的第二实施例的方案：
第二种方案，相比于第一种方案而言最大的区别在于从P衬底器件更换为了N衬底器件，因此作为所述载流子控制区的控制栅极上加的电压从正压变为了负压，作为所述载流子收集和读出区的N型衬底在曝光时加的电压从负压变成了正压，但作为所述载流子控制区的控制栅极上输出的二值化电压和入射光子数依旧是一对乘法的关系，因此只需要对控制栅电压和N型衬底电压进行些许变化，依旧可以实现和第一种方案大体相似的乘法运算。
3)、采用上述光电计算单元的第三实施例的方案：
以计算乘法运算A*W为例，计算示意图如图26所示，图中一个标有V 字符的方框单元即代表一个采用第三种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1   (9-3-1)
m和所使用的单元个数相当，取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制转化后的二值化数据，按比特位并行的将上述m个二值化的数据以调制过的电压的形式，输入到m个单元的作为载流子控制区的控制栅上。
在第三种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000066
其中，N elec为进行电荷耦合层中的光电子数量，V G为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据N elec等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V G为0时，浮栅MOSFET内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据N elec的乘法结果；当V G等于一个足以使得浮栅MOSFET内产生沟道的电压大小时，V DS假如也给予恒定值，输出结果只取决于光输入端数据N elec，其输出结果依旧符合恒定值1和光输入端输入量N elec乘法的结果。
同时式(9-3-2)中，V DS和V G、N elec天生即为相乘的关系，因此在P型衬底源漏间输入和并行输入的控制栅上二值化数据对应的比特位相对应的位权2 0、2 1、2 2……2 m-1，即等同于进行了移位操作，之后直接通过电流汇聚的方式完成累加运算，即可无需控制系统操作，就可完成一个完整的乘法运算。
N elec代表光输入端的输入量，为第一位乘数；并行输入的V G代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区的P型衬底的源漏间电压V DS给予和二值化数据相应比特位位权相当的调制过的电压，随着V G的并行输入，并行输出的载流子收集和读出区中读出区的输出电流I D经汇聚完成相加操作，再通过AD转换后送入控制系统，即可获得乘法A*W的运算结果。即等于进行了如(9-3-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a) (9-3-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
4)、采用上述光电计算单元的第四实施例的方案：
以计算乘法运算A*W为例，计算示意图如图26所示，图中一个标有V字符的方框单元即代表一个采用第四种方案的光电计算单元，其中A通过电输入端输入，W通过光输入端输入。
首先，将A在控制系统中进行二进制转化：
A＝A 0A 1A 2……A m-1   (9-4-1)
m和所使用的单元个数相当，取决于电输入端数据的位宽。
再通过控制系统，将所述A的二进制转化后的二值化数据，按比特位并行的将上述m个二值化的数据以调制过的电压的形式，输入到m个单元的作为载流子控制区的复位管漏端上。
在第四种方案中，源漏输出电流符合公式：
Figure PCTCN2019111513-appb-000067
其中，X photo为作为光电子收集和读出区的读出区的光电二极管中收集的光电子数，V d1为代表控制栅极的电压，当控制栅极输入二值化数据为0时，即等于输入使得无论光输入端数据X photo等于多少，都足以使得输出电流I D等于0的电压值；当控制栅极输入二值化数据为1时，即等于输入恒定的控制栅电压。因为当V d1为0时，读出管内不存在导电沟道，电流为0，输出结果为0，符合电输入端数据0和光输入端数据X photo的乘法结果；当V d1等于一个足以使得读出管内产生沟道的电压大小时，V d2假如也给予恒定值，输出结果只取决于光输入端数据X photo，其输出结果依旧符合恒定值1和光输入端输入量X photo乘法的结果。
同时式(9-4-2)中，V DS和V G、X photo天生即为相乘的关系，因此在读出管的漏端输入和并行输入的控制栅上二值化数据对应的比特位相对应的位权2 0、2 1、2 2……2 m-1，即等同于进行了移位操作，之后直接通过电流汇聚的方式完成累加运算，即可无需控制系统操作，就可完成一个完整的乘法运算。
X photo代表光输入端的输入量，为第一位乘数；并行输入的V d1代表电输入端的输入量，为第二位乘数的二值化数据；同时作为载流子收集和读出区中读出区的读出管的漏端电压V d2给予和二值化数据相应比特位位权相当的调 制过的电压，随着V d1的并行输入，并行输出的载流子收集和读出区中读出区的输出电流I D经汇聚完成相加操作，再通过AD转换后送入控制系统，即可获得乘法A*W的运算结果。即等于进行了如(9-4-3)式所述的计算：
R＝kW(A 0*2 0+A 1*2 1+A 2*2 2+…+A m*2 m-1+a)  (9-4-3)
其中a和k都为常数。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
采取本方案进行乘法运算，相较于传统乘法运算器有如下优势：
1、集成度高，数个光电计算单元就可实现乘法运算，相较于传统乘法器动辄上万晶体管而言有巨大的优势。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
向量加法器的方案，对应权利要求23、24
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用多个上述第一、二、三种加法器之一所述的光电计算加法器，来实现至少两个维度至少为二的向量的向量加法运算。
1)、采用上述第一种加法器的方案：
对于上述第一种加法器，等效于进行运算：
R＝d(aX+bY+c)  (10-1-1)
其中，R为加法运算结果，X photo为光输入端输入量，Y为电输入端输入量，d、a、b和c都为和单元参数有关的常数。
向量加法，即为两个维度相同的待加向量对应序号的元素一一相加，得到一个维度和待加向量相同的结果向量，以两个维度为k的待加向量的加法运算A+B为例：
R＝A+B＝(A 0+B 0，A 1+B 1……A k-1+B k-1)  (10-1-2)
从式(10-1-2)可以看出，向量加法运算可以拆分成k个两位输入的单独加法运算，因此使用k个上述第一种加法器，可以组成向量加法器，如图27所示，其中，每一个中间写有“V加法器”的方框都代表一个单独的上述第一种加法器。
将待加向量输入控制系统，在控制系统中将待加向量拆分成一个个独立 元素，并将序号相同的元素作为同一个加法器的两位加数输入，输入同一个加法器；完成加法运算后，再将运算结果输入回控制系统，重新按照元素序号组成结果向量，即完成了完整的向量加法运算。因为上述第一种加法器只能支持两位加数的输入，因此本方案的向量加法器也只能支持两个待加向量的输入。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用上述第二种加法器的方案：
对于上述第二种加法器，等效于进行运算：
R＝b(aX+k 1Y 1+k 2Y 2……k nY n+c)   (10-2-1)
其中，R为加法运算结果，X photo光输入端输入量，Y 1到Y n为多载流子控制区电输入端输入量，b、a、c和k 1到k n都为和加法器单元参数有关的常数。
向量加法，即为两个维度相同的待加向量对应序号的元素一一相加，得到一个维度和待加向量相同的结果向量，以n个维度为m的待加向量的加法运算A 1+A 2…+A n为例：
R＝A 1+A 2…A n＝(A 10+A 20…+A n0，……，A 1m+A 2m…+A nm)  (10-2-2)
从式(10-2-2)可以看出，n个向量加法运算可以拆分成m个n位加数输入的单独加法运算，因此使用n个上述第二种加法器，可以组成向量加法器，如图27所示，其中，每一个中间写有“V加法器”的方框都代表一个单独的上述第二种加法器。
将待加向量输入控制系统，在控制系统中将待加向量拆分成一个个独立元素，并将序号相同的元素作为同一个加法器的两位加数输入，输入同一个加法器；完成加法运算后，再将运算结果输入回控制系统，重新按照元素序号组成结果向量，即完成了完整的向量加法运算。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
3)、采用上述第三种加法器的方案：
对于上述第三种加法器，等效于进行运算：
R＝k(aX 1+aX 2…+aX n+c)  (10-3-1)
其中，R为加法运算结果，X 1到X n为多个单独光电计算单元的光输入端 输入量，n和使用的并联光电计算单元数量相当，a、c和k都为和加法器单元参数有关的常数。
上述第三种加法器，和上述第二种加法器相同，可以进行加数大于2的加法运算，因此采用上述第三种加法器组成的向量加法器和采用上述第二种加法器组成的向量加法器方案相似，不再重复叙述。
采取本方案进行向量加法运算，相较于传统向量加法运算器有如下优势：
1、集成度高，数个光电计算单元就可实现向量加法运算。
2、输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
向量点乘器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用上述多种种乘法器之一所述的光电计算乘法器，来实现两个维度至少为二的向量的向量点乘运算。
1)、采用上述第一种乘法器的方案：
对于上述第一种乘法器，等效于进行运算：
R＝c(aX+b)Y     (11-1-1)
其中，R为乘法运算结果，X为光输入端输入量，Y为电输入端输入量，c、a、b都为和单元参数有关的常数。
向量点乘，即为两个维度相同的待乘向量对应序号的元素一一相乘，得到一个维度和待乘向量相同的结果向量，以两个维度为k的待乘向量的乘法运算A·B为例：
R＝A·B＝(A 0*B 0，A 1*B 1……A k-1*B k-1)  (11-1-2)
从式(11-1-2)可以看出，向量点乘运算可以拆分成k个两位输入的单独乘法运算，因此使用k个上述第一种乘法器，可以组成向量点乘器，图27所示的向量加法器，只需要将图中每一个中间写有“V加法器”的方框都改为“V乘法器”，代表一个单独的上述第一种乘法器，即可进行所述向量点乘运算。
将待乘向量输入控制系统，在控制系统中将待乘向量拆分成一个个独立元素，并将序号相同的元素作为同一个乘法器的两位乘数输入，输入同一个乘 法器；完成乘法运算后，再将运算结果输入回控制系统，重新按照元素序号组成结果向量，即完成了完整的向量点乘运算。因为上述第一种乘法器只能支持两位加数的输入，因此本方案的向量加法器也只能支持两个待加向量的输入，如需进行多个待乘向量输入的点乘运算只需进行多次两两点乘运算即可。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用上述第二、三、四种乘法器的方案：
上述第二、三、四种乘法器，和上述第一种乘法器相似，支持两位乘数输入的乘法运算，使用上述三种乘法器组成向量点乘器的方案和使用第一种乘法器组成向量点乘器方案类似，不再重复阐述。
采取本方案进行向量点乘运算，相较于传统向量点乘运算器有如下优势：
1、集成度高，数个光电计算单元就可实现向量点乘运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
高位宽乘法器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用上述多种种乘法器之一所述的光电计算乘法器，来实现两个高位宽乘数的乘法运算。
1)、采用上述第一种乘法器的方案：
对于上述第一种乘法器，等效于进行运算：
R＝c(aX+b)Y    (12-1-1)
其中，R为乘法运算结果，X为光输入端输入量，Y为电输入端输入量，c、a、b都为和单元参数有关的常数。
高位宽乘法，即为先将两个高位宽乘数按比特位拆分，再按照高低位依次两两相乘后，再将结果移位后相加，完成完整的高位宽乘法运算。以两个高位宽乘数A*B为例，将高位宽乘数拆分成多个位宽为k的低位宽乘数，再进行高低位相乘：
Figure PCTCN2019111513-appb-000068
从式(12-1-2)可以看出，高位宽乘法分为以下步骤：
1)高位宽乘数拆分；
2)高低位交叉相乘；
3)交叉相乘结果移位；
4)移位结果累加。
使用控制系统进行拆分和移位累加工作，使用(n-1)*(m-1)个上述第一种乘法器进行高低位交叉相乘运算，即可实现完整的高位宽乘法，如图28所述，图中每一个写有“V乘法器”的方框即表示一个上述第一种乘法器，以及此乘法器的输出在控制系统中需要完成的移位位数，实线表示数据输入，虚线表示数据累加。
将待乘的高位宽乘数输入控制系统，在控制系统中将高位宽乘数按比特位拆分成两组低位宽乘数，并将两组低位宽乘数两两组合，输入不同的乘法器；完成乘法运算后，再将运算结果输出回控制系统，按照两个输入低位宽乘数的比特位进行相应的移位操作，再将移位后的结果累加，即完成了完整的向量点乘运算。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用上述第二、三、四种乘法器的方案：
上述第二、三、四种乘法器，和上述第一种乘法器相似，支持两位乘数输入的乘法运算，使用上述三种乘法器组成高位宽乘法器的方案和使用上述第一种乘法器组成高位宽乘法器方案类似，不再重复阐述。
采取本方案进行高位宽乘法运算，相较于传统高位宽乘法器有如下优势：
1、集成度高，数个光电计算单元就可实现高位宽乘法运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
串行矩阵向量乘法器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用多个发光单元和上述实施例中所述的光电计算单元，来实现维度符合矩阵向量乘法规则的一个矩阵和一个向量的乘法运算。
此矩阵向量乘法器的输出端的个数，具体取决于使用的光电计算单元的 输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则矩阵向量乘法器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
本发明需要使用的光电计算单元数默认应与待乘矩阵中元素的个数相当，所述矩阵包含向量，即矩阵如果为3行1列，则使用的光电计算单元数目则为3，但如果光电计算单元的数目大于矩阵中元素的数目，如使用6个光电计算单元排成3行2列，则不影响运算。
1)、采用上述光电计算单元的第一实施例的方案：
以计算向量A和矩阵W的乘法运算A*W为例,其中A为n*1向量，W为m*n矩阵，如式(13-1-1)，计算示意图如图29所示，图中标有V字符的方框单元即代表采用第一种方案的光电计算单元，其中向量A中的元素通过电输入端输入，矩阵W中的元素通过光输入端输入。
Figure PCTCN2019111513-appb-000069
首先，类似于上述第二种乘法器所述的串行输入乘法器的电输入方式，将A每一个的元素在控制系统中进行二进制转化：
Figure PCTCN2019111513-appb-000070
k取决于向量中单个元素的位宽。
将采用根据上述第一实施例的光电计算单元，按照如图29所示的形式排列成阵列，其中阵列的行数为n，列数为m，并且将所述阵列的所有同一行的光电计算单元的作为所述载流子控制区的控制栅极都相连，输入同样的电输入数据；将所述阵列的所有同一列的光电计算单元的作为所述载流子收集和读出区的P型衬底的输出端都相连，使得输出的电流汇聚相加。
输入时，将矩阵中的m*n个数据，通过光输入端依次输入到m*n个光电计算单元中；将向量中的元素从同行单元相连的控制栅极上串行输入，同一 元素不同比特位的二值数据分时依次输入，当控制栅上输入的是最低比特位的数据时，矩阵中的元素和向量中元素的最低比特位的二值数据进行对应位的相乘，即等于进行了运算(13-1-3)：
Figure PCTCN2019111513-appb-000071
电流汇聚前，n*m的光电计算单元阵列，每一个单元的计算结果分别为：
Figure PCTCN2019111513-appb-000072
再经每一列的输出端都相连的输出电流电路，即等于进行了按列相加运算，结果(13-1-4)经汇聚相加后，最下方的矩阵向量乘法输出端输出为：
Figure PCTCN2019111513-appb-000073
此结果即为式(13-1-3)的运算结果，完成了向量最低比特位和矩阵的矩阵向量乘法运算。
将计算结果(13-1-5)经过AD转换后输入控制系统，因为其为最低比特位故而左移0位，再将向量的第二低比特位作为电输入端数据输入控制栅极，得到向量第二低比特位和矩阵的矩阵向量乘法结果，输入控制系统后左移1位，并与之前所述向量最低比特位和矩阵乘法结果进行向量加法，以此类推，串行输入完向量的所有比特位二值数据，在控制系统后依次移位和累加后，即得到最终的矩阵向量运算结果，等同于进行了如下运算：
Figure PCTCN2019111513-appb-000074
Figure PCTCN2019111513-appb-000075
所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用根据上述第二、三、四实施例的光电计算单元的方案：
第二、三、四种方案，和第一种方案相似，同样可以通过串行输入的方式，完成两个乘数输入的乘法运算，如上述第二种乘法器所述，因此前文所述的使用第一种方案光电计算单元组成的矩阵向量乘法器，改为使用第二、三、四种方案所述光电计算单元构成的矩阵向量乘法器也同样可以完成运算，唯一的区别只在于：
1)假如使用第二种光电计算单元方案，则因为P衬底器件更换为了N衬底器件，控制栅极和衬底上的电压极性反转了，其大小也需重新调制。
2)假如使用第三种光电计算单元方案，则因为光输入方式的改变，从P型衬底的收集变为了电荷耦合层的收集，因此光输入量需要重新调制。
3)假如使用第四种光电计算单元方案，则并接的载流子控制区不再是控制栅极，而是复位管漏端。
采取本方案进行矩阵向量乘法运算，相较于传统矩阵向量乘法器有如下优势：
1、集成度高，数个光电计算单元就可实现矩阵向量乘法运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
并行矩阵向量乘法器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用多个发光单元和上述实施例中所述的光电计算单元，来实现维度符合矩阵向量乘法规则的一个矩阵和一个向量的乘法运算。本发明提出的实现方案 和上述串行矩阵向量乘法器的区别在于使用更多的光电计算单元和发光单元组成阵列，通过并行输入的方式输入向量中元素的二值化数据，运算速度更高，但是需要更多的单元。
此矩阵向量乘法器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则矩阵向量乘法器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
本发明需要使用的光电计算单元数默认应与待乘矩阵中元素的个数乘以单个元素的位宽的结果相等，所述矩阵包含向量，但如果光电计算单元的数目大于矩阵中元素的数目，则不影响运算。
1)、采用上述光电计算单元的第一实施例的方案：
以计算向量A和矩阵W的乘法运算A*W为例,其中A为n*1向量，W为m*n矩阵，如式(13-1-1)，其中向量A中的元素通过电输入端输入，矩阵W中的元素通过光输入端输入。
Figure PCTCN2019111513-appb-000076
首先，类似于上述第三种乘法器所述的并行输入乘法器的电输入方式，将A每一个的元素在控制系统中进行二进制转化：
Figure PCTCN2019111513-appb-000077
k取决于向量中单个元素的位宽。
将采用根据上述第一实施例的光电计算单元，总共需使用k*m*n个单元，将上述单元分成k组，每个组的单元m*n个，将每一组的单元排列成和上述串行矩阵向量乘法器阵列相同的阵列，即按照图30所示的形式排列成阵列，总共k个上述阵列，每个阵列的行数为n，列数为m，并且将所述所有组的所有阵列的所有同一行的光电计算单元的作为所述载流子控制区的控制栅极都 相连，输入同样的电输入数据；将所述所有组的所有阵列的所有同一列的光电计算单元的作为所述载流子收集和读出区的P型衬底的输出端都相连，使得输出的电流汇聚相加。
输入时，将矩阵中的m*n个数据，通过光输入端依次输入到每一组的m*n个光电计算单元中，所有组的阵列输入相同的光输入端数据；将向量中的元素从同行单元相连的控制栅极上并行输入。向量中各元素的第零比特位，即(A 00,A10,…,An0)将上述二值矩阵的每一个元素分别输入第0组阵列的各行的控制栅上，同样，后续第i比特位，输入到第i组阵列的控制栅上，将二值化后的向量数据一一并行输入到k组阵列的全部控制栅上。对于第0组阵列，矩阵中的元素和向量中元素的第零比特位的二值数据进行对应位的相乘，即等于进行了运算(14-1-3)：
Figure PCTCN2019111513-appb-000078
电流汇聚前，第零组n*m的光电计算单元阵列每一个单元的计算结果分别为：
Figure PCTCN2019111513-appb-000079
再经每一列的输出端都相连的输出电流电路，即等于进行了按列相加运算，结果(14-1-4)经汇聚相加后，最下方的第零组阵列输出端输出为：
Figure PCTCN2019111513-appb-000080
此结果即为式(14-1-3)的运算结果，完成了向量第零比特位和矩阵的矩阵向量乘法运算。
和上述第零组阵列的计算过程相似，其他第1到第k-1组阵列分别从每一行的控制栅上输入向量第1比特位到第k-1比特位的二值化数据，分别输 出相应的矩阵向量乘法结果后从输出端输出，再将k组的计算结果经过AD转换后输入控制系统，第i组阵列的结果向量所有元素左移i位，然后在控制系统中将完成移位后的所有组的输出结果按照向量加法的规则累加，即得到最终的矩阵向量运算结果，等同于进行了如下运算：
Figure PCTCN2019111513-appb-000081
运算的过程，如图31所示，其中图中的每一个中间写有“串行矩阵向量乘法器”的方框即代表一个n*m的单元阵列，装置的示意图，大致如图31所示。
所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用根据上述第二、三、四实施例的光电计算单元的方案：
第二、三、四种方案，和第一种方案相似，同样可以通过并行输入的方式，完成两个乘数输入的乘法运算，如上述第三种乘法器所述，因此前文所述的使用第一种方案光电计算单元组成的矩阵向量乘法器，改为使用第二、三、四种方案所述光电计算单元构成的矩阵向量乘法器也同样可以完成运算，唯一的区别只在于：
1)假如使用第二种光电计算单元方案，则因为P衬底器件更换为了N衬底器件，控制栅极和衬底上的电压极性反转了，其大小也需重新调制。
2)假如使用第三种光电计算单元方案，则因为光输入方式的改变，从P型衬底的收集变为了电荷耦合层的收集，因此光输入量需要重新调制。
3)假如使用第四种光电计算单元方案，则并接的载流子控制区不再是控制栅极，而是复位管漏端。
采取本方案进行矩阵向量乘法运算，相较于传统矩阵向量乘法器有如下优势：
1、集成度高，数个光电计算单元就可实现矩阵向量乘法运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
池化运算器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用向量点乘器、12之一所述的光电矩阵向量乘法器，来实现平均池化运算。
1)、采用上述向量点乘器的方案：
对于上述向量点乘器，等效于进行运算：
Figure PCTCN2019111513-appb-000082
其中，A为向量输入端，即电输入端输入的向量数据，通过串行的方式输入，W为矩阵输入端，即电输入端输入的数据，输出的结果为m*1维度的向量。
池化运算包含很多类运算，例如平均池化、最大池化等，本发明所述的池化运算器，只针对平均池化运算。
平均池化，即求平均数，例如式(15-1-2)
Figure PCTCN2019111513-appb-000083
从式(13-1-2)可以看出，平均池化运算可以等效为下面的向量相乘运算：
Figure PCTCN2019111513-appb-000084
因此，使用适合运算矩阵输入端数据维度为n列1行矩阵(向量)的如 上述向量点乘器，使用n*1个所述的光电计算单元，即可完成上述运算。
首先通过控制系统，判断待池化矩阵中元素的个数，再在控制系统中将待池化矩阵所有元素都拆散，再重新组合成一维向量，从所述矩阵向量乘法器的向量输入端输入，再通过光输入端对矩阵向量乘法器中所有单元输入相同的相当于矩阵中元素个数的倒数的光输入端数据，所述矩阵向量乘法器的输出端的一个输出量即待池化矩阵的平均池化运算结果。所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用上述高位宽乘法器的方案：
上述高位宽乘法器，和上述向量点乘器相似，唯一不同的区别在于向量输入端数据为并行输入，运算速度更快但需要更多的光电计算单元，如果使用上述高位宽乘法器来计算式(15-1-3)，则需要4*K个光电计算单元，K为待池化矩阵A中元素的位宽，而使用上述向量点乘器来计算则只需要4个光电计算单元。
采取本方案进行池化运算，相较于传统池化运算器有如下优势：
1、集成度高，数个光电计算单元就可实现池化运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入，针对池化运算中多次运算平均池化分母不变尤为有优势。
卷积运算器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用多个发光单元和上述实施例中所述的光电计算单元，来实现矩阵的卷积运算。
此卷积运算器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则卷积运算器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
同上述串行、并行矩阵向量乘法器的方案相同，如果使用的光电计算单元数目大于实际所需的个数，并不影响运算结果的正确性。
1)、采用上述光电计算单元的第一实施例的方案：
以矩阵A的针对于卷积核a的卷积运算为例，简单介绍下卷积运算的过程，其中A为10*10矩阵，a为3*3的卷积核，步长为1，如式(16-1-1)：
Figure PCTCN2019111513-appb-000085
卷积运算的规则，是待卷积矩阵在卷积核的映射下和卷积核中元素一一作用，再按照相应的步长移动卷积核，进行下一次映射，如图32所示，要求解(16-1-1)中的卷积运算，需要进行以下几个步骤：
1)补零操作：
将待卷积矩阵A从10*10矩阵扩展为12*12矩阵，即在0行之上，0列之左，10行之下和10列之又各添加一行/列，添加的行列中的元素全部为0，故而叫补零，经过后，矩阵A变为矩阵A 0，如(16-1-2)：
Figure PCTCN2019111513-appb-000086
2)确定初始卷积核位置：
卷积核的初始位置和矩阵A的最左上角重合，即卷积核a的3行3列分别对应矩阵A 0的第0、1、2行和第0、1、2列，再将卷积核中的元素和与卷积核对应位置的矩阵A 0中的元素一一相乘,如式(16-1-3)，变为9个乘法结果，再将所述9个乘法结果全部累加，得到当前卷积核位置的卷积运算结果，叫做R 00，即为完成(16-1-4)所述运算：
Figure PCTCN2019111513-appb-000087
(a 00*0)+(a 01*0)+(a 02*0)+(a 10*0)+(a 11*A 00)+(a 12*A 01)+(a 20*0)+(a 21*A 10)+(a 22*A 11)＝R 00     (16-1-4)
3)移动卷积核的位置：
因为事先约定了，此次卷积运算的步长为1，因此将卷积核的位置左移1列，即左移1列后卷积核a的3行3列分别对应矩阵A 0的第0、1、2行和第1、2、3列，之后再在当前位置下进行卷积运算，将卷积运算结果叫做R 01
4)待卷积核遍历整个矩阵A 0后，一共可以得到(10+2-2) 2个卷积结果，将所述卷积结果按照对应的卷积核位置排列为矩阵，得到(16-1-5)
Figure PCTCN2019111513-appb-000088
上述矩阵R，即为带卷积矩阵A，在卷积核a的作用下进行步长为1的卷积运算的结果。
从上述卷积运算的步骤中可以看出，卷积运算即为多次两个矩阵对应元素两两相乘再累加的运算，其中所述元素两两相乘的两个矩阵，其中一个矩阵为卷积核，为在多次运算中不变的量，另一个矩阵为带卷积矩阵与卷积核位置对应的元素，在多次运算中为变化的量，因此可以利用发明1所述的采用第一种光电计算单元方案的光电计算单元，发挥光输入存储可以存储数据这一优势特性，采用光输入端输入卷积核数据，并通过电输入端输入带卷积矩阵数据进行卷积运算，这样可以极大提高能效比和运算速度。因此，单元的电输入端为卷积运算器的待卷积矩阵数据输入端，光输入端为卷积核输入端。
同矩阵向量乘法一样，卷积运算器也可以分为串行输入和并行输入两种，主要区别为使用单元的数量和电输入端数据输入的方式，串行输入方案如下：
根据卷积运算方式，使用数量和卷积核中元素数量相当的采用第一种方案的光电计算单元，将单元排列成和卷积核维度相同的阵列，并将载流子收集和读出区中读出区的输出端全部相连，通过汇聚完成相加，如图33所示，为针对卷积核维度为3*3的单元阵列。图33中一个中间写有V的方框就代表一个采用第一种方案的光电计算单元。
首先，将卷积核数据通过光输入端，一一输入到所述单元当中，再将矩阵中当前卷积核对应位置的数据转化为二进制，然后串行从所述作为载流子控 制区的控制栅上输入所述阵列中，输出的结果汇聚相加后经过AD转换进入控制系统，再经过移位和累加，即得到当前卷积核位置的卷积运算结果，之后在移动卷积核，利用之前光输入预存好的卷积核数据，直接重新输入电输入数据，即可获得下一个卷积核位置对应的卷积运算结果，以此类推，直到卷积核便利整个待卷积矩阵，然后将输出的卷积结果重新组合成结果矩阵，即完成了全部卷积运算。
如果使用并行输入的卷积运算器，只需要将使用单元数量变为原来的k倍，其中k为带卷积矩阵中元素的位宽，并且将单元变为k组和卷积核维度相同的阵列，同样输出端全部相连，再使用类似于并行矩阵向量乘法器的方法进行电输入端数据并行的输入即可。
所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用根据上述第二、三、四实施例的光电计算单元的方案：
第二、三、四种方案，和第一种方案相似，同样可以通过串行或并行行输入的方式，完成卷积运算，因此前文所述的使用第一种方案光电计算单元组成的卷积运算器，改为使用第二、三、四种方案所述光电计算单元构成的矩阵向量乘法器也同样可以完成运算，唯一的区别只在于：
1)假如使用第二种光电计算单元方案，则因为P衬底器件更换为了N衬底器件，控制栅极和衬底上的电压极性反转了，其大小也需重新调制。
2)假如使用第三种光电计算单元方案，则因为光输入方式的改变，从P型衬底的收集变为了电荷耦合层的收集，因此光输入量需要重新调制。
3)假如使用第四种光电计算单元方案，则作为载流子控制区的不再是控制栅极，而是复位管漏端。
采取本方案进行卷积运算，相较于传统卷积运算器有如下优势：
1、集成度高，数个光电计算单元就可实现卷积运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入，针对卷积运算中多次运算卷积核不变尤为有优势。
神经网络加速器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用上述串行、并行矩阵向量乘法器、池化运算器和卷积运算器的方案，配以相应的控制系统，来实现神经网络算法推理的加速工作。
神经网络算法的推理，以最常见的ALEXnet网络为例，由卷积层和全连接层组成，可以进行如人脸识别等工作，网络的详细结构如图34所示，其中卷积层中包含的运算有卷积运算、池化运算和非线性函数运算；全连接层中包含的运算有矩阵向量乘运算、池化运算和非线性函数运算，可以看到除了非线性函数运算，其他运算在本发明中都已提及了相应的光电运算加速器方案。而非线性函数运算有多种方式，其中最常见的为RELU函数，其函数图像如图35所示，不难看出RELU函数对于小于0的输入，输出都为0，而对大于0的输入，输出都为其本身，因此函数本身仅相当于一个判断大小是否大于0的逻辑控制单元，通过控制系统完成RELU函数运算相当便捷，因此使用上述的4种在神经网络算法中最为常见的计算方式的光电运算器和光电计算方法，已经能够构成一个完整的神经网络加速器和加速方法。
使用光电计算单元来进行神经网络加速最大的好处在于光输入的存储特性，依旧以ALEXnet网络为例，对于ALEXnet网络，每一层的输出数据的维度，都为固定值，如上述卷积运算器的方案中所述，在卷积层中进行卷积运算时，因为卷积核在多次运算中数据是不变的，因此利用光输入数据的存储优势，打一次光即可完成多次甚至全部的卷积运算工作，这极大的降低了存储单元和光电计算单元之间来回交互数据所需要的时间和能量消耗。
对于池化也同样，因为网络中每一层输入输出的数据的维度都为固定值，因此平均池化的分母：待池化矩阵中元素的数量同样为不变的量，通过光输入的存储特性也可以极大的提高运算速度。
在全连接层中，大量的矩阵向量乘的存在是传统计算方式最感到无力的部分，然而所述矩阵向量乘中，矩阵数据为通过训练获得的固定权值，一但完成训练，权值的值就不再改变，因此在进行推理运算时，同样通过光输入的方式将权值输入光电计算单元当中，可以大大提高运算效率。
ALEXnet网络的输入数据为227*227*3的三维矩阵数据，首先经过卷积层1，如图34所述。
卷积层1中卷积核大小为11*11，数量为96个，步长为4的卷积运算， 使用如上述的卷积运算器的方案，则需要最少96个如上述的针对卷积核尺寸11*11的卷积运算器。卷积层1中的池化运算使用平均池化，因为内核尺寸为3*3，因此为9个数平均为1个数，因此最少需要一个如上述池化运算器所述的针对3*3矩阵输入的池化运算器。
以此类推，卷积层2中，最少需要256个如上述的卷积核尺寸为5*5的卷积运算器，需要至少一个如上述池化运算器所述的针对3*3矩阵输入的池化运算器。
卷积层3中，最少需要384个如上述的针对卷积核尺寸为3*3的卷积运算器。
卷积层4中，最少需要384个如上述的针对卷积核尺寸为3*3的卷积运算器。
卷积层5中，最少需要256个如上述的针对卷积核尺寸为3*3的卷积运算器，至少一个如上述池化运算器所述的针对3*3矩阵输入的池化运算器。
全连接层1中，最小需要一个如上述串行、并行矩阵向量乘法器所述的支持4096*9216规模矩阵、1*9216规模向量的矩阵向量乘法器。
全连接层2中，最小需要一个如上述串行、并行矩阵向量乘法器所述的支持4096*4096规模矩阵、1*4096规模向量的矩阵向量乘法器。
全连接层3中，最小需要一个如上述串行、并行矩阵向量乘法器所述的支持1000*4096规模矩阵、1*4096规模向量的矩阵向量乘法器。
综述，总共需要上述如此数量的矩阵向量乘法器、池化运算器和卷积运算器，配以相应的控制系统部分，就可以组成完整的ALEXnet网络加速器，如需要提高计算速度，可以考虑使用并行输入的方式，消耗更多的计算器，获得更高的计算速度。
所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
采取本方案进行神经网络加速，相较于传统神经网络加速器有如下优势：
1、集成度高，完成完整加速工作使用的光电计算单元少。
2、针对矩阵向量乘、卷积运算、池化运算中矩阵权值、卷积核和池化运算的平均值分母在多次运算中不变的特点，采用光输入输入上述运算量，能将光输入的存储特性最大化发挥出来。
CT算法加速器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用多个发光单元和上述实施例中所述的光电计算单元，来实现CT算法的加速工作。
此CT算法加速器的输出端的个数，具体取决于使用的光电计算单元的输出端的个数，例如如果使用具有两个输出端的上述实施例中所述的光电计算单元，则CT算法加速器也具有两个输出端，下文的详细叙述中默认采取有一个输出端的光电计算单元。
同上述串行、并行矩阵向量乘法器相同，如果使用的光电计算单元数目大于实际所需的个数，并不影响运算结果的正确性。
1)、采用上述光电计算单元的第一实施例的方案：
CT算法的大致内容如下，CT，即电子计算机断层扫描，它是利用精确准直的X线束、γ射线、超声波等，与灵敏度极高的计算器一同围绕人体的某一部位作一个接一个的断面扫描，具有扫描时间快，图像清晰等特点特点。
CT的拍摄方式和X光的拍摄方式有较大不同，如图36所示，从上至下分别为对一物体用X光和CT的拍摄方式。
CT拍摄，即通过接收到的从不同角度穿过待观测物体一断层的X光强度，来判断出此断层内部物质分部的方法，而将接收到的多组不同断层的一维沿不同角度入射的X光强度转化为二维的多组不同断层的二维物质分部图片的算法，就为CT算法。
CT算法的大致内容如下，如图37所示，图中不规则形状物体即待拍摄物体的这一断层的截面图，多束X光从不同角度穿过它，其中第i条穿过它的射线即为图中所示角度入射的射线，此物体的截面图，即为通过CT拍摄和CT算法希望复原的断层扫描图，将此断层图分割成一个个像素，从第一行第一列开始数，第一行第一列为第一个像素，总共N个像素，第j个像素刚好被第i条X光穿过。
X光穿过物体时会被吸收，根据物质的种类不同(水，细胞组织，骨头等)吸收的量大小也不同，通过判断吸收量多少就能间接判断出所拍摄物体是什么物质。图37中所示截面图中，不同像素的位置对应有不同种类的物质，因此X光穿过这些像素后，会受到不同程度的吸收，沿着不同角度入射的X光 因为穿过的物质不同，当其出射物体后剩余的能量也就不同。定义，图37中所示物体截面内各个像素的灰度值，即代表X光穿过单位像素面积这种物体时，剩余能量的多少，灰度值越高，代表X光穿过这个像素后损失的能量越少，因此，对于第i条射线而言，假设其沿图37所述角度穿过物体，则剩余能量pi为：
p i＝ω i1x 1+ω i2x 2……+ω iNx N    (18-1-1)
式18-1-1中，ω代表穿透系数，ω ij就代表第i条射线是否穿过了第j个像素，如果穿过了，则代表第i条射线被第j个像素中的物体吸收了一部分能量，则ω ij＝1，x j为第j个像素对X光的吸收系数，也就是需要重建的断层扫面图片中第j个像素的灰度值，为待求解量；如果第i条射线没有穿过第j个像素，则代表第j个像素没有吸收第i条射线的能量，则ω ij＝0，将ω称谓投影系数。
综上所述，针对第i条射线的公式如(18-1-1)，则针对所有射线(共L条)的公式如(18-1-2)：
ω 11x 1+ω 12x 2+ω 13x 3+…+ω 1Nx N＝p 1
ω 21x 1+ω 22x 2+ω 23x 3+…+ω 2Nx N＝p 2
…………………………………………………
ω L1x 1+ω L2x 2+ω L3x 3+…+ω LNx N＝p L   (18-1-2)
式(18-1-2)为一多元方程组，x为待重建断层图片像素灰度值，即需要求解的量，其他都为已知量，根据线性代数知识可知，如果L大于等于N，则此方程有唯一解，即可以还原出断层扫面图片。
通常用来求解上述方程的方法称作代数重建算法：
假如式(18-1-2)不是有N个未知数的由L个方程组成的方程组，而是有2个未知数的由2个方程组成的方程组，则这两个方程组可以表示为二维平面里的两条线，因为方程有解，这两条线必定有交点，而交点的坐标即为方程组的解。快速求解方程组解的方法为：
1)在所述平面内随便找一点作为初始迭代点；
2)做所述初始迭代点做方程组第一个方程代表的直线上的投影点，将此投影点作为第二次迭代的点；
3)过所述的第二次迭代的点，做方程组第二个方程代表的直线上 的投影点，将此投影点作为第三次迭代的点；
4)继续将第三迭代点对第一条直线做投影，然后再对第二条直线做投影，反复迭代，直到结果收敛，所述点即为两个直线的交点，也就是方程的解。
上述迭代投影的图示过程如图38所述。
上述过程的数学表达式，即为反复运算迭代式(18-1-3)：
Figure PCTCN2019111513-appb-000089
其中，
Figure PCTCN2019111513-appb-000090
为进行第i次投影时的投影点，也就是第i次迭代时的结果向量，而
Figure PCTCN2019111513-appb-000091
为进行第i次投影时的多维空间平面的系数(方程组系数)，也同样是此方程组对应的射线穿过截面时的投影系数向量。式(18-1-3)迭代次数越多，方程组的解
Figure PCTCN2019111513-appb-000092
也就越准。
迭代式(18-1-3)中，需要反复计算向量向量乘法
Figure PCTCN2019111513-appb-000093
由全部的
Figure PCTCN2019111513-appb-000094
向量组成的矩阵，称之为CT算法中的系统矩阵ω：
Figure PCTCN2019111513-appb-000095
因为
Figure PCTCN2019111513-appb-000096
的实际物理意义是该射线是否穿过了所述像素，穿过了则为1，没穿过则为0，而CT机器射线的发射角度多为固定角度，因此，对于多次CT拍摄而言，系统矩阵ω多为固定值，因此，通过使用发明1中第一种方案所述的光电计算单元的光输入端的存储特性来输入系统矩阵中的数据，会极大的提高能效比和运算速度。
公式(18-1-3)的核心是向量向量乘法
Figure PCTCN2019111513-appb-000097
因此使用如图39所述的 单元阵列可以实现此部计算的加速工作，图中每一个中间写有V的方框，都代表一个采用第一种方案的光电计算单元，以系统矩阵规模为N*L，X射线数目为L的CT算法为例，假设电输入端数据为串行输入，则需要使用的光电计算单元数目为N*L个，将所述数目的光电计算单元排列成N行L列，且同列的所有单元的作为所述载流子收集和读出区的P型衬底的输出端都相连在一起，使运算结果汇聚相加；所有单元的作为所述载流子控制区的控制栅极都相互独立。
工作时，通过光输入端将系统矩阵中的数据全部一一对应输入维度和系统矩阵相同的阵列当中，为CT算法加速器的系统矩阵输入端，之后开始迭代，第一次迭代时，随机生成初始迭代值，带入式(18-1-3)，将初始迭代值转化为二进制，并通过所述阵列的电输入端串行输入阵列中的第一列单元当中，和上述串行矩阵向量乘法器类似，光输入数据和电输入数据完成相乘后，经电流汇聚输出，然后再控制系统中完成移位和累加操作，获得此次迭代中向量乘法的结果，再在控制系统中完成除向量乘法的其他运算，即可完成此次迭代；将上次迭代的结果作为下次迭代的电输入量转化为二进制，串行输入所述阵列第二列单元当中，光输入数据和电输入数据完成相乘后，经电流汇聚输出，然后再控制系统中完成移位和累加操作，获得此次迭代中向量乘法的结果，再在控制系统中完成除向量乘法的其他运算，即完成了第二次迭代；以此类推，直到在所属阵列第L列中完成第L次迭代后，再将第L+1次迭代的输入数据输入第1列阵列中，直到获得认为准确的迭代结果，然后通过控制系统输出给显示系统，即可查看到CT断层扫面的最终结果图片。
如果使用并行输入的CT算法加速器器，只需要将使用单元数量变为原来的k倍，其中k为带卷积矩阵中元素的位宽，并且将单元变为k组和系统矩阵维度相同的阵列，同样同列的单元输出端全部相连，再使用类似于并行矩阵向量乘法器的方法进行电输入端数据并行的输入即可。
所述的控制系统，可以是数字电路，也可以是计算机、单片机、FPGA等多种逻辑控制单元。
2)、采用根据上述第二、三、四实施例的光电计算单元的方案：
第二、三、四种方案，和第一种方案相似，同样可以通过串行或并行行输入的方式，完成CT算法加速的工作，因此前文所述的使用第一种方案光电计 算单元组成的CT算法加速器，改为使用第二、三、四种方案所述光电计算单元构成的矩阵向量乘法器也同样可以完成运算，唯一的区别只在于：
1)假如使用第二种光电计算单元方案，则因为P衬底器件更换为了N衬底器件，控制栅极和衬底上的电压极性反转了，其大小也需重新调制。
2)假如使用第三种光电计算单元方案，则因为光输入方式的改变，从P型衬底的收集变为了电荷耦合层的收集，因此光输入量需要重新调制。
3)假如使用第四种光电计算单元方案，则作为载流子控制区的不再是控制栅极，而是复位管漏端。
采取本方案进行CT算法加速，相较于传统CT算法加速器有如下优势：
1、集成度高，完成完整加速工作使用的光电计算单元少。
2、针对CT算法中系统矩阵中多次运算不变的特点，采用光输入输入上述运算量，能将光输入的存储特性最大化发挥出来。
单精度浮点乘法器的方案
本发明提出了多种光电计算装置和光电计算方法的具体实现方案，通过使用上述高位宽乘法器，和上述第一、二、三种加法器之一所述的光电加法器，来实现两个单精度浮点数的乘法运算。
单精度浮点数，即通过类似科学计数法的方式表述一个带有小数部分的实数，一个单精度浮点数位宽为32位，其中1位符号位，通过一个二进制数表述正负；8位指数位，通过8位2进制数表述小数点左侧部分数的大小；23位尾数位，通过23位2进制数表述小数点右侧部分数的大小，如式(19-1-1)：
(1)符号位(10000111)指数位(10000000000000000000000)尾数位＝(-1) 1*2 1000111-01111111*1.10000000000000000000000＝-2 135-127*1.5＝-384     (19-1-1)
因此，两个浮点数A和B的乘法过程，如式(19-1-2)所示：
A＝(A) 符号位(A) 指数位(A) 尾数位
B＝(B) 符号位(B) 指数位(B) 尾数位
Figure PCTCN2019111513-appb-000098
Figure PCTCN2019111513-appb-000099
不难看出，两个单精度浮点数的乘法就是两个单精度浮点数的符号位相乘、指数位相加再减去127、尾数位相乘的结果。
综上，所述的光电单精度浮点乘法器，也就是需要运算符号位相乘、指数位相加和尾数位相乘三部分运算。其中符号位只需通过通用逻辑判断正负即可，指数位8比特位宽加数的加法再减去01111111，只需要使用如上述第一、二、三种加法器运算即可；而尾数位的两个23比特位宽乘数的乘法运算，因为乘数位宽较大，故而需要使用上述高位宽乘法器来进行运算，上述多种乘法器之一所述的光电计算乘法器，通常适用于光输入端输入精度在8比特左右，最高不超过16比特位宽的乘数输入的乘法运算。
通过控制系统将所述两位待乘单精度浮点数拆分为符号位、指数位和尾数位，将符号位通过控制系统判断正负，指数位输入高位宽乘法器的两个高位宽乘数输入端，尾数位输入光电加法器的两个加数输入端。将三部分输出的结果返回给控制系统，并在控制系统中重新组合成单精度浮点数，即完成了完整的单精度浮点数乘法。
本发明利用半导体材料的光电特性，公开了一种基本的光电混合运算方法和运算器件。由于半导体材料对入射光子可以具有较高的灵敏度、较长的光信号存储时间，并且本身较易于提高集成度，本发明对计算技术具有实质性的提高。
采取本方案进行单精度浮点乘法运算，相较于传统单精度浮点乘法器有如下优势：
1、集成度高，只需要数个光电计算单元就可完成单精度浮点数乘法运算。
2、光输入数据具有存储特性，可在断光后长时间保存在器件内，下次运算时无需重新进行光输入。
数字控制逻辑的权利要求
本发明提出了一种光电计算模块的数字逻辑控制系统，用于控制光电计算模块的状态以及数据输入输出。
下面以上述并行矩阵向量乘光电计算模块的数字逻辑控制系统为例，简 要叙述数字控制逻辑的工作方法。
使用并行矩阵向量乘光电计算模块运算矩阵向量乘法：
Figure PCTCN2019111513-appb-000100
并假设矩阵W中每个元素的位宽为8比特，则至少需要8组n列m行个单元的光电计算阵列来组成能够运算A*W的并行输入矩阵向量乘模块。
假定使用的单元数量就为上述的最低要求，使用8组n列m行个单元来组成运算模块，并且同一组阵列的同行的载流子控制区都向量，同一组阵列同列的载流子收集和读出区的输出端都向量，和说明14中描述的相同。
首先，该光电计算模块的数字控制阵列分为以下几个部分：数据输入部分、光输入控制部分、光接收控制部分、电输入接收控制部分、输出控制部分和自检控制部分，控制的对象有8组n*m的光电运算阵列以及和这些阵列供电的电源模块，以及驱动发光阵列的驱动器。
电源模块，可以提供光电运算阵列在接收光信号、接收电信号、运算以及输出、复位光信号等各个状态下各功能区所需的各种电压。如对于发明1中光电计算单元的第一种实施方案而言，接收光信号时P型衬底需要加-3V，接收电信号时，控制栅上需要加4V或者0V，输出时P型衬底的读出区MOSFET的源漏之间需要加0.5V，复位时衬底需要加1V，则给其供电的电源模块则需要至少能提供-3V、0V、1V、4V这几种电压，并在数字控制逻辑的控制下，在所需的时刻将电压给予阵列中单元的相应部位。
完整的运算过程如下：
1)数据输入
将矩阵数据W和向量数据A输入到数据输入部分，数据输入部分发送给光输入控制部分和电输入接收控制部分并预存于寄存器中。
2)光输入
将光输入控制部分的寄存器中的矩阵数据W中的每一个元素，通过光输入控制部分转化为发光阵列中发光单元需要发光的时长，发送给发光阵列的驱动器，驱动器转化为脉冲，驱动发光阵列发光，实现光输入。
3)光接收
光输入的同时，通过光接收控制部分，发送接收光信号对应的状态信号给电源模块，电源模块改变供电电压，使计算阵列中的单元进入光接收状态，例如，使用发明1中第一种实施方案的光电计算单元，则电源模块在接收到接收光信号的状态信号后，给P型衬底-3V，读出区源漏浮空，控制栅0V，使P型衬底中产生耗尽层，当再有光子入射时，就会吸收该光子产生光生载流子，完成光输入。
4)电输入并接收
光输入完成后，通过光输入控制部分控制驱动器，停止打光；再通过电输入接收部分，发送电输入的状态信号给电源模块，使计算阵列中的单元进入电输入状态，并将寄存器中的向量数据A以并行地方式输入到计算阵列的载流子控制区中。如假如使用发明1中第一种实施方案的光电计算单元，则电源模块此时需要给予控制栅0V或3V的电压，具体给予0V还是3V受到电输入接收控制部分的控制，如果该单元的电输入量应为0，则0V电压施加到控制栅上；如电输入量为1，则3V电压施加到控制栅上，同时，P型衬底保持施加-3V不变，读出区源漏依旧浮空。
5)运算和读出过程
电输入完成后，通过输出控制部分发送输出运算结果的状态信号给电源模块，使光电计算单元进入输出状态，假如使用发明1中第一种实施方案的光电计算单元，则电源模块此时需要给予读出区源漏之间0.5V的电压差，并且保持P型衬底-3V和控制栅上0V/3V电压。作为运算结果的输出电流经汇聚后，先进入AD转换，输出控制部分发送开始AD转换的信号给AD转换器，AD转换器完成转换后从输出端输出转换后的结果和转换结束信号给输出控制部分，接收到转换结束信号后，输出控制部分将接收到的转换结果再送入到移位器和累加器进行移位和累加，得到最终的A*W运算的结果向量后将此结果存储到寄存器中，并发送运算结束的状态信号给电源模块，电源模块结束本次运算。如假如使用发明1中第一种实施方案的光电计算单元，则电源模块在结束运算时需取消施加在读出区源漏之间的0.5V电压差和控制栅上的0V/3V电输入二值信号，但是保持P型衬底的-3V不变，以维持光输入信号的“存储”，等待下一次运算。
6)光输入信号复位过程
如完成本次运算后，光输入数据不再参与之后的运算，需要重新进行下一次光输入，则通过输出控制部分发送光输入数据复位信号给电源模块，电源模块对计算阵列中的单元进行光输入数据的复位。如假如使用发明1中第一种实施方案的光电计算单元，则电源模块此时需要给予P型衬底1V，控制栅0V的电压，同时保持读出区源漏浮空。复位完成后，输出控制部分发送复位完成信号给电源模块，电源模块停止供电，等待下一次光输入。
7)自检过程
自检过程发生在运算模块工作之前，用于对计算阵列中的单元是否发生损坏进行检查。
工作开始前，如需开始自检，自检控制部分发送状态信号给电源模块，电源模块对所有组的所有列的第一行开始自检，如假如使用发明1中第一种实施方案的光电计算单元，则电源模块此时需先给予控制栅3V电压，读出区源漏之间0.5V的电压，输出电流经每一列的输出端输出给自检控制部分，如发现有列输出端存在无电流输出的现象，则判断此列的第一个单元损坏；之后，再撤去控制栅上的3V电压，读出区源漏之间依旧保持0.5V，通过自检控制部分判断每一列的输出电流，如发现有列输出端存在断掉控制栅3V电压后依旧有电流的现象，则判断此列第一个单元损坏。
完成了对第一行的自检，自检控制部分控制换行，对第二行开始自检，自检条件相同，直到完成全部行的自检，即完成了全部自检。
数字控制逻辑的示意图如图40所示。
数字控制逻辑的具体实现方式，可以是数字电路，单片机，FPGA等多种。
其他实施例
本实施例提供了单个采用根据上述第一实施例的光电计算单元的实测光响应曲线，并借助于此在机台上实测获得的光响应曲线作为单个光电计算单元的模型，搭建成了如上述并行输入矩阵向量乘法器的模型和如上述的卷积运算器的模型，并借助于所述搭建成的模型组件成了完整的使用根据上述第一实施例的光电计算单元组建的神经网络加速器。通过用此加速器模型，使用仿真软件尝试仿真推理完整的类AlexNet的网络(不同于上述神经网络加速 器的方案中提到的标准AlexNet网络)对CIFAR-10数据集中的图片进行分类预测这一功能，并对运行结果的准确度进行评估。
单个光电计算单元实测结果以及网络仿真分析
单元参数和测试条件
所使用的采用根据上述第一实施例的光电计算单元的实测光响应曲线如图41所示，其中横坐标为通过曝光时间表征的入射光子数X，纵坐标为作为所述载流子收集和读出区的P型衬底中读出区MOSFET输出端的运算结果大小，运算结果以电流的形式输出。测试时，作为载流子控制区的控制栅极，即V G加3V电压，P型衬底加-3V电压，并给与合适的源漏间电压时所对应的输出结果。
可以看到，除了末尾处的一点不线性，光电计算单元的读出电流和入射光子数有着较好的线性度，和发明1中的公式(1-15)描述相符，实际使用时，只需要截去末尾不线性部分进行运算即可获得更高的计算精确度。
为了获得一个较为保守的仿真结果，没有截去末尾的不线性部分，而是采用了完整的整条曲线来搭建神经网络加速器。
网络结构和数据集
所仿真的类AlexNet的网络模型所包含的结构如图42所示，此类AlexNet网络模型由六层卷积层、五层池化层以及两层全连接层组成，并使用ReLU作为激活函数。为了提高仿真程序运行的速度，池化层没有使用上述池化运算器，而是直接假设使用通用逻辑来进行池化运算。
此网络实现的功能为目标识别，使用的图片数据集为CIFAR-10数据集。该数据集共有60000张彩色图像，这些图像大小是32*32*3，分为10个类，每类6000张图。这里面有50000张用于训练，构成了5个训练批，每一批10000张图；另外10000用于测试，单独构成一批。先使用数据集中的照片进行训练，获得收敛的权值后再将权值带入网络进行推理，用搭建的神经网络加速器模型来仿真运行类AlexNet，最后得出此神经网络加速器模型进行目标识别的准确度高低。很显然，导致最后识别结果不准确的因素有两点，一个网络本身，以及通过训练所获得的权值并不完美所带来的和推理时计算准确度无 关的识别误差；另一个就是因为由计算器件单管模型搭建的神经网络加速器模型存在计算误差，而带来的识别误差。
AD转换精度
通过上述并行矩阵向量乘法器和上述卷积运算器的方案的介绍，不难发现，无论是矩阵向量乘法器每一列的输出端，还是卷积运算器一个卷积核的总输出端，都必须接有一个AD转换，将模拟的电流运算结果转化为数字量，才能送入控制系统参与后续操作，因此，此AD转换的精度将会极大的影响计算的精度。
如上述并行矩阵向量乘法器的方案中所述，在图31所示的并行矩阵向量乘法器当中，一共有k组规模为m*n的阵列，假设每一组阵列的每一列下加装一个AD，并且认为光输入端输入的值范围为(-127,127)，并且将正的光输入值和负的光输入值分别输入到不同矩阵当中，AD位宽为nbit，矩阵向量乘中矩阵的行数为m行，则AD转换精度为：
Figure PCTCN2019111513-appb-000101
其中，127代表单个光电计算单元的输出最大值，即光输入端输入最大值127和电输入端输入二值化后的最大值1相乘的结果，127*m则是一整列单元因电流汇聚后的输出最大值，又因为将光输入端数据分正负矩阵输入的情况下，考虑到正矩阵或负矩阵中数值有一半概率为0，所以实际计算中m的值需要除以2，得到最后的AD转换精度如式21-1所示。
以的类AlexNet网络中的全连接7层为例，此层输入的矩阵规模为2048*1024，输入的向量规模为2048*1，并假设向量中单个元素的位宽为8，则此时需要使用k＝8组规模为2048行*1024列的阵列，AD位数为8，此时AD的精度为：
Figure PCTCN2019111513-appb-000102
即AD转换后可以识别的最小单位为508，小于此值的输出会被舍去，从而造成一定的精度下降。
同理，卷积运算器也会受到类似的因为AD造成的精度下降，不再重复叙述。
网络权值的范围
对于的网络中的全连接层，权值即为矩阵数据，权值的来源为网络的训练，在训练时可以自定义权值的精度，如式(21-2)中就认为权值的精度为8bit，即范围为(-127,127)，训练时权值的精度越高，假设不存在任何计算误差的情况下，网络的准确度也就越高，但是运行的压力也就越大。权值精度对不存在计算误差的理想网络运行的结果如下表，结果为进行推理时目标分类的准确度：
8bit(权值) 7bit(权值) 6bit(权值) 5bit(权值) 4bit(权值)
8bit(激励) 90.830 90.820 90.730 90.380 88.040
可以看到，当向量数据精度为8bit时，权值取8bit和4bit精度差距只有2％左右，因此使用4bit的权值精度进行训练，当收敛后使用训练好的4bit权值带入的仿真模型进行模拟推理运算，对于卷积层中的卷积核中的数据，也同样使用4bit。
网络仿真结果
Figure PCTCN2019111513-appb-000103
从上述仿真的精度可以看到，的神经网络加速器模型跑出的分类准确度为85.4％，只比不存在任何计算误差的理想准确度结果88％相差了3％不到，为一个较高的精度，足够胜任神经网络加速的工作。
同时，假设单个AD的延迟为20ns，则可以推断出每一层网络的运行延迟为0.164ms，跑完一次完整的网络推理需要的时间也就是1.312ms，这相对 于光输入数据少则数秒，多则数年(采用根据上述第三实施例的光电计算单元)的保持时间而言，已经是一个相当短的时间了，即便是数秒的维持时间，也足以在一次光输入的时间窗口内运行上千次完整的网络推理。如果将上述神经网络加速器用于视频监控中的物体识别，则完整网络1.312ms的推理耗时可以轻松满足上百帧的视频实时监控，而达到这一指标，不考虑外围逻辑电路，最少总共只需要使用约200万个光电计算单元，假设一个光电计算单元面积为3um*3um，则芯片尺寸只有5mm*5mm不到；根据单个光电计算单元的实测结果，每个光电计算单元在读出状态下的功率为仅为0.1uW级别，整个网络推理耗时1.312ms中，每个单元最多只需要运行八分之一的时间，不运行时的漏电流可以忽略不计，因此芯片运行的总功率只有不到0.05W。无论是功耗还是芯片面积，在获得同等计算力的情况下，这都是使用GPU加速神经网络推理不可比拟的。
效果
下表格为预估的光电存算一体芯片和谷歌的TPU芯片在功耗、芯片面积、运算能力以及制作工艺等方面的对比图，其中光电存算一体芯片的参数和性能指标来源于理论推理和仿真结果。
Figure PCTCN2019111513-appb-000104
Figure PCTCN2019111513-appb-000105
可以看出，即便光电存算一体芯片在工作主频远远低于TPU芯片的情况下，其每秒操作数依旧远远高于TPU芯片，这主要是因为光电存算一体芯片中的计算阵列中，单个器件即能完成乘法操作，而电流的汇聚又完成了一次加法操作，因此单个单元就可在一个机械周期中贡献两个操作数，这远远优于TPU芯片，同时也导致了芯片面积也小于TPU芯片；而光电存算一体芯片的另一大优势：光输入的存储特性，又导致了光电存算一体芯片在功耗上会远远低于TPU芯片；另外，上述参数都为基于65nm工艺制作的情况下得出的，而谷歌TPU则是28nm工艺的产物，这又给光电存算一体芯在未来通过工艺节点的缩小提高器件性能上创造了可能；最后，可以看出，根据仿真和推导结果，目前的光电存算一体芯片的大部分功耗都浪费在了数字控制。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (49)

  1. 一种光电计算单元，采用光输入和电输入两种方式输入运算量，包括一个半导体多功能区结构，其中，所述半导体多功能区结构包括至少一个载流子控制区、至少一个耦合区、以及至少一个光生载流子收集区和读出区，其中：
    采用光输入的运算量，即光输入量，通过入射光子转化为光生载流子的方式来完成输入；采用电输入的运算量，即电输入量，通过直接注入载流子的方式来完成输入；
    所述载流子控制区，被设置为控制并调制所述光电计算单元内的载流子，并且作为所述光电计算单元的电输入端口，输入其中一个运算量作为电输入量；或者被设置为只控制并调制所述光电计算单元内的载流子，通过其他区域输入电输入量；
    所述耦合区，被设置为连接光生载流子收集区和读出区中的收集区和读出区，使得光子入射产生的光生载流子作用于所述光电计算单元内的载流子，形成运算关系；
    所述光生载流子收集区和读出区，其中收集区被设置为吸收入射的光子并收集产生的光生载流子，并且作为所述光电计算单元的光输入端口，输入其中一个运算量作为光输入量；读出区被设置为作为所述光电计算单元的电输入端口，输入其中一个运算量作为电输入量，并且作为所述光电计算单元的输出端口，输出被光输入量和电输入量作用后的载流子作为单元输出量；或者通过其他区域输入电输入量，读出区只作为所述光电计算单元的输出端口，输出被光输入量和电输入量作用后的载流子，作为单元输出量。
  2. 如权利要求1所述的光电计算单元，其中：包括作为所述载流子控制区的控制栅极、作为所述耦合区的电荷耦合层，以及作为所述光生载流子收集区和读出区的P型衬底，其中：
    所述作为光生载流子收集区和读出区的P型半导体衬底，包括左侧收集区和右侧读出区，所述左侧收集区被设置为用以产生用于光电子收集的耗尽层，并通过右侧读出区读出收集的光电子电荷量，作为光输入端的输入量；所述右侧读出区，包含浅槽隔离、N型漏端和N型源端，被设置为用于读出，同时 也可以作为电输入端，输入其中一位运算量；
    所述作为耦合区的电荷耦合层，被设置用作连接光生载流子收集和读出区中的收集区和读出区，使收集区衬底内耗尽区开始收集光电子以后，收集区衬底表面势就会受到收集的光电子数量影响；并且通过电荷耦合层的连接，使得读出区半导体衬底表面势受到收集区半导体衬底表面势影响，进而影响读出区源漏间电流大小，从而通过判断读出区源漏间电流来读出收集区收集的光电子数量；
    所述作为载流子控制区的控制栅，被设置为用以在其上施加一个脉冲电压，使得在P型半导体衬底读出区中产生用于激发光电子的耗尽区，同时也可以作为电输入端，输入其中一个运算量；
    用于隔离的底层介质层，被设置在所述P型半导体衬底和所述电荷耦合层之间；用于隔离的顶层介质层，被设置在电荷耦合层和所述控制栅之间。
  3. 如权利要求1所述的光电计算单元，其中：包括作为所述载流子控制区的控制栅极、作为所述耦合区的电荷耦合层，以及作为所述光生载流子收集区和读出区的N型衬底，其中：
    所述作为光生载流子收集区和读出区的N型半导体衬底，包括左侧收集区和右侧读出区，所述左侧收集区被设置用以产生用于光空穴收集的耗尽层，并通过右侧读出区读出收集的光空穴电荷量，作为光输入端的输入量；所述右侧读出区，包含浅槽隔离、P型漏端和P型源端，被设置为用于读出，同时也可以作为电输入端，输入其中一位运算量；
    所述作为耦合区的电荷耦合层，用以连接光生载流子收集区和读出区中的收集区和读出区，被设置为使收集区衬底内耗尽区开始收集光空穴以后，收集区衬底表面势就会受到收集的光空穴数量影响；通过电荷耦合层的连接，使得读出区半导体衬底表面势受到收集区半导体衬底表面势影响，进而影响读出区源漏间电流，从而通过判断读出区源漏间电流来读出收集区收集的光空穴数量；
    所述作为载流子控制区的控制栅，被设置为用以在其上施加一个负脉冲电压，使得在N型半导体衬底读出区中产生用于激发光空穴的耗尽区，同时也可以作为电输入端，输入其中一位运算量；
    用于隔离的底层介质层，被设置在所述N型半导体衬底和所述电荷耦合层之间；用于隔离的顶层介质层，被设置在电荷耦合层和所述控制栅之间。
  4. 如权利要求1所述的光电计算单元，其中：包括作为所述载流子控制区的控制栅极、作为所述耦合区的电荷耦合层，以及作为所述光生载流子收集区和读出区的P型衬底，其中：
    所述作为光生载流子收集区和读出区的P型半导体衬底，包含一个N型漏端和一个N型源端，被设置为同时承担感光和读出的工作，同时也可以作为电输入端，输入其中一位运算量；
    所述作为耦合区的电荷耦合层，被设置为用以储存进入其中的光电子，并改变读出时单元阈值大小，进而影响读出区源漏间电流，从而通过判断读出区源漏间电流来读出感光时产生并且进入电荷耦合层中的光电子数量；
    所述作为载流子控制区的控制栅，被设置为用以在其上施加一个脉冲电压，使得在P型半导体衬底读出区中产生用于激发光电子的耗尽区，同时也可以作为电输入端，输入其中一个运算量；
    用于隔离的底层介质层，被设置在所述P型半导体衬底和所述电荷耦合层之间；用于隔离的顶层介质层，被设置在所述电荷耦合层和所述控制栅之间。
  5. 如权利要求1所述的光电计算单元，其中：包括作为所述载流子控制区的复位管、作为所述耦合区的光电子耦合引线，以及作为所述光生载流子收集区和读出区的光电二极管和读出管，此外，还包括选址管，用于将所述光电计算单元组成阵列时行列选址使用，其中：
    所述作为光生载流子收集区和读出区的光电二极管和读出管，其中，光电二极管被设置为负责感光，所述光电二极管的N区通过作为耦合区的所述光电子耦合引线连接到读出管的控制栅和复位管的源端上；所述读出管，其源端和选址管漏端连接，被设置为用于读出，同时也可以作为电输入端，输入其中一位运算量；
    所述作为耦合区的光电子耦合引线，被设置为连接作为光生载流子收集区和读出区中的收集区和读出区的光电二极管和作为读出区的读出管，将光电二极管N区电势施加到读出管控制栅上；
    所述所谓载流子控制区的复位管，被设置为通过其漏端输入一个正电压作用于光电二极管，当复位管打开时，所述正电压即会作用在光电二极管上，使光电二极管产生耗尽区并感光，同时也可以作为电输入端，输入其中一位运算量；
    所述选址管，被设置为用于控制整个光电计算单元的输出。
  6. 如权利要求1所述的光电计算单元，其中，还包括一个在光学上与光电计算单元相对应的发光单元，所述发光单元被设置为发出的光在所述光电计算单元中产生光生载流子，被作为光电计算单元的光输入量，并且与所述光电计算单元中电输入端输入的电输入量相互作用，所得结果被设置为光电运算结果。
  7. 根据权力要求6所述的光电计算单元，其中，所述发光单元由一个信号转换驱动器进行驱动，所述信号转换驱动器被设置为将数字信号转化为发光单元的驱动电流脉冲脉宽，同时驱动整片多个发光单元组成的发光阵列，或通过选址来驱动特定的相关的发光单元，使得所述相关的发光单元产生相应时长的光信号，所述光信号被设置为作为相应光电计算单元的光学输入量。
  8. 如权利要求6所述的光电计算单元，被设置为组成二维或三维阵列，形成光电计算模块，实现各种特定的运算功能。
  9. 一种光电计算阵列，由多个如权利要求6所述的光电计算单元组成，其中，所述发光阵列和光电计算阵列之间带有一层或多层光学结构，用以实现来自所述发光阵列的光被照射到所述光电计算阵列预定位置的对焦方式，实现发光阵列和光电计算阵列之间的光学对应。
  10. 一种由光电计算单元执行的光电计算方法，所述光电计算单元包括至少一个发光单元和至少一个光电计算单元，所述光电计算单元包括一个半导体多功能区结构，所述多功能区结构包括载流子控制区、耦合区、以及光生载流子收集区和读出区，其中所述方法包括：
    将所述发光单元设置为发出光，并且所述光照射到所述光电计算单元，并经所述载流子控制区控制，在光生载流子收集区和读出区中的收集区中产生光生载流子，作为光电计算单元的第一个运算量；
    在所述多功能区中的其中一个区产生电运算量并输入相应的载流子，所述载流子作为光电计算单元的第二个运算量；
    将代表所述第一个运算量的光生载流子与代表所述第二个运算量的载流子共同作用于光生载流子读出区的载流子，被作用后的载流子作为所述光电运算的结果；
    将作为光电运算结果的载流子，在所述光生载流子收集区和读出区的读出区的输出端输出。
  11. 如权利要求6所述的光电计算单元，被用于作为加法器，包含一个所述发光单元以及一个光电计算单元，所述光电计算单元至少包含载流子控制区、耦合区和光生载流子收集区和读出区，其中：
    所述发光单元，被设置为发出代表第一个加数的光信号；
    所述载流子控制区，用于控制并调制所述光电计算单元内的载流子，并被设置为光电计算单元的电输入端，用于输入第二个加数；
    所述耦合区，被设置为连接光生载流子收集区和读出区，并使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述光生载流子收集区和读出区，包含一个光输入端和至少一个结果输出端，其中：所述光生载流子收集区和读出区中的收集区，被设置为吸收发光单元发出的光，产生并收集光生载流子，并且在所述光输入端输入第一个加数，所述第一个加数和所述第二个加数共同作用于光生载流子收集区和读出区中读出区里的载流子，并且被作用后的载流子经结果输出端被作为加法器的结果输出。
  12. 如权利要求10所述的光电计算方法，被用于进行加法运算，其中：
    所述发光单元发出的光子所产生的光生载流子被设置为第一个加数；
    在所述载流子控制区注入载流子，并且将所述载流子作为第二个加数；
    在所述光生载流子收集区和读出区中，使代表所述第一加数的光生载流子 和代表所述第二加数的载流子共同作用于光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子被作为所述加法运算的结果，在光电子收集区和读出区被输出。
  13. 如权利要求6所述的光电计算单元，被用于作为多个加数同时相加的加法器，包含一个所述发光单元一个光电计算单元，所述光电计算单元至少包含载流子控制区、耦合区、以及光生载流子收集区和读出区，其中：
    所述发光单元，被设置为发出代表第一个加数的光信号；
    所述载流子控制区，被设置为采用并排的多控制区结构，以用于控制并调制单元内的载流子，并作为加法器的电输入端，输入其他多个加数；
    所述耦合区，被设置为连接光生载流子收集区和读出区，并使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述光生载流子收集区和读出区，包含一个光输入端和至少一个结果输出端，其中，光生载流子收集区和读出区中的收集区，被设置为吸收发光单元发出的光，产生光生载流子并收集，并作为所述加法器的光输入端口，被输入其中一个加数，由电输入端和光输入端共同输入的多个加数共同作用于光生载流子收集区和读出区中读出区里的载流子，并且所述光生载流子读出区中的载流子经结果输出端被作为加法器的结果输出。
  14. 如权利要求10所述的光电计算方法，用于进行多个加数的加法运算，其中：
    所述发光单元发出的光子所产生的光生载流子被设置为第一个加数；
    所述载流子控制区被设置为多栅极结构，并且将从多栅极输入的载流子作为其他多个加数；
    在所述光生载流子收集区和读出区中，使代表所述第一加数的光生载流子和代表所述其他加数的载流子共同作用于光生载流子收集区和读出区中读出区的载流子，并且被作用后的载流子作为所述加法运算的结果，在光电子收集区和读出区的输出端被输出。
  15. 如权利要求6所述的光电计算单元，被用于作为至少两个加数的加法 器，包含至少两个所述发光单元和至少两个所述光电计算单元，所述光电计算单元，至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    至少两个所述发光单元，被设置为发出代表至少两个加数的光信号；
    至少两个光电计算单元的输出端，被设置为彼此相连，其中所述至少两个光电计算单元的载流子控制区，被设置为输入一个恒定电压值，用于控制并驱动单元内的载流子；
    所述至少两个光电计算单元的耦合区，负责连接光生载流子收集区和读出区，并被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述至少两个光电计算单元的光生载流子收集区和读出区，每个各包含一个光输入端和至少一个结果输出端，其中所述至少两个光电计算单元的光输入端，被设置为分别接受至少两个发光单元发出的所述光信号，所述光信号分别被作为加法器的加数；所述至少两个结果输出端，被设置为输出受光输入端输入量影响的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，并经汇聚后得到最终结果，所述最终结果被作为加法运算的结果输出。
  16. 如权利要求10所述的光电计算方法，用于进行至少两个加数的加法运算，其中：
    所述至少两个发光单元发出的光信号，作为加法器的至少两个加数，对应地照射到至少两个对应的光电计算单元；
    在所述至少两个光生载流子收集区和读出区中，使代表相应加数的光生载流子作用于相应的光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在一个恒定电压的驱动下，以电流的形式输出，再流经相连的输出端完成电流的汇聚，所述汇聚后的电流值被作为加法器的结果输出。
  17. 如权利要求6所述的光电计算单元，被用于作为乘法器，包含所述一个发光单元以及一个光电计算单元，所述光电计算单元至少包含载流子控制区、耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元，在被设置为发出代表第一个乘数的光信号；
    所述载流子控制区，被设置为输入恒定的电压值，用于控制并驱动单元内的载流子；
    所述耦合区，连接光生载流子收集区和读出区，并被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述光生载流子收集区和读出区，包含一个光输入端、一个电输入端和至少一个结果输出端，其中，光生载流子收集区和读出区中的收集区，被设置为吸收发光单元发出的光，产生光生载流子并收集，为乘法器的光输入端口，输入第一个乘数；所述电输入端口，被设置为输入乘法器的第二位乘数，并且所述光生载流子收集区和读出区中读出区内的被第一位乘数和第二位乘数共同作用的载流子，作为光输入量和电输入量作用后的载流子，在光电子收集区和读出区的输出端作为结果被输出。
  18. 如权利要求10所述的光电计算方法，被用于进行乘法运算，其中：
    所述发光单元发出的光子所产生的光生载流子被设置为乘法器的第一个乘数；
    在所述光生载流子收集区和读出区，从读出区的电输入端口输入的载流子被设置为乘法器的第二个乘数，使代表所述第一乘数的光生载流子和代表所述第二加数的载流子共同作用于光生载流子收集区和读出区中读出区内的载流子，并且被作用后的所述载流子被作为乘法器的结果，在光电子收集区和读出区的输出端被输出。
  19. 如权利要求6所述的光电计算单元，被用于作为乘法器，包含一个所述发光单元一个光电计算单元，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元，被设置为发出代表第一个乘数的光信号；
    所述载流子控制区，被设置为控制并调制单元内的载流子，并作为光电计算单元的电输入端，串行的按照高低位的顺序输入经过二进制转换的第二个乘数；
    所述耦合区，被设置为负责连接光生载流子收集区和读出区，使光生载流 子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述光生载流子收集区和读出区，包含一个光输入端和至少一个结果输出端，其中，光生载流子收集区和读出区中的收集区，被设置为吸收发光单元发出的光，产生光生载流子并收集，为乘法器的光输入端口，输入第一个乘数；所述第一个乘数和所述第二个乘数的二进制各比特位上的二值化输入量共同作用于光生载流子收集区和读出区中读出区里的载流子，并且所述读出区中的载流子经结果输出端被作为第一个乘数和第二个乘数各比特位上的值的乘法结果被依次串行地输出，再经过移位和拼接工作，得到最终的乘法结果。
  20. 如权利要求10所述的光电计算方法，被用于进行乘法运算，其中：
    所述发光单元发出的光子所产生的光生载流子被设置为乘法器的光输入端数据，为第一个乘数；
    将被代表为第二位乘数的量被转化为二进制，并按照比特位高低串行地从所述载流子控制区以被调制过的载流子形式注入，且所述被调制的载流子被作为乘法器的第二个乘数，从电输入端输入；
    在所述载流子收集区和读出区中，使代表所述第一个乘法量的光生载流子和代表所述第二个乘法量的串行输入地载流子控制区载流子依次共同作用于相应的光生载流子收集区和读出区中读出区的载流子；
    在光电子收集区和读出区的输出端的输出量，作为结果被输出，再依次被移位和累加，所得结果为最终的乘法运算结果。
  21. 如权利要求6所述的光电计算单元，用于作为乘法器，包含至少两个所述发光单元和至少两个所述光电计算单元，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其中还包括：
    所述至少两个发光单元，被设置为发出数值相同的光信号，所述光信号被作为第一个乘数；
    至少两个光电计算单元，被设置为并行排列，但不改变发光单元在光学上与之对应的关系，其中所述至少两个光电计算单元的载流子控制区，被设置用于控制并调制单元内的载流子，并且按照比特位高低，将经过二进制转化后的第二个乘数的二值数据，并行地输入到所述至少两个并行排列的光电计算单 元上，作为乘法器的电输入端数据，其组合被作为第二个乘数；
    所述至少两个光电计算单元的耦合区，连接光生载流子收集区和读出区，被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述至少两个光电计算单元的光生载流子收集区和读出区，每个各包含一个光输入端和至少一个结果输出端，其中所述至少两个光电计算单元的光输入端，被设置为接受至少两个发光单元发出的所述光信号；所述至少两个结果输出端，被设置为输出受第一个乘数和第二个乘数各个比特位数据共同影响的光生载流子收集区和读出区中读出区里的载流子，并且在至少两个光电子收集区和读出区的输出端输出，进行移位和累加的操作，其结果被作为乘法器的结果被输出。
  22. 如权利要求10所述的光电计算方法，被用于进行乘法运算，其中：
    所述至少两个发光单元发出的光子所产生的光生载流子被设置为乘法器的光输入端数据，作为第一个乘数；
    将代表第二个乘数的量转化为二进制，并按照比特位高低并行地从所述至少两个载流子控制区以被调制过的载流子形式分别注入不同的单元中，且所述被调制的载流子，被作为第二个乘数；
    在所述至少两个载流子收集区和读出区中，使代表所述第一个乘法量的光生载流子和代表所述第二个乘法量不同比特位二值数据的载流子控制区载流子，分别作用于相应的至少两个光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在光电子收集区和读出区的输出端作为结果被输出，再经过移位和累加操作，被作为最终的乘法器运算结果。
  23. 如权利要求6所述的光电计算单元，被用于作为乘法器，包含至少两个所述发光单元和至少两个所述光电计算单元，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其中还包括：
    所述至少两个发光单元，被设置为发出数值相同的光信号，所述光信号被作为第一个乘数；
    至少两个光电计算单元，被设置为并行排列，但不改变发光单元在光学上 与之的对应关系，并将输出端相连，其中，所述至少两个光电计算单元的载流子控制区，被设置用于控制并调制单元内的载流子，并且按照比特位高低，将经过二进制转化后的第二个乘数的二值数据并行的输入到所述至少两个并行排列的光电计算单元上，作为乘法器的电输入端数据，为第二个乘数；
    所述至少两个光电计算单元的耦合区负责连接光生载流子收集区和读出区，被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述至少两个光电计算单元的光生载流子收集区和读出区，每个各包含一个光输入端、一个电输入端和至少一个结果输出端，其中，所述光电计算单元的光输入端被设置为接受至少两个发光单元发出的所述光信号；所述电输入端，被设置为按照载流子控制区上输入数据比特位的高低，输入代表所述比特位位权的载流子；所述至少两个结果输出端，输出受第一个乘数、第二个乘数的各个比特位数据和各个比特位位权共同影响的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，并经汇聚后输出最后的乘法结果。
  24. 如权利要求10所述的光电计算方法，被用于进行乘法运算，其中：
    所述至少两个发光单元发出的光子所产生的光生载流子被设置为乘法器的光输入端数据，为第一个乘数；
    将被作为第二个乘数的量被转化为二进制，并按照比特位高低并行地从所述至少两个载流子控制区以被调制过的载流子形式分别注入不同的单元中，且所述被调制的载流子，被作为第二个乘数；
    在所述至少两个载流子收集区和读出区中，通过电输入端输入被设置为和载流子控制区上输入数据比特位位权相当的载流子，并且使代表所述第一个乘法量的光生载流子和代表所述第二个乘法量不同比特位的二值数据的载流子控制区的载流子，以及代表位权的载流子收集区和读出区的电输入端载流子，共同作用于相应的至少两个光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子以电流的形式输出，并加以汇聚，其结果被作为所述乘法器的结果输出。
  25. 如权利要求11、13、15中任一项所述的光电计算单元，被用于组成光电计算向量加法器，用于进行至少两组维度至少为二的向量的加法运算，其中，所述光电计算加法器包含至少两个加数输入端和结果输出端，其特征还在于：
    至少两个所述光电计算加法器，被设置为并行排列；
    每一个所述加法器的输入端，被设置为输入至少两位加数，代表至少两个待加向量相同序号的对应元素，其中，使用的加法器输入端的数量，不少于所述待加向量的数量；
    每一个所述加法器的输出端，被设置为输出两个向量相同序号对应元素相加的结果，所述至少两个结果被组合，拼接成一个完整的向量，所述完整的向量为所述向量加法器的运算结果。
  26. 如权利要求12、14、16中任一项所述的光电计算方法，被用于进行向量加法运算，用于进行至少两组维度至少为二的向量的加法运算，其中：
    将所述至少两个待加向量按照维度进行拆分，形成多组独立的加数；
    将每一组独立的加数输入到每一个加法器的加数输入端，其中使用的加法器输入端的数量不少于待加向量的数量；
    将所述至少两个加法器输出端的输出结果，按照输入的向量元素序号，重新拼接成一个完整的向量，所述完整的向量即为至少两个待加向量加法运算后的结果向量。
  27. 如权利要求19、21、23、25中任一项所述的光电计算单元，被用于组成光电计算向量点乘器，用于进行维度至少为二的向量的点乘运算，其中，所述光电计算乘法器包含两个乘数输入端和结果输出端，其中：
    至少两个所述光电计算乘法器，被设置为独立并行排列；
    每一个乘法器的输入端，被设置为输入待乘向量相同序号的对应元素的乘数；
    每一个乘法器的输出端，被设置为输出两个待乘向量相同序号对应元素相乘的结果，所述至少两个结果，拼接成一个完整的向量，所述完整向量为所述向量点乘器的运算结果。
  28. 如权利要求20、22、24、26中任一项所述的光电计算方法，被用于进行向量点乘运算，用于进行维度至少为二的向量的点乘运算，其中：
    将两个待乘向量按照维度进行拆分，形成多组独立的乘数；
    将每一组独立的乘数输入到每一个乘法器的乘数输入端；
    将所述至少两个乘法器输出端的输出结果，按照输入的向量元素序号，重新拼接成一个完整的向量，所述完整的向量即为两个待乘向量点乘后的结果向量。
  29. 如权利要求19、21、23、25中任一项所述的光电计算单元，被用于组成高位宽乘法器，其中每个所述光电计算乘法器包含两个乘数输入端和结果输出端，其中还包括：
    至少四个所述光电计算乘法器，被设置为并行排列；
    所述至少四个乘法器的输入端，其输入量被设置为经过高低位拆分后的待乘数部分数据的乘数；
    所述至少四个乘法器的输出端，被设置为输出两个待乘数相应高低位相乘后的结果，其中至少四个乘法器输出的结果，被按照输入数据的位权进行相应的移位和累加，得到一个完整的高位宽数，并作为最终的乘法结果。
  30. 如权利要求20、22、24、26中任一项所述的光电计算方法，被用于进行高位宽乘法运算，其中：
    将两个待乘高位宽数按照比特位进行高低位拆分，将两个高位宽乘数拆分成两组低位宽乘数，所述高位宽乘数拆成的份数取决于高位宽乘数的具体位宽；
    拆分后的两组低位宽乘数按照两两相乘的组合规则，分别输入到至少四个乘法器的乘数输入端，其中，使用的乘法器的数量，取决于待乘高位宽乘数具体位宽；
    将所述至少四个乘法器输出端的输出结果按照输入的乘数的位宽高低，进行相应的移位操作，再将移位后的结果累加，最终的累加结果即为两个高位宽乘数相乘后的结果。
  31. 如权利要求6所述的光电计算单元，包含多个所述发光单元和所述光电计算单元，组成串行矩阵向量乘法器；所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元，被设置为发出待乘矩阵中数据的光信号；
    所述光电计算单元，被设置为排列成和待乘矩阵行列数相同的单元阵列，但不改变发光单元在光学上与之的对应关系，其中所述单元阵列每一列的所有单元的光生载流子收集区和读出区的输出端彼此相连，所述单元阵列每一行的所有单元的载流子控制区彼此相连；
    所述单元阵列中每一行单元的载流子控制区，被设置用于控制并调制单元内的载流子，并且按列输入被设置为代表向量中各个元素的载流子，为矩阵向量乘法器的向量数据输入端；其中，所述向量中各个元素的数据被设置为转化为二进制后，按照比特位串行的将代表二值化后数据的载流子输入到各个行的载流子控制区；
    所述光电计算单元的耦合区，负责连接光生载流子收集区和读出区，被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述多个光电计算单元的光生载流子收集区和读出区，每个单元包含一个光输入端和至少一个结果输出端，其中，所述光电计算单元的光输入端被设置为接受相应的发光单元发出的光信号并输入矩阵中的数据，被设置为矩阵向量乘法器的矩阵数据输入端；所述结果输出端，被设置为输出受矩阵数据和向量数据共同作用的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，再按列汇聚，并且将结果进行输出；所输出的结果再按输入的比特位进行移位操作，然后累加，即得到最终的结果向量。
  32. 如权利要求10所述的光电计算方法，用于进行矩阵向量乘法运算，其中：
    所述发光单元发出的光子所产生的光生载流子被设置为矩阵向量乘法器的光输入端数据，为待乘的矩阵数据；
    将所述光电计算单元排列成和待乘矩阵行列数相同的单元阵列，但不改变 发光单元在光学上与之的对应关系，其中，所述单元阵列每一列的所有单元的光生载流子收集区和读出区的输出端彼此相连，所述单元阵列每一行的所有单元的载流子控制区彼此相连；
    向量数据中的每个元素被转化为二进制，并按照比特位高低串行地从被设置为同行相连的载流子控制区以被调制过的载流子形式，将不代表不同元素的数据分别注入不同的行中，为待乘的向量数据；
    在所述载流子收集区和读出区中，使代表所述矩阵数据的光生载流子和代表所述向量数据不同比特位二值数据的载流子控制区载流子共同作用于相应的光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在恒定电压的驱动下，以电流的形式输出，并按列汇聚，再完成移位和累加操作，即得到最终乘法结果向量。
  33. 如权利要求6所述的光电计算单元，被用于组成并行矩阵向量乘法器，包含多个所述发光单元和多个所述光电计算单元，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元被设置为发出待乘矩阵中数据的光信号；
    所述光电计算单元，被设置得分成多组，每一组单元再排列成和待乘矩阵行列数相同的单元阵列，但不改变发光单元在光学上与之的对应关系，其中，所述单元阵列每一列的所有单元的光生载流子收集区和读出区的输出端彼此相连，所述单元阵列每一行的所有单元的载流子控制区彼此相连；
    每一组单元阵列中每一行单元的载流子控制区，被设置为用于控制并调制单元内的载流子，并且并行地按组按列输入被设置为代表向量中各个元素二值化后对应比特位数据的载流子，为矩阵向量乘法器的向量数据输入端；
    多个所述光电计算单元的耦合区负责连接光生载流子收集区和读出区，被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    多个所述光电计算单元的光生载流子收集区和读出区，每个单元包含一个光输入端和至少一个结果输出端，其中，多个所述光电计算单元的光输入端，被设置为接受多个发光单元发出的所述光信号，输入矩阵中的数据，为矩阵向量乘法器的矩阵数据输入端；所述多个结果输出端，被设置为输出受矩阵数据 和向量数据共同作用的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，再按列汇聚后按输入的比特位进行移位操作最后累加，形成最终的结果向量。
  34. 如权利要求10所述的光电计算方法，被用于进行矩阵向量乘法运算，其中：
    所述多个发光单元发出的光子所产生的光生载流子被设置为矩阵向量乘法器的光输入端数据，为矩阵数据；
    将多个光电计算单元分成多组，每一组单元再排列成和待乘矩阵行列数相同的单元阵列，但不改变发光单元在光学上与之的对应关系，其中，所述单元阵列每一列的所有单元的光生载流子收集区和读出区的输出端都相连，所述单元阵列每一行的所有单元的载流子控制区都相连；
    向量数据中的每个元素被转化为二进制，并行地从相应组的被设置为同行相连的载流子控制区以被调制过的载流子形式，将代表不同元素不同比特位的数据分别注入不同组的不同的行中，为向量数据；
    在多个所述载流子收集区和读出区中，使代表所述矩阵数据的光生载流子和代表所述向量数据不同比特位二值数据的载流子控制区载流子分别共同作用于相应的多个光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在恒定电压的驱动下，以电流的形式输出，并按列汇聚，再经过移位和累加操作，即得到最终结果向量。
  35. 如权利要求31、33中任一项所述的光电计算单元，被用于组成平均池化运算器，用于至少包含两个元素的矩阵的池化运算，所述光电矩阵向量乘法器包含一个矩阵输入端、一个向量输入端和结果输出端，其中包括：
    光电矩阵向量乘法器，列数为1，行数和待池化矩阵元素个数相当，作为待池化矩阵的平均池化运算器；
    所述光电矩阵向量乘法器的向量输入端，作为电输入端，输入待池化矩阵中的不同元素，为所述池化运算器的待池化矩阵输入端；矩阵输入端，作为光输入端，输入列数为1，行数和待池化矩阵元素个数相同，且每个元素都为待池化矩阵元素个数的倒数的矩阵，为平均值分母输入端；
    所述结果输出端，被设置为输出待池化矩阵最终的平均池化结果。
  36. 如权利要求32、34中任一项所述的光电计算方法，被用于进行平均池化运算，用于进行元素个数至少为2的矩阵的平均池化运算，其中：
    将待池化矩阵拆分成一个个独立的元素，再将拆分后的所有元素重新组成维度和待池化矩阵元素个数相当的向量；
    所述矩阵向量乘法器，适用于进行待乘矩阵行数和待池化矩阵元素个数相等、列数为1的矩阵向量运算；
    将所述待池化矩阵拆分后重组的向量，作为矩阵向量乘法器的向量输入端，即电输入端数据，输入到矩阵向量乘法器中；将维度和所使用的矩阵向量乘法器相同，每一个元素都为待池化矩阵元素个数的倒数的矩阵作为矩阵向量乘法器的矩阵输入端，即光输入端数据，输入到矩阵向量乘法器中，作为平均池化运算中求平均值的分母；
    所述结果输出端输出结果即为待池化矩阵中每一个元素除以元素个数再相加的结果，即待池化矩阵平均池化后的结果。
  37. 如权利要求6所述的光电计算单元，组成串行卷积运算器，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元，被设置为发出代表卷积核中数据的光信号；
    所述光电计算单元，被设置为排列成和卷积核行列数相等的阵列，但不改变发光单元在光学上与之的对应关系，其中，所述单元阵列的所有单元的光生载流子收集区和读出区的输出端彼此相连，汇总成一个输出端；
    所述阵列中每个光电计算单元的载流子控制区，被设置用于控制并调制单元内的载流子，并且串行输入被设置为代表经过补0操作后的待卷积矩阵中和初始卷积核位置对应的小矩阵中各个元素相应比特位数据的载流子，为卷积运算器的待卷积矩阵数据输入端；其中，所述小矩阵中数据被设置为转化为二进制后，按照比特位串行的将代表二值化后数据的载流子输入到各个单元的载流子控制区；
    所述阵列中光电计算单元的耦合区，连接光生载流子收集区和读出区，被 设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述阵列中每一个光电计算单元的光生载流子收集区和读出区，包含一个光输入端和至少一个结果输出端，其中，所述光输入端被设置为接受发光单元发出的所述光信号，输入卷积核中的数据，为卷积运算器的卷积核输入端；所述每一个单元的输出端，被设置为输出受待卷积矩阵分割出的小矩阵相应比特位数据和卷积核数据共同影响的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，再经并联的输出端使得阵列中全部光电计算单元的输出电流全部汇聚后，最后按输入的比特位进行移位操作然后累加，得到当前卷积核位置对应的卷积运算结果；按卷积运算所需步长移动卷积核的位置，重新输入当前卷积核位置对应的待卷积矩阵数据分割出的小矩阵数据，得到输出值后继续移动卷积核，直到完成全部卷积运算；将所述全部输出值重新组成相应维度的矩阵，即得到最终卷积运算的结果。
  38. 如权利要求10所述的光电计算方法，用于进行卷积运算，其中：
    所述发光单元发出的光子所产生的光生载流子被设置为卷积运算器的光输入端数据，为卷积核数据；
    将光电计算单元排列成和所述卷积运算卷积核行列数相同的单元阵列，但不改变发光单元在光学上与之的对应关系，其中，所述单元阵列中的每一个光电计算单元的所有载流子收集区和读出区中读出区的输出端都相连，汇聚成一个输出端；
    将待卷积矩阵经过补零操作后，按照卷积核当前的位置，分割出维度和卷积核大小相当的小矩阵，并将小矩阵中的每个元素转化为二进制，并按照比特位高低串行地从所述载流子控制区以被调制过的载流子形式输入到每一个单元当中，为待卷积矩阵数据；
    在所述阵列中单元的载流子收集区和读出区中，使代表所述待卷积矩阵中分割出的小矩阵相应比特位数据的光生载流子和代表所述卷积核数据的载流子控制区载流子分别共同作用于相应的光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在恒定电压的驱动下，以电流的形式输出，并全部汇聚，再完成移位和累加操作，得到当前卷积核位置对应的卷积运 算结果；
    按卷积运算所需步长移动卷积核的位置，重新输入当前卷积核位置对应的待卷积矩阵数据分割出的小矩阵数据，得到输出值后继续移动卷积核，直到完成全部卷积运算；将所述全部输出值重新组成相应维度的矩阵，即得到最终卷积运算的结果。
  39. 如权利要求6所述的光电计算单元，被用于组成并行卷积运算器，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元，被设置为发出代表卷积核中数据的光信号；
    所述数量的光电计算单元，被设置为分成多组，并且每一组都排列成行列数和卷积核行列数相等的阵列，但不改变发光单元在光学上与之的对应关系，其中，所述每一组阵列的所有单元的光生载流子收集区和读出区的输出端都相连，汇总成一个输出端；
    所述每一组阵列中每个光电计算单元的载流子控制区，被设置用于控制并调制单元内的载流子，并且并行输入被设置为代表经过补0操作后的待卷积矩阵中和初始卷积核位置对应的小矩阵中各个元素相应比特位数据的载流子，为卷积运算器的待卷积矩阵数据输入端；其中，所述小矩阵中数据被设置为转化为二进制后，将相应比特位对应的数据输入到相应组的单元阵列中；
    所述各个组阵列中光电计算单元的耦合区负责连接光生载流子收集区和读出区，被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述各个组阵列中每一个光电计算单元的光生载流子收集区和读出区，包含一个光输入端和至少一个结果输出端，其中，所述光输入端，用以接受发光单元发出的所述光信号，输入卷积核中的数据，为卷积运算器的卷积核输入端，不同组的阵列接收相同的光输入数据；所述每一个单元的输出端，被设置为输出受待卷积矩阵分割出的小矩阵相应比特位数据和卷积核数据共同影响的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，再经并联的输出端使得阵列中全部光电计算单元的输出电流全部汇聚，最后按输入的比特位进行移位操作然后累加，得到当前卷积核 位置对应的卷积运算结果；按卷积运算所需步长移动卷积核的位置，重新输入当前卷积核位置对应的待卷积矩阵数据分割出的小矩阵数据，得到输出值后继续移动卷积核，直到完成全部卷积运算；将所述全部输出值重新组成相应维度的矩阵，即得到最终卷积运算的结果。
  40. 如权利要求10所述的光电计算方法，被用于进行卷积运算，其中：
    所述发光单元发出的光子所产生的光生载流子被设置为卷积运算器的光输入端数据，为卷积核数据；
    将光电计算单元分成多组，每一组都排列成行列数和卷积核行列数相等的阵列，但不改变发光单元在光学上与之的对应关系，其中，所述每一组单元阵列中的每一个光电计算单元的所有载流子收集区和读出区中读出区的输出端都相连，汇聚成一个输出端；
    将待卷积矩阵经过补零操作后，按照卷积核当前的位置，分割出维度和卷积核大小相当的小矩阵，再将小矩阵中的每个元素转化为二进制，并将相应比特位数据并行地输入相应组阵列的载流子控制区，以被调制过的载流子形式输入到每一个单元当中，为待卷积矩阵数据；
    在所述光电计算单元的载流子收集区和读出区中，使代表所述待卷积矩阵中分割出的小矩阵相应比特位数据的光生载流子和代表所述卷积核数据的载流子控制区载流子分别共同作用于相应的光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在恒定电压的驱动下，以电流的形式输出，一个组阵列的所有输出电流全部汇聚，再完成移位和累加操作，即得到当前卷积核位置对应的卷积运算结果；
    按卷积运算所需步长移动卷积核的位置，重新输入当前卷积核位置对应的待卷积矩阵数据分割出的小矩阵数据，得到输出值后继续移动卷积核，直到完成全部卷积运算；将所述全部输出值重新组成相应维度的矩阵，即得到最终卷积运算的结果。
  41. 一种神经网络算法加速装置，包括如权利要求31或33所述的光电矩阵向量乘法器、如权利要求35所述的平均池化运算器以及如权利要求37或39所述的卷积运算器，其中：
    所述矩阵向量乘法器的矩阵输入端，被设置为输入网络权值，从向量输入端输入上一级网络的输出数据或初始数据；
    所述平均池化运算器的平均值分母输入端，被设置为输入待池化矩阵中元素个数的倒数；待池化矩阵输入端，被设置为输入待池化数据；
    所述卷积运算器的卷积核输入端，被设置为输入卷积核中的数据；从待卷积矩阵输入端输入卷积核当前位置对应的待卷积矩阵中的小矩阵数据，以及非线性函数模块，由电学计算元件组成，被设置为运算非线性函数；
    通用逻辑运算模块，包括电学运算器和/或基于权利要求1所述光电计算单元，被设置为用于整合并控制所述矩阵向量乘法器、平均池化运算器以及卷积运算器的运算功能。
  42. 一种神经网络运算的加速方法，采用如权利要求32或34所述的矩阵向量乘法的光电计算方法、如权利要求36所述的池化运算的光电计算方法以及如权利要求38或40所述的卷积的光电计算方法，其特征还在于：
    从有关的矩阵向量乘法器的矩阵输入端输入网络权值，从所述矩阵向量乘法器的向量输入端输入上一级网络的输出数据或初始数据；
    从有关的平均池化运算器的平均值分母输入端输入待池化矩阵中元素个数的倒数，从所述平均池化运算器的待池化矩阵输入端输入待池化数据；
    从有关的卷积运算器的卷积核输入端输入卷积核中的数据，从所述卷积运算器的待卷积矩阵输入端输入卷积核当前位置对应的待卷积矩阵中的小矩阵数据；
    采用由电学计算元件组成的非线性函数模块，用于运算非线性函数；
    采用通用逻辑运算模块，所述通用逻辑运算模块包括电学运算器和/或基于权利要求1所述光电计算单元，用于整合并控制所述矩阵向量乘法器、平均池化运算器以及卷积运算器的运算功能。
  43. 如权利要求6所述的光电计算单元，被用于组成以代数重建算法为基础的CT算法加速器，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元，被设置为发出CT算法中系统矩阵中数据的光信号；
    所述光电计算单元，被设置为排列成和系统矩阵行列数相等的阵列，但不改变发光单元在光学上与之的对应关系，其中，所述单元阵列的同一列的所有光电计算单元的载流子收集区和读出区的读出区的输出端彼此相连，汇总成一个输出端，不同列的输出端相互独立；
    所述阵列中每个光电计算单元的载流子控制区，被设置用于控制并调制单元内的载流子，并且串行输入被设置为和当前迭代次数对应的预测图像像素数据二值化后相应比特位数据的载流子，为CT算法加速器的预测图像数据输入端；
    所述阵列中光电计算单元的耦合区负责连接光生载流子收集区和读出区，被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述阵列中每一个光电计算单元的光生载流子收集区和读出区，包含一个光输入端和至少一个结果输出端，其中，所述光输入端用以接受发光单元发出的所述光信号，输入系统矩阵中的数据，为CT算法加速器的系统矩阵输入端；所述每一个单元的输出端，输出受当前迭代预测图像像素数据相应比特位数据和系统矩阵数据共同影响的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，再经同列并联的输出端使得阵列中全部光电计算单元的输出电流全部汇聚后，最后按输入的比特位进行移位操作然后累加，再在控制系统中完成其他非矩阵向量乘的运算内容后，进入下一次迭代，并且，初始迭代时，第一次迭代的预测图像像素数据输入所述阵列第一列中单元的载流子控制区，从第一列获得输出结果后经控制系统处理进入第二次迭代，将第二次迭代的预测图像像素数据输入所述阵列的第二列中单元的载流子控制区，以此类推，完成所有列的迭代后输出结果并返回第一列继续迭代，完成全部迭代后输出数据给控制系统后再送达显示系统成像，获得处理过的CT图片。
  44. 如权利要求10所述的光电计算方法，被用于进行CT算法加速，其中：
    将所述发光单元发出的光子所产生的光生载流子设置为CT算法加速器的光输入端数据，为系统矩阵数据；
    将光电计算单元排列成和所述系统矩阵行列数相同的单元阵列，但不改变 发光单元在光学上与之的对应关系，其中，所述单元阵列中同一列的每一个光电计算单元的所有载流子收集区和读出区中读出区的输出端都相连，汇聚成一个输出端；
    按照当前的迭代次数，将对应预测图像像素数据向量中的每个元素转化为二进制，并按照比特位高低串行地从所述载流子控制区以被调制过的载流子形式输入到每一个单元当中，为预测图像数据；
    在所述阵列中单元的载流子收集区和读出区中，使代表所述当前迭代次数预测图像像素相应比特位数据的光生载流子和代表所述系统矩阵数据的载流子控制区载流子分别共同作用于相应的光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在恒定电压的驱动下，以电流的形式输出，并按列汇聚，完成移位和累加操作，再在控制系统中完成其他非矩阵向量乘的运算内容后，进入下一次迭代；
    初始迭代时，第一次迭代的预测图像像素数据输入所述阵列第一列中单元的载流子控制区，从第一列获得输出结果后经控制系统处理进入第二次迭代，将第二次迭代的预测图像像素数据输入所述阵列的第二列中单元的载流子控制区，以此类推，完成所有列的迭代后输出结果并返回第一列继续迭代，完成全部迭代后输出数据给控制系统后再送达显示系统成像，获得处理过的CT图片。
  45. 如权利要求6所述的光电计算单元，被用于组成以代数重建算法为基础CT算法加速器，所述光电计算单元至少包含载流子控制区，耦合区和光生载流子收集区和读出区，其特征为：
    所述发光单元被设置为发出CT算法中系统矩阵中数据的光信号；
    所述光电计算单元被设置为分成多组，并且每一组都排列成行列数和系统矩阵行列数相等的阵列，但不改变发光单元在光学上与之的对应关系，其中，所述各个组阵列的同一列的所有光电计算单元的载流子收集区和读出区的读出区的输出端都相连，汇总成一个输出端，不同组不同列的输出端相互独立；
    所述每一组阵列中每个光电计算单元的载流子控制区，被设置用于控制并调制单元内的载流子，并且并行输入被设置为和当前迭代次数对应的预测图像像素数据二值化后相应比特位数据的载流子，为CT算法加速器的预测图像 数据输入端，其中，所述预测图像数据被设置为转化为二进制后，将相应比特位对应的数据输入到相应组的单元阵列中；
    所述阵列中光电计算单元的耦合区负责连接光生载流子收集区和读出区，被设置为使光生载流子收集区和读出区中收集区的光生载流子作用于所述读出区中的载流子；
    所述阵列中每一个光电计算单元的光生载流子收集区和读出区，包含一个光输入端和至少一个结果输出端，其中，所述的光输入端，用以接受发光单元发出的所述光信号，输入系统矩阵中的数据，为CT算法加速器的系统矩阵输入端，不同组的阵列接收相同的光输入数据；所述的每一个单元的输出端，输出受当前迭代预测图像像素数据相应比特位数据和系统矩阵数据共同影响的光生载流子收集区和读出区中读出区里的载流子，又在固定电压的驱动下以电流的形式输出，再经同列并联的输出端使得阵列中全部光电计算单元的输出电流全部汇聚后，最后按输入的比特位进行移位操作然后累加，再在控制系统中完成其他非矩阵向量乘的运算内容后，进入下一次迭代，并且，初始迭代时，第一次迭代的预测图像像素数据输入所述各个组阵列第一列中单元的载流子控制区，从第一列获得输出结果后经控制系统处理进入第二次迭代，将第二次迭代的预测图像像素数据输入所述各个组阵列的第二列中单元的载流子控制区，以此类推，完成所有列的迭代后输出结果并返回第一列继续迭代，完成全部迭代后输出数据给控制系统后再送达显示系统成像，获得处理过的CT图片。
  46. 如权利要求10所述的光电计算方法，被用于进行CT算法加速，其中：
    将所述发光单元发出的光子所产生的光生载流子设置为CT算法加速器的光输入端数据，为系统矩阵数据；
    将光电计算单元分成多组，并且每一组都排列成行列数和系统矩阵行列数相等的阵列，但不改变发光单元在光学上与之的对应关系，其中，所述单元阵列中同一列的每一个光电计算单元的所有载流子收集区和读出区中读出区的输出端都相连，汇聚成一个输出端；
    按照当前的迭代次数，将对应预测图像像素数据向量中的每个元素转化为二进制，并将相应比特位数据并行地输入相应组阵列的载流子控制区，以被调 制过的载流子形式输入到每一个单元当中，为预测图像数据；
    在所述阵列中单元的载流子收集区和读出区中，使代表所述当前迭代次数预测图像像素相应比特位数据的光生载流子和代表所述系统矩阵数据的载流子控制区载流子分别共同作用于相应的光生载流子收集区和读出区中读出区的载流子，并且被作用后的所述载流子在恒定电压的驱动下，以电流的形式输出，并按列汇聚，完成移位和累加操作，再在控制系统中完成其他非矩阵向量乘的运算内容后，进入下一次迭代；
    初始迭代时，第一次迭代的预测图像像素数据输入所述各个组阵列第一列中单元的载流子控制区，从第一列获得输出结果后经控制系统处理进入第二次迭代，将第二次迭代的预测图像像素数据输入所述各个组阵列的第二列中单元的载流子控制区，以此类推，完成所有列的迭代后输出结果并返回第一列继续迭代，完成全部迭代后输出数据给控制系统后再送达显示系统成像，获得处理过的CT图片。
  47. 一种单精度浮点乘法器，包括如权利要求29所述的光电计算单元和权利要求11、13、15、17中任一项所述的光电计算单元，用于进行单精度浮点数的乘法运算，其中，所述高位宽光电计算乘法器，包含两个高位宽乘数输入端和结果输出端；所述光电加法器，包含两个加数输入端和结果输出端，其中：
    所述高位宽光电计算乘法器的两个高位宽乘数输入端，被设置为尾数输入端，将经过加一操作的两个待乘单精度浮点数的尾数位数据输入高位宽乘法器的两个高位宽输入端，完成相乘后，输出尾数位运算结果给控制系统，
    所述光电加法器的两个加数输入端，被设置为指数输入端，将两个待乘的单精度浮点数的指数位数据输入加数输入端，完成相加后输出指数位运算结果给控制系统，
    所述控制系统，被设置为完成两个待乘单精度浮点数的符号位判断操作，输出相乘后的符号位数据，再与被输出到控制系统的尾数位运算结果、指数位运算结果重新组合成浮点数，最终得到的结果即两个待乘单精度浮点数的乘法结果。
  48. 一种单精度浮点乘法计算方法，采用如权利要求30所述的高位宽乘法 的光电计算方法以及权利要求12、14、16、18中任一项所述的光电计算方法，其中：
    将两个待乘单精度浮点数拆分为两个指数位数据，两个符号位数据和两个尾数位数据，并对所述两个尾数位数据进行加一操作，
    所述两个指数位数据输入光电计算加法器的两个加数输入端，输出结果作指数位运算结果，
    所述两个经过加一操作的尾数位数据输入高位宽乘法器的两个高位宽乘数输入端，输出结果作为尾数位运算结果，
    所述两个符号位数据由一个控制系统完成正负判断后，和尾数位运算结果、指数位运算结果重新组合成浮点数，所获得的两个待乘单精度浮点数，被作为最终乘法结果。
  49. 一种光电计算模块的数字逻辑控制方法，用于如权利要求9所述的光电运算模块的控制，其中：
    通过数字控制逻辑的数据输入部分接收需要进行运算的被运算量，并将需要通过光来输入的数据发送给光输入控制部分，将需要通过电来输入的数据发送给电输入接收控制部分，
    通过数字控制逻辑的光输入控制部分控制发光阵列的驱动装置，使发光阵列产生代表所述光输入量的光子，并入射光电计算单元，
    通过数字控制逻辑的光接收控制部分，控制计算阵列中的光电计算单元，根据具体运算步骤，使需要接收光输入数据的光电计算单元的相应功能区，处于接收光信号状态，并接收入射的代表所述光输入量的光子，完成光输入，通过数字控制逻辑的电输入接收控制部分，控制计算阵列中的光电计算单元，根据具体运算步骤，使需要接收电输入数据的光电计算单元的相应功能区，处于接收电信号状态，并接收输入的代表所述电输入量的载流子，完成电输入，进行运算，
    通过数字控制逻辑的输出控制部分，将计算产生的输出数据按照不同的计算方法进行相应的处理，得到输出所需的计算结果，
    通过数字控制逻辑的自检控制部分，将自检信号输入待自检的光电计算单元，接收光电计算单元的返回信号后得到自检结果，判断待自检的光电计算单 元是否异常。
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