WO2020103322A1 - 一种保护信号产生电路和保护装置 - Google Patents

一种保护信号产生电路和保护装置

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Publication number
WO2020103322A1
WO2020103322A1 PCT/CN2019/070988 CN2019070988W WO2020103322A1 WO 2020103322 A1 WO2020103322 A1 WO 2020103322A1 CN 2019070988 W CN2019070988 W CN 2019070988W WO 2020103322 A1 WO2020103322 A1 WO 2020103322A1
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WO
WIPO (PCT)
Prior art keywords
flip
signal
flop
trigger
level
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PCT/CN2019/070988
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English (en)
French (fr)
Inventor
黄笑宇
Original Assignee
惠科股份有限公司
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Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US17/264,315 priority Critical patent/US11171633B2/en
Publication of WO2020103322A1 publication Critical patent/WO2020103322A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H03K3/02335—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present application relates to the field of storage technology, and in particular to a protection signal generating circuit and a protection device.
  • TFT-LCD Thin Film Transistor Liquid Crystal
  • PCB Print Circuit Board
  • S-COF Source-Chip on Film, source film drive chip
  • G-COF Gate-Chip on Film, gate film drive The chip
  • the current protection signal is logically controlled by externally inputting high / low levels. When the machine setting is wrong or external interference, there is a risk that the software will be rewritten.
  • An object of the present application is to provide a protection signal generating circuit, including but not limited to solving the problem that there is a risk that the software data of the chip may be rewritten when the machine is set incorrectly or outside interference.
  • the protection signal generation circuit includes:
  • a first trigger configured to input an enable signal and an external signal, and output a first level according to the enable signal and the external signal
  • a second trigger connected to the first trigger, and outputting a protection signal according to the preset change of the first level and the external signal;
  • the feedback device is connected between the output end of the second flip-flop and the input end of the first flip-flop, and outputs the enable signal.
  • the external signal is a periodic high and low level signal.
  • the second trigger is a falling edge trigger D flip-flop; when the control end of the first trigger receives When the external signal is at the rising edge, the logic level of the input end of the first flip-flop is assigned to the output end of the first flip-flop, when the control end of the second flip-flop receives the When the external signal is at the falling edge, the logic level of the input terminal of the second flip-flop is assigned to the output terminal of the second flip-flop.
  • the feedback device includes a first switching tube and a second switching tube
  • the first switching tube and the second switching tube are connected between a logic high level and a logic low level.
  • the first switch tube is a P-type insulated gate field effect transistor
  • the second switch tube is an N-type insulated gate field effect transistor
  • the source of the first switch tube Connected to a logic high level Connected to a logic high level
  • the second switch tube is connected to a logic low level
  • the gate of the first switch tube and the gate of the second switch tube are both connected to the output of the second flip-flop, so The drain of the first switch tube and the drain are both connected to the input terminal of the first flip-flop.
  • the protection signal is a level signal.
  • it further includes a first ground resistance and a second ground resistance, the first ground resistance is connected between the input terminal of the first flip-flop and ground, and the second ground resistance is connected Between the control end of the first trigger and the ground.
  • the input enable signal is a level signal
  • the input enable signal when the external signal has no input, the input enable signal is a low level
  • Another object of the present application is to provide a protection device that is connected to a memory chip, characterized in that the protection device includes:
  • a first trigger configured to input an enable signal and an external signal, and output a first level according to the enable signal and the external signal
  • a second trigger connected to the first trigger, and outputting a protection signal according to the preset change of the first level and the external signal;
  • the feedback device is connected between the output terminal of the second trigger and the input terminal of the first trigger, and outputs the enable signal
  • the memory chip receives the protection signal, and controls writing and reading of data according to the protection signal.
  • the external signal is a periodic high and low level signal.
  • the second trigger is a falling edge trigger D flip-flop; when the control end of the first trigger receives When the external signal is at the rising edge, the logic level of the input end of the first flip-flop is assigned to the output end of the first flip-flop, when the control end of the second flip-flop receives the When the external signal is at the falling edge, the logic level of the input terminal of the second flip-flop is assigned to the output terminal of the second flip-flop.
  • the feedback device includes a first switching tube and a second switching tube
  • the first switching tube and the second switching tube are connected between a logic high level and a logic low level.
  • the first switch tube is a P-type insulated gate field effect transistor
  • the second switch tube is an N-type insulated gate field effect transistor
  • the source of the first switch tube Connected to a logic high level Connected to a logic high level
  • the second switch tube is connected to a logic low level
  • the gate of the first switch tube and the gate of the second switch tube are both connected to the output of the second flip-flop, so The drain of the first switch tube and the drain are both connected to the input terminal of the first flip-flop.
  • the protection signal is a level signal.
  • it further includes a first ground resistance and a second ground resistance, the first ground resistance is connected between the input terminal of the first flip-flop and ground, and the second ground resistance is connected Between the control end of the first trigger and the ground.
  • the input enable signal is a level signal
  • the input enable signal when the external signal has no input, the input enable signal is a low level
  • Another object of the present application is to provide a protection signal generation circuit, the protection signal generation circuit including:
  • a first trigger configured to input an enable signal and an external signal, and output a first level according to the enable signal and the external signal
  • a second trigger connected to the first trigger, and outputting a protection signal according to the preset change of the first level and the external signal;
  • the feedback device is connected between the output terminal of the second trigger and the input terminal of the first trigger, and outputs the enable signal
  • the first trigger is a rising edge trigger D flip-flop
  • the second trigger is a falling edge trigger D flip-flop; when the external signal received by the control end of the first trigger is on a rising edge , Assign the logic level of the input end of the first flip-flop to the output end of the first flip-flop, when the external signal received by the control end of the second flip-flop is on the falling edge, The logic level of the input end of the second flip-flop is assigned to the output end of the second flip-flop; when the number of rising and falling edges of the external signal is an even number, the protection signal is high, The external signal allows writing or reading of data.
  • the protection signal generating circuit determines the output level of the protection signal by detecting the change of the preset level of the external signal, thereby controlling the signal writing of the chip, avoiding the misoperation and external interference to change the protection signal Possibility to avoid the risk of software being rewritten.
  • FIG. 1 is a schematic structural diagram of a protection signal generating circuit provided by an embodiment of the present application.
  • FIG. 2 is an example circuit schematic diagram of a protection signal generation circuit provided by an embodiment of the present application.
  • the protection signal generating circuit includes: a first flip-flop 10, a second flip-flop 20, and a feedback device 30, and the protection signal is determined by detecting a preset level change of the external signal F The output level of WP_O, thereby controlling the signal writing and signal reading of the chip.
  • the first flip-flop 10 is configured to input the enable signal E and the external signal F, and output a first level according to the enable signal E and the external signal F;
  • the second flip-flop 20 is connected to the first flip-flop 10 according to the first level and
  • the external signal F outputs the protection signal WP_O;
  • the feedback device 30 is connected between the output terminal Q2 of the second flip-flop 20 and the input terminal D1 of the first flip-flop 10, and outputs the enable signal E.
  • the external signal F is a periodic high and low level signal
  • the input enable signal E is also a level signal.
  • the input D1 of the first flip-flop 10 is connected to the output of the feedback device 30, and receives the enable signal output by the feedback device 30 E
  • the control terminal C1 of the first flip-flop 10 inputs the external signal F
  • the output terminal Q1 of the first flip-flop 10 is connected to the input terminal D2 of the second flip-flop 20
  • the control terminal C2 of the second flip-flop 20 inputs the external signal F
  • the output terminal Q2 of the second flip-flop 20 outputs the protection signal WP_O
  • the input terminal of the feedback device 30 is connected to the output terminal Q2 of the second flip-flop 20.
  • the first flip-flop 10 is a rising edge trigger D flip-flop
  • the second flip-flop 20 is a falling edge trigger D flip-flop.
  • the external signal F received by the control terminal C1 of the first flip-flop 10 is on the rising edge, it will The logic level of the input terminal D1 of the first flip-flop 10 is assigned to the output terminal Q1 of the first flip-flop 10.
  • the external signal F received by the control terminal C2 of the second flip-flop 20 is on the falling edge, the The logic level of the input D2 of the second flip-flop 20 is assigned to the output Q2 of the second flip-flop 20.
  • the feedback device 30 includes a first switching tube M1 and a second switching tube M2.
  • the first switching tube M1 and the second switching tube M2 are connected between a logic high level and a logic low level.
  • the feedback device 30 outputs a logic high level or logic low level according to the protection signal WP_O output by the second flip-flop 20, and outputs the logic high level or logic low level as the enable signal E to the first flip-flop 10
  • the input D1 The input D1.
  • the first switch tube is a P-type insulated gate field effect tube
  • the second switch tube is an N-type insulated gate field effect tube, that is, the first switch tube M1 is further a P-type MOS tube
  • the second switch tube M2 is further an N-type tube MOS tube
  • the source of the first switch tube M1 is connected to a logic high level
  • the second switch tube M2 is connected to a logic low level
  • the gate of the first switch tube M1 and the gate of the second switch tube M2 are connected to the second trigger
  • the output terminal Q2 of the converter 20, the drain of the first switch M1 and the drain of the second switch M2 are both connected to the input D1 of the first flip-flop 10.
  • the output of the feedback device 30 is determined by the signals output from the output terminal Q2 of the second flip-flop 20 to the gate of the first switch M1 and the gate of the second switch M2, when the output Q2 of the second flip-flop 20 is high At level, the first switch M1 is turned on, the second switch M2 is turned off, the feedback device 30 outputs a logic high level, when the output Q2 of the second flip-flop 20 is low, the first switch M1 is turned off Off, the second switch M2 is turned on, and the output of the feedback device 30 is at a logic low level.
  • first grounding resistor R1 and a second grounding resistor R2
  • first grounding resistor R1 is connected between the input terminal D1 of the first flip-flop 10 and ground
  • second grounding resistor R2 is connected to the first flip-flop 10 Between the control terminal C1 and ground.
  • the input terminal D1 of the first flip-flop 10 is grounded through the first grounding resistor R1, and a low level is input.
  • the control terminal C2 of the second flip-flop 20 and the input terminal D2 of the second flip-flop 20 are both Grounded through the second grounding resistor R2, input low level.
  • the external signal F and the enable signal E are at a logic low level.
  • the first trigger 10 will trigger the first The value of the enable signal E input from the input terminal D1 of the device 10 is assigned to the output terminal Q1 of the first flip-flop 10, that is, the input terminal D2 of the second flip-flop 20 is set to a low level at this time, when the external signal F At the falling edge, the second flip-flop 20 assigns the value of the input D2 of the second flip-flop 20 to the output Q2 of the second flip-flop 20, that is, the output Q2 of the second flip-flop 20 is low Level, that is, the protection signal WP_O is low, and when the output terminal Q2 of the second flip-flop 20 is low, the first switch M1 is turned on, the second switch M2 is turned off, even if the value of the signal E Change from low level to high level.
  • the output terminal Q2 of the second flip-flop 20 is assigned a high level, That is, the protection signal WP_O becomes a high level, and when the output terminal Q2 of the second flip-flop 20 is a high level, the first switch M1 is turned off, and the second switch M2 is turned on, even if the value of the enable signal E is high The level changes to a low level, and the cycle is repeated.
  • the present application also provides a protection device connected to the memory chip.
  • the protection device includes: a first flip-flop 10, a second flip-flop 20, and a feedback device 30.
  • the first flip-flop 10 is configured to input the enable signal E and the external signal F, and output a first level according to the enable signal E and the external signal F;
  • the second flip-flop 20 is connected to the first flip-flop 10 according to The first level and the preset change of the external signal F output the protection signal WP_O;
  • the feedback device 30 is connected between the output terminal Q2 of the second flip-flop 20 and the input terminal D1 of the first flip-flop 10, and outputs the enable signal E ;
  • the memory chip receives the protection signal WP_O, and controls the writing and reading of data according to the protection signal WP_O.
  • the present application also provides a protection signal generation circuit of another embodiment.
  • the protection signal generation circuit includes: a first flip-flop 10, a second flip-flop 20, and a feedback device 30.
  • the first flip-flop 10 is configured to input the enable signal E and the external signal F, and output a first level according to the enable signal E and the external signal F;
  • the second flip-flop 20 is connected to the first flip-flop 10 according to The first level and the preset change of the external signal F output the protection signal WP_O;
  • the feedback device 30 is connected between the output terminal Q2 of the second flip-flop 20 and the input terminal D1 of the first flip-flop 10, and outputs the enable signal E ;
  • the first flip-flop 10 is a rising edge trigger D flip-flop
  • the second flip-flop 20 is a falling edge trigger D flip-flop; when the external signal F received by the control terminal C1 of the first flip-flop 10 is on the rising edge,
  • the logic level of the input terminal D1 of the first flip-flop 10 is assigned to the output terminal Q1 of the first flip-flop 10, when the external signal F received by the control terminal C2 of the second flip-flop 20 is on the falling edge, the second The logic level of the input D2 of the
  • the embodiment of the present invention provides a protection signal generation circuit
  • the protection signal generation circuit includes: a first flip-flop 10, a second flip-flop 20 and a feedback device 30, by detecting the rising edge and falling edge of the external signal F
  • the number of signals determines the output level of the protection signal WP_O, thereby controlling the signal writing and reading of the chip, avoiding the possibility of misoperation and external interference to change the protection signal WP_O, and avoiding the risk of software being rewritten.

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Abstract

一种保护信号产生电路和保护电路，其包括第一触发器，配置为输入使能信号和外部信号，根据所述使能信号和所述外部信号输出第一电平；第二触发器，与所述第一触发器连接，根据所述第一电平和所述外部信号输出保护信号；反馈器件，连接于所述第二触发器的输出端和所述第一触发器的输入端之间，输出所述使能信号。

Description

一种保护信号产生电路和保护装置
本申请要求于2018年11月20日提交中国专利局，申请号为201811384860.4，申请名称为“保护信号产生电路和保护装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，尤其涉及一种保护信号产生电路和保护装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。TFT-LCD主要驱动原理是系统主板将R/G/B压缩信号、控制信号及电源通过线材与线路板上的电子连接器相连接，数据经过PCB(Printed Circuit Board，印制电路板)板上的TCON(Timing Controller，时序控制器)芯片处理后，经PCB板，通过S-COF(Source-Chip on Film，源极薄膜驱动芯片)和G-COF(Gate-Chip on Film，栅极薄膜驱动芯片)与显示区连接，从而使得LCD获得所需的电源、信号，线路板上有多颗芯片需要进行软体写入。为防止软体的错误写入，则需要保护信号。目前的保护信号是通过外部直接输入高/低电平进行逻辑控制，在机台设定错误或外界干扰时，则存在软体被改写的风险。
申请内容
本申请的一个目的在于提供一种保护信号产生电路，包括但不限于解决芯 片软件数据在机台设定错误或外界干扰时，存在被改写的风险的问题。
本申请实施例采用的技术方案是：
一种保护信号产生电路，所述保护信号产生电路包括：
第一触发器，配置为输入使能信号和外部信号，根据所述使能信号和所述外部信号输出第一电平；
第二触发器，与所述第一触发器连接，根据所述第一电平和所述外部信号的预设变化情况输出保护信号；
反馈器件，连接于所述第二触发器的输出端和所述第一触发器的输入端之间，输出所述使能信号。
在其中一实施例中，其中，所述外部信号为周期变换高低电平信号。
在其中一实施例中，其中，所述第一触发器为上升沿触发D触发器，所述第二触发器为下降沿触发D触发器；当所述第一触发器的控制端接收到的所述外部信号的处于上升沿时，将所述第一触发器的输入端的逻辑电平赋值给所述第一触发器的输出端，当所述第二触发器的控制端接收到的所述外部信号的处于下降沿时，将所述第二触发器的输入端的逻辑电平赋值给所述第二触发器的输出端。
在其中一实施例中，其中，所述反馈器件包括第一开关管和第二开关管，所述第一开关管和所述第二开关管连接于逻辑高电平和逻辑低电平之间。
在其中一实施例中，其中，所述第一开关管为P型绝缘栅型场效应管，所述第二开关管为N型绝缘栅型场效应管，所述第一开关管的源极连接逻辑高电平，所述第二开关管连接逻辑低电平，所述第一开关管的栅极和所述第二开关管的栅极均连接所述第二触发器的输出端，所述第一开关管的漏极和所述的 漏极均连接所述第一触发器的输入端。
在其中一实施例中，其中，所述保护信号为电平信号。
在其中一实施例中，其中，还包括第一接地电阻和第二接地电阻，所述第一接地电阻连接于所述第一触发器的输入端和地之间，所述第二接地电阻连接于所述第一触发器的控制端和地之间。
在其中一实施例中，其中，所述输入使能信号为电平信号，所述外部信号无输入时，所述输入使能信号为低电平。
本申请的另一目的在于提供一种保护装置，所述保护装置与存储芯片连接，其特征在于，所述保护装置包括：
第一触发器，配置为输入使能信号和外部信号，根据所述使能信号和所述外部信号输出第一电平；
第二触发器，与所述第一触发器连接，根据所述第一电平和所述外部信号的预设变化情况输出保护信号；
反馈器件，连接于所述第二触发器的输出端和所述第一触发器的输入端之间，输出所述使能信号；
所述存储芯片接收所述保护信号，并根据所述保护信号控制数据的写入和读取。
在其中一实施例中，其中，所述外部信号为周期变换高低电平信号。
在其中一实施例中，其中，所述第一触发器为上升沿触发D触发器，所述第二触发器为下降沿触发D触发器；当所述第一触发器的控制端接收到的所述外部信号的处于上升沿时，将所述第一触发器的输入端的逻辑电平赋值给所述第一触发器的输出端，当所述第二触发器的控制端接收到的所述外部信号的处于下降沿时，将所述第二触发器的输入端的逻辑电平赋值给所述第二触发 器的输出端。
在其中一实施例中，其中，所述反馈器件包括第一开关管和第二开关管，所述第一开关管和所述第二开关管连接于逻辑高电平和逻辑低电平之间。
在其中一实施例中，其中，所述第一开关管为P型绝缘栅型场效应管，所述第二开关管为N型绝缘栅型场效应管，所述第一开关管的源极连接逻辑高电平，所述第二开关管连接逻辑低电平，所述第一开关管的栅极和所述第二开关管的栅极均连接所述第二触发器的输出端，所述第一开关管的漏极和所述的漏极均连接所述第一触发器的输入端。
在其中一实施例中，其中，所述保护信号为电平信号。
在其中一实施例中，其中，还包括第一接地电阻和第二接地电阻，所述第一接地电阻连接于所述第一触发器的输入端和地之间，所述第二接地电阻连接于所述第一触发器的控制端和地之间。
在其中一实施例中，其中，所述输入使能信号为电平信号，所述外部信号无输入时，所述输入使能信号为低电平。
本申请的另一目的在于提供一种保护信号产生电路，所述保护信号产生电路包括：
第一触发器，配置为输入使能信号和外部信号，根据所述使能信号和所述外部信号输出第一电平；
第二触发器，与所述第一触发器连接，根据所述第一电平和所述外部信号的预设变化情况输出保护信号；
反馈器件，连接于所述第二触发器的输出端和所述第一触发器的输入端之间，输出所述使能信号；
所述第一触发器为上升沿触发D触发器，所述第二触发器为下降沿触发D 触发器；当所述第一触发器的控制端接收到的所述外部信号的处于上升沿时，将所述第一触发器的输入端的逻辑电平赋值给所述第一触发器的输出端，当所述第二触发器的控制端接收到的所述外部信号的处于下降沿时，将所述第二触发器的输入端的逻辑电平赋值给所述第二触发器的输出端；当所述外部信号的上升沿和下降沿的数量为偶数时，所述保护信号为高电平，所述外部信号允许数据的写入或读取。
本申请实施例提供的保护信号产生电路，通过检测外部信号的预设电平变化情况，确定保护信号的输出电平，从而控制芯片的信号写入，避免了误操作和外部干扰改变保护信号的可能性，避免了软件被改写的风险。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
标注说明：
保护信号WP_O 第一触发器10 第二触发器20 反馈器件30 使能信号E 外部信号F 第一开关管M1 第二开关管M2 第一接地电阻R1 第二接地电阻R2 接地端GND 外部电源VDD
图1是本申请实施例提供的保护信号产生电路结构示意图；
图2是本申请实施例提供的保护信号产生电路的示例电路原理图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实 施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
如图1所示，本申请实施例提供的保护信号产生电路包括：第一触发器10、第二触发器20和反馈器件30，通过检测外部信号F的预设电平变化情况，确定保护信号WP_O的输出电平，从而控制芯片的信号写入和信号读取。
第一触发器10配置为输入使能信号E和外部信号F，根据使能信号E和外部信号F输出第一电平；第二触发器20与第一触发器10连接，根据第一电平和外部信号F输出保护信号WP_O；反馈器件30连接于第二触发器20的输出端Q2和第一触发器10的输入端D1之间，输出使能信号E。其中，外部信号F为周期变换高低电平信号，输入使能信号E也为电平信号。
如图1所示，其中，第一触发器10和第二触发器20为D触发器，第一 触发器10的输入端D1连接反馈器件30的输出端，接收反馈器件30输出的使能信号E，第一触发器10的控制端C1输入外部信号F，第一触发器10的输出端Q1连接第二触发器20的输入端D2，第二触发器20的控制端C2输入外部信号F，第二触发器20的输出端Q2输出保护信号WP_O，反馈器件30的输入端连接第二触发器20的输出端Q2。第一触发器10为上升沿触发D触发器，第二触发器20为下降沿触发D触发器，当第一触发器10的控制端C1端接收到的外部信号F的处于上升沿时，将第一触发器10的输入端D1的逻辑电平赋值给第一触发器10的输出端Q1，当第二触发器20的控制端C2端接收到的外部信号F的处于下降沿时，将第二触发器20的输入端D2的逻辑电平赋值给第二触发器20的输出端Q2。
反馈器件30包括第一开关管M1和第二开关管M2，第一开关管M1和第二开关管M2连接于逻辑高电平和逻辑低电平之间。反馈器件30根据第二触发器20输出的保护信号WP_O，输出逻辑高电平或逻辑低电平，并将该逻辑高电平或逻辑低电平作为使能信号E输出至第一触发器10的输入端D1。
第一开关管为P型绝缘栅型场效应管，第二开关管为N型绝缘栅型场效应管，即第一开关管M1进一步为P型MOS管，第二开关管M2进一步为N型MOS管，第一开关管M1的源极连接逻辑高电平，第二开关管M2连接逻辑低电平，第一开关管M1的栅极和第二开关管M2的栅极均连接第二触发器20的输出端Q2，第一开关管M1的漏极和第二开关管M2的漏极均连接第一触发器10的输入端D1。反馈器件30的输出由第二触发器20的输出端Q2输出至第一开关管M1的栅极和第二开关管M2的栅极的信号决定，当第二触发器20的输出端Q2为高电平时，第一开关管M1导通，第二开关管M2关断，反馈器件30输出为逻辑高电平，当第二触发器20的输出端Q2为低电平时， 第一开关管M1关断，第二开关管M2导通，反馈器件30输出为逻辑低电平。
进一步，还包括第一接地电阻R1和第二接地电阻R2，第一接地电阻R1连接于第一触发器10的输入端D1和地之间，第二接地电阻R2连接于第一触发器10的控制端C1和地之间。在无外部信号F输入时，第一触发器10的输入端D1通过第一接地电阻R1接地，输入低电平，第二触发器20的控制端C2以及第二触发器20的输入端D2均通过第二接地电阻R2接地，输入低电平。
实际应用中，当系统上电时，外部信号F和使能信号E为逻辑低电平，外部信号F输入后，当外部信号F处于上升沿时，此时第一触发器10将第一触发器10的输入端D1输入的使能信号E的值赋值给第一触发器10的输出端Q1，即此时第二触发器20的输入端D2被设定为低电平，当外部信号F处于下降沿时，此时第二触发器20将第二触发器20的输入端D2的值赋值给第二触发器20的输出端Q2，即此时第二触发器20的输出端Q2为低电平，即保护信号WP_O为低电平，而当第二触发器20的输出端Q2为低电平时，第一开关管M1导通，第二开关管M2关断，即使能信号E的值由低电平变为高电平。同理，使能信号E的值由低电平变为高电平后，当外部信号F再经过一次上升沿和一次下降沿时，第二触发器20的输出端Q2赋值为高电平，即保护信号WP_O变为高电平，而当第二触发器20的输出端Q2为高电平时，第一开关管M1关断，第二开关管M2导通，即使能信号E的值由高电平变为低电平，以此循环。
综上所述，可以通过计算外部信号F的上升沿和下降沿的数量，决定保护信号WP_O的输出电平，通过判断保护信号WP_O的电平确定PCB上的各芯片是否可以进行软件写入和读取。具体来说，假定芯片的保护信号WP_O输 入端为高电平有效，当上升沿和下降沿的数量为奇数时，保护信号WP_O为低电平，外部信号F无法对芯片进行软件写入或读取，当上升沿和下降沿的数量为偶数时，保护信号WP_O为高电平，外部信号F允许对芯片进行软件写入或读取。
在上述保护信号产生电路的基础上，本申请还提供了一种保护装置，保护装置与存储芯片连接，该保护装置包括：第一触发器10、第二触发器20和反馈器件30。
其中，第一触发器10，配置为输入使能信号E和外部信号F，根据使能信号E和外部信号F输出第一电平；第二触发器20，与第一触发器10连接，根据第一电平和外部信号F的预设变化情况输出保护信号WP_O；反馈器件30，连接于第二触发器20的输出端Q2和第一触发器10的输入端D1之间，输出使能信号E；存储芯片接收保护信号WP_O，并根据保护信号WP_O控制数据的写入和读取。
本申请还提供另一实施例的保护信号产生电路，该保护信号产生电路包括：第一触发器10、第二触发器20和反馈器件30。
其中，第一触发器10，配置为输入使能信号E和外部信号F，根据使能信号E和外部信号F输出第一电平；第二触发器20，与第一触发器10连接，根据第一电平和外部信号F的预设变化情况输出保护信号WP_O；反馈器件30，连接于第二触发器20的输出端Q2和第一触发器10的输入端D1之间，输出使能信号E；第一触发器10为上升沿触发D触发器，第二触发器20为下降沿触发D触发器；当第一触发器10的控制端C1接收到的外部信号F的处于上升沿时，将第一触发器10的输入端D1的逻辑电平赋值给第一触发器10的输出端Q1，当第二触发器20的控制端C2接收到的外部信号F的处于下降 沿时，将第二触发器20的输入端D2的逻辑电平赋值给第二触发器20的输出端Q2；当外部信号F的上升沿和下降沿的数量为偶数时，保护信号WP_O为高电平，外部信号F允许数据的写入或读取。
综上，本发明实施例提供了一种保护信号产生电路，该保护信号产生电路包括：第一触发器10、第二触发器20和反馈器件30，通过检测外部信号F的上升沿和下降沿的数量，确定保护信号WP_O的输出电平，从而控制芯片的信号写入和读取，避免了误操作和外部干扰改变保护信号WP_O的可能性，避免了软件被改写的风险。
以上仅为本申请的可选实施例而已，并不用于限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (17)

  1. 一种保护信号产生电路，所述保护信号产生电路包括：
    第一触发器，配置为输入使能信号和外部信号，根据所述使能信号和所述外部信号输出第一电平；
    第二触发器，与所述第一触发器连接，根据所述第一电平和所述外部信号的预设变化情况输出保护信号；
    反馈器件，连接于所述第二触发器的输出端和所述第一触发器的输入端之间，输出所述使能信号。
  2. 如权利要求1所述的保护信号产生电路，其中，所述外部信号为周期变换高低电平信号。
  3. 如权利要求1所述的保护信号产生电路，其中，所述第一触发器为上升沿触发D触发器，所述第二触发器为下降沿触发D触发器；当所述第一触发器的控制端接收到的所述外部信号的处于上升沿时，将所述第一触发器的输入端的逻辑电平赋值给所述第一触发器的输出端，当所述第二触发器的控制端接收到的所述外部信号的处于下降沿时，将所述第二触发器的输入端的逻辑电平赋值给所述第二触发器的输出端。
  4. 如权利要求1所述的保护信号产生电路，其中，所述反馈器件包括第一开关管和第二开关管，所述第一开关管和所述第二开关管连接于逻辑高电平和逻辑低电平之间。
  5. 如权利要求4所述的保护信号产生电路，其中，所述第一开关管为P型绝缘栅型场效应管，所述第二开关管为N型绝缘栅型场效应管，所述第一开关管的源极连接逻辑高电平，所述第二开关管连接逻辑低电平，所述第一开 关管的栅极和所述第二开关管的栅极均连接所述第二触发器的输出端，所述第一开关管的漏极和所述的漏极均连接所述第一触发器的输入端。
  6. 如权利要求1所述的保护信号产生电路，其中，所述保护信号为电平信号。
  7. 如权利要求1所述的保护信号产生电路，其中，还包括第一接地电阻和第二接地电阻，所述第一接地电阻连接于所述第一触发器的输入端和地之间，所述第二接地电阻连接于所述第一触发器的控制端和地之间。
  8. 如权利要求1所述的保护信号产生电路，其中，所述使能信号为电平信号，所述外部信号无输入时，所述使能信号为低电平。
  9. 一种保护装置，所述保护装置与存储芯片连接，其特征在于，所述保护装置包括：
    第一触发器，配置为输入使能信号和外部信号，根据所述使能信号和所述外部信号输出第一电平；
    第二触发器，与所述第一触发器连接，根据所述第一电平和所述外部信号的预设变化情况输出保护信号；
    反馈器件，连接于所述第二触发器的输出端和所述第一触发器的输入端之间，输出所述使能信号；
    所述存储芯片接收所述保护信号，并根据所述保护信号控制数据的写入和读取。
  10. 如权利要求9所述的保护装置，其中，所述外部信号为周期变换高低电平信号。
  11. 如权利要求9所述的保护装置，其中，所述第一触发器为上升沿触发D触发器，所述第二触发器为下降沿触发D触发器；当所述第一触发器的控 制端接收到的所述外部信号的处于上升沿时，将所述第一触发器的输入端的逻辑电平赋值给所述第一触发器的输出端，当所述第二触发器的控制端接收到的所述外部信号的处于下降沿时，将所述第二触发器的输入端的逻辑电平赋值给所述第二触发器的输出端。
  12. 如权利要求9所述的保护装置，其中，所述反馈器件包括第一开关管和第二开关管，所述第一开关管和所述第二开关管连接于逻辑高电平和逻辑低电平之间。
  13. 如权利要求12所述的保护装置，其中，所述第一开关管为P型绝缘栅型场效应管，所述第二开关管为N型绝缘栅型场效应管，所述第一开关管的源极连接逻辑高电平，所述第二开关管连接逻辑低电平，所述第一开关管的栅极和所述第二开关管的栅极均连接所述第二触发器的输出端，所述第一开关管的漏极和所述的漏极均连接所述第一触发器的输入端。
  14. 如权利要求9所述的保护装置，其中，所述保护信号为电平信号。
  15. 如权利要求9所述的保护装置，其中，还包括第一接地电阻和第二接地电阻，所述第一接地电阻连接于所述第一触发器的输入端和地之间，所述第二接地电阻连接于所述第一触发器的控制端和地之间。
  16. 如权利要求9所述的保护装置，其中，所述输入使能信号为电平信号，所述外部信号无输入时，所述输入使能信号为低电平。
  17. 一种保护信号产生电路，所述保护信号产生电路包括：
    第一触发器，配置为输入使能信号和外部信号，根据所述使能信号和所述外部信号输出第一电平；
    第二触发器，与所述第一触发器连接，根据所述第一电平和所述外部信号的预设变化情况输出保护信号；
    反馈器件，连接于所述第二触发器的输出端和所述第一触发器的输入端之间，输出所述使能信号；
    所述第一触发器为上升沿触发D触发器，所述第二触发器为下降沿触发D触发器；当所述第一触发器的控制端接收到的所述外部信号的处于上升沿时，将所述第一触发器的输入端的逻辑电平赋值给所述第一触发器的输出端，当所述第二触发器的控制端接收到的所述外部信号的处于下降沿时，将所述第二触发器的输入端的逻辑电平赋值给所述第二触发器的输出端；当所述外部信号的上升沿和下降沿的数量为偶数时，所述保护信号为高电平，所述外部信号允许数据的写入或读取。
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