WO2020113659A1 - 一种驱动方法、驱动电路及显示装置 - Google Patents

一种驱动方法、驱动电路及显示装置 Download PDF

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Publication number
WO2020113659A1
WO2020113659A1 PCT/CN2018/121208 CN2018121208W WO2020113659A1 WO 2020113659 A1 WO2020113659 A1 WO 2020113659A1 CN 2018121208 W CN2018121208 W CN 2018121208W WO 2020113659 A1 WO2020113659 A1 WO 2020113659A1
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Prior art keywords
signal
circuit
driving
output
control signal
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PCT/CN2018/121208
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Priority to US17/043,717 priority Critical patent/US11295689B2/en
Publication of WO2020113659A1 publication Critical patent/WO2020113659A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present application design and display technology field particularly relates to a driving method, a driving circuit and a display device.
  • the system board passes the R/G/B compressed signal, control signal and power signal through the wire and the printed circuit board (Printed Circuit Board, PCB)
  • the connectors are connected, and then the video data is processed by the Timing Controller (TCON) chip on the printed circuit board, and then through the printed circuit board, through the source film driver chip (Source-Chip on Film, S-COF) and The gate film driving chip (Gate-Chip Film, G-COF) is connected to the display area of the panel, thereby enabling the liquid crystal display to obtain the required power signal.
  • TCON Timing Controller
  • the driving circuit needs to be initialized after the thin film transistor liquid crystal display is powered on, the voltage difference across the corresponding liquid crystal will appear when the scanning line is turned on, thereby causing abnormal flashing.
  • An object of the present application is to provide a driving method, including but not limited to, when the scanning line is turned on, the voltage difference appearing across the corresponding liquid crystal is eliminated, thereby eliminating the phenomenon of the occurrence of flashing abnormality.
  • An object of this application is to provide a driving method, including:
  • the timing control circuit receives the execution control signal, and outputs a start scan signal according to the execution control signal.
  • the calculating the drive control signal and the drive voltage signal and outputting the corresponding execution control signal includes:
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a high-level signal.
  • the driving circuit is a source driving chip.
  • the timing control circuit is a timing control chip, and the timing control chip is configured to output a start scan signal to the source driving chip.
  • the timing control circuit receives the execution control signal and outputs a start scan signal according to the execution control signal, including:
  • the start scan signal is output through the timing control circuit.
  • the driving method further includes:
  • timing control circuit After the timing control circuit outputs the start scan signal, it stops receiving the execution control signal.
  • the voltage of the initial scan signal is a reference voltage for deflection of liquid crystal molecules.
  • Another object of the present application is to provide a driving circuit, the driving circuit includes:
  • Scan drive circuit set to output drive voltage signal
  • the timing control circuit is set to output drive control signals
  • the logic processing circuit is respectively connected to the driving circuit and the timing control circuit, and is configured to perform and calculate the driving control signal and the driving voltage signal, and output a corresponding execution control signal;
  • the timing control circuit is further configured to output a start scan signal according to the execution control signal.
  • the logic processing circuit includes an AND gate, and the first input terminal of the AND gate is connected as a first input terminal of the logic processing circuit to the drive control signal output terminal of the timing control circuit,
  • the second input terminal of the AND gate is used as the second input terminal of the logic processing circuit to be connected to the drive voltage signal output terminal of the scan drive circuit, and the output terminal of the AND gate is used as the output terminal of the logic processing circuit .
  • the timing control circuit is a timing control chip, and the logic processing circuit is integrated in the timing control chip.
  • the scan driving circuit is a driving chip, and the logic processing circuit is integrated in the driving chip.
  • the start scan signal is output through the timing control circuit.
  • the timing control circuit after the timing control circuit outputs the start scan signal, it stops receiving the execution control signal.
  • Yet another object of this application is to provide a display device, including:
  • control circuit includes a drive circuit
  • the driving circuit includes:
  • Scan drive circuit set to output drive voltage signal
  • the timing control circuit is set to output drive control signals
  • the logic processing circuit is respectively connected to the driving circuit and the timing control circuit, and is configured to perform and calculate the driving control signal and the driving voltage signal, and output a corresponding execution control signal;
  • the timing control circuit is further configured to output a start scan signal according to the execution control signal.
  • An embodiment of the present application provides a driving amplifier, a driving circuit, and a display device, by receiving a driving control signal output from a timing control circuit and a driving voltage signal output from the driving circuit, and performing the driving control signal and the driving voltage signal And calculation to output the corresponding execution control signal, and then the timing control circuit outputs the starting scan signal according to the execution control signal, so that the scan signal can be effectively output, and the drive circuit is initialized after the thin film transistor liquid crystal display is powered on When the scan line is turned on, the voltage difference across the corresponding liquid crystal is eliminated, thereby eliminating the purpose of the flashing phenomenon.
  • FIG. 1 is a schematic flowchart of a driving method provided by an embodiment of the present application
  • TP drive control signal
  • Sout drive voltage signal
  • OP execution control signal
  • FIG. 3 is a schematic flowchart of a driving method provided by another embodiment of this application.
  • FIG. 4 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • FIG. 8 is a structural block diagram of a display device provided by an embodiment of the present application.
  • FIG. 1 is a schematic flowchart of a driving method provided by an embodiment of the present application.
  • the driving method in this embodiment includes:
  • Step S10 Receive the drive control signal output by the timing control circuit and the drive voltage signal output by the drive circuit;
  • Step S20 Perform calculation and calculation on the drive control signal and the drive voltage signal, and output a corresponding execution control signal;
  • Step S30 The timing control circuit receives the execution control signal, and outputs a start scan signal according to the execution control signal.
  • the timing control circuit is a timing control chip (T-CON), and the driving circuit is a source driving chip, wherein the timing control chip is configured to output a driving control signal to the source driving chip and output a start scan signal.
  • T-CON timing control chip
  • the driving circuit is a source driving chip, wherein the timing control chip is configured to output a driving control signal to the source driving chip and output a start scan signal.
  • the timing control chip is further configured to output a start scan signal to the driver IC (Gate).
  • the reference voltage (Vcom) When the thin film transistor liquid crystal display is powered on, the reference voltage (Vcom) will reach the set reference voltage in a very short time, and the drive circuit output voltage (Sout) due to reset is still in voltage overflow
  • the execution control The signal is output to the timing control circuit, which is set to control the timing control circuit to output a starting scan signal, which is set to control the driving chip to output a scanning signal set to turn on the pixel unit in the display panel.
  • the calculating the drive control signal and the drive voltage signal and outputting the corresponding execution control signal includes:
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a high-level signal.
  • FIG. 2 is a waveform diagram of a driving control signal (TP), a driving voltage signal (Sout), and an execution control signal (OP) provided by an embodiment of the present application.
  • TP driving control signal
  • Sout driving voltage signal
  • OP execution control signal
  • the timing control circuit outputs the start scan signal after receiving the execution control signal, and the display panel start working.
  • the timing control circuit receives the execution control signal and outputs a start scan signal according to the execution control signal, including:
  • the start scan signal is output through the timing control circuit.
  • the timing control circuit if the execution control signal is low, the timing control circuit does not output the start scan signal.
  • FIG. 3 is a schematic flowchart of a driving method according to another embodiment of this application.
  • the driving method in this embodiment further includes:
  • Step S40 After the timing control circuit outputs the start scan signal, stop receiving the execution control signal.
  • the timing control circuit After the timing control circuit outputs the start scan signal, the display panel is turned on. Therefore, the timing control circuit stops receiving the execution control signal and is no longer affected by the execution control signal. Only after the display panel is turned on next time, the timing The control circuit outputs the drive control signal again.
  • the voltage of the initial scan signal is a reference voltage for deflection of liquid crystal molecules.
  • the driving circuit in this embodiment includes:
  • the scanning driving circuit 10 is set to output a driving voltage signal
  • the timing control circuit 30 is configured to output drive control signals
  • the logic processing circuit 20 is respectively connected to the scan driving circuit 10 and the timing control circuit 30, and is configured to perform and calculate the driving control signal and the driving voltage signal, and output the corresponding execution control signal;
  • the timing control circuit 30 is further configured to output a start scan signal according to the execution control signal.
  • the timing control circuit 30 is a timing control chip (T-CON), and the scan driving circuit 10 is a source driving chip, wherein the timing control chip is configured to output a driving control signal to the source driving chip and to drive The chip (Gate IC) outputs the start scan signal.
  • T-CON timing control chip
  • the scan driving circuit 10 is a source driving chip, wherein the timing control chip is configured to output a driving control signal to the source driving chip and to drive The chip (Gate IC) outputs the start scan signal.
  • the drive control signal (TP) output from the timing control circuit 30 and the drive voltage signal (Sout) output from the scan drive circuit 10 are calculated, and the corresponding execution control signal (OP ), the execution control signal is output to the timing control circuit, which is set to control the timing control circuit to output a starting scan signal, which is set to control the driving chip to output a scanning signal set to turn on the pixel unit in the display panel.
  • the drive control signal (TP) output by the timing control circuit 30 and the drive voltage signal (Sout) output by the scan drive circuit 10 are calculated and include:
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a high-level signal.
  • the timing control circuit outputs the start scan signal after receiving the execution control signal, and the display panel starts to work .
  • the start scan signal is output through the timing control circuit.
  • the timing control circuit if the execution control signal is low, the timing control circuit does not output the start scan signal.
  • the timing control circuit 30 after the timing control circuit 30 outputs the start scan signal, the display panel is turned on. Therefore, the timing control circuit 30 stops receiving the execution control signal and is no longer affected by the execution control signal. Only after the display panel is turned on next time Then, the timing control circuit 30 outputs the drive control signal again.
  • the voltage of the initial scan signal is a reference voltage for deflection of liquid crystal molecules.
  • FIG. 5 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • the logic processing circuit 20 includes an AND gate AND.
  • the first input terminal of the AND gate AND is connected as a first input terminal of the logic processing circuit 20 to the drive control signal output terminal of the timing control circuit 30, and the AND gate AND
  • the second input terminal of the logic processing circuit 20 is connected to the drive voltage signal output terminal of the scan driving circuit 10 as the second input terminal, and the output terminal of the AND gate AND is used as the output terminal of the logic processing circuit 20.
  • the timing control circuit 30 is further configured to stop receiving the execution control signal after the start scan signal is output.
  • the timing control circuit 30 is a timing control chip, and the logic processing circuit 20 is integrated in the timing control chip.
  • the scan driving circuit 10 is a driving chip, and the logic processing circuit 20 is integrated in the driving chip.
  • FIG. 6 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application. As shown in FIG. 6, the driving circuit in this embodiment includes:
  • the scan drive circuit 10 is configured to output a drive voltage signal
  • the timing control circuit 30 is set to output a driving control signal
  • the scan drive circuit 10 further includes an AND gate processing circuit 101, which is configured to perform AND calculation of the drive control signal and the drive voltage signal, and output a corresponding execution control signal;
  • the timing control circuit 30 is further configured to output a start scan signal according to the execution control signal.
  • the AND gate processing circuit 101 includes an AND gate AND, and the first input terminal of the AND gate AND is connected as the first input terminal of the AND gate processing circuit 101 to the drive control signal output terminal of the timing control circuit 30, and The second input terminal of the gate AND is connected as the second input terminal of the AND gate processing circuit 101 to the drive voltage signal output terminal of the scan drive circuit 10, and the output terminal of the AND gate AND is used as the output terminal of the AND gate processing circuit 101.
  • the driving circuit in this embodiment includes:
  • the scan drive circuit 10 is configured to output a drive voltage signal
  • the timing control circuit 30 is set to output a driving control signal
  • the timing control circuit 30 further includes an AND gate processing circuit 101, and the AND gate processing circuit 101 is configured to AND the drive control signal and the drive voltage signal, and output the corresponding execution control signal;
  • the timing control circuit 30 is further configured to output a start scan signal according to the execution control signal.
  • the AND gate processing circuit 101 includes an AND gate AND, and the first input terminal of the AND gate AND is connected as the first input terminal of the AND gate processing circuit 101 to the drive control signal output terminal of the timing control circuit 30, and The second input terminal of the gate AND is connected as the second input terminal of the AND gate processing circuit 101 to the drive voltage signal output terminal of the scan drive circuit 10, and the output terminal of the AND gate AND is used as the output terminal of the AND gate processing circuit 101.
  • the display device 60 in this embodiment includes:
  • control circuit 61 wherein the control circuit 61 includes a driving circuit 610;
  • the driving circuit 610 includes:
  • the scanning driving circuit 10 is set to output a driving voltage signal
  • the timing control circuit 30 is configured to output drive control signals
  • the logic processing circuit 20 is respectively connected to the scan driving circuit 10 and the timing control circuit 30, and is configured to perform and calculate the driving control signal and the driving voltage signal, and output the corresponding execution control signal;
  • the timing control circuit 30 is further configured to output a start scan signal according to the execution control signal.
  • the timing control circuit 30 is a timing control chip (T-CON), and the scan driving circuit 10 is a source driving chip, wherein the timing control chip is configured to output a driving control signal to the source driving chip and to drive The chip (Gate IC) outputs the start scan signal.
  • T-CON timing control chip
  • the scan driving circuit 10 is a source driving chip, wherein the timing control chip is configured to output a driving control signal to the source driving chip and to drive The chip (Gate IC) outputs the start scan signal.
  • the drive control signal (TP) output from the timing control circuit 30 and the drive voltage signal (Sout) output from the scan drive circuit 10 are calculated, and the corresponding execution control signal (OP ), the execution control signal is output to the timing control circuit, which is set to control the timing control circuit to output a starting scan signal, which is set to control the driving chip to output a scanning signal set to turn on the pixel unit in the display panel.
  • the drive control signal (TP) output by the timing control circuit 30 and the drive voltage signal (Sout) output by the scan drive circuit 10 are calculated and include:
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a low-level signal
  • the execution control signal is set to a high-level signal.
  • the timing control circuit outputs the start scan signal after receiving the execution control signal, and the display panel starts to work .
  • the start scan signal is output through the timing control circuit.
  • the timing control circuit if the execution control signal is low, the timing control circuit does not output the start scan signal.
  • the timing control circuit 30 after the timing control circuit 30 outputs the start scan signal, the display panel is turned on. Therefore, the timing control circuit 30 stops receiving the execution control signal and is no longer affected by the execution control signal. Only after the display panel is turned on next time Then, the timing control circuit 30 outputs the drive control signal again.
  • the voltage of the initial scan signal is a reference voltage for deflection of liquid crystal molecules.
  • FIG. 5 is a schematic structural diagram of a driving circuit provided by another embodiment of the present application.
  • the logic processing circuit 20 includes an AND gate AND.
  • the first input terminal of the AND gate AND is connected as a first input terminal of the logic processing circuit 20 to the drive control signal output terminal of the timing control circuit 30, and the AND gate AND
  • the second input terminal of the logic processing circuit 20 is connected to the drive voltage signal output terminal of the scan driving circuit 10 as the second input terminal, and the output terminal of the AND gate AND is used as the output terminal of the logic processing circuit 20.
  • the timing control circuit 30 is further configured to stop receiving the execution control signal after the start scan signal is output.
  • the timing control circuit 30 is a timing control chip, and the logic processing circuit 20 is integrated in the timing control chip.
  • the scan driving circuit 10 is a driving chip, and the logic processing circuit 20 is integrated in the driving chip.
  • the driving circuit 610 includes:
  • the scan drive circuit 10 is configured to output a drive voltage signal
  • the timing control circuit 30 is set to output a driving control signal
  • the scan drive circuit 10 further includes an AND gate processing circuit 101, which is configured to perform AND calculation of the drive control signal and the drive voltage signal, and output a corresponding execution control signal;
  • the timing control circuit 30 is further configured to output a start scan signal according to the execution control signal.
  • the AND gate processing circuit 101 includes an AND gate AND, and the first input terminal of the AND gate AND is connected as the first input terminal of the AND gate processing circuit 101 to the drive control signal output terminal of the timing control circuit 30, and The second input terminal of the gate AND is connected as the second input terminal of the AND gate processing circuit 101 to the drive voltage signal output terminal of the scan drive circuit 10, and the output terminal of the AND gate AND is used as the output terminal of the AND gate processing circuit 101.
  • the driving circuit 610 may further include:
  • the scan drive circuit 10 is configured to output a drive voltage signal
  • the timing control circuit 30 is set to output a driving control signal
  • the timing control circuit 30 further includes an AND gate processing circuit 101, which is configured to AND the drive control signal and the drive voltage signal, and output a corresponding execution control signal;
  • the timing control circuit 30 is further configured to output a start scan signal according to the execution control signal.
  • the AND gate processing circuit 101 includes an AND gate AND.
  • the first input terminal of the AND gate AND is connected as the first input terminal of the AND gate processing circuit 101 to the drive control signal output terminal of the timing control circuit 30, and
  • the second input terminal of the gate AND is connected as the second input terminal of the AND gate processing circuit 101 to the drive voltage signal output terminal of the scan drive circuit 10, and the output terminal of the AND gate AND is used as the output terminal of the AND gate processing circuit 101.
  • the display device 60 may be any type of display device provided with the drive circuit 610, such as a liquid crystal display device (Liquid Crystal Display, LCD), an organic electro-laser display (Organic Electroluminesence Display, OLED) display device, Quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display device or curved display device, etc.
  • a liquid crystal display device Liquid Crystal Display, LCD
  • OLED Organic Electroluminesence Display
  • QLED Quantum dot light emitting diode
  • QLED Quantum Dot Light Emitting Diodes
  • the display panel 62 includes a pixel array composed of multiple rows of pixels and multiple columns of pixels.
  • control circuit 61 may be implemented by a general-purpose integrated circuit, such as a central processing unit (Central Processing Unit, CPU), or an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC).
  • CPU Central Processing Unit
  • ASIC Application Specific Integrated Circuit
  • An embodiment of the present application provides a driving amplifier, a driving circuit, and a display device, by receiving a driving control signal output from a timing control circuit and a driving voltage signal output from the driving circuit, and performing the driving control signal and the driving voltage signal And calculation to output the corresponding execution control signal, and then the timing control circuit outputs the starting scan signal according to the execution control signal, so that the scan signal can be effectively output, and the drive circuit is initialized after the thin film transistor liquid crystal display is powered on When the scan line is turned on, the voltage difference across the corresponding liquid crystal is eliminated, thereby eliminating the purpose of the flashing phenomenon.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Multimedia (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种驱动方法、驱动电路及显示装置（60），通过接收时序控制电路（30）输出的驱动控制信号（TP）和驱动电路输出的驱动电压信号（Sout），并将驱动控制信号（TP）和驱动电压信号（Sout）进行与计算，以输出对应的执行控制信号（OP），然后时序控制电路（30）根据执行控制信号（OP）输出起始扫描信号。

Description

一种驱动方法、驱动电路及显示装置
本申请要求于2018年12月03日提交中国专利局，申请号为201811466272.5，发明名称为“一种驱动方法、驱动电路以及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请设计显示技术领域，尤其涉及一种驱动方法、驱动电路以及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。在薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)中，系统主板将R/G/B压缩信号、控制信号及电源信号通过线材与印刷电路板(Printed Circuit Board，PCB)上的连接器相连接，然后视频数据经过印刷电路板上的时序控制电路(Timing Controller，TCON)芯片处理后，经过印刷电路板，通过源级薄膜驱动芯片(Source-Chip on Film，S-COF)和栅极薄膜驱动芯片(Gate-Chip on Film，G-COF)与面板的显示区连接，从而使得液晶显示器获得所需的电源信号。
然而，由于驱动电路在薄膜晶体管液晶显示器在上电后需要进行初始化，会使得在扫描线被打开时，对应的液晶两端的电压出现电压差，从而出现闪现异常。
申请内容
本申请的一个目的在于提供一种驱动方法，包括但不限于实现在扫描线被打开时，消除对应的液晶两端出现的电压差，从而消除发生的闪现异常的现象。
本申请的一个目的在于提供一种驱动方法，包括：
接收时序控制电路输出的驱动控制信号和驱动电路输出的驱动电压信号；
将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号；
所述时序控制电路接收所述执行控制信号，并根据所述执行控制信号输出起始扫描信号。
在一个实施例中，所述将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号，包括：
若所述驱动控制信号为低电平信号，所述驱动电压信号为高电平信号，则将所述执行 控制信号设置为低电平信号；
若所述驱动控制信号为高电平信号，所述驱动电压信号为低电平信号，则将所述执行控制信号设置为低电平信号；
若所述驱动控制信号为高电平信号，所述驱动电压信号为高电平信号，则将所述执行控制信号设置为高电平信号。
在一个实施例中，所述驱动电路为源极驱动芯片。
在一个实施例中，所述时序控制电路为时序控制芯片，所述时序控制芯片设置为向所述源极驱动芯片输出起始扫描信号。
在一个实施例中，所述时序控制电路接收所述执行控制信号，并根据所述执行控制信号输出起始扫描信号，包括：
若所述执行控制信号为高电平信号，则通过所述时序控制电路输出所述起始扫描信号。
在一个实施例中，所述驱动方法还包括：
在所述时序控制电路输出所述起始扫描信号后，停止接收所述执行控制信号。
在一个实施例中，所述起始扫描信号的电压为液晶分子偏转的基准电压。
本申请的另一目的在于提供一种驱动电路，所述驱动电路包括：
扫描驱动电路，设置为输出驱动电压信号；
时序控制电路，设置为输出驱动控制信号；以及
逻辑处理电路，分别与所述驱动电路和所述时序控制电路连接，设置为将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号；
所述时序控制电路，还设置为根据所述执行控制信号输出起始扫描信号。
在一个实施例中，所述逻辑处理电路，包括与门，所述与门的第一输入端作为所述逻辑处理电路的第一输入端与所述时序控制电路的驱动控制信号输出端连接，所述与门的第二输入端作为所述逻辑处理电路的第二输入端与所述扫描驱动电路的驱动电压信号输出端连接，所述与门的输出端作为所述逻辑处理电路的输出端。
在一个实施例中，所述时序控制电路为时序控制芯片，所述逻辑处理电路集成于所述时序控制芯片内。
在一个实施例中，所述扫描驱动电路为驱动芯片，所述逻辑处理电路集成于所述驱动芯片内。
在一个实施例中，所述执行控制信号为高电平信号时，则通过所述时序控制电路输出所述起始扫描信号。
在一个实施例中，所述时序控制电路输出所述起始扫描信号后，停止接收所述执行控 制信号。
本申请的再一目的在于提供一种显示装置，包括：
显示面板；以及
控制电路，所述控制电路包括驱动电路；
所述驱动电路包括：
扫描驱动电路，设置为输出驱动电压信号；
时序控制电路，设置为输出驱动控制信号；以及
逻辑处理电路，分别与所述驱动电路和所述时序控制电路连接，设置为将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号；
所述时序控制电路，还设置为根据所述执行控制信号输出起始扫描信号。
本申请实施例提供了一种驱动放大、驱动电路及显示装置，通过接收时序控制电路输出的驱动控制信号和驱动电路输出的驱动电压信号，并将所述驱动控制信号和所述驱动电压信号进行与计算，以输出对应的执行控制信号，然后时序控制电路根据该执行控制信号输出起始扫描信号，以使得扫描信号可以进行有效输出，实现了驱动电路在薄膜晶体管液晶显示器在上电后进行初始化，扫描线被打开时，消除对应的液晶两端的电压出现电压差，从而消除闪现现象的目的。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请的一个实施例提供的驱动方法的流程示意图；
图2为本申请的一个实施例提供的驱动控制信号(TP)、驱动电压信号(Sout)以及执行控制信号(OP)的波形示意图；
图3为本申请的另一个实施例提供的驱动方法的流程示意图；
图4为本申请的一个实施例提供的驱动电路的结构示意图；
图5为本申请的另一个实施例提供的驱动电路的结构示意图；
图6为本申请的另一个实施例提供的驱动电路的结构示意图；
图7为本申请的另一个实施例提供的驱动电路的结构示意图
图8是本申请的一个实施例提供的显示装置的结构框图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不设置为限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅设置为便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
图1为本申请的一个实施例提供的驱动方法的流程示意图。
如图1所示，本实施例中的驱动方法，包括：
步骤S10：接收时序控制电路输出的驱动控制信号和驱动电路输出的驱动电压信号；
步骤S20：将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号；
步骤S30：所述时序控制电路接收所述执行控制信号，并根据所述执行控制信号输出起始扫描信号。
在一个实施例中，时序控制电路为时序控制芯片(T-CON IC)，驱动电路为源极驱动芯片，其中，时序控制芯片设置为向源极驱动芯片输出驱动控制信号输出起始扫描信号。
在一个实施例中，时序控制芯片还设置为向驱动芯片(Gate IC)输出起始扫描信号。
在薄膜晶体管液晶显示器在上电时，参考电压(Vcom)会在很短的时间内达到设定的基准电压，而驱动电路此时由于复位导致其输出的驱动电压信号(Sout)还处于电压溢出状态，在本实施例中，通过将时序控制电路输出的驱动控制信号(TP)和驱动电路输出的驱动电压信号(Sout)进行与计算，并输出对应的执行控制信号(OP)，该执行控制信号输出至时序控制电路，设置为控制时序控制电路输出起始扫描信号，该起始扫描信号设置为控制驱动芯片输出设置为打开显示面板中的像素单元的扫描信号。
在一个实施例中，所述将所述驱动控制信号和所述驱动电压信号进行与计算，并输出 对应的执行控制信号，包括：
若所述驱动控制信号为低电平信号，所述驱动电压信号为高电平信号，则将所述执行控制信号设置为低电平信号；
若所述驱动控制信号为高电平信号，所述驱动电压信号为低电平信号，则将所述执行控制信号设置为低电平信号；
若所述驱动控制信号为高电平信号，所述驱动电压信号为高电平信号，则将所述执行控制信号设置为高电平信号。
图2为本申请的一个实施例提供的驱动控制信号(TP)、驱动电压信号(Sout)以及执行控制信号(OP)的波形示意图。
如图2所示，当驱动控制信号和驱动电压信号均为高电平信号时，执行控制信号为高电平，此时，时序控制电路接收到执行控制信号后输出起始扫描信号，显示面板开始工作。
在一个实施例中，所述时序控制电路接收所述执行控制信号，并根据所述执行控制信号输出起始扫描信号，包括：
若所述执行控制信号为高电平信号，则通过所述时序控制电路输出所述起始扫描信号。
在一个实施例中，若执行控制信号为低电平时，时序控制电路则不输出起始扫描信号。
图3为本申请的另一个实施例提供的驱动方法的流程示意图。
参见图3，本实施例中的驱动方法还包括：
步骤S40：在所述时序控制电路输出所述起始扫描信号后，停止接收所述执行控制信号。
在本实施例中，时序控制电路输出起始扫描信号后，显示面板开机完成，因此，时序控制电路停止接收执行控制信号，不再受执行控制信号影响，只有在下次显示面板开机启动后，时序控制电路再次输出驱动控制信号。
在一个实施例中，起始扫描信号的电压为液晶分子偏转的基准电压。
图4为本申请的一个实施例提供的驱动电路的结构示意图。如图4所示，本实施例中的驱动电路包括：
扫描驱动电路10，设置为输出驱动电压信号；
时序控制电路30，设置为输出驱动控制信号；以及
逻辑处理电路20，分别与扫描驱动电路10和时序控制电路30连接，设置为将驱动控制信号和驱动电压信号进行与计算，并输出对应的执行控制信号；
时序控制电路30，还设置为根据执行控制信号输出起始扫描信号。
在一个实施例中，时序控制电路30为时序控制芯片(T-CON IC)，扫描驱动电路10 为源极驱动芯片，其中，时序控制芯片设置为向源极驱动芯片输出驱动控制信号和向驱动芯片(Gate IC)输出起始扫描信号。
在薄膜晶体管液晶显示器在上电时，参考电压(Vcom)会在很短的时间内达到设定的基准电压，而扫描驱动电路10此时由于复位导致其输出的驱动电压信号(Sout)还处于电压溢出状态，在本实施例中，通过将时序控制电路30输出的驱动控制信号(TP)和扫描驱动电路10输出的驱动电压信号(Sout)进行与计算，并输出对应的执行控制信号(OP)，该执行控制信号输出至时序控制电路，设置为控制时序控制电路输出起始扫描信号，该起始扫描信号设置为控制驱动芯片输出设置为打开显示面板中的像素单元的扫描信号。
在一个实施例中，时序控制电路30输出的驱动控制信号(TP)和扫描驱动电路10输出的驱动电压信号(Sout)进行与计算，包括：
若驱动控制信号为低电平信号，驱动电压信号为高电平信号，则将执行控制信号设置为低电平信号；
若驱动控制信号为高电平信号，驱动电压信号为低电平信号，则将执行控制信号设置为低电平信号；
若驱动控制信号为高电平信号，驱动电压信号为高电平信号，则将执行控制信号设置为高电平信号。
参见图2，当驱动控制信号和驱动电压信号均为高电平信号时，执行控制信号为高电平，此时，时序控制电路接收到执行控制信号后输出起始扫描信号，显示面板开始工作。
在一个实施例中，若执行控制信号为高电平信号，则通过时序控制电路输出起始扫描信号。
在一个实施例中，若执行控制信号为低电平时，时序控制电路则不输出起始扫描信号。
在一个实施例中，时序控制电路30输出起始扫描信号后，显示面板开机完成，因此，时序控制电路30停止接收执行控制信号，不再受执行控制信号影响，只有在下次显示面板开机启动后，时序控制电路30再次输出驱动控制信号。
在一个实施例中，起始扫描信号的电压为液晶分子偏转的基准电压。
图5为本申请的另一个实施例提供的驱动电路的结构示意图。如图5所示，逻辑处理电路20，包括与门AND，与门AND的第一输入端作为逻辑处理电路20的第一输入端与时序控制电路30的驱动控制信号输出端连接，与门AND的第二输入端作为逻辑处理电路20的第二输入端与扫描驱动电路10的驱动电压信号输出端连接，与门AND的输出端作为逻辑处理电路20的输出端。
在一个实施例中，时序控制电路30，还设置为在输出起始扫描信号后，停止接收执行 控制信号。
在一个实施例中，所述时序控制电路30为时序控制芯片，所述逻辑处理电路20集成于所述时序控制芯片内。
在一个实施例中，所述扫描驱动电路10为驱动芯片，所述逻辑处理电路20集成于所述驱动芯片内。
图6为本申请的另一个实施例提供的驱动电路的结构示意图。如图6所示，本实施例中的驱动电路包括：
扫描驱动电路10，设置为输出驱动电压信号；以及
时序控制电路30，设置为输出驱动控制信号；
其中，扫描驱动电路10还包括与门处理电路101，设置为将驱动控制信号和驱动电压信号进行与计算，并输出对应的执行控制信号；
时序控制电路30，还设置为根据执行控制信号输出起始扫描信号。
在一个实施例中，与门处理电路101，包括与门AND，与门AND的第一输入端作为与门处理电路101的第一输入端与时序控制电路30的驱动控制信号输出端连接，与门AND的第二输入端作为与门处理电路101的第二输入端与扫描驱动电路10的驱动电压信号输出端连接，与门AND的输出端作为与门处理电路101的输出端。
图7为本申请的另一个实施例提供的驱动电路的结构示意图。如图7所示，本实施例中的驱动电路包括：
扫描驱动电路10，设置为输出驱动电压信号；以及
时序控制电路30，设置为输出驱动控制信号；
其中，时序控制电路30还包括与门处理电路101，与门处理电路101设置为将驱动控制信号和驱动电压信号进行与计算，并输出对应的执行控制信号；
时序控制电路30，还设置为根据执行控制信号输出起始扫描信号。
在一个实施例中，与门处理电路101，包括与门AND，与门AND的第一输入端作为与门处理电路101的第一输入端与时序控制电路30的驱动控制信号输出端连接，与门AND的第二输入端作为与门处理电路101的第二输入端与扫描驱动电路10的驱动电压信号输出端连接，与门AND的输出端作为与门处理电路101的输出端。
图8为本申请的一个实施例提供的显示装置的结构示意图。如图8所示，本实施例中的显示装置60，包括：
显示面板60；以及
控制电路61，其中，控制电路61包括驱动电路610；
其中，驱动电路610包括：
扫描驱动电路10，设置为输出驱动电压信号；
时序控制电路30，设置为输出驱动控制信号；以及
逻辑处理电路20，分别与扫描驱动电路10和时序控制电路30连接，设置为将驱动控制信号和驱动电压信号进行与计算，并输出对应的执行控制信号；
时序控制电路30，还设置为根据执行控制信号输出起始扫描信号。
在一个实施例中，时序控制电路30为时序控制芯片(T-CON IC)，扫描驱动电路10为源极驱动芯片，其中，时序控制芯片设置为向源极驱动芯片输出驱动控制信号和向驱动芯片(Gate IC)输出起始扫描信号。
在薄膜晶体管液晶显示器在上电时，参考电压(Vcom)会在很短的时间内达到设定的基准电压，而扫描驱动电路10此时由于复位导致其输出的驱动电压信号(Sout)还处于电压溢出状态，在本实施例中，通过将时序控制电路30输出的驱动控制信号(TP)和扫描驱动电路10输出的驱动电压信号(Sout)进行与计算，并输出对应的执行控制信号(OP)，该执行控制信号输出至时序控制电路，设置为控制时序控制电路输出起始扫描信号，该起始扫描信号设置为控制驱动芯片输出设置为打开显示面板中的像素单元的扫描信号。
在一个实施例中，时序控制电路30输出的驱动控制信号(TP)和扫描驱动电路10输出的驱动电压信号(Sout)进行与计算，包括：
若驱动控制信号为低电平信号，驱动电压信号为高电平信号，则将执行控制信号设置为低电平信号；
若驱动控制信号为高电平信号，驱动电压信号为低电平信号，则将执行控制信号设置为低电平信号；
若驱动控制信号为高电平信号，驱动电压信号为高电平信号，则将执行控制信号设置为高电平信号。
参见图2，当驱动控制信号和驱动电压信号均为高电平信号时，执行控制信号为高电平，此时，时序控制电路接收到执行控制信号后输出起始扫描信号，显示面板开始工作。
在一个实施例中，若执行控制信号为高电平信号，则通过时序控制电路输出起始扫描信号。
在一个实施例中，若执行控制信号为低电平时，时序控制电路则不输出起始扫描信号。
在一个实施例中，时序控制电路30输出起始扫描信号后，显示面板开机完成，因此，时序控制电路30停止接收执行控制信号，不再受执行控制信号影响，只有在下次显示面板开机启动后，时序控制电路30再次输出驱动控制信号。
在一个实施例中，起始扫描信号的电压为液晶分子偏转的基准电压。
图5为本申请的另一个实施例提供的驱动电路的结构示意图。如图5所示，逻辑处理电路20，包括与门AND，与门AND的第一输入端作为逻辑处理电路20的第一输入端与时序控制电路30的驱动控制信号输出端连接，与门AND的第二输入端作为逻辑处理电路20的第二输入端与扫描驱动电路10的驱动电压信号输出端连接，与门AND的输出端作为逻辑处理电路20的输出端。
在一个实施例中，时序控制电路30，还设置为在输出起始扫描信号后，停止接收执行控制信号。
在一个实施例中，所述时序控制电路30为时序控制芯片，所述逻辑处理电路20集成于所述时序控制芯片内。
在一个实施例中，所述扫描驱动电路10为驱动芯片，所述逻辑处理电路20集成于所述驱动芯片内。
在一个实施例中，如图6所示，驱动电路610包括：
扫描驱动电路10，设置为输出驱动电压信号；以及
时序控制电路30，设置为输出驱动控制信号；
其中，扫描驱动电路10还包括与门处理电路101，设置为将驱动控制信号和驱动电压信号进行与计算，并输出对应的执行控制信号；
时序控制电路30，还设置为根据执行控制信号输出起始扫描信号。
在一个实施例中，与门处理电路101，包括与门AND，与门AND的第一输入端作为与门处理电路101的第一输入端与时序控制电路30的驱动控制信号输出端连接，与门AND的第二输入端作为与门处理电路101的第二输入端与扫描驱动电路10的驱动电压信号输出端连接，与门AND的输出端作为与门处理电路101的输出端。
如图7所示，在一个实施例中，驱动电路610还可以包括：
扫描驱动电路10，设置为输出驱动电压信号；以及
时序控制电路30，设置为输出驱动控制信号；
其中，时序控制电路30还包括与门处理电路101，设置为将驱动控制信号和驱动电压信号进行与计算，并输出对应的执行控制信号；
时序控制电路30，还设置为根据执行控制信号输出起始扫描信号。
在一个实施例中，与门处理电路101，包括与门AND，与门AND的第一输入端作为与门处理电路101的第一输入端与时序控制电路30的驱动控制信号输出端连接，与门AND的第二输入端作为与门处理电路101的第二输入端与扫描驱动电路10的驱动电压信号输出 端连接，与门AND的输出端作为与门处理电路101的输出端。
在一个实施例中，显示装置60可以为设置有上述驱动电路610的任意类型的显示装置，例如液晶显示装置(Liquid Crystal Display，LCD)、有机电激光显示(Organic Electroluminesence Display，OLED)显示装置、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示装置或曲面显示装置等。
在一个实施例中，显示面板62包括由多行像素和多列像素组成的像素阵列。
在一个实施例中，控制电路61，可以通过通用集成电路，例如中央处理器(Central Processing Unit，CPU)，或通过专用集成电路(Application Specific Integrated Circuit，ASIC)来实现。
本申请实施例提供了一种驱动放大、驱动电路及显示装置，通过接收时序控制电路输出的驱动控制信号和驱动电路输出的驱动电压信号，并将所述驱动控制信号和所述驱动电压信号进行与计算，以输出对应的执行控制信号，然后时序控制电路根据该执行控制信号输出起始扫描信号，以使得扫描信号可以进行有效输出，实现了驱动电路在薄膜晶体管液晶显示器在上电后进行初始化，扫描线被打开时，消除对应的液晶两端的电压出现电压差，从而消除闪现现象的目的。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所述仅为本申请的可选实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种驱动方法，包括：
    接收时序控制电路输出的驱动控制信号和驱动电路输出的驱动电压信号；
    将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号；
    所述时序控制电路接收所述执行控制信号，并根据所述执行控制信号输出起始扫描信号。
  2. 如权利要求1所述的驱动方法，其中，所述将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号，包括：
    若所述驱动控制信号为低电平信号，所述驱动电压信号为高电平信号，则将所述执行控制信号设置为低电平信号；
    若所述驱动控制信号为高电平信号，所述驱动电压信号为低电平信号，则将所述执行控制信号设置为低电平信号；
    若所述驱动控制信号为高电平信号，所述驱动电压信号为高电平信号，则将所述执行控制信号设置为高电平信号。
  3. 如权利要求1所述的驱动方法，其中，所述驱动电路为源极驱动芯片。
  4. 如权利要求3所述的驱动方法，其中，所述时序控制电路为时序控制芯片，所述时序控制芯片设置为向所述源极驱动芯片输出起始扫描信号。
  5. 如权利要求1所述的驱动方法，其中，所述时序控制电路接收所述执行控制信号，并根据所述执行控制信号输出起始扫描信号，包括：
    若所述执行控制信号为高电平信号，则通过所述时序控制电路输出所述起始扫描信号。
  6. 如权利要求1所述的驱动方法，其中，所述驱动方法还包括：
    在所述时序控制电路输出所述起始扫描信号后，停止接收所述执行控制信号。
  7. 如权利要求1所述的驱动方法，其中，所述起始扫描信号的电压为液晶分子偏转的基准电压。
  8. 一种驱动电路，所述驱动电路包括：
    扫描驱动电路，设置为输出驱动电压信号；
    时序控制电路，设置为输出驱动控制信号；以及
    逻辑处理电路，分别与所述驱动电路和所述时序控制电路连接，设置为将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号；
    所述时序控制电路，还设置为根据所述执行控制信号输出起始扫描信号。
  9. 如权利要求8所述的驱动电路，其中，所述逻辑处理电路，包括与门，所述与门的第一输入端作为所述逻辑处理电路的第一输入端与所述时序控制电路的驱动控制信号输出端连接，所述与门的第二输入端作为所述逻辑处理电路的第二输入端与所述扫描驱动电路的驱动电压信号输出端连接，所述与门的输出端作为所述逻辑处理电路的输出端。
  10. 如权利要求8所述的驱动电路，其中，所述时序控制电路为时序控制芯片，所述逻辑处理电路集成于所述时序控制芯片内。
  11. 如权利要求8所述的驱动电路，其中，所述扫描驱动电路为驱动芯片，所述逻辑处理电路集成于所述驱动芯片内。
  12. 如权利要求8所述的驱动电路，其中，所述执行控制信号为高电平信号时，则通过所述时序控制电路输出所述起始扫描信号。
  13. 如权利要求8所述的驱动电路，其中，所述时序控制电路输出所述起始扫描信号后，停止接收所述执行控制信号。
  14. 一种显示装置，包括：
    显示面板；以及
    控制电路，所述控制电路包括驱动电路；
    所述驱动电路包括：
    扫描驱动电路，设置为输出驱动电压信号；
    时序控制电路，设置为输出驱动控制信号；以及
    逻辑处理电路，分别与所述驱动电路和所述时序控制电路连接，设置为将所述驱动控制信号和所述驱动电压信号进行与计算，并输出对应的执行控制信号；
    所述时序控制电路，还设置为根据所述执行控制信号输出起始扫描信号。
  15. 如权利要求14所述的显示装置，其中，所述逻辑处理电路，包括与门，所述与门的第一输入端作为所述逻辑处理电路的第一输入端与所述时序控制电路的驱动控制信号输出端连接，所述与门的第二输入端作为所述逻辑处理电路的第二输入端与所述扫描驱动电路的驱动电压信号输出端连接，所述与门的输出端作为所述逻辑处理电路的输出端。
  16. 如权利要求14所述的显示装置，其中，所述时序控制电路为时序控制芯片，所述逻辑处理电路集成于所述时序控制芯片内。
  17. 如权利要求14所述的显示装置，其中，所述扫描驱动电路为驱动芯片，所述逻辑处理电路集成于所述驱动芯片内。
  18. 如权利要求14所述的显示装置，其中，所述执行控制信号为高电平信号时，则通过所述时序控制电路输出所述起始扫描信号。
  19. 如权利要求14所述的显示装置，其中，所述时序控制电路输出所述起始扫描信号后，停止接收所述执行控制信号。
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