WO2020098514A1 - 横向扩散金属氧化物半导体器件及其制造方法 - Google Patents

横向扩散金属氧化物半导体器件及其制造方法 Download PDF

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WO2020098514A1
WO2020098514A1 PCT/CN2019/115011 CN2019115011W WO2020098514A1 WO 2020098514 A1 WO2020098514 A1 WO 2020098514A1 CN 2019115011 W CN2019115011 W CN 2019115011W WO 2020098514 A1 WO2020098514 A1 WO 2020098514A1
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field oxygen
layer
field
contact hole
oxygen contact
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French (fr)
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汪广羊
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a laterally diffused metal oxide semiconductor device, and also relates to a method of manufacturing a laterally diffused metal oxide semiconductor device.
  • the on-resistance (Rdson) is one of the parameters we are most concerned about.
  • LDMOS laterally diffused metal oxide semiconductor
  • LDMOS laterally diffused metal oxide semiconductor
  • a polysilicon field that is, a polysilicon field plate is provided on the field oxide layer to enhance the depletion of the drift region.
  • the thinner the field oxygen layer the stronger the effect of the polysilicon field plate to enhance the depletion of the drift region, and the BV can be improved on the basis that Rdson is basically unchanged.
  • the thickness of the field oxygen layer cannot be infinitely small, because the electric field strength between the drain region and the gate will limit the BV, which will cause the dielectric between the drain region and the gate to break down.
  • a laterally diffused metal oxide semiconductor device including: a substrate; a drift region provided in the substrate; a gate structure provided on the substrate, including a gate dielectric layer and a gate dielectric layer The gate layer on the top; the drain region, provided in the substrate on one side of the gate structure, in contact with the drift region; the source region, provided on the substrate on the other side of the gate structure Medium; a field oxygen layer, which is provided on the surface of the drift region; and a polysilicon field plate, which is provided on the field oxygen layer; the laterally diffused metal oxide semiconductor device is also provided with a field penetrating into the field oxygen layer Oxygen contact holes, field oxygen contact holes are filled with conductive material.
  • a method for manufacturing a laterally diffused metal oxide semiconductor device includes: obtaining a substrate, a drift region is formed in the substrate, a field oxygen layer is formed on the surface of the drift region; and a gate dielectric is formed on the substrate An electric layer; forming a polysilicon layer on the gate dielectric layer and the field oxygen layer; performing photolithography and etching on the polysilicon layer to form a gate layer on the gate dielectric layer and a polysilicon on the field oxygen layer A field plate; forming a dielectric layer on the gate layer and the polysilicon field plate; and using contact hole photolithography and etching to form a field oxygen contact hole penetrating the dielectric layer into the field oxygen layer, so
  • the contact hole lithography plate includes a field oxygen contact hole pattern corresponding to the field oxygen contact hole.
  • FIG. 1 is a schematic structural view of a laterally diffused metal oxide semiconductor device in an embodiment
  • FIG. 2 is a schematic diagram of the structure shown in FIG. 1 with a field oxygen contact hole in a plan view added;
  • FIG. 3 is a flowchart of a method for manufacturing a laterally diffused metal oxide semiconductor device in an embodiment.
  • first element, component, region, layer, or section discussed below can be represented as a second element, component, region, layer, or section.
  • Spatial relationship terms such as “below”, “below”, “below”, “below”, “above”, “above”, etc. It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then elements or features described as “below” or “beneath” or “below” will be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. In this way, a change from the shown shape due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted area shown as a rectangle generally has round or curved features and / or implant concentration gradients at its edges, rather than a binary change from the implanted area to the non-implanted area. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is proceeding. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.
  • the vocabulary in the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art.
  • the P + type represents the P type with heavy doping concentration
  • the P type represents medium P-type doping concentration
  • P-type represents P-type with light doping concentration
  • N + type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents light-doping concentration N type.
  • FIG. 1 is a schematic structural view of a laterally diffused metal oxide semiconductor device in an embodiment
  • FIG. 2 is a schematic view of the structure shown in FIG. 1 with a field oxygen contact hole in a plan view added.
  • the laterally diffused metal oxide semiconductor device includes a substrate 10, a drift region 20, a gate structure, a drain region 32, a source region 34, a field oxygen layer 40, a polysilicon field plate 44 and a field oxygen contact hole.
  • the drift region 20 is provided in the substrate 10.
  • the gate structure is provided on the substrate 10 and includes a gate dielectric layer (not shown in FIGS. 1 and 2) and a gate layer 44 on the gate dielectric layer.
  • the drain region 32 is disposed in the substrate 10 on one side of the gate structure and is in contact with the drift region 20; in this embodiment, the drain region 32 is disposed in the drift region 20 (in FIG. 1, it is disposed in the gate In the substrate 10 on the right side of the structure).
  • the source region 34 is provided in the substrate 10 on the other side of the gate structure (in FIG. 1, it is provided in the substrate 10 on the left side of the gate structure).
  • the field oxygen layer 40 is disposed on the surface of the drift region 20.
  • the field oxygen layer 40 is specifically disposed on the surface of the drift region 20 between the drain region 32 and the source region 34.
  • a polysilicon field plate 42 is provided on the field oxygen layer 40.
  • the field oxygen contact hole penetrates into the field oxygen layer 40, and the field oxygen contact hole is filled with a conductive material. In different embodiments, there may be one field oxygen contact hole, or a plurality of contact holes.
  • the above-mentioned laterally diffused metal oxide semiconductor device by providing a field oxygen contact hole, can not only have a stronger drain drift region depletion than the solution where the field oxygen layer 40 does not provide a contact hole, thereby reducing the on-resistance, and affecting the BV Relatively small.
  • the field oxygen contact holes include at least two groups, and each group of field oxygen contact holes includes at least one contact hole.
  • the shallower the depth of the oxygen layer 40, the oxygen contact holes in each field are filled with a conductive material.
  • the pore diameter of the field oxygen contact hole with a shallower penetration into the field oxygen layer is smaller, and the pore diameter of the field oxygen contact hole with a deeper penetration into the field oxygen layer is larger, it can be understood that
  • the size and depth of the field oxygen contact hole are not necessarily related, for example, the field oxygen contact holes may be the same size, or the diameter of the field oxygen contact hole penetrating deep into the field oxygen layer may be smaller.
  • the field oxygen layer 40 near the drain region 32 is appropriately thickened, and the field oxygen layer far from the drain region 32 is appropriately thinned (ie, from the drain (The thickness of the bottom of the contact hole near the pole region 32 to the bottom of the field oxygen layer 40 is thicker, and the thickness of the bottom of the contact hole farther from the drain region 32 to the bottom of the field oxygen layer 40 is thinner), which can both maximize depletion and solve
  • the thickness of the field oxygen layer 40 will limit the problem of BV.
  • the field oxygen contact holes may also be arranged in different ways, and each contact hole may be in a different depth manner from the embodiment shown in FIG. 1, for example, the direction of the gradient of the depth is opposite, or there is no specific rule for the depth.
  • the gate layer 44 is a polysilicon gate, that is, the material of the polysilicon field plate 42 is the same, so that it can be deposited and formed by photolithography and etching in the same process.
  • metal, metal nitride, metal silicide, or similar compounds may be used as the material of the gate layer 44.
  • the substrate 10 is a semiconductor substrate, and its material may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. are stacked on the insulator.
  • the constituent material of the substrate 10 is single crystal silicon.
  • the substrate 10 has the second conductivity type
  • the drift region 20 has the first conductivity type
  • the drain region 32 and the source region 34 have the first conductivity type.
  • the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
  • the drift region 20 has different conductivity types according to the specific type of LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 20 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, the drift region 20 is a P-type drift region. In the embodiment shown in FIG. 1, the drift region 20 is an N-drift region. Generally speaking, the doping concentration of the drift region 20 is lower, which is lower than the doping concentration of the drain region 32 and the source region 34, which is equivalent to forming a region of higher resistance between the source and the drain. Increasing the breakdown voltage and reducing the parasitic capacitance between the source and drain are beneficial to improve the frequency characteristics of the device.
  • the gate dielectric layer may include conventional dielectric materials such as silicon oxide, nitride, and oxynitride with a dielectric constant from about 4 to about 20 (measured in vacuum), or, gate dielectric
  • the dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the drain region 32 and the source region 34 are N-type doped ion heavily doped (N +) drain and source.
  • the laterally diffused metal oxide semiconductor device includes at least one set of first field oxygen contact holes that penetrates through the polysilicon field plate 42 and then continues down into the field oxygen layer 40, and at least one set of uncovered polysilicon field plates The position of 42 penetrates into the second field oxygen contact hole of the field oxygen layer 40 (for example, the second field oxygen contact hole 47 shown in FIG. 1). In other embodiments, only a field oxygen contact hole that penetrates through the polysilicon field plate and then penetrates down into the field oxygen layer may be provided, or only a field oxygen contact hole that penetrates into the field oxygen layer at a position that does not cover the polysilicon field plate is provided .
  • the diameter of any second field oxygen contact hole is smaller than the diameter of any first field oxygen contact hole, and the depth of any second field oxygen contact hole penetrating into the field oxygen layer is shallower than that of any first field The depth of the oxygen contact hole penetrating into the field oxygen layer.
  • the laterally diffused metal oxide semiconductor device further includes a dielectric layer and a metal layer.
  • a dielectric layer (not shown in FIG. 1) is provided on the gate layer, polysilicon field plate, drain region and source region, and a metal layer (not shown in FIG. 1) is provided above the dielectric layer.
  • the metal layer includes a ground connection 52.
  • the conductive material in at least one set of field oxygen contact holes is electrically connected to the ground connection 52 to be grounded.
  • the metal plugs in the field oxygen contact hole 41 and the field oxygen contact hole 43 are connected to the ground wire 52.
  • the metal plug in the field oxygen contact hole is connected with the source terminal, it will increase the gate drain capacitance (Cgd), which has a great influence on the switching characteristics of the device, so the metal plug in the field oxygen contact hole is directly connected to the ground (GND), Not only can maximize depletion, but also effectively reduce capacitance.
  • Cgd gate drain capacitance
  • the conductive material in at least one set of field oxygen contact holes is not electrically connected to the metal layer to float.
  • the metal plug in the field oxygen contact hole 47 floats.
  • ONBV on-state breakdown voltage
  • the floating field oxygen contact hole is a group of field oxygen contact holes closest to the drain region 32.
  • the inventor believes that this arrangement can achieve a better compromise between ONBV and OFFBV. It can be understood that, in other embodiments, the metal plug in the field oxygen contact hole at other positions may also float.
  • the LDMOS device further includes a body region 30.
  • the body region 30 is located on the side of the gate layer 44 away from the drift region 20 and is spaced from the drift region 20.
  • the source region 34 is formed in the body region 30.
  • the body region 30 has the opposite conductivity type as the drift region 20, that is, the body region 30 has the second conductivity type.
  • the body region 30 is a P-shaped body region.
  • the LDMOS device further includes a body lead-out region 36 provided in the body region 30.
  • the body lead-out area 36 has the same conductivity type as the body area 30.
  • the body region 30 is P-type
  • the body extraction region 36 may also be P-type, and its doping concentration is greater than that of the body region.
  • the body extraction region 36 is heavily doped with P-type impurities.
  • the LDMOS device in addition to the field oxygen contact hole, is also provided with a drain contact hole, a source contact hole, a gate contact hole, and a body contact hole.
  • the metal plug in the gate contact hole is electrically connected to the gate layer 44 to lead the gate out.
  • the metal plug in the drain contact hole is electrically connected to the drain region 32 to lead the drain.
  • the metal plug in the source contact hole is electrically connected to the source electrode 34 to lead the source electrode out.
  • the metal plug in the contact hole of the body area electrically connects the body lead-out area 36 to lead the body area out.
  • the conductive material filled in the drain contact hole, the source contact hole, the gate contact hole, the body region contact hole and each group of field oxygen contact holes may be any suitable conductive material known to those skilled in the art, including but not limited to metal Material; wherein, the metal material may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al.
  • each contact hole may be filled with the same conductive material, for example, tungsten metal, etc., or different conductive materials.
  • the present application also provides a method for manufacturing a laterally diffused metal oxide semiconductor device, which can be used to manufacture the laterally diffused metal oxide semiconductor device described in any of the above embodiments.
  • 3 is a flowchart of a method for manufacturing a laterally diffused metal oxide semiconductor device in an embodiment, including the following steps:
  • the substrate is a semiconductor substrate, the material of which may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), insulator S-SiGeOI, silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI) are stacked on top.
  • SOI silicon on insulator
  • SSOI silicon on insulator
  • SiGeOI silicon-germanium-on-insulator
  • GeOI germanium-on-insulator
  • the gate dielectric layer may include conventional dielectric materials such as silicon oxide, nitride, and oxynitride with a dielectric constant from about 4 to about 20 (measured in vacuum), or, gate dielectric
  • the dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the gate dielectric layer may be formed by a process known in the art, such as a thermal oxidation process.
  • the polysilicon layer may be formed by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma chemistry For vapor deposition (PECVD), methods such as sputtering and physical vapor deposition (PVD) can also be used.
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • LTCVD fast thermal chemical vapor deposition
  • PECVD plasma chemistry For vapor deposition
  • PVD physical vapor deposition
  • the thickness of the polysilicon layer can be a suitable thickness according to the size of the device, and is not specifically limited herein.
  • step S330 may be any one of the deposition processes.
  • the body region may also be formed in the substrate before the gate layer and the polysilicon field plate are formed.
  • the body region is located on the side of the gate layer away from the drift region and is spaced from the drift region.
  • the body region has the opposite conductivity type as the drift region.
  • the body region may be formed using, for example, ion implantation, for example, after step S330 and before S340, body region photolithography and etching are performed to remove the gate material at the location where the body region is to be formed, and then to be formed into the substrate by ion implantation P-type doped impurities such as boron are implanted into the body region, and the body region can be formed by thermal diffusion after implantation.
  • the drain region and the source region can also be formed after the gate layer and the polysilicon field plate are formed.
  • the drain region is provided in the substrate on one side of the gate layer, and is in contact with the drift region, in one embodiment it is provided in the drift region.
  • the source region is provided in the substrate on the other side of the gate layer.
  • the drain and source regions have the first conductivity type.
  • the drain region and the source region are N-type, which may also be a source and drain heavily doped with N-type doped ions.
  • a method of forming a source electrode and a drain electrode includes performing source-drain ion implantation on a region of a semiconductor substrate where the source electrode and the drain electrode are to be formed, and forming a drain region in the substrate on both sides of the gate layer And source region.
  • the patterned photoresist layer that exposes the intended formation of the drain region and the source region can be formed by using a photolithography process, and then the patterned photoresist layer is used as a mask to perform source and drain ion implantation, and finally use For example, the ashing method removes the patterned photoresist layer.
  • an annealing process may also be performed.
  • the annealing may use any annealing treatment method well known to those skilled in the art, including but not limited to rapid thermal annealing, furnace tube annealing, peak annealing, laser annealing, etc., for example, performing rapid
  • the heating annealing process uses a high temperature of 900 to 1050 ° C to activate the dopants in the source / drain regions and simultaneously repair the lattice structure of the surface of the semiconductor substrate damaged in each ion implantation process.
  • a lightly doped drain (LDD) is separately formed between the source / drain regions and each gate.
  • the dielectric layer is an interlayer dielectric (ILD).
  • the interlayer medium may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal) CVD manufacturing process or a high density plasma (HDP) manufacturing process, such as Doped silica glass (USG), phosphorosilicate glass (PSG) or borophosphosilicate glass (BPSG).
  • the interlayer medium may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped Ethoxysilane (BTEOS).
  • the deposited interlayer dielectric can also be planarized by a planarization method (such as chemical mechanical polishing CMP), so that the interlayer dielectric has a flat surface.
  • a planarization method such as chemical mechanical polishing CMP
  • a contact hole lithography plate is used for photolithography and etching to form a field oxygen contact hole penetrating the dielectric layer into the field oxygen layer.
  • the contact hole lithography plate includes a field oxygen contact hole pattern corresponding to at least the field oxygen contact hole.
  • a field oxygen contact hole is formed by providing a field oxygen contact hole pattern on the contact hole lithography plate. It can deplete the drift region of the drain end more strongly than the field oxygen without contact holes, thereby reducing the on-resistance, and has a relatively small impact on BV. Since only the specially designed contact hole photolithography pattern can reduce the surface electric field (RESURF), it will not increase the manufacturing cost.
  • RESURF surface electric field
  • those skilled in the art may also use other processes known in the art to manufacture and form field oxygen contact holes. These processes do not necessarily require the field oxygen contact holes to be opened to form deep holes. That is to say, the oxygen contact holes in each field can be the same size, or the size and depth of the oxygen contact holes in the field are not necessarily related.
  • a field oxygen contact hole pattern with different sizes is provided on the contact hole lithography plate, so that the closer to the drain in the etching window (field oxygen contact hole etching window) formed after photolithography The smaller the etching window of the polar region. Since the etching rate of the field oxygen contact hole is affected by the size of the etching window, the closer the field oxygen contact hole obtained by etching is to the drain region, the shallower the depth, and the field oxygen contact hole of different depth can be obtained to drift The zone is depleted, forming a good ladder so that the depletion tends to the intensity we want. Since only the specially designed contact hole photolithography pattern can reduce the surface electric field (RESURF), it will not increase the manufacturing cost.
  • RESURF surface electric field
  • the laterally diffused metal oxide semiconductor device includes at least one set of first field oxygen contact holes that penetrates through the polysilicon field plate and then continues down into the field oxygen layer, and at least one set of locations where the polysilicon field plate is not covered The second field oxygen contact hole penetrating into the field oxygen layer.
  • the diameter of any second field oxygen contact hole is smaller than the diameter of any first field oxygen contact hole, and the depth of any second field oxygen contact hole penetrating into the field oxygen layer is shallower than that of any first field The depth of the oxygen contact hole penetrating into the field oxygen layer.
  • the conductive material in the at least one set of field oxygen contact holes is electrically connected to the ground wire so as to be grounded.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种横向扩散金属氧化物半导体器件及其制造方法，所述器件包括：衬底(10)；漂移区(20)；栅极结构；漏极区(32)；源极区(34)；场氧层(40)；多晶硅场板(44)；所述器件还设有穿入所述场氧层内的场氧接触孔，场氧接触孔中填充有导电材料。

Description

横向扩散金属氧化物半导体器件及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种横向扩散金属氧化物半导体器件，还涉及一种横向扩散金属氧化物半导体器件的制造方法。
背景技术
对于功率器件(Power Device)，导通电阻(Rdson)是我们最为关注的参数之一。横向扩散金属氧化物半导体(LDMOS)器件的一种做法是增强漏端漂移区的耗尽来提高耐压。漂移区浓度越淡，耗尽越多，击穿电压(BV)越高，Rdson越大；漂移区浓度越高，耗尽越少，BV越低，Rdson越小。
一种增强漂移区耗尽的做法是多晶硅搭场，即场氧化层上设置多晶硅场板来增强漂移区的耗尽。场氧层越薄、多晶硅场板增强漂移区耗尽的效果就越强，可以在Rdson基本不变基础上提高BV。但是场氧层的厚度不可能无限小，因为漏极区与栅极之间的电场强度会限制BV，即会导致漏极区与栅极之间介质发生击穿。
发明内容
基于此，有必要提供一种能够在保证BV的前提下，降低导通电阻的横向扩散金属氧化物半导体器件及其制造方法。
一种横向扩散金属氧化物半导体器件，包括：衬底；漂移区，设置在所述衬底中；栅极结构，设置在所述衬底上，包括栅极介电层和栅极介电层上的栅极层；漏极区，设置在所述栅极结构其中一侧的衬底中，与所述漂移区相接触；源极区，设置在所述栅极结构另一侧的衬底中；场氧层，设置在所述漂移区表面；及多晶硅场板，设置在所述场氧层上；所述横向扩散金属氧 化物半导体器件还设有穿入所述场氧层内的场氧接触孔，场氧接触孔中填充有导电材料。
一种横向扩散金属氧化物半导体器件的制造方法，包括：获取衬底，所述衬底中形成有漂移区，所述漂移区表面形成有场氧层；在所述衬底上形成栅极介电层；在所述栅极介电层和场氧层上形成多晶硅层；对所述多晶硅层进行光刻及刻蚀，形成栅极介电层上的栅极层和场氧层上的多晶硅场板；在所述栅极层和多晶硅场板上形成介质层；及使用接触孔光刻版光刻并刻蚀形成贯穿所述介质层进入所述场氧层内的场氧接触孔，所述接触孔光刻版包括与所述场氧接触孔对应的场氧接触孔图形。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中横向扩散金属氧化物半导体器件的结构示意图；
图2是图1所示结构增加了俯视下的场氧接触孔的示意图；
图3是一实施例中横向扩散金属氧化物半导体器件的制造方法的流程图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件 的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中横向扩散金属氧化物半导体器件的结构示意图，图2是图1所示结构增加了俯视下的场氧接触孔的示意图。参照图2，横向扩散金属氧化物半导体器件包括衬底10、漂移区20、栅极结构、漏极区32、源极区34、场氧层40、多晶硅场板44及场氧接触孔。
其中，漂移区20设置在衬底10中。栅极结构设置在衬底10上，包括栅极介电层(图1和图2中未示)和栅极介电层上的栅极层44。漏极区32设置在栅极结构其中一侧的衬底10中，与漂移区20相接触；在本实施例中，漏极区32设置在漂移区20中(图1中为设置在栅极结构右侧的衬底10中)。源极区34设置在栅极结构另一侧的衬底10中(图1中为设置在栅极结构左侧的衬底10中)。场氧层40设置在漂移区20表面，在本实施例中，场氧层40具体是设于漂移区20位于漏极区32和源极区34之间的表面。多晶硅场 板42设置在场氧层40上。场氧接触孔穿入场氧层40内，场氧接触孔中填充有导电材料。在不同的实施例中，场氧接触孔可以为一个，也可以设置多个。
上述横向扩散金属氧化物半导体器件，通过设置场氧接触孔，既能够比场氧层40不设置接触孔的方案有更强的漏端漂移区耗尽从而降低导通电阻，对BV的影响又相对较小。
在图1所示实施例中，场氧接触孔包括至少两组，每组场氧接触孔包括至少一个接触孔，越靠近漏极区32的组的场氧接触孔孔径越小、穿入场氧层40的深度越浅，各场氧接触孔中填充有导电材料。在图2所示实施例中，有4组(4排)场氧接触孔，分别是场氧接触孔41、场氧接触孔43、场氧接触孔45、场氧接触孔47。虽然在图1所示的实施例中，穿入场氧层越浅的场氧接触孔的孔径越小、穿入场氧层越深的场氧接触孔的孔径越大，但可以理解的，在其他实施例中，场氧接触孔的大小与深度没有必然关系，例如各场氧接触孔可以一样大，或者穿入场氧层深的场氧接触孔的孔径可以较小。
图1所示实施例通过设置深浅不一的场氧接触孔，使得距漏极区32近的场氧层40适当变厚、距漏极区32远的场氧层适当变薄(即距漏极区32近的接触孔底部到场氧层40底部的厚度较厚、距漏极区32远的接触孔底部到场氧层40底部的厚度较薄)，既能够尽量地增强耗尽，又能够解决场氧层40的厚度会限制BV的问题。在其他实施例中，场氧接触孔也可以采用其他排列方式，各接触孔可以为与图1所示实施例不同的深浅方式，例如深浅梯度的方向相反，或者深浅没有特定的规律等。
在图1所示实施例中，栅极层44为多晶硅栅，即与多晶硅场板42的材质相同，从而可以在同一道工艺中淀积并光刻刻蚀形成。在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极层44的材料。
在一个实施例中，衬底10为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在图1所示的实施例中，衬底10的构成材料选用单晶硅。
在一个实施例中，衬底10具有第二导电类型，漂移区20具有第一导电类型，漏极区32和源极区34具有第一导电类型。在一个实施例中，第一导电类型是N型，第二导电类型是P型；在另一个实施例中，第一导电类型是P型，第二导电类型是N型。
根据具体的LDMOS器件的类型，漂移区20具有不同的导电类型。例如，若LDMOS器件为N型LDMOS器件，则漂移区20为N型漂移区；若LDMOS器件为P型LDMOS器件，则漂移区20为P型漂移区。在图1所示的实施例中，漂移区20为N-漂移区。一般来说，漂移区20的掺杂浓度较低，其低于漏极区32和源极区34的掺杂浓度，相当于在源极和漏极之间形成一个电阻较高的区域，能够提高击穿电压，并减小了源极和漏极之间的寄生电容，有利于提高器件的频率特性。
在一个实施例中，栅极介电层可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅极介电层可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
在图1所示的实施例中，漏极区32和源极区34为N型掺杂离子重掺杂(N+)的漏极和源极。
在一个实施例中，横向扩散金属氧化物半导体器件包括至少一组贯穿多晶硅场板42后继续向下贯穿进入场氧层40的第一场氧接触孔，和至少一组在未覆盖多晶硅场板42的位置贯穿进入场氧层40的第二场氧接触孔(例如图1所示的第二场氧接触孔47)。在其他实施例中，也可以只设置贯穿多晶硅场板后继续向下贯穿进入场氧层的场氧接触孔，或者只设置在未覆盖多晶硅场板的位置贯穿进入场氧层的场氧接触孔。在一个实施例中，任一第二场氧接触孔的孔径小于任一第一场氧接触孔的孔径，任一第二场氧接触孔穿入场氧层的深度浅于任一第一场氧接触孔的穿入场氧层的深度。
在一个实施例中，横向扩散金属氧化物半导体器件还包括介质层和金属 层。介质层(图1未示)设置在栅极层、多晶硅场板、漏极区及源极区上，金属层(图1未标示)设置在介质层上方。在图1所示的实施例中，金属层包括接地连线52，各组场氧接触孔中，至少一组场氧接触孔中的导电材料电性连接接地连线52从而接地。在图2所示的实施例中，场氧接触孔41和场氧接触孔43中的金属塞连接接地连线52。
如果场氧接触孔中的金属塞与源端连接一起，会增加栅漏电容(Cgd)，对器件开关特性影响很大，所以把场氧接触孔中的金属塞直接连接地线(GND)，既可以实现最大限度的增强耗尽，又可以有效降低电容。
在一个实施例中，至少一组场氧接触孔中的导电材料不与金属层电性连接从而浮空。在图2所示实施例中，场氧接触孔47中的金属塞浮空。
发明人实际测试发现，器件的开态击穿电压(ONBV)会受到接地的场氧接触孔的影响。因此如果对ONBV的设计值有较高的要求，则需要考虑把靠近漏端的场氧接触孔浮空，以降低漏端的电场强度。具体可以根据器件需要的开态击穿电压(ONBV)与关态击穿电压(OFFBV)来进行折中，确定需要浮空的场氧接触孔的阵列组合(即需要浮空的场氧接触孔的数量和位置)。
在一个实施例中，浮空的场氧接触孔为最靠近漏极区32的一组场氧接触孔，发明人认为这样设置可以在ONBV和OFFBV间取得较好的折中。可以理解的，在其他实施例中也可以是其他位置的场氧接触孔中的金属塞浮空。
在图1和图2所示的实施例中，LDMOS器件还包括体区30。体区30位于栅极层44远离漂移区20的一侧，并与漂移区20间隔。源极区34形成在体区30中。体区30具有和漂移区20相反的导电类型，即体区30具有第二导电类型。在图1所示实施例中，体区30为P形体区。
在图1和图2所示的实施例中，LDMOS器件还包括在体区30中设置的体引出区36。体引出区36与体区30导电类型相同。例如，体区30为P型，则体引出区36也可以为P型，且其掺杂浓度大于体区的掺杂浓度，例如体引出区36为P型杂质重掺杂。
在图1和图2所示的实施例中，除了场氧接触孔以外，LDMOS器件还设 有漏极接触孔、源极接触孔、栅极接触孔、体区接触孔。栅极接触孔中的金属塞电连接栅极层44，以将栅极引出。漏极接触孔中的金属塞电连接漏极区32，以将漏极引出。源极接触孔中的金属塞电连接源极34，以将源极引出。体区接触孔中的金属塞电连接体引出区36，以将体区引出。
漏极接触孔、源极接触孔、栅极接触孔、体区接触孔及各组场氧接触孔中填充的导电材料可以为本领域技术人员熟知的任何适合的导电材料，包括但不限于金属材料；其中，所述金属材料可以包括Ag、Au、Cu、Pd、Pt、Cr、Mo、Ti、Ta、W和Al中的一种或几种。
在一个实施例中，各接触孔可以填充相同的导电材料，例如均填充钨金属等，也可以填充不同的导电材料。
本申请还提供一种横向扩散金属氧化物半导体器件的制造方法，可以用于制造上述任一实施例所述的横向扩散金属氧化物半导体器件。图3是一实施例中横向扩散金属氧化物半导体器件的制造方法的流程图，包括下列步骤：
S310，获取衬底。
衬底中形成有漂移区，漂移区表面形成有场氧层。在一个实施例中，衬底为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
S320，在衬底上形成栅极介电层。
在一个实施例中，栅极介电层可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物，或者，栅极介电层可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于：氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
栅极介电层可以用本领域习知的工艺形成，例如热氧化工艺。
S330，在栅极介电层和场氧化层上形成多晶硅层。
在一个实施例中，多晶硅层的形成方法可以采用化学气相沉积法(CVD)， 如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(LTCVD)、等离子体化学气相沉积(PECVD)，也可使用例如溅镀及物理气相沉积(PVD)等方法。多晶硅层的厚度可以根据器件的尺寸使用适合的厚度，在此不做具体限制。
在一个实施例中，LDMOS器件的制造过程中可以有两次栅极材质的淀积工艺，步骤S330可以为其中的任一次淀积工艺。
S340，进行光刻及刻蚀，形成栅极介电层上的栅极层和场氧层上的多晶硅场板。
对多晶硅层进行光刻及刻蚀，形成栅极介电层上的栅极层和场氧层上的多晶硅场板。
在一个实施例中，还可在形成栅极层和多晶硅场板之前，于衬底中形成体区。体区位于栅极层远离漂移区的一侧，并与漂移区间隔。体区具有和漂移区相反的导电类型。可以使用例如离子注入的方法形成体区，例如，在步骤S330之后、S340之前进行体区光刻及刻蚀，去除预定形成体区位置的栅极材质，然后通过离子注入向衬底内预定形成体区的区域注入P型掺杂杂质例如硼，注入之后可以通过热扩散形成体区。
在一个实施例中，还可在形成栅极层和多晶硅场板之后形成漏极区和源极区。漏极区设置在栅极层的一侧的衬底中，与漂移区相接触，在一个实施例中为设置在漂移区中。源极区设置在栅极层的另一侧的衬底中。在一个实施例中，漏极区和源极区具有第一导电类型。例如，漏极区和源极区为N型，其还可以为N型掺杂离子重掺杂的源极和漏极。
在一个实施例中，形成源极和漏极的方法包括对半导体衬底中预定形成源极和漏极的区域执行源漏离子注入，在栅极层两侧的衬底中分别形成漏极区和源极区。可以通过利用光刻工艺首先形成暴露出预定形成漏极区和源极区的图案化的光刻胶层，再以该图案化的光刻胶层为掩膜，进行源漏离子注入，最后利用例如灰化的方法去除图案化的光刻胶层。
随后，还可以进行退火工艺，示例性地，退火可以使用本领域技术人员 熟知的任何的退火处理方法，包括但不限于快速热退火、炉管退火、峰值退火、激光退火等，例如，进行快速升温退火工艺，利用900至1050℃的高温来活化源极/漏极区域内的掺杂质，并同时修补在各离子注入工艺中受损的半导体衬底表面的晶格结构。此外，亦可视产品需求及功能性考量，另于源极区/漏极区与各栅极之间分别形成轻掺杂漏极(LDD)。
S350，在栅极层和多晶硅场板上形成介质层。
在一个实施例中，该介质层为层间介质(ILD)。层间介质可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介质也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。
在一个实施例中，还可以通过平坦化的方法(例如化学机械研磨CMP)对沉积的层间介质进行平坦化，以使层间介质具有平坦的表面。
S360，光刻并刻蚀形成贯穿介质层进入场氧层内的场氧接触孔。
使用接触孔光刻版光刻并刻蚀形成贯穿介质层进入场氧层内的场氧接触孔，接触孔光刻版包括与至少场氧接触孔对应的场氧接触孔图形。
上述横向扩散金属氧化物半导体器件的制造方法，通过在接触孔光刻版上设置场氧接触孔图形来形成场氧接触孔。既能够比场氧不设置接触孔有更强的漏端漂移区耗尽从而降低导通电阻，对BV的影响又相对较小。由于仅通过特殊设计的接触孔光刻版图形，就可以实现降低表面电场(RESURF)，因此不会增加制造成本。
在一个实施例中，接触孔光刻版上的场氧接触孔图形有至少两组，不同组的场氧接触孔图形的大小不等，越靠近漏极区的组的场氧接触孔图形越大、越远离漏极区的场氧接触孔图形越小，从而使得越靠近漏极区的组的场氧接触孔孔径越小、穿入场氧层越浅。可以理解的，在其他实施例中，本领域技术人员也可以使用其他的本领域习知工艺制造形成场氧接触孔，这些工艺并 不一定需要场氧接触孔开得大才能形成深孔，也就是说各场氧接触孔可以一样大、或者场氧接触孔大小与深度没有必然关系。
上述横向扩散金属氧化物半导体器件的制造方法，在接触孔光刻版上设置大小不同的场氧接触孔图形，使得光刻后形成的刻蚀窗口(场氧接触孔刻蚀窗口)中越靠近漏极区的刻蚀窗口越小。由于场氧接触孔的刻蚀速率会受刻蚀窗口的大小影响，因此刻蚀得到的场氧接触孔越靠近漏极区、深度就越浅，能够得到不同深度的场氧接触孔来对漂移区进行耗尽，形成很好的阶梯使耗尽趋于我们想要的强度。由于仅通过特殊设计的接触孔光刻版图形，就可以实现降低表面电场(RESURF)，因此不会增加制造成本。
在一个实施例中，横向扩散金属氧化物半导体器件包括至少一组贯穿多晶硅场板后继续向下贯穿进入场氧层的第一场氧接触孔，和至少一组在未覆盖多晶硅场板的位置贯穿进入场氧层的第二场氧接触孔。在一个实施例中，任一第二场氧接触孔的孔径小于任一第一场氧接触孔的孔径，任一第二场氧接触孔穿入场氧层的深度浅于任一第一场氧接触孔的穿入场氧层的深度。
在一个实施例中，至少一组场氧接触孔中的导电材料电性连接接地连线从而接地。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向扩散金属氧化物半导体器件，包括：
    衬底；
    漂移区，设置在所述衬底中；
    栅极结构，设置在所述衬底上，包括栅极介电层和栅极介电层上的栅极层；
    漏极区，设置在所述栅极结构其中一侧的衬底中，与所述漂移区相接触；
    源极区，设置在所述栅极结构另一侧的衬底中；
    场氧层，设置在所述漂移区表面；及
    多晶硅场板，设置在所述场氧层上；
    所述横向扩散金属氧化物半导体器件还设有穿入所述场氧层内的场氧接触孔，场氧接触孔中填充有导电材料。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述场氧接触孔包括至少两组，每组包括至少一个场氧接触孔，越靠近所述漏极区的组的场氧接触孔穿入场氧层越浅。
  3. 根据权利要求2所述的横向扩散金属氧化物半导体器件，其中，所述至少两组场氧接触孔包括至少一组贯穿所述多晶硅场板后继续向下贯穿进入场氧层的第一场氧接触孔，和至少一组在未覆盖多晶硅场板的位置贯穿进入场氧层的第二场氧接触孔。
  4. 根据权利要求3所述的横向扩散金属氧化物半导体器件，其中，任一第二场氧接触孔的孔径小于任一第一场氧接触孔的孔径，任一第二场氧接触孔穿入场氧层的深度浅于任一第一场氧接触孔的穿入场氧层的深度。
  5. 根据权利要求1-4中任一项所述的横向扩散金属氧化物半导体器件，其中，还包括介质层和金属层，所述介质层设置在所述栅极层、多晶硅场板、漏极区及源极区上，所述金属层设置在所述介质层上方，所述金属层包括接地连线；所述至少两组场氧接触孔中，至少一组场氧接触孔中的导电材料电 性连接所述接地连线从而接地。
  6. 根据权利要求5所述的横向扩散金属氧化物半导体器件，其中，所述至少两组场氧接触孔中，至少一组场氧接触孔中的导电材料不与所述金属层电性连接从而浮空。
  7. 根据权利要求6所述的横向扩散金属氧化物半导体器件，其中，所述浮空的场氧接触孔为最靠近所述漏极区的一组场氧接触孔。
  8. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，穿入场氧层越浅的所述场氧接触孔的孔径越小、穿入场氧层越深的所述场氧接触孔的孔径越大。
  9. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述栅极层的材质为多晶硅，所述场氧层设于所述漂移区位于漏极区和源极区之间的表面。
  10. 根据权利要求1所述的横向扩散金属氧化物半导体器件，其中，所述衬底具有第二导电类型，所述漂移区具有第一导电类型，所述漏极区和源极区具有第一导电类型，所述第一导电类型和第二导电类型为相反的导电类型。
  11. 一种横向扩散金属氧化物半导体器件的制造方法，包括：
    获取衬底，所述衬底中形成有漂移区，所述漂移区表面形成有场氧层；
    在所述衬底上形成栅极介电层；
    在所述栅极介电层和场氧层上形成多晶硅层；
    对所述多晶硅层进行光刻及刻蚀，形成栅极介电层上的栅极层和场氧层上的多晶硅场板；
    在所述栅极层和多晶硅场板上形成介质层；及
    使用接触孔光刻版光刻并刻蚀形成贯穿所述介质层进入所述场氧层内的场氧接触孔，所述接触孔光刻版包括与所述场氧接触孔对应的场氧接触孔图形。
  12. 根据权利要求11所述的制造方法，其中，所述接触孔光刻版包括至 少两组场氧接触孔图形，以形成至少两组场氧接触孔，不同组的场氧接触孔图形的大小不等，从而使得越靠近所述横向扩散金属氧化物半导体器件的漏极区的组的场氧接触孔孔径越小、穿入场氧层越浅。
  13. 根据权利要求12所述的制造方法，其中，所述至少两组场氧接触孔包括至少一组贯穿所述多晶硅场板后继续向下贯穿进入场氧层的第一场氧接触孔，和至少一组在未覆盖多晶硅场板的位置贯穿进入场氧层的第二场氧接触孔。
  14. 根据权利要求13所述的制造方法，其中，任一所述第二场氧接触孔的孔径小于任一所述第一场氧接触孔的孔径，任一所述第二场氧接触孔穿入所述场氧层的深度浅于任一所述第一场氧接触孔的穿入场氧层的深度。
  15. 根据权利要求12所述的制造方法，其中，还包括在所述介质层上形成金属层的步骤，所述金属层包括接地连线；所述至少两组场氧接触孔中，至少部分场氧接触孔中的导电材料电性连接所述接地连线从而接地。
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