WO2020098514A1 - Dispositif à semi-conducteur à oxyde métallique à diffusion latérale et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur à oxyde métallique à diffusion latérale et son procédé de fabrication Download PDF

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Publication number
WO2020098514A1
WO2020098514A1 PCT/CN2019/115011 CN2019115011W WO2020098514A1 WO 2020098514 A1 WO2020098514 A1 WO 2020098514A1 CN 2019115011 W CN2019115011 W CN 2019115011W WO 2020098514 A1 WO2020098514 A1 WO 2020098514A1
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Prior art keywords
field oxygen
layer
field
contact hole
oxygen contact
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PCT/CN2019/115011
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English (en)
Chinese (zh)
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汪广羊
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无锡华润上华科技有限公司
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Publication of WO2020098514A1 publication Critical patent/WO2020098514A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a laterally diffused metal oxide semiconductor device, and also relates to a method of manufacturing a laterally diffused metal oxide semiconductor device.
  • the on-resistance (Rdson) is one of the parameters we are most concerned about.
  • LDMOS laterally diffused metal oxide semiconductor
  • LDMOS laterally diffused metal oxide semiconductor
  • a polysilicon field that is, a polysilicon field plate is provided on the field oxide layer to enhance the depletion of the drift region.
  • the thinner the field oxygen layer the stronger the effect of the polysilicon field plate to enhance the depletion of the drift region, and the BV can be improved on the basis that Rdson is basically unchanged.
  • the thickness of the field oxygen layer cannot be infinitely small, because the electric field strength between the drain region and the gate will limit the BV, which will cause the dielectric between the drain region and the gate to break down.
  • a laterally diffused metal oxide semiconductor device including: a substrate; a drift region provided in the substrate; a gate structure provided on the substrate, including a gate dielectric layer and a gate dielectric layer The gate layer on the top; the drain region, provided in the substrate on one side of the gate structure, in contact with the drift region; the source region, provided on the substrate on the other side of the gate structure Medium; a field oxygen layer, which is provided on the surface of the drift region; and a polysilicon field plate, which is provided on the field oxygen layer; the laterally diffused metal oxide semiconductor device is also provided with a field penetrating into the field oxygen layer Oxygen contact holes, field oxygen contact holes are filled with conductive material.
  • a method for manufacturing a laterally diffused metal oxide semiconductor device includes: obtaining a substrate, a drift region is formed in the substrate, a field oxygen layer is formed on the surface of the drift region; and a gate dielectric is formed on the substrate An electric layer; forming a polysilicon layer on the gate dielectric layer and the field oxygen layer; performing photolithography and etching on the polysilicon layer to form a gate layer on the gate dielectric layer and a polysilicon on the field oxygen layer A field plate; forming a dielectric layer on the gate layer and the polysilicon field plate; and using contact hole photolithography and etching to form a field oxygen contact hole penetrating the dielectric layer into the field oxygen layer, so
  • the contact hole lithography plate includes a field oxygen contact hole pattern corresponding to the field oxygen contact hole.
  • FIG. 1 is a schematic structural view of a laterally diffused metal oxide semiconductor device in an embodiment
  • FIG. 2 is a schematic diagram of the structure shown in FIG. 1 with a field oxygen contact hole in a plan view added;
  • FIG. 3 is a flowchart of a method for manufacturing a laterally diffused metal oxide semiconductor device in an embodiment.
  • first element, component, region, layer, or section discussed below can be represented as a second element, component, region, layer, or section.
  • Spatial relationship terms such as “below”, “below”, “below”, “below”, “above”, “above”, etc. It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then elements or features described as “below” or “beneath” or “below” will be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. In this way, a change from the shown shape due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted area shown as a rectangle generally has round or curved features and / or implant concentration gradients at its edges, rather than a binary change from the implanted area to the non-implanted area. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is proceeding. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.
  • the vocabulary in the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art.
  • the P + type represents the P type with heavy doping concentration
  • the P type represents medium P-type doping concentration
  • P-type represents P-type with light doping concentration
  • N + type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents light-doping concentration N type.
  • FIG. 1 is a schematic structural view of a laterally diffused metal oxide semiconductor device in an embodiment
  • FIG. 2 is a schematic view of the structure shown in FIG. 1 with a field oxygen contact hole in a plan view added.
  • the laterally diffused metal oxide semiconductor device includes a substrate 10, a drift region 20, a gate structure, a drain region 32, a source region 34, a field oxygen layer 40, a polysilicon field plate 44 and a field oxygen contact hole.
  • the drift region 20 is provided in the substrate 10.
  • the gate structure is provided on the substrate 10 and includes a gate dielectric layer (not shown in FIGS. 1 and 2) and a gate layer 44 on the gate dielectric layer.
  • the drain region 32 is disposed in the substrate 10 on one side of the gate structure and is in contact with the drift region 20; in this embodiment, the drain region 32 is disposed in the drift region 20 (in FIG. 1, it is disposed in the gate In the substrate 10 on the right side of the structure).
  • the source region 34 is provided in the substrate 10 on the other side of the gate structure (in FIG. 1, it is provided in the substrate 10 on the left side of the gate structure).
  • the field oxygen layer 40 is disposed on the surface of the drift region 20.
  • the field oxygen layer 40 is specifically disposed on the surface of the drift region 20 between the drain region 32 and the source region 34.
  • a polysilicon field plate 42 is provided on the field oxygen layer 40.
  • the field oxygen contact hole penetrates into the field oxygen layer 40, and the field oxygen contact hole is filled with a conductive material. In different embodiments, there may be one field oxygen contact hole, or a plurality of contact holes.
  • the above-mentioned laterally diffused metal oxide semiconductor device by providing a field oxygen contact hole, can not only have a stronger drain drift region depletion than the solution where the field oxygen layer 40 does not provide a contact hole, thereby reducing the on-resistance, and affecting the BV Relatively small.
  • the field oxygen contact holes include at least two groups, and each group of field oxygen contact holes includes at least one contact hole.
  • the shallower the depth of the oxygen layer 40, the oxygen contact holes in each field are filled with a conductive material.
  • the pore diameter of the field oxygen contact hole with a shallower penetration into the field oxygen layer is smaller, and the pore diameter of the field oxygen contact hole with a deeper penetration into the field oxygen layer is larger, it can be understood that
  • the size and depth of the field oxygen contact hole are not necessarily related, for example, the field oxygen contact holes may be the same size, or the diameter of the field oxygen contact hole penetrating deep into the field oxygen layer may be smaller.
  • the field oxygen layer 40 near the drain region 32 is appropriately thickened, and the field oxygen layer far from the drain region 32 is appropriately thinned (ie, from the drain (The thickness of the bottom of the contact hole near the pole region 32 to the bottom of the field oxygen layer 40 is thicker, and the thickness of the bottom of the contact hole farther from the drain region 32 to the bottom of the field oxygen layer 40 is thinner), which can both maximize depletion and solve
  • the thickness of the field oxygen layer 40 will limit the problem of BV.
  • the field oxygen contact holes may also be arranged in different ways, and each contact hole may be in a different depth manner from the embodiment shown in FIG. 1, for example, the direction of the gradient of the depth is opposite, or there is no specific rule for the depth.
  • the gate layer 44 is a polysilicon gate, that is, the material of the polysilicon field plate 42 is the same, so that it can be deposited and formed by photolithography and etching in the same process.
  • metal, metal nitride, metal silicide, or similar compounds may be used as the material of the gate layer 44.
  • the substrate 10 is a semiconductor substrate, and its material may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. are stacked on the insulator.
  • the constituent material of the substrate 10 is single crystal silicon.
  • the substrate 10 has the second conductivity type
  • the drift region 20 has the first conductivity type
  • the drain region 32 and the source region 34 have the first conductivity type.
  • the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
  • the drift region 20 has different conductivity types according to the specific type of LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 20 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, the drift region 20 is a P-type drift region. In the embodiment shown in FIG. 1, the drift region 20 is an N-drift region. Generally speaking, the doping concentration of the drift region 20 is lower, which is lower than the doping concentration of the drain region 32 and the source region 34, which is equivalent to forming a region of higher resistance between the source and the drain. Increasing the breakdown voltage and reducing the parasitic capacitance between the source and drain are beneficial to improve the frequency characteristics of the device.
  • the gate dielectric layer may include conventional dielectric materials such as silicon oxide, nitride, and oxynitride with a dielectric constant from about 4 to about 20 (measured in vacuum), or, gate dielectric
  • the dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the drain region 32 and the source region 34 are N-type doped ion heavily doped (N +) drain and source.
  • the laterally diffused metal oxide semiconductor device includes at least one set of first field oxygen contact holes that penetrates through the polysilicon field plate 42 and then continues down into the field oxygen layer 40, and at least one set of uncovered polysilicon field plates The position of 42 penetrates into the second field oxygen contact hole of the field oxygen layer 40 (for example, the second field oxygen contact hole 47 shown in FIG. 1). In other embodiments, only a field oxygen contact hole that penetrates through the polysilicon field plate and then penetrates down into the field oxygen layer may be provided, or only a field oxygen contact hole that penetrates into the field oxygen layer at a position that does not cover the polysilicon field plate is provided .
  • the diameter of any second field oxygen contact hole is smaller than the diameter of any first field oxygen contact hole, and the depth of any second field oxygen contact hole penetrating into the field oxygen layer is shallower than that of any first field The depth of the oxygen contact hole penetrating into the field oxygen layer.
  • the laterally diffused metal oxide semiconductor device further includes a dielectric layer and a metal layer.
  • a dielectric layer (not shown in FIG. 1) is provided on the gate layer, polysilicon field plate, drain region and source region, and a metal layer (not shown in FIG. 1) is provided above the dielectric layer.
  • the metal layer includes a ground connection 52.
  • the conductive material in at least one set of field oxygen contact holes is electrically connected to the ground connection 52 to be grounded.
  • the metal plugs in the field oxygen contact hole 41 and the field oxygen contact hole 43 are connected to the ground wire 52.
  • the metal plug in the field oxygen contact hole is connected with the source terminal, it will increase the gate drain capacitance (Cgd), which has a great influence on the switching characteristics of the device, so the metal plug in the field oxygen contact hole is directly connected to the ground (GND), Not only can maximize depletion, but also effectively reduce capacitance.
  • Cgd gate drain capacitance
  • the conductive material in at least one set of field oxygen contact holes is not electrically connected to the metal layer to float.
  • the metal plug in the field oxygen contact hole 47 floats.
  • ONBV on-state breakdown voltage
  • the floating field oxygen contact hole is a group of field oxygen contact holes closest to the drain region 32.
  • the inventor believes that this arrangement can achieve a better compromise between ONBV and OFFBV. It can be understood that, in other embodiments, the metal plug in the field oxygen contact hole at other positions may also float.
  • the LDMOS device further includes a body region 30.
  • the body region 30 is located on the side of the gate layer 44 away from the drift region 20 and is spaced from the drift region 20.
  • the source region 34 is formed in the body region 30.
  • the body region 30 has the opposite conductivity type as the drift region 20, that is, the body region 30 has the second conductivity type.
  • the body region 30 is a P-shaped body region.
  • the LDMOS device further includes a body lead-out region 36 provided in the body region 30.
  • the body lead-out area 36 has the same conductivity type as the body area 30.
  • the body region 30 is P-type
  • the body extraction region 36 may also be P-type, and its doping concentration is greater than that of the body region.
  • the body extraction region 36 is heavily doped with P-type impurities.
  • the LDMOS device in addition to the field oxygen contact hole, is also provided with a drain contact hole, a source contact hole, a gate contact hole, and a body contact hole.
  • the metal plug in the gate contact hole is electrically connected to the gate layer 44 to lead the gate out.
  • the metal plug in the drain contact hole is electrically connected to the drain region 32 to lead the drain.
  • the metal plug in the source contact hole is electrically connected to the source electrode 34 to lead the source electrode out.
  • the metal plug in the contact hole of the body area electrically connects the body lead-out area 36 to lead the body area out.
  • the conductive material filled in the drain contact hole, the source contact hole, the gate contact hole, the body region contact hole and each group of field oxygen contact holes may be any suitable conductive material known to those skilled in the art, including but not limited to metal Material; wherein, the metal material may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al.
  • each contact hole may be filled with the same conductive material, for example, tungsten metal, etc., or different conductive materials.
  • the present application also provides a method for manufacturing a laterally diffused metal oxide semiconductor device, which can be used to manufacture the laterally diffused metal oxide semiconductor device described in any of the above embodiments.
  • 3 is a flowchart of a method for manufacturing a laterally diffused metal oxide semiconductor device in an embodiment, including the following steps:
  • the substrate is a semiconductor substrate, the material of which may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), insulator S-SiGeOI, silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI) are stacked on top.
  • SOI silicon on insulator
  • SSOI silicon on insulator
  • SiGeOI silicon-germanium-on-insulator
  • GeOI germanium-on-insulator
  • the gate dielectric layer may include conventional dielectric materials such as silicon oxide, nitride, and oxynitride with a dielectric constant from about 4 to about 20 (measured in vacuum), or, gate dielectric
  • the dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100.
  • Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
  • the gate dielectric layer may be formed by a process known in the art, such as a thermal oxidation process.
  • the polysilicon layer may be formed by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma chemistry For vapor deposition (PECVD), methods such as sputtering and physical vapor deposition (PVD) can also be used.
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • LTCVD fast thermal chemical vapor deposition
  • PECVD plasma chemistry For vapor deposition
  • PVD physical vapor deposition
  • the thickness of the polysilicon layer can be a suitable thickness according to the size of the device, and is not specifically limited herein.
  • step S330 may be any one of the deposition processes.
  • the body region may also be formed in the substrate before the gate layer and the polysilicon field plate are formed.
  • the body region is located on the side of the gate layer away from the drift region and is spaced from the drift region.
  • the body region has the opposite conductivity type as the drift region.
  • the body region may be formed using, for example, ion implantation, for example, after step S330 and before S340, body region photolithography and etching are performed to remove the gate material at the location where the body region is to be formed, and then to be formed into the substrate by ion implantation P-type doped impurities such as boron are implanted into the body region, and the body region can be formed by thermal diffusion after implantation.
  • the drain region and the source region can also be formed after the gate layer and the polysilicon field plate are formed.
  • the drain region is provided in the substrate on one side of the gate layer, and is in contact with the drift region, in one embodiment it is provided in the drift region.
  • the source region is provided in the substrate on the other side of the gate layer.
  • the drain and source regions have the first conductivity type.
  • the drain region and the source region are N-type, which may also be a source and drain heavily doped with N-type doped ions.
  • a method of forming a source electrode and a drain electrode includes performing source-drain ion implantation on a region of a semiconductor substrate where the source electrode and the drain electrode are to be formed, and forming a drain region in the substrate on both sides of the gate layer And source region.
  • the patterned photoresist layer that exposes the intended formation of the drain region and the source region can be formed by using a photolithography process, and then the patterned photoresist layer is used as a mask to perform source and drain ion implantation, and finally use For example, the ashing method removes the patterned photoresist layer.
  • an annealing process may also be performed.
  • the annealing may use any annealing treatment method well known to those skilled in the art, including but not limited to rapid thermal annealing, furnace tube annealing, peak annealing, laser annealing, etc., for example, performing rapid
  • the heating annealing process uses a high temperature of 900 to 1050 ° C to activate the dopants in the source / drain regions and simultaneously repair the lattice structure of the surface of the semiconductor substrate damaged in each ion implantation process.
  • a lightly doped drain (LDD) is separately formed between the source / drain regions and each gate.
  • the dielectric layer is an interlayer dielectric (ILD).
  • the interlayer medium may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal) CVD manufacturing process or a high density plasma (HDP) manufacturing process, such as Doped silica glass (USG), phosphorosilicate glass (PSG) or borophosphosilicate glass (BPSG).
  • the interlayer medium may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped Ethoxysilane (BTEOS).
  • the deposited interlayer dielectric can also be planarized by a planarization method (such as chemical mechanical polishing CMP), so that the interlayer dielectric has a flat surface.
  • a planarization method such as chemical mechanical polishing CMP
  • a contact hole lithography plate is used for photolithography and etching to form a field oxygen contact hole penetrating the dielectric layer into the field oxygen layer.
  • the contact hole lithography plate includes a field oxygen contact hole pattern corresponding to at least the field oxygen contact hole.
  • a field oxygen contact hole is formed by providing a field oxygen contact hole pattern on the contact hole lithography plate. It can deplete the drift region of the drain end more strongly than the field oxygen without contact holes, thereby reducing the on-resistance, and has a relatively small impact on BV. Since only the specially designed contact hole photolithography pattern can reduce the surface electric field (RESURF), it will not increase the manufacturing cost.
  • RESURF surface electric field
  • those skilled in the art may also use other processes known in the art to manufacture and form field oxygen contact holes. These processes do not necessarily require the field oxygen contact holes to be opened to form deep holes. That is to say, the oxygen contact holes in each field can be the same size, or the size and depth of the oxygen contact holes in the field are not necessarily related.
  • a field oxygen contact hole pattern with different sizes is provided on the contact hole lithography plate, so that the closer to the drain in the etching window (field oxygen contact hole etching window) formed after photolithography The smaller the etching window of the polar region. Since the etching rate of the field oxygen contact hole is affected by the size of the etching window, the closer the field oxygen contact hole obtained by etching is to the drain region, the shallower the depth, and the field oxygen contact hole of different depth can be obtained to drift The zone is depleted, forming a good ladder so that the depletion tends to the intensity we want. Since only the specially designed contact hole photolithography pattern can reduce the surface electric field (RESURF), it will not increase the manufacturing cost.
  • RESURF surface electric field
  • the laterally diffused metal oxide semiconductor device includes at least one set of first field oxygen contact holes that penetrates through the polysilicon field plate and then continues down into the field oxygen layer, and at least one set of locations where the polysilicon field plate is not covered The second field oxygen contact hole penetrating into the field oxygen layer.
  • the diameter of any second field oxygen contact hole is smaller than the diameter of any first field oxygen contact hole, and the depth of any second field oxygen contact hole penetrating into the field oxygen layer is shallower than that of any first field The depth of the oxygen contact hole penetrating into the field oxygen layer.
  • the conductive material in the at least one set of field oxygen contact holes is electrically connected to the ground wire so as to be grounded.

Abstract

L'invention concerne un dispositif à semi-conducteur à oxyde métallique à diffusion latérale et son procédé de fabrication. Le dispositif comprend : un substrat (10), une région de dérive (20), une structure de grille, une région de drain (32), une région de source (34), une couche d'oxyde de champ (40), et une plaque de champ de silicium polycristallin (44) ; et le dispositif comprend en outre des trous de contact d'oxyde de champ pénétrant dans la couche d'oxyde de champ, et les trous de contact d'oxyde de champ sont remplis d'un matériau conducteur.
PCT/CN2019/115011 2018-11-13 2019-11-01 Dispositif à semi-conducteur à oxyde métallique à diffusion latérale et son procédé de fabrication WO2020098514A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811343321.6 2018-11-13
CN201811343321.6A CN111180504A (zh) 2018-11-13 2018-11-13 横向扩散金属氧化物半导体器件及其制造方法

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