WO2020095362A1 - Dispositif d'aide à la conception, procédé d'aide à la conception et dispositif d'apprentissage automatique - Google Patents

Dispositif d'aide à la conception, procédé d'aide à la conception et dispositif d'apprentissage automatique Download PDF

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Publication number
WO2020095362A1
WO2020095362A1 PCT/JP2018/041202 JP2018041202W WO2020095362A1 WO 2020095362 A1 WO2020095362 A1 WO 2020095362A1 JP 2018041202 W JP2018041202 W JP 2018041202W WO 2020095362 A1 WO2020095362 A1 WO 2020095362A1
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WIPO (PCT)
Prior art keywords
board
data
substrate
emc
pattern
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PCT/JP2018/041202
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English (en)
Japanese (ja)
Inventor
光彦 神田
安泰 関本
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2019528777A priority Critical patent/JP6599057B1/ja
Priority to PCT/JP2018/041202 priority patent/WO2020095362A1/fr
Priority to CN201880099221.5A priority patent/CN113056742B/zh
Publication of WO2020095362A1 publication Critical patent/WO2020095362A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/10—Noise analysis or noise optimisation

Definitions

  • the present invention relates to a design support device, a design support method, and a machine learning device that support the design of a board incorporated in an electronic device.
  • EMC Electro Magnetic Compatibility
  • EMI Electro Magnetic Interference
  • EMS Electro Magnetic Susceptibility
  • the measurement result of the EMC is affected when the arrangement of electronic components on the substrate, the routing and width of the pattern formed on the substrate, the distance between adjacent patterns, and the like change. Since the EMC measurement result is influenced by a plurality of factors, knowledge about EMC and board design experience are required to efficiently design a substrate whose measurement result satisfies the standard.
  • Patent Document 1 describes an invention that enables efficient countermeasures against EMI of a board on which electronic components are mounted.
  • the electromagnetic wave radiated from the substrate is measured while changing the measurement position, and the measurement data is analyzed for each measurement position to calculate one or more feature amounts. Further, the feature amount calculated for each measurement position is classified by cluster analysis, and the classification result is presented to the user together with the measurement position.
  • Patent Document 1 when a user such as a designer determines that an EMI countermeasure is necessary, a substrate for which the countermeasure is taken is actually manufactured, and an electromagnetic wave emitted from the manufactured substrate is measured again. There is a problem in that it is necessary to calculate and classify the characteristic amount, and it takes time to design the board.
  • the present invention has been made in view of the above, and an object of the present invention is to obtain a design support apparatus capable of improving the design efficiency of a substrate by enabling measures for EMC before actually manufacturing the substrate. To aim.
  • a design support device is compatible with board data including information on a board and a board pattern formed on the board and an electromagnetic environment of an electronic device in which the board is incorporated.
  • an analysis unit that analyzes the learning data including the evaluation data indicating the evaluation result of the sex and learns the variation factor of the electromagnetic environment compatibility.
  • the design support device analyzes when new board data including information on a board pattern formed on a new board that is a board before being incorporated in an electronic device and evaluated for electromagnetic compatibility is input.
  • An evaluation unit is provided for identifying a variation factor of electromagnetic environment compatibility of an electronic device in which the new board is incorporated, based on a learning result of the variation factor by the unit.
  • the design support device has an effect that it is possible to improve the design efficiency of the board by enabling EMC countermeasures before actually manufacturing the board.
  • FIG. 1 is a first diagram for explaining an operation of an analysis unit of the design support device according to the first exemplary embodiment.
  • FIG. 3 is a third diagram for explaining the operation of the analysis unit of the design support device according to the first embodiment.
  • FIG. 5 is a diagram showing an example of a first analysis result generated by the analysis unit of the design support apparatus according to the first embodiment.
  • FIG. 3 is a diagram showing an example of a list of first analysis results generated by the analysis unit of the design support apparatus according to the first embodiment.
  • FIG. 5 is a diagram showing an example of a second analysis result generated by the analysis unit of the design support apparatus according to the first embodiment.
  • the flowchart which shows an example of operation
  • FIG. 1 is a diagram showing an example of a first analysis result generated by the analysis unit of the design support apparatus according to the first embodiment.
  • FIG. 3 is a diagram showing an example of a list of first analysis results generated by the analysis unit of
  • FIG. 11 is a diagram showing an example of a first analysis result generated by the analysis unit of the design support apparatus according to the second embodiment.
  • FIG. 11 is a diagram showing an example of a list of first analysis results generated by the analysis unit of the design support apparatus according to the second embodiment.
  • FIG. 11 is a diagram showing an example of a second analysis result generated by the analysis unit of the design support apparatus according to the second embodiment.
  • FIG. 8 is a diagram showing a configuration example of a design support device according to a third exemplary embodiment.
  • FIG. 16 is a diagram showing an example of a second analysis result generated by the analysis unit of the design support apparatus according to the third embodiment.
  • FIG. 6 is a diagram showing a configuration example of a design support device according to a fourth exemplary embodiment.
  • a design support device, a design support method, and a machine learning device according to an embodiment of the present invention will be described below in detail with reference to the drawings.
  • the present invention is not limited to this embodiment.
  • the learning data includes board data representing a board to be incorporated in the electronic device and EMC evaluation data showing an EMC evaluation result of the electronic device in which the board is incorporated.
  • the board represented by the board data included in the learning data is a designed board.
  • the new board data represents a newly created board.
  • the structure of the board data included in the learning data and the structure of the new board data are the same.
  • the design support device becomes the EMC change factor among the board elements included in the board represented by the input new board data based on the learning result of the EMC change factor. Generate information about the board element. This allows the board designer to obtain information on the EMC variation factor before actually manufacturing the board represented by the new board data and evaluating the EMC, and changing the design as necessary. Will be able to take measures.
  • FIG. 1 is a diagram showing a configuration example of a design support device according to the first exemplary embodiment of the present invention.
  • the design support device 1 according to the first embodiment includes a data acquisition unit 11, an analysis unit 12, a storage unit 13, and an evaluation unit 14.
  • the data acquisition unit 11, the analysis unit 12, and the storage unit 13 configure a machine learning device 20 that learns EMC variation factors.
  • the data acquisition unit 11 acquires data from outside the design support device 1.
  • the data acquired by the data acquisition unit 11 corresponds to the board data 111 and the EMC evaluation data 112 that form the learning data 110, and the new board data 121.
  • the board data 111 and the EMC evaluation data 112 are acquired by the data acquisition unit 11 in a correlated state.
  • the board data 111 is data representing the board, and is configured to include information such as the shape and layer configuration of the board and the shape of the board pattern that is a pattern formed on the board.
  • the board data 111 is, for example, CAD data obtained from a CAD (Computer Aided Design) used for designing a board, or data obtained by converting the CAD data.
  • the board data 111 may include data of parts mounted on the board in addition to the CAD data or the data obtained by converting the CAD data.
  • the component data is data indicating where each component mounted on the board is arranged.
  • the EMC evaluation data 112 is the evaluation data showing the EMC evaluation result of the electronic device in which the board represented by the associated board data 111 is incorporated, that is, the electromagnetic environment compatibility evaluation result.
  • the new board data 121 is data representing a board to be newly designed, and is similar to the board data 111.
  • the board data 111 and the new board data 121 respectively represent boards to be incorporated in the same type of electronic device. That is, each of the board data 111 and the new board data 121 represents a board that is incorporated in an electronic device of the same type and realizes a similar function.
  • the board represented by the new board data 121 corresponds to a board in which a part of the board represented by the board data 111 has been redesigned or a newly designed board.
  • the board whose design has been changed includes a board whose design has been changed as a countermeasure for EMC.
  • the board represented by the new board data 121 is a board before being incorporated in an electronic device and evaluated for EMC.
  • the analysis unit 12 receives the learning data 110 and stores the board data 111 and the EMC evaluation data 112 included in the received learning data 110 in the storage unit 13. Further, the analysis unit 12 uses the board data 111 and the EMC evaluation data 112 received from the data acquisition unit 11, performs machine learning using the board data 111 and the EMC evaluation data 112 as teacher data, and learns a pattern affecting the EMC. To do. That is, when the analysis unit 12 receives the learning data 110 from the data acquisition unit 11, the analysis unit 12 operates as a learning unit of the machine learning device 20.
  • the analysis unit 12 stores the board data 111 and the EMC evaluation data 112 received from the data acquisition unit 11 in the storage unit 13 It is compared with the board data 111 and the EMC evaluation data 112 received in the above. The analysis unit 12 then generates information on a pattern that affects the EMC based on the comparison result.
  • the data acquisition unit 11 acquires the substrate data 111 of a certain substrate and the EMC evaluation data 112 of the electronic device in which the substrate is incorporated, and then the substrate obtained by changing a part of the pattern formed on the substrate (hereinafter , The changed board) and the EMC evaluation data 112 of the electronic device in which the changed board is incorporated are acquired by the data acquisition unit 11.
  • the analysis unit 12 first compares the two acquired substrate data 111 to identify how the pattern formed on the substrate has been changed, and further compares the two EMC evaluation data 112. By doing so, it is possible to know whether or not the change contents of the board affect the EMC. By repeatedly performing such an operation, the analysis unit 12 generates information on a pattern that affects the EMC.
  • the learning operation performed by the analysis unit 12 will be described separately.
  • the storage unit 13 holds various data acquired by the data acquisition unit 11 from the outside and the learning result by the analysis unit 12, that is, information on patterns that influence the EMC generated by the analysis unit 12.
  • the evaluation unit 14 receives the new board data 121 and evaluates the received new board data 121. Specifically, the evaluation unit 14 identifies a variation factor of the EMC of the electronic device in which the board represented by the new board data 121 is incorporated. In the process of identifying the EMC variation factor, the above-described “information of the pattern affecting the EMC” stored in the storage unit 13 is used. That is, when the evaluation unit 14 receives the new board data 121, the evaluation unit 14 specifies the EMC variation factor of the electronic device in which the board represented by the new board data 121 is incorporated based on the learning result by the analysis unit 12.
  • the evaluation unit 14 After evaluating the new board data 121, the evaluation unit 14 outputs the evaluation result as the evaluation result 131 of the new board.
  • the evaluation result 131 of the new board may be output by generating data indicating the evaluation result and outputting it as a file, or by displaying the evaluation result on a display device (not shown).
  • the display format of the evaluation result may be any format that the user can understand. For example, whether the evaluation result is good or bad is displayed in text.
  • FIG. 3 is a diagram illustrating a configuration example of hardware that realizes the design support device 1.
  • the design support device 1 is realized by the processor 101, the storage device 102, the input device 103, the display device 104, and the communication interface 105.
  • the hardware shown in FIG. 3 is, for example, a personal computer.
  • the design support device 1 installs the program for operating as the design support device 1 in the storage device of the personal computer, that is, the storage device 102 shown in FIG. It is realized by the processor 101 executing the created program. That is, the data acquisition unit 11, the analysis unit 12, and the evaluation unit 14 illustrated in FIG. 1 are realized by the processor 101 executing a program installed in the storage device 102 and operating as the design support apparatus 1. ..
  • the processor 101 is a CPU (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP (Digital Signal Processor)) and the like.
  • the storage device 102 is a nonvolatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), or a flash memory, a magnetic disk, or the like.
  • the storage device 102 holds a program for the processor 101 to operate as the design support device 1.
  • the storage device 102 is also used as a work memory when the processor 101 executes various processes.
  • the storage device 102 also constitutes the storage unit 13 shown in FIG.
  • the input device 103 is a mouse, keyboard, touch panel, or the like.
  • the input device 103 includes hardware used when the user inputs the learning data 110 and the new board data 121 shown in FIG. 1, for example, a connection interface of an external memory.
  • the display device 104 is a liquid crystal monitor, a display, or the like, and is used when the evaluation unit 14 shown in FIG. 1 displays the content of the evaluation result 131 of the new board.
  • the communication interface 105 is a network interface card or the like.
  • the design support device 1 may acquire at least one of the learning data 110 and the new board data 121 from another device via the network to which the communication interface 105 is connected.
  • FIG. 4 is a flowchart showing an example of a learning operation performed by the design support device 1 according to the first exemplary embodiment.
  • the data acquisition unit 11 acquires the board data 111 and the EMC evaluation data 112 corresponding to the board data 111 (steps S11 and S12).
  • the analysis unit 12 receives the board data 111 and the EMC evaluation data 112 acquired by the data acquisition unit 11, and analyzes each received data (step S13).
  • step S13 the analysis unit 12 receives the board data 111 and the EMC evaluation data 112 received this time from the data acquisition unit 11, and the board data 111 and the EMC received in the past from the data acquisition unit 11 and stored in the storage unit 13.
  • the data is analyzed by comparing it with the evaluation data 112.
  • the board data 111 and the EMC evaluation data 112 received this time from the data acquisition unit 11 are referred to as first learning data
  • the board data 111 and the EMC evaluation received in the past stored in the storage unit 13 are referred to.
  • the data 112 may be referred to as second learning data.
  • the board data 111 received this time from the data acquisition unit 11 may be referred to as first board data, and the board data 111 received in the past stored in the storage unit 13 may be referred to as second board data.
  • the EMC evaluation data 112 received this time from the data acquisition unit 11 is referred to as first EMC evaluation data, and the previously received EMC evaluation data 112 stored in the storage unit 13 is referred to as second EMC evaluation data.
  • first EMC evaluation data the previously received EMC evaluation data 112 stored in the storage unit 13 is referred to as second EMC evaluation data.
  • the first learning data is compared with each of the second learning data. If the second learning data does not exist, that is, if the analysis unit 12 receives the first learning data from the data acquisition unit 11 for the first time, the analysis unit 12 receives the comparison data without performing the comparison process.
  • the data that is, the board data 111 and the EMC evaluation data 112 are stored in the storage unit 13. Details of the operation of the analysis unit 12 will be described later.
  • the analysis unit 12 stores the analysis result in the storage unit 13 (step S14). At this time, the analysis unit 12 also stores the first learning data received from the data acquisition unit 11 in the storage unit 13. That is, the analysis unit 12 adds the board data 111 and the EMC evaluation data 112 acquired by the data acquisition unit 11 in steps S11 and S12 to the second learning data.
  • FIG. 5 is a flowchart showing an example of the operation of the analysis unit 12 of the design support device 1 according to the first exemplary embodiment.
  • FIG. 5 shows the operation performed by the analysis unit 12 in step S13 shown in FIG.
  • the analysis unit 12 When receiving the first learning data, the analysis unit 12 receives the first learning data, the first substrate pattern that is the substrate pattern formed on the substrate represented by the first substrate data included in the first learning data, and the second substrate pattern.
  • the difference between the board patterns is extracted by comparing with the second board pattern, which is the board pattern formed on the board represented by one of the board data (step S21).
  • the analysis unit 12 When comparing the first board pattern and the second board pattern, the analysis unit 12 generates an image of each board pattern based on the first board data and the second board data, and compares the images. By doing so, the difference is extracted.
  • the width of the pattern existing at the position A of the first substrate pattern and the width of the pattern existing at the position A of the second substrate pattern are different, the width of the pattern existing at the position A is extracted as the difference. ..
  • the distance between the pattern existing at the position B of the first substrate pattern and the pattern adjacent thereto is different from the distance between the pattern existing at the position B of the second substrate pattern and the pattern adjacent thereto, The interval between the pattern existing at the position B and the pattern adjacent thereto is extracted as a difference point.
  • the analysis unit 12 extracts in step S21.
  • the analysis unit 12 detects the distance between the pattern A1 and the pattern A2 existing in the first substrate pattern and the pattern A1 and the pattern A2 existing at the corresponding positions in the second substrate pattern. Compare with the interval. In the case of the example shown in FIG. 6, the interval between the pattern A1 and the pattern A2 included in the first substrate pattern and the interval between the pattern A1 and the pattern A2 included in the second substrate pattern are different. The interval between the pattern A1 and the pattern A2 is determined to be a difference, and this difference is extracted. Further, for example, as shown in FIG. 7, the analysis unit 12 compares the pattern C1 existing in the first substrate pattern with the pattern C1 existing in the corresponding position of the second substrate pattern. In the case of the example shown in FIG.
  • the analysis unit 12 determines the width of the pattern C1 as a difference. To judge. Further, for example, when the pattern C1 existing in the first substrate pattern does not exist in the corresponding position of the second substrate pattern, as shown in FIG. 8, the analyzing unit 12 determines the presence or absence of the pattern C1 as a difference. to decide.
  • the analysis unit 12 determines, in step S21, the part data included in the first board data and the part data included in the second board data. And to extract the difference between the component mounted on the substrate represented by the first substrate data and the component mounted on the substrate represented by the second substrate data together with the above-described substrate pattern difference. You can In the following description, for simplification, the analysis unit 12 extracts the difference between the board patterns and mounts the parts mounted on the board represented by the first board data and the board represented by the second board data. Differences from parts will not be extracted.
  • each of the differences in the board patterns extracted by the analysis unit 12 may be referred to as a board element.
  • the above-mentioned “spacing between the pattern A1 and the pattern A2”, “width of the pattern C1”, “presence / absence of the pattern C1” and the like correspond to the substrate element.
  • the analysis unit 12 confirms the first EMC evaluation data corresponding to the first board pattern and the second EMC evaluation data corresponding to the second board pattern, and the board pattern extracted in step S21. It is determined whether or not the difference of 1 affects the EMC (step S22).
  • the analysis unit 12 does not affect the EMC by the difference between the board patterns extracted in step S21. To judge.
  • the EMC evaluation level indicated by the first EMC evaluation data is different from the EMC evaluation level indicated by the second EMC evaluation data, it is determined that the difference between the board patterns extracted in step S21 affects the EMC.
  • FIG. 9 is a diagram illustrating an example of a first analysis result generated by the analysis unit 12 according to the first embodiment.
  • the analysis unit 12 extracts the width of the pattern A1, the interval between the patterns A1 and A2, and the presence or absence of the pattern B5 as different points in step S21, and in step S22.
  • the analysis unit 12 confirms whether or not the first analysis result has been generated with all the second board data (step S24). If there is second substrate data for which the first analysis result has not been generated (step S24: No), the analysis unit 12 is one of the second substrate data for which the first analysis result has not been generated. Is selected, and the steps S21 to S23 described above are executed again using the selected second board data.
  • step S24 When the analysis unit 12 generates the first analysis result with all the second substrate data (step S24: Yes), the information of the substrate pattern that affects the EMC based on the first analysis result.
  • step S25 The first analysis result used in step S25 is, for example, the one shown in FIG. FIG. 10 is a diagram showing an example of a list of first analysis results generated by the analysis unit 12 according to the first embodiment. Differences corresponding to the numbers # 1 to # 7 in FIG. 10 and the numbers subsequent thereto and the presence / absence of influence on the EMC are generated and added each time step S23 described above is executed.
  • step S23 the difference corresponding to the number # 1 and the presence / absence of influence on the EMC are generated in step S23 executed for the first time, and the difference corresponding to the number # 2 and the presence / absence of influence on the EMC are generated for the second time. It is generated in the executed step S23.
  • step S25 the analysis unit 12 adds, for example, a predetermined score to each difference point having the presence / absence of influence on EMC as “present”, and determines that the presence / absence of influence on EMC is “absence”.
  • the points indicating the degree of influence on EMC are calculated for each difference point without adding the points, and this is used as the second analysis result.
  • the analysis unit 12 first adds, for example, a score of 1 to each of the three difference points of number # 1 (width of pattern A1, distance between pattern A1 and pattern A2, presence / absence of pattern B5).
  • the analysis unit 12 adds a score of 1 to each of the two difference points with the number # 2 (width of the pattern A2, width of the pattern A3). Similarly, a score of 1 is added to each of the differences between the numbers # 3, # 5, # 7, .... As a result, the second analysis result as shown in FIG. 11 is generated.
  • the “distance between the pattern A1 and the pattern A2” in the substrate element has a score of “+5” indicating the degree of influence on EMC, and Among them, the degree of influence on EMC is greatest.
  • the "distance between the pattern C5 and the pattern C6" in the substrate element has a score of "0" indicating the degree of influence on EMC, and the degree of influence on EMC is small. That is, when the “space between pattern A1 and pattern A2” changes, the EMC measurement result changes significantly, and even when the “space between pattern C5 and pattern C6” changes, the EMC measurement result does not change significantly.
  • the second analysis result includes the information of the board element that affects the EMC and the information of the board element that does not affect the EMC or that has a small effect on the EMC.
  • the board elements having a degree of influence greater than 0 are factors that change the EMC.
  • the analysis unit 12 identifies the board element that becomes the EMC variation factor by adding a predetermined number of points for each difference point with or without the influence on the EMC being “present”.
  • the first board pattern represented by the first board data and the second board pattern represented by one of the second board data are compared, and one board element is extracted as a difference point, the first board pattern
  • the first board pattern By checking the EMC evaluation data 112 corresponding to the data and the EMC evaluation data 112 corresponding to the second board data, it is possible to know whether or not the extracted board element affects the EMC.
  • the first board pattern represented by the first board data and the second board pattern represented by one of the second board data are compared and a plurality of board elements are extracted as a difference, the first board pattern is extracted.
  • each of the extracted board elements affects the EMC only by checking the EMC evaluation data 112 corresponding to the board data and the EMC evaluation data 112 corresponding to the second board data. Because, only one of the plurality of substrate elements may affect the EMC, or all substrate elements may affect the EMC. Further, it is possible that some of the plurality of substrate elements include one that improves the EMC and one that deteriorates the EMC. Therefore, the analysis unit 12 confirms whether or not there is an influence on the EMC for each substrate element included as a difference in one first analysis result, and if there is an influence, adds a score to each substrate element. Then, the degree of influence on EMC is calculated. When the number of the second substrate patterns to be compared with the first substrate pattern increases, the number of the board elements having a large influence on the EMC increases, and the board elements having a large influence on the EMC are narrowed down.
  • FIG. 12 is a flowchart showing an example of the operation of the evaluation unit 14 of the design support device 1 according to the first exemplary embodiment.
  • FIG. 12 shows an operation in which the evaluation unit 14 evaluates the pattern formed on the new board represented by the new board data 121.
  • the data acquisition unit 11 acquires the new board data 121 (step S31).
  • the evaluation unit 14 selects one of the board elements that affect the EMC and confirms whether the selected board element is included in the new board (step S32).
  • the board element that affects the EMC is one having a certain degree or more of "influence degree" among the difference points included in the second analysis result shown in FIG.
  • the evaluation unit 14 confirms whether or not the selected board element is included in the pattern formed on the new board.
  • step S33 If the selected board element is included in the new board (step S33: Yes), the evaluation unit 14 stores the selected board element as a board element that affects the EMC (step S34). After that, the evaluation unit 14 confirms whether or not the confirmation is completed for all the board elements that affect the EMC (step S35), and when the confirmation is not completed (step S35: No), returns to step S32. , EMC of other board elements are subjected to the processing of steps S32 to S34 described above.
  • step S33 If the determination in step S33 is “No”, the evaluation unit 14 executes step S35 without executing step S34.
  • the evaluation unit 14 generates and outputs the evaluation result of the new board when the confirmation is completed for all the board elements that affect the EMC (step S35: Yes) (step S36).
  • FIG. 13 shows an example of the evaluation result of the new board output by the evaluation unit 14 in step S36.
  • the evaluation unit 14 outputs, as an evaluation result, a table showing the locations and the degree of influence that may affect the EMC.
  • a place that may affect the EMC is a variation factor of the EMC and corresponds to the content of the substrate element of the second analysis result shown in FIG.
  • the degree of influence included in the evaluation result of the new substrate roughly indicates the value of the degree of influence included in the second analysis result.
  • the degree of influence included in the evaluation result of the new substrate is set to “large”, and the degree of influence included in the second analysis result is set to “large”.
  • the influence degree included in the evaluation result of the new substrate is set to “medium”.
  • the second threshold value ⁇ the first threshold value.
  • the degree of influence included in the evaluation result of the new substrate is set to “small”.
  • the designer When the evaluation result of the new board is as shown in FIG. 13, the designer, if the result of the EMC measurement of the electronic device incorporating the new board represented by the new board data 121 is non-conforming, as a countermeasure for EMC. It can be seen that it is effective to change the design of the new substrate and adjust the “space between the pattern A1 and the pattern A2”. Further, it can be seen that the adjustment of the “width of the pattern B1” and the “width of the pattern B4” is also effective. The designer can efficiently proceed with the EMC countermeasures by performing adjustment in order from the portion having the greatest influence.
  • the design support device 1 acquires the board data 111 and the EMC evaluation data 112 corresponding thereto as the learning data 110, and the acquired learning data 110 and the previously acquired learning data 110. Based on the learning data, the information of the board element that affects the EMC is generated and stored. The information on the board element that affects the EMC is the information included in the above-described second analysis result. Further, when the design support device 1 acquires new board data, the design support apparatus 1 obtains the information of the board element that influences the EMC included in the new board represented by the new board data, based on the information of the board element that affects the EMC. , Is output as the evaluation result of the new substrate. As a result, the designer of the new board can easily know the board elements that are likely to affect the EMC, and can efficiently design the board.
  • Each board represented by the board data 111 and the new board data 121 acquired by the data acquisition unit 11 of the design support device 1 may be a multilayer board.
  • the analysis unit 12 compares the pattern formed on the substrate represented by the substrate data 111 newly acquired by the data acquisition unit 11 with the pattern formed on the substrate represented by the previously acquired substrate data. The patterns formed in the intermediate layers are also compared.
  • Embodiment 2 The design support apparatus according to the second embodiment will be described.
  • the configuration of the design support device according to the second embodiment is the same as that of the design support device 1 according to the first embodiment (see FIG. 1).
  • the operation of the analysis unit 12 and the evaluation unit 14 of the setting support device according to the present embodiment is different from that of the design support device 1 according to the first embodiment. Therefore, the operations of the analysis unit 12 and the evaluation unit 14 will be described, and the description of the same parts as those in the first embodiment will be omitted.
  • FIG. 14 is a flowchart showing an example of the operation of the analysis unit 12 of the design support device 1 according to the second exemplary embodiment.
  • the flowchart shown in FIG. 14 is obtained by replacing steps S22, S23 and S25 of the flowchart shown in FIG. 5 with steps S22a, S23a and S25a. Since each processing of steps S21 and S24 shown in FIG. 14 is the same as each processing of steps S21 and S24 shown in FIG. 5, description thereof will be omitted.
  • the analysis unit 12 After executing step S21, the analysis unit 12 according to the second embodiment confirms the first EMC evaluation data corresponding to the first substrate pattern and the second EMC evaluation data corresponding to the second substrate pattern. Then, the influence of the difference between the two substrate patterns compared in step S21, that is, the difference between the first substrate pattern and the second substrate pattern on the EMC is specified (step S22a).
  • the analysis unit 12 specifically describes the difference between the board patterns extracted in step S21. To determine the content of the impact on EMC.
  • the width of the pattern B1 included in the first substrate pattern is wider than the width of the pattern B1 included in the second substrate pattern, and the interval between the patterns C1 and C2 included in the first substrate pattern is , Wider than the interval between the patterns C1 and C2 included in the second substrate pattern, and the EMC evaluation level indicated by the first EMC evaluation data is better than the EMC evaluation level indicated by the second EMC evaluation data.
  • the analysis unit 12 determines that the EMC evaluation level is improved when the width of the pattern B1 is wide and the interval between the pattern C1 and the pattern C2 is wide.
  • the analysis unit 12 affects the EMC by the difference between the two board patterns compared in step S21. Judge not to give.
  • step S22a the analysis unit 12 according to the second embodiment performs the first analysis showing the processing result of step S22a, that is, the content of the influence of the difference between the two substrate patterns compared in step S21 on the EMC.
  • a result is generated (step S23a).
  • FIG. 15 is a diagram illustrating an example of the first analysis result generated by the analysis unit 12 according to the second embodiment.
  • the "difference" shown in FIG. 15 shows how the substrate pattern changes. Further, “change of EMC” indicates how the EMC changes when the change shown in the “difference point” occurs in the substrate pattern.
  • step S24 When the analysis unit 12 according to the second embodiment generates the first analysis result with all the second substrate data (step S24: Yes), the analysis unit 12 performs steps S21, S22a, and S23a shown in FIG. A comparison process is performed using a plurality of first analysis results generated by repeated execution, and a second analysis result is generated based on the comparison results (step S25a).
  • the first analysis result used in step S25a is as shown in FIG. 16, for example.
  • FIG. 16 is a diagram showing an example of a list of first analysis results generated by the analysis unit 12 according to the second embodiment.
  • the "differences" and “EMC changes" corresponding to the numbers # 1 to # 7 and the numbers following this in FIG. 16 are generated and added each time the above-described step S23a is executed.
  • step S23a the difference corresponding to the number # 1 and the presence / absence of influence on the EMC are generated in step S23a executed for the first time, and the difference corresponding to the number # 2 and the presence / absence of influence on the EMC are generated for the second time. It is generated in the executed step S23a.
  • Each of the first analysis results included in the list of first analysis results illustrated in FIG. 16 represents how the EMC changes when one or more difference points change. ..
  • the first analysis result of the number # 1 (a) the width of the pattern A1 is expanded, (b) the interval between the pattern A1 and the pattern A2 is expanded, and (c) the pattern B5 is eliminated.
  • the EMC is improved.
  • this alone does not reveal which of the above changes (a) to (c) contributes to the improvement of EMC.
  • the first analysis result of the number # 6 shows that the EMC does not change when the interval between the pattern A1 and the pattern A2 increases and the pattern B5 disappears.
  • the first analysis result of the number # 6 shows that the EMC does not change even if the changes of the above (b) and (c) occur. Therefore, by comparing the first analysis result of number # 1 and the first analysis result of number # 6, when the change shown in (a) above occurs, that is, when the width of the pattern A1 is expanded. It can be seen that the EMC is improved. As described above, by comparing the first analysis results of the respective numbers, it is possible to specify how one difference affects EMC. Therefore, the analysis unit 12 compares the first analysis results generated by executing the above-described step S23a with each other to determine how each difference between the substrates affects the EMC. A second analysis result indicating the identified result is generated.
  • the influence of one difference on the EMC includes the case where the EMC does not change, that is, the case where the difference does not affect the EMC.
  • the case where the two first analysis results are compared to identify how one difference affects the EMC has been described, but the analysis unit 12 compares three or more first analysis results. By doing so, it may be possible to specify how one difference affects EMC.
  • the analysis unit 12 compares the result of identifying how one difference affects the EMC with one or more first analysis results so that the other difference is EMC. In some cases, the impact on
  • FIG. 17 is a diagram showing an example of the second analysis result generated by the analysis unit 12 according to the second embodiment.
  • the second analysis result shown in FIG. 17 includes the board element, the presence / absence of the influence, and the content of the influence.
  • the analysis unit 12 performs a comparison process using two or more first analysis results, and the effect of one difference on the EMC, that is, the effect of the EMC when one substrate element changes.
  • the second analysis result is updated each time it is determined whether or not the EMC is not affected.
  • the evaluation unit 14 according to the second embodiment operates according to the flowchart shown in FIG. 12, but in step S32, the processing is performed using the second analysis result having the content shown in FIG. That is, in step S32, the evaluation unit 14 selects one of the substrate elements whose “presence or absence of influence” item “present” shown in FIG. 17 is “present”, and the selected substrate element is formed into a pattern to be formed on a new substrate. Check if it is included. Further, in step S36, the evaluation unit 14 changes the "impact degree" of the evaluation result of the new board shown in FIG. 13 to "content of influence" instead of the evaluation result of the new board shown in FIG. Is output. The “content of influence” included in the evaluation result of the new board output by the evaluation unit 14 according to the second embodiment is the same as the “content of influence” included in the second analysis result shown in FIG. ..
  • the analysis unit 12 generates information indicating the content of the influence of the change of one board element on the EMC based on the learning data.
  • the information indicating the effect of the change of one board element on the EMC is the second analysis result described above.
  • the evaluation unit 14 acquires new board data
  • each of the board elements included in the new board represented by the new board data is based on the information indicating the influence of the change of one board element on the EMC.
  • Information on the influence on EMC is output as the evaluation result of the new substrate.
  • FIG. 18 is a diagram illustrating a configuration example of the design support device according to the third embodiment.
  • the design support device 1a according to the third embodiment replaces the analysis unit 12 and the evaluation unit 14 of the design support device 1 described in the first and second embodiments with an analysis unit 12a and an evaluation unit 14a, and further, a countermeasure plan generation unit.
  • the configuration has 15 added.
  • the operation of each component other than the analysis unit 12a, the evaluation unit 14a, and the countermeasure plan generation unit 15 is similar to that of the first and second embodiments, and thus the description thereof is omitted.
  • the data acquisition unit 11, the analysis unit 12a, and the storage unit 13 configure the machine learning device 20a according to the third embodiment.
  • the analysis unit 12a operates as a learning unit of the machine learning device 20a.
  • the analysis unit 12a performs the process performed by the analysis unit 12 according to the first embodiment and the process performed by the analysis unit 12 according to the second embodiment, and the second analysis result described in the first embodiment (see FIG. 11). (Refer to FIG. 17) and the second analysis result described in Embodiment 2 (see FIG. 17) are merged to generate a second analysis result. Specifically, the analysis unit 12a uses the “board element” and the “impact degree” included in the second analysis result according to the first embodiment shown in FIG. 11 and the second embodiment shown in FIG. A second analysis result having a configuration including “presence or absence of influence” and “content of influence” included in the second analysis result is generated. FIG.
  • FIG 19 is a diagram illustrating an example of the second analysis result generated by the analysis unit 12a of the design support device 1a according to the third embodiment. Since the “presence or absence of influence” can be known from the “degree of influence”, the second analysis result generated by the analysis unit 12a does not need to include “presence or absence of influence”.
  • the evaluation unit 14a performs the processes of steps S31 to S35 of the flowchart illustrated in FIG. 12, and if “Yes” is determined in step S35, the evaluation unit 14a is formed on the new substrate.
  • the information on the board element that influences the EMC included in the pattern is output to the countermeasure plan generating unit 15. It should be noted that the evaluation unit 14a does not output the information of the board element that influences the EMC when it is determined to be “Yes” in step S35, but is executed in step S34 when it is determined to be “Yes” in step S33.
  • Information about the board element that affects the EMC may be output to the countermeasure plan generating unit 15. In this case, when the evaluation unit 14a determines “Yes” in step S35, the evaluation unit 14a notifies the countermeasure plan generation unit 15 that the output of the information on the board element that affects the EMC has been completed.
  • the countermeasure plan generation unit 15 generates a countermeasure plan 132 for improving the EMC of the new substrate based on the information received from the evaluation unit 14a and the second analysis result stored in the storage unit 13. Output.
  • the evaluation unit 14a may include the top N pieces (N is 1 or more) having a large value of “influence degree” included in the second analysis result illustrated in FIG. 19 among the board elements indicated by the information received from the evaluation unit 14a. (Integer of), and the countermeasure plan 132 is generated based on the “content of influence” corresponding to the selected substrate element.
  • the countermeasure plan generation unit 15 selects “the interval between the pattern A1 and the pattern A2”, and the interval becomes narrow in this board element. Since the EMC is deteriorated, information indicating a change content that widens the interval between the pattern A1 and the pattern A2 is generated and output as the countermeasure plan 132.
  • the countermeasure plan generation unit 15 may determine the number N of board elements selected in the process of generating the countermeasure plan 132 based on the degree of influence of the board elements on the EMC. For example, in the countermeasure plan generating unit 15, there is a substrate element indicated by the information received from the evaluating unit 14a, in which the value of the “impact degree” included in the second analysis result is larger than a predetermined threshold value. If so, the value of N is determined as the first number. In addition, the countermeasure plan generating unit 15 includes, among the board elements indicated by the information received from the evaluating unit 14a, a board element whose “impact degree” included in the second analysis result is larger than a predetermined threshold value. If not, the value of N is determined to be a second number larger than the first number.
  • the EMC When there is an impact value greater than the threshold value, it is considered that the EMC is improved by taking measures at some locations in order from the greatest impact value. On the other hand, if there is no one whose influence level value is larger than the threshold value, it may be necessary to take measures to more places in order to improve the EMC. Therefore, in this example, the second number is made larger than the first number.
  • the countermeasure plan generating unit 15 is configured to generate the countermeasure plan 132, but the countermeasure plan generating unit 15 is deleted, and instead of the countermeasure plan generating unit 15, the evaluation unit 14a generates the countermeasure plan 132. It may be configured to generate.
  • the analysis unit 12a changes the EMC of one board element based on the learning data, as in the analysis unit 12 described in the second embodiment.
  • the information which shows the content of the influence on is generated.
  • the evaluation unit 14a extracts the board element included in the new board represented by the new board data, which influences the EMC, and the countermeasure plan generation unit 15 extracts the extracted board element.
  • a measure for improving the EMC of the new substrate is generated based on the information indicating the content of the influence of the change of one substrate element on the EMC.
  • a board element having a large influence on EMC is selected, and a countermeasure plan for the selected board element is generated. This allows the designer of the new board to know how to change the board element having a large influence when the EMC countermeasure is necessary, and to efficiently design the board. It will be possible.
  • FIG. 20 is a diagram illustrating a configuration example of the design support device according to the fourth embodiment.
  • the design support device 1b according to the fourth embodiment has a configuration in which the analysis unit 12 of the design support device 1 described in the first and second embodiments is replaced with an analysis unit 12a, and a design rule generation unit 16 is added.
  • the operation of each component other than the analysis unit 12a and the design rule generation unit 16 is the same as in the first and second embodiments, and thus the description thereof is omitted.
  • the analysis unit 12a of the design support device 1b according to the present embodiment is the same as the analysis unit 12a of the design support device 1a according to the third embodiment, so description thereof will be omitted.
  • the design rule generation unit 16 generates and outputs the board pattern design rule 133 based on the second analysis result held in the storage unit 13 when a predetermined condition is satisfied, for example.
  • the board pattern design rule 133 may be output by generating data indicating the design rule and outputting it as a file, or by displaying the design rule on a display device (not shown).
  • the above-mentioned predetermined condition corresponds to, for example, the case where an operation for instructing the start of design rule generation is received from a user who is a designer of a new board. Further, when the design support device 1b receives the learning data 110 and the analysis unit 12a performs the processing and the second analysis result held in the storage unit 13 is updated accordingly, the design rule generation unit 16 It may be determined that the predetermined condition is satisfied.
  • the design rule generation unit 16 selects, for example, a board element having a value of “influence degree” equal to or greater than a predetermined threshold value from “board elements” included in the second analysis result, and corresponds to the selected board element. Based on the “content of influence”, the board pattern design rule 133 is generated. If the second analysis result is shown in FIG. 19 and the threshold value is “+2”, the design rule generation unit 16 causes the “width of the pattern A1” and the “pattern A1 The “interval of the pattern A2" and the “width of the pattern A2” are selected, and the "width of the pattern A1 and the width of the pattern A2 are narrowed and the width of the pattern A1 is reduced based on the content of influence of each selected substrate element on the EMC. And the pattern A2 is widened, a design rule is generated and output as a board pattern design rule 133.
  • the configuration in which the design rule generation unit 16 is added to the design support device 1 described in the first and second embodiments and the analysis unit 12 is replaced with the analysis unit 12a has been described. Not limited. The configuration may be such that the design rule generation unit 16 is added to the design support device 1a described in the third embodiment.
  • the design support device 1b includes the design rule generation unit 16 that generates the board pattern design rule based on the second analysis result described in the third embodiment. This allows the board designer to confirm the board pattern design rule 133 when newly designing the board and proceed with the design while considering the influence on the EMC. As a result, the number of times of remodeling for EMC countermeasures is suppressed, and board design can be efficiently performed.
  • the analysis unit learns the patterns that affect the EMC
  • the patterns formed on the substrate are compared with each other.
  • the components mounted on the board may be compared with each other.
  • the analysis unit uses the component data, and when the components arranged at the same location on each board to be compared are different, the difference between the components is extracted as a difference point.
  • the change of the parts can be made an option when the EMC countermeasure is taken, and a more flexible countermeasure can be taken.
  • machine learning is performed using the board data 111 and the EMC evaluation data 112 to learn the pattern affecting the EMC, that is, the information of the pattern affecting the EMC is updated. ..
  • the data used for learning is not limited to this.
  • circuit diagram data may be used in addition to the board data 111 and the EMC evaluation data 112 described above.
  • the analysis unit (analysis units 12 and 12a) described in each embodiment first compares the circuit patterns corresponding to the respective substrates when comparing the substrate patterns formed on the two substrates. By confirming the drawing data, it is specified in which area of the substrate the pattern relating to which function is formed. Examples of the functions here include functions such as a power supply function, a communication function, and a control function. That is, the analysis unit confirms the circuit diagram data to identify in which area of the substrate the pattern that implements each function, such as the pattern of the power supply circuit, the pattern of the communication circuit, the pattern of the control circuit, is formed. .. After that, the analysis unit compares the patterns and extracts the differences for each region in which the patterns that realize the respective functions are formed.
  • the analysis unit By comparing the patterns formed in the first regions of the two substrates and extracting the differences, the patterns formed in the second regions of the two substrates are compared.
  • the process of extracting the difference point and the process of comparing the patterns formed in the respective third regions of the two substrates with each other to extract the difference point are performed and the extraction of the difference point is completed, The first analysis result obtained is generated.
  • the analysis unit described in each embodiment when using the circuit diagram data, the analysis unit described in each embodiment generates the first analysis result and the second analysis result for each area in which the pattern for realizing each function is formed. You may go. For example, when the pattern of the power supply circuit, the pattern of the communication circuit, and the pattern of the control circuit are formed on one substrate, the analysis unit determines the first analysis result and the second analysis result of the power supply circuit and the communication circuit. Of the first analysis result and the second analysis result of the control circuit, and the first analysis result and the second analysis result of the control circuit are generated.
  • the circuit classification for each function included in the circuit diagram can be utilized. Therefore, it becomes clear which function has a problem in the pattern to be realized, and it is possible to easily know the place where the countermeasure is required. Further, even if the boards are incorporated in different products, if patterns of circuits for realizing the same function are formed, the patterns are compared to obtain the first analysis result and the second analysis result. A learning operation to generate can be performed. That is, the analysis unit 12 can learn patterns that affect the EMC by using the board data 111, the EMC evaluation data 112, and the circuit diagram data for more products. As a result, it is possible to improve the evaluation accuracy when the evaluation unit described in each embodiment evaluates the new board data 121.
  • 1 design support device 11 data acquisition unit, 12, 12a analysis unit, 13 storage unit, 14, 14a evaluation unit, 15 countermeasure plan generation unit, 16 design rule generation unit, 20, 20a machine learning device, 110 learning data, 111 board data, 112 EMC evaluation data, 121 new board data, 131 new board evaluation results.

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Abstract

L'invention porte sur un dispositif d'aide à la conception (1) comprenant : une unité d'analyse (12) qui apprend des causes de variations de la compatibilité électromagnétique (CEM) d'un dispositif électronique dans lequel un substrat est incorporé, par analyse de données d'apprentissage (110) qui comprennent des données de substrat (111), comprenant des informations concernant le substrat et un motif de substrat formé sur le substrat, et qui comprennent également des données d'évaluation de CEM (112) représentant des résultats d'évaluation de la compatibilité électromagnétique ; et une unité d'évaluation (14) qui, lors de la réception de données de nouveau substrat (121) comprenant des informations concernant un motif de substrat formé sur un nouveau substrat, identifie des causes de variations de la compatibilité électromagnétique d'un dispositif électronique dans lequel le nouveau substrat est incorporé, sur la base des résultats d'apprentissage de causes de variations provenant de l'unité d'analyse (12), le nouveau substrat n'ayant pas encore été incorporé dans le dispositif électronique dans le but d'évaluer la compatibilité électromagnétique.
PCT/JP2018/041202 2018-11-06 2018-11-06 Dispositif d'aide à la conception, procédé d'aide à la conception et dispositif d'apprentissage automatique WO2020095362A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022034364A (ja) * 2020-08-18 2022-03-03 三菱電機株式会社 機械学習装置、設計支援装置、機械学習方法および設計支援方法
WO2022074750A1 (fr) * 2020-10-06 2022-04-14 富士通株式会社 Programme de génération de données d'apprentissage, procédé de génération de données d'apprentissage et dispositif de génération de données d'apprentissage
EP3992835A1 (fr) 2020-10-29 2022-05-04 Fujitsu Limited Programme d'apprentissage machine, procédé d'apprentissage machine et système informatique
WO2024122148A1 (fr) * 2022-12-06 2024-06-13 株式会社日立製作所 Système informatique, procédé de présentation d'élément de test et programme de présentation d'élément de test

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7409220B2 (ja) 2020-05-12 2024-01-09 富士通株式会社 推定プログラム、モデル生成プログラム、推定方法、モデル生成方法、推定装置およびモデル生成装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247207A (ja) * 1997-03-05 1998-09-14 Toshiba Corp 不具合部分推定システム
JP2002149720A (ja) * 2000-11-07 2002-05-24 Ricoh Co Ltd 電磁環境適合性検討支援装置と電磁環境適合性検討支援方法とコンピュータ読み取り可能な記録媒体
JP2005107870A (ja) * 2003-09-30 2005-04-21 Fujitsu Ltd 解析モデル作成装置
JP2012149933A (ja) * 2011-01-18 2012-08-09 Fujitsu Ltd 指標算出プログラム及び方法並びに設計支援装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012119512A (ja) * 2010-12-01 2012-06-21 Hitachi High-Technologies Corp 基板の品質評価方法及びその装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247207A (ja) * 1997-03-05 1998-09-14 Toshiba Corp 不具合部分推定システム
JP2002149720A (ja) * 2000-11-07 2002-05-24 Ricoh Co Ltd 電磁環境適合性検討支援装置と電磁環境適合性検討支援方法とコンピュータ読み取り可能な記録媒体
JP2005107870A (ja) * 2003-09-30 2005-04-21 Fujitsu Ltd 解析モデル作成装置
JP2012149933A (ja) * 2011-01-18 2012-08-09 Fujitsu Ltd 指標算出プログラム及び方法並びに設計支援装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022034364A (ja) * 2020-08-18 2022-03-03 三菱電機株式会社 機械学習装置、設計支援装置、機械学習方法および設計支援方法
JP7357593B2 (ja) 2020-08-18 2023-10-06 三菱電機株式会社 機械学習装置、設計支援装置、機械学習方法および設計支援方法
WO2022074750A1 (fr) * 2020-10-06 2022-04-14 富士通株式会社 Programme de génération de données d'apprentissage, procédé de génération de données d'apprentissage et dispositif de génération de données d'apprentissage
JP7416279B2 (ja) 2020-10-06 2024-01-17 富士通株式会社 訓練データ生成プログラム、訓練データ生成方法及び訓練データ生成装置
EP3992835A1 (fr) 2020-10-29 2022-05-04 Fujitsu Limited Programme d'apprentissage machine, procédé d'apprentissage machine et système informatique
US11669662B2 (en) 2020-10-29 2023-06-06 Fujitsu Limited Machine learning method and computing system
WO2024122148A1 (fr) * 2022-12-06 2024-06-13 株式会社日立製作所 Système informatique, procédé de présentation d'élément de test et programme de présentation d'élément de test

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