WO2020093434A1 - 显示驱动电路以及显示装置 - Google Patents

显示驱动电路以及显示装置 Download PDF

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Publication number
WO2020093434A1
WO2020093434A1 PCT/CN2018/115780 CN2018115780W WO2020093434A1 WO 2020093434 A1 WO2020093434 A1 WO 2020093434A1 CN 2018115780 W CN2018115780 W CN 2018115780W WO 2020093434 A1 WO2020093434 A1 WO 2020093434A1
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WIPO (PCT)
Prior art keywords
signal
circuit
output
scan
control
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PCT/CN2018/115780
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English (en)
French (fr)
Inventor
李汶欣
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/292,358 priority Critical patent/US20200143727A1/en
Publication of WO2020093434A1 publication Critical patent/WO2020093434A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present application relates to the field of display technology, in particular to a display driving circuit and a display device.
  • Display device such as TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display ), Has become an indispensable product in modern IT and video products. With the requirement of large size and high resolution of the display device, there are more and more driving circuits of the display device. Therefore, in order to ensure the charging time of the display pixels on each line of signal line under the condition that the scanning time of one frame of picture is fixed , Using pre-charge technology to charge the display pixels in advance.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • the embodiments of the present application provide a display driving circuit and a display device, which realize that during the display driving process, the display pixels of each row of signal lines can be guaranteed to be precharged.
  • An embodiment of the present application provides a display driving circuit, including a plurality of scanning signal output circuits.
  • the plurality of scanning signal output circuits output scanning driving signals to corresponding row signal lines according to control signals of a timing control circuit to drive row signals Online display unit;
  • Each scan signal output circuit includes a signal output control circuit, and by the control of the signal output control circuit, when a scan drive signal is output for a row signal line of a preset row, the output duration of the scan drive signal is extended.
  • the row signal lines of the preset row are a preset number of row signal lines starting from the first row.
  • the signal output control circuit includes:
  • the signal trigger circuit includes two input ports and one output port, the two input ports respectively receive the scan driving signal and the first control signal, and output the scan driving signal when the first control signal meets the trigger condition;
  • the first logic circuit includes two input ports and an output port. One input port is connected to the output port of the signal trigger circuit, and the other input port receives a second control signal.
  • the logic unit outputs the After performing a logical operation on the scan drive signal and the second control signal, the calculated scan drive signal is output.
  • the first logic circuit is a logical OR gate.
  • the first logic circuit is a logical AND gate.
  • the signal trigger circuit includes at least one trigger integrated circuit, and the trigger integrated circuit outputs the received scan driving signal when the first control signal is received and the first control signal is a rising edge.
  • the signal trigger circuit is a D flip-flop.
  • the second control signal is an enable signal, which is set to control the output of the scan driving signal.
  • the first control signal is a clock signal.
  • the received scan drive signal is a frame start signal; in the signal output control circuit connected to the row signal line of the remaining rows, the received scan drive signal is The previous signal outputs the scan drive signal output by the signal trigger circuit in the control circuit.
  • each of the scan signal output circuits further includes a second logic circuit.
  • the second logic circuit receives the third control signal and the scan drive signal, and performs a logical operation on the third control signal and the scan drive signal to output To signal trigger circuit.
  • the third control signal is a horizontal scanning direction control signal.
  • An embodiment of the present application further provides a display driving circuit, which includes a plurality of scanning signal output circuits that output scanning driving signals to corresponding row signal lines according to the control signals of the timing control circuit to drive The display unit on the row signal line; the plurality of scan signal output circuits are correspondingly connected to the row signal line, and the scan signal output circuit connected to the row signal line starting from the first row is the first scan signal output circuit, and the remaining rows The scan signal output circuit connected by the row signal line is the second scan signal output circuit; and
  • Each scan signal output circuit includes a signal output control circuit, and by the control of the signal output control circuit, when the scan signal output circuit outputs the scan drive signal to the row signal line, the scan drive signal output by the first scan signal output circuit Is longer than the scan driving signal output by the second scan signal output circuit.
  • the signal output control circuit includes:
  • the signal trigger circuit includes two input ports and one output port, the two input ports respectively receive the scan driving signal and the first control signal, and output the scan driving signal when the first control signal meets the trigger condition;
  • the first logic circuit includes two input ports and an output port. One input port is connected to the output port of the signal trigger circuit, and the other input port receives a second control signal.
  • the logic unit outputs the After performing a logical operation on the scan drive signal and the second control signal, the calculated scan drive signal is output.
  • the first logic circuit is a logical OR gate.
  • the second logic circuit is a logical AND gate.
  • An embodiment of the present application also provides a display device, including:
  • the display drive device is configured to drive the display unit to perform display.
  • the display drive device includes a plurality of scan signal output circuits that output scan drive signals to corresponding rows according to control signals of the timing control circuit A signal line to drive the display unit on the row signal line; each scan signal output circuit includes a signal output control circuit, and by the control of the signal output control circuit, a scan drive signal is output on the row signal line of the preset row Time, the output duration of the scan drive signal is extended.
  • the display drive device includes a drive controller, a scan drive circuit, and a data drive circuit.
  • the drive controller outputs a drive control signal to control the scan drive circuit and the data drive circuit to output corresponding drive signals to drive the The display unit works.
  • the scan driving circuit outputs the scan driving signal, and outputs to the row signal line through the scan signal output circuit.
  • the drive controller outputs a control signal, and the output control signal is output to the scan signal output circuit to control the output of the scan drive signal.
  • the display pixels on the row signal lines of the preset rows that cannot be precharged can extend the charging time, thereby ensuring the charging effect of the display pixels on each row and row signal lines , which in turn makes the screen display even.
  • FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of functional modules of a display driving circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a logical structure of a display driving circuit according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of signal waveforms of a display driving circuit according to an embodiment of the present application for scanning and driving row signal lines;
  • FIG. 5 is a schematic diagram of a logical structure of a display driving circuit according to another embodiment of the present application.
  • first”, “second”, etc. are for descriptive purposes only, and cannot be understood as instructions or hints Its relative importance or implicitly indicates the number of technical features indicated.
  • the features defined with “first” and “second” may include at least one of the features either explicitly or implicitly.
  • the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of those skilled in the art to realize. When the combination of technical solutions contradicts or cannot be realized, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.
  • an embodiment of the present application proposes a new type of display driving scheme to ensure the charging of all display pixels of the display device during the display driving process The effect is to achieve uniform brightness of the display device.
  • FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • the display device includes a substrate 10 and a display driving device 11. specifically,
  • a display area 101 and a non-display area 102 are formed on the substrate 10; wherein, the display area 101 includes a plurality of display units, and the plurality of display units may be arranged in a matrix structure of rows and columns, of course, it is not limited to a matrix arrangement structure, but may be other Arrangement.
  • Each display unit includes at least one display pixel.
  • the display area 101 is further formed with a signal line and a switching device arranged crosswise.
  • the signal line may specifically include a first signal line and a second signal line electrically connected to the switching device.
  • the switching device When the scan driving signal on a signal line is activated, the switching device is activated. At this time, the display pixel will receive the data signal from the second signal line through the activated switching device, and light up according to the data signal.
  • the above switching device may include but is not limited to TFT (Thin Film Transistor (thin film transistor), for example, can also include field effect transistors, transistors, etc.
  • the above-mentioned first signal line and second signal line may also be referred to as scan lines and data lines.
  • the above display driving device may specifically include a driving controller 11, a scanning driving circuit 12, and a data driving circuit 13, wherein the driving controller 11 outputs a driving control signal to control the scanning driving circuit 12 and the data driving circuit 13 to output corresponding driving signals to drive Display pixels work.
  • the scan drive circuit 12 outputs the scan drive signal line by line, and if the display pixels of the current line receive the scan drive signal, the corresponding switching device starts to work.
  • the display pixels of the current row will receive the data signal output by the data driving circuit 13 through the activated switching device, and the data signals are transmitted to the display pixels of the current row through the activated switching device to charge the display pixels of the current row, thereby driving the current The display pixels of the row light up.
  • the display driving device completes the driving of the display pixels of all rows row by row or interlace, the update of one frame of picture is completed.
  • the display driving device of the embodiment of the present application uses a precharge technology, that is, while controlling the row driving circuit 12 to output the row driving signal to the current row signal line, it also outputs the row driving signal to another row signal line (hereinafter referred to as: Precharged row signal line), so that the switching device on the current row signal line and the switching device on the precharged row signal line can start working, and then the data signal is transmitted to the current row signal line through the activated switching device Display pixels and display pixels on the pre-charged row signal lines. At this time, the data signal charges the display pixels on the signal line of the current row. When the charging voltage reaches the driving voltage of the display pixel, the display pixels of the current row are driven to light.
  • Precharged row signal line another row signal line
  • the rest of the data signals pre-charge the display pixels on the pre-charged line signal line, that is, the voltage on the display pixels on the pre-charged line signal line reaches a certain value (but it is not enough to drive the display pixels of the current line Bright), when the scan driving circuit 12 scans to the pre-charged row signal line, as long as a voltage signal with a smaller amplitude is provided, the charging voltage on the pre-charged row signal line can quickly reach the display pixel point Bright voltage, so as to quickly drive the display pixels to light up.
  • the response speed of the display pixels can be improved, when performing the display driving, the first line or several lines of the line scan often cannot be pre-charged, resulting in a row signal line that cannot be pre-charged
  • the display pixels on the display have a poor charging effect, which in turn makes the screen display uniform.
  • FIG. 2 is a schematic diagram of functional modules of a display driving circuit according to an embodiment of the present application.
  • the display driving circuit proposed by the technical solution of the present application includes: a plurality of scanning signal output circuits 120, each scanning signal output circuit 120 is electrically connected to the driving controller 11 for receiving the control signal output by the driving controller 11, and according to the driving The control signal output by the controller 11 outputs a scan driving signal to the row signal line to scan the display unit on the row signal line.
  • Each scan signal output circuit 120 includes a signal output control circuit 121, and under the control of the signal control unit 121, when a scan driving signal is output for a row signal line of a preset row, the output duration of the scan driving signal is extended.
  • the plurality of scan signal output circuits 120 are connected to the row signal lines in one-to-one correspondence, and the scan signal output circuit connected to the row signal lines of the preset row is defined as the first scan signal output circuit, and the row signal lines of the remaining rows
  • the scan signal output circuit is a second scan signal output circuit.
  • the display pixels on the row signal lines of the preset rows that cannot be precharged can extend the charging time, thereby ensuring the charging effect of the display pixels on each row and row signal lines , which in turn makes the screen display even.
  • control signals output by the drive controller may include a frame start signal STV, a clock signal CPV, a scanning direction control signal L / R, an enable signal OE, and so on.
  • the frame start signal STV is the start signal for the start of a frame.
  • the scanning direction control signal L / R controls the line scanning direction, for example, from top to bottom and bottom to top.
  • the enable signal OE is used to control the output of the scan drive signal. For example, when the OE signal is at a high level, the scan drive signal is output, and when the OE signal becomes a low level, the scan drive signal stops outputting.
  • Each scan signal output circuit 120 is controlled to output a scan drive signal to the corresponding row signal line by the control signal output by the drive controller.
  • FIG. 3 is a schematic diagram of a logical structure of a display driving circuit according to an embodiment of the present application.
  • the signal output control circuit 121 includes:
  • the signal trigger circuit 1211 includes two input ports and an output port.
  • the two input ports respectively receive a scan driving signal and a first control signal, and output a scan driving signal when the first control signal meets the trigger condition;
  • the first logic circuit 1212 includes two input ports and one output port, one input port and the output port of the signal trigger circuit, and the other input port receives the second control signal, and the first logic circuit drives the scan of the signal trigger circuit output After performing logical operation on the signal and the second control signal, the calculated scan driving signal is output.
  • the signal trigger circuit 1211 includes at least one trigger integrated circuit, such as a D flip-flop.
  • the signal trigger circuit 1211 outputs the received scan driving signal when the first control signal is received and the first control signal meets the trigger condition.
  • the trigger condition of the D flip-flop is a rising edge trigger, that is, when the first control signal is received and the first control signal is at the rising edge, the trigger is triggered and the scan driving signal is output.
  • the signal trigger circuit may further include other triggers that implement the same function, and the trigger may use other trigger conditions, such as falling edge triggering and the like.
  • the first logic circuit 1212 includes at least one logic gate circuit, for example, a logic AND gate, a logic OR gate, a NAND gate, a NOR gate, and so on.
  • a logic gate circuit performs logical operation on the received scan driving signal and the second control signal signal and outputs the signal, thereby controlling the logic level and output duration of the scan driving signal.
  • the first logic circuit 1212 is a logical OR gate, and in the signal output control circuit 121 connected to the row signal line of the remaining row, the first logic circuit 1212 is the logical AND gate.
  • the first logic circuit of different logic circuits is provided to control the output duration of the scan drive signal, so that the display pixels on the row signal lines of the preset rows that cannot be precharged can extend the charging time, thereby ensuring that each row of row signal lines The charging effect of the display pixels can further achieve uniform display of the screen.
  • the received scan driving signal is the frame start signal STV; in the signal output control circuit 121 connected to the row signal line of the remaining rows, the received scan
  • the drive signal is a scan drive signal output by the signal trigger circuit 1211 in the previous signal output control circuit 121.
  • the row signal lines of the preset row are a preset number of row signal lines starting from the first row.
  • the preset number is 4, for example.
  • the preset number may be 1 or 2, or other numbers.
  • the preset number is mainly set according to the number of row signal lines that cannot be precharged.
  • FIG. 4 is a schematic diagram of signal waveforms of the display driving circuit according to an embodiment of the present application for scanning and driving row signal lines.
  • the drive controller 11 outputs a frame start signal STV, and controls the scan drive circuit 12 to perform line scanning through the frame start signal STV.
  • the drive controller 11 controls the scan drive circuit 12 to output a scan drive signal, and the switching device on the line signal line for progressive or interlaced drive starts from the first line, and the data drive circuit 13
  • the output charging signal charges the display pixels on the row signal line through the switching device that starts working.
  • the scan driving circuit 12 charges the display pixels on the row signal line of the first row
  • the scan driving signal also drives the switching device on the row signal line of the fifth row to start operation, so the charging signal output by the data driving circuit 13
  • the display pixels on the 5th row signal line are also precharged.
  • the signal output control circuit 121 connected to the row signal line of the preset row performs a logical OR operation between the scan driving signal output by the signal trigger circuit 1211 and the OE signal, and then outputs the operation After the scan drive signal. Therefore, in the scan drive signal output by the signal output control circuit connected to the row signal line of the preset row, the output duration starts from the rising edge of the clock signal CKV and continues until the rising edge of the next clock signal CKV ends. For example, the duration of the scan drive signal output to the row signal line G1 of the first row is t1.
  • the scan drive signal output from the signal trigger circuit 1211 and the OE signal perform a logical AND operation, and then output the calculated scan drive signal. Therefore, in the scan driving signal output by the signal output control circuit connected to the row signal line of the other row, the output duration thereof is consistent with the duration of the high level of the OE signal. That is, if the OE signal outputs a high level, the scan drive signal is output; if the OE signal outputs a low level, the scan drive signal is stopped. For example, the duration of the scan drive signal output to the row signal line G5 of the fifth row is t2.
  • the scan drive signal output from the signal trigger circuit 1211 performs the logical OR operation with the OE signal, and then outputs the calculated scan drive signal.
  • the controller 11 controls the scan drive circuit 12 to scan and drive the row signal lines of other rows, so that when the data drive circuit 13 precharges the row signal lines of other rows, the output duration of the scan drive signal output by the scan drive circuit 12 and the OE The high level of the signal lasts for the same duration. For example, the duration of the scan driving signal output to the row signal line G5 of the fifth row during precharge is t3.
  • the technical solution is used to extend the start-up time of the switching device on the row signal line of the preset row, thereby extending the display pixels of the preset row
  • the charging time further ensures the display effect of the display pixels of all the row signal lines.
  • FIG. 5 is a schematic diagram of a logical structure of a display driving circuit according to another embodiment of the present application.
  • Each scan signal output circuit 120 further includes a second logic circuit 122.
  • the second logic circuit 122 receives the third control signal and the scan driving signal, and performs a logical operation on the third control signal and the scan driving signal before outputting to the signal trigger Circuit 1211.
  • the second logic circuit 122 includes at least one logic gate circuit, such as a logical AND gate, a logical OR gate, a NAND gate, a NOR gate, and so on.
  • the third control signal is the line scanning direction control signal L / R.
  • the line scan control signal is used to control whether to start scanning from the first line or the last line when the frame scanning starts. For example, when L / R is high, scanning starts from the first line, and when L / R is low, scanning starts from the last line.

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Abstract

一种显示驱动电路及显示装置，显示驱动电路包括多个扫描信号输出电路，该多个扫描信号输出电路根据时序控制电路的控制信号，输出扫描驱动信号至对应的行信号线，来驱动行信号线上的显示单元；每一扫描信号输出电路均包括信号输出控制电路，且通过信号输出控制电路的控制，在为预设行的行信号线输出扫描驱动信号时，对该扫描驱动信号的输出时长进行延长。

Description

显示驱动电路以及显示装置
相关申请
本申请要求2018年11月5日申请的，申请号为201821813112.9，名称为“显示驱动电路以及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，尤其涉及显示驱动电路及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
显示装置，例如TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器 ），已经成为了现代IT、视讯产品中不可缺少的产品。随着显示装置大尺寸、高解析度的要求，显示装置的驱动线路越来越多，由此在一帧画面的扫描时间固定的情况下，为了保证每一行信号线上的显示像素的充电时间，采用预充电技术，提前给显示像素充电。
但是，目前的预充电技术无法保证每一行信号线的显示像素均能实现预充电，亟待改进。
申请内容
本申请实施例通过提供一种显示驱动电路及显示装置，实现了显示驱动过程中，能保证每一行信号线的显示像素均能实现预充电。
本申请实施例提供了一种显示驱动电路，包括多个扫描信号输出电路，该多个扫描信号输出电路根据时序控制电路的控制信号，输出扫描驱动信号至对应的行信号线，来驱动行信号线上的显示单元；以及
每一扫描信号输出电路均包括信号输出控制电路，且通过所述信号输出控制电路的控制，在为预设行的行信号线输出扫描驱动信号时，对该扫描驱动信号的输出时长进行延长。
可选地，所述预设行的行信号线为首行开始的预设数量的行信号线。
可选地，所述信号输出控制电路包括：
信号触发电路，包括两输入端口和一输出端口，所述两输入端口分别接收扫描驱动信号及第一控制信号，并在第一控制信号满足触发条件时，输出扫描驱动信号；以及
第一逻辑电路，包括两输入端口和一输出端口，一输入端口与所述信号触发电路的输出端口连接，另一输入端口接收第二控制信号，所述逻辑单元将所述信号触发电路输出的扫描驱动信号与所述第二控制信号进行逻辑运算后，输出运算后的扫描驱动信号。
可选地，与预设行的行信号线连接的信号输出控制电路中，第一逻辑电路为逻辑或门。
可选地，与其余行的行信号线连接的信号输出控制电路中，第一逻辑电路为逻辑与门。
可选地，所述信号触发电路包括至少一触发集成电路，所述触发集成电路在接收到第一控制信号，且第一控制信号为上升沿时，将接收到的扫描驱动信号输出。
可选地，所述信号触发电路为D触发器。
可选地，所述第二控制信号为使能信号，设置为控制扫描驱动信号的输出。
可选地，所述第一控制信号为时钟信号。
可选地，与首行的行信号线连接的信号输出控制电路中，接收的扫描驱动信号为帧起始信号；其余行的行信号线连接的信号输出控制电路中，接收的扫描驱动信号为前一信号输出控制电路中信号触发电路输出的扫描驱动信号。
可选地，所述每一扫描信号输出电路还包括第二逻辑电路，该第二逻辑电路接收第三控制信号和扫描驱动信号，并对第三控制信号和扫描驱动信号进行逻辑运算后，输出至信号触发电路。
可选地，所述第三控制信号为行扫描方向控制信号。
本申请实施例还提供一种显示驱动电路，其中，包括多个扫描信号输出电路，该多个扫描信号输出电路根据时序控制电路的控制信号，输出扫描驱动信号至对应的行信号线，来驱动行信号线上的显示单元；所述多个扫描信号输出电路与行信号线对应连接，且与首行开始4行的行信号线连接的扫描信号输出电路为第一扫描信号输出电路，其余行的行信号线连接的扫描信号输出电路为第二扫描信号输出电路；以及
每一扫描信号输出电路均包括信号输出控制电路，且通过所述信号输出控制电路的控制，在扫描信号输出电路对行信号线输出扫描驱动信号时，第一扫描信号输出电路输出的扫描驱动信号的时长比第二扫描信号输出电路输出的扫描驱动信号的时长更长。
可选地，所述信号输出控制电路包括：
信号触发电路，包括两输入端口和一输出端口，所述两输入端口分别接收扫描驱动信号及第一控制信号，并在第一控制信号满足触发条件时，输出扫描驱动信号；以及
第一逻辑电路，包括两输入端口和一输出端口，一输入端口与所述信号触发电路的输出端口连接，另一输入端口接收第二控制信号，所述逻辑单元将所述信号触发电路输出的扫描驱动信号与所述第二控制信号进行逻辑运算后，输出运算后的扫描驱动信号。
可选地，所述第一扫描信号输出电路中的信号输出控制电路中，第一逻辑电路为逻辑或门。
可选地，所述第二扫描信号输出电路中的信号输出控制电路中，第二逻辑电路为逻辑与门。
本申请实施例还提供一种显示装置，包括：
基板，所述基板上形成显示区和非显示区，所述显示区内设置多个显示单元；以及
显示驱动装置，设置为驱动所述显示单元进行显示，所述显示驱动装置包括多个扫描信号输出电路，该多个扫描信号输出电路根据时序控制电路的控制信号，输出扫描驱动信号至对应的行信号线，来驱动行信号线上的显示单元；每一扫描信号输出电路均包括信号输出控制电路，且通过所述信号输出控制电路的控制，在为预设行的行信号线输出扫描驱动信号时，对该扫描驱动信号的输出时长进行延长。
可选地，所述显示驱动装置包括驱动控制器、扫描驱动电路、数据驱动电路，所述驱动控制器输出驱动控制信号，来控制扫描驱动电路和数据驱动电路输出对应的驱动信号，驱动所述显示单元工作。
可选地，所述扫描驱动电路输出所述扫描驱动信号，并通过所述扫描信号输出电路输出至行信号线。
可选地，所述驱动控制器输出控制信号，该输出控制信号输出至所述扫描信号输出电路，来控制扫描驱动信号的输出。
本申请实施例通过对扫描驱动信号输出时长的控制，使得无法进行预充电的预设行的行信号线上的显示像素可以延长充电时间，从而保证每一行行信号线上的显示像素的充电效果，进而使得画面显示均匀。
附图说明
图1是本申请一实施例的显示装置的结构示意图；
图2是本申请一实施例的显示驱动电路的功能模块示意图；
图3为本申请一实施例的显示驱动电路的逻辑结构示意图；
图4是本申请一实施例的显示驱动电路进行行信号线扫描驱动的信号波形示意图；
图5是本申请另一实施例的显示驱动电路的逻辑结构示意图。
具体实施方式
为了更好的理解上述技术方案，下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请实施例为解决显示驱动方案无法满足显示装置的大尺寸、高解析度的要求的技术问题，提出一种新型的显示驱动方案，在显示驱动过程中，保证显示装置所有的显示像素的充电效果，实现显示装置的亮度均匀。
为方便本申请实施方案的理解，在描述本申请具体实施方案之前，先简单介绍一实施例结构的显示装置的驱动原理。
参照图1，图1是本申请一实施例的显示装置的结构示意图。该显示装置包括基板10、显示驱动装置11。具体地，
基板10上形成有显示区101和非显示区102；其中，显示区101内包括多个显示单元，该多个显示单元可呈行列分布的矩阵结构，当然不限于矩阵排列结构，也可以为其他排列方式。每个显示单元中包括至少一显示像素。
可选地，该显示区101还形成有交叉设置的信号线路以及开关器件，信号线路具体可包括与开关器件电性连接的第一信号线和第二信号线，该开关器件用于接收到第一信号线上的扫描驱动信号时，启动开关器件，此时显示像素将通过启动的开关器件从第二信号线上接收数据信号，并根据数据信号点亮。具体地，上述开关器件可包括但不限于TFT（Thin Film Transistor，薄膜晶体管），例如还可包括场效应管、三极管等等。上述第一信号线和第二信号线还可称为扫描线和数据线。
上述显示驱动装置具体可包括驱动控制器11、扫描驱动电路12、数据驱动电路13，其中驱动控制器11输出驱动控制信号，来控制扫描驱动电路12和数据驱动电路13输出对应的驱动信号，驱动显示像素工作。具体地，扫描驱动电路12逐行输出扫描驱动信号，若当前行的显示像素接收到该扫描驱动信号时，对应的开关器件启动工作。当前行的显示像素将通过启动的开关器件接收数据驱动电路13输出的数据信号，该数据信号通过启动的开关器件传输至当前行的显示像素，以对当前行的显示像素进行充电，从而驱动当前行的显示像素点亮。以此类推，显示驱动装置逐行或隔行完成所有行显示像素的驱动后，完成一帧画面的更新。
本申请实施例的显示驱动装置采用预充电技术，即在控制行驱动电路12输出行驱动信号至当前行信号线的同时，还输出行驱动信号至其他的另一行信号线（下文称之为：预充电的行信号线），从而使得当前行信号线上的开关器件和预充电的行信号线上的开关器件均能启动工作，进而数据信号通过启动的开关器件传输至当前行信号线上的显示像素和预充电的行信号线上的显示像素。此时，数据信号对当前行信号线上的显示像素进行充电，当充电电压达到显示像素的驱动电压时，则驱动当前行的显示像素点亮。同时，其余的数据信号对预充电的行信号线上的显示像素进行预充电，即预充电的行信号线上的显示像素上的电压达到一定的值（但是还不够驱动当前行的显示像素点亮），在扫描驱动电路12扫描至该预充电的行信号线时，只要提供较少幅值的电压信号，即可使得该预充电的行信号线上的充电电压快速达到能够驱动显示像素点亮的电压，从而达到快速驱动显示像素点亮的目的。
上述显示驱动装置采用预充电技术时，虽然能提高显示像素的反应速度，但是在进行显示驱动时，往往行扫描的最初一行或几行无法实现预充电，从而导致无法进行预充电的行信号线上的显示像素的充电效果较差，进而使得画面显示均匀。
对此，参照图2，图2是本申请一实施例的显示驱动电路的功能模块示意图。本申请技术方案提出的显示驱动电路包括：多个扫描信号输出电路120，每个扫描信号输出电路120均与驱动控制器11电连接，用于接收驱动控制器11输出的控制信号，并根据驱动控制器11输出的控制信号输出扫描驱动信号至行信号线，来对驱动行信号线上的显示单元进行扫描。每一扫描信号输出电路120均包括信号输出控制电路121，通过该信号控制单元121的控制，在为预设行的行信号线输出扫描驱动信号时，对该扫描驱动信号的输出时长进行延长。
具体地，上述多个扫描信号输出电路120与行信号线一一对应连接，定义与预设行的行信号线连接的扫描信号输出电路为第一扫描信号输出电路，其余行的行信号线连接的扫描信号输出电路为第二扫描信号输出电路。通过信号控制单元121的控制，使得第一扫描信号输出电路输出的扫描驱动信号的时长比第二扫描信号输出电路输出的扫描驱动信号的时长要长。
本申请实施例通过对扫描驱动信号输出时长的控制，使得无法进行预充电的预设行的行信号线上的显示像素可以延长充电时间，从而保证每一行行信号线上的显示像素的充电效果，进而使得画面显示均匀。
可选地，上述驱动控制器输出的控制信号可包括帧起始信号STV、时钟信号CPV、扫描方向控制信号L/R、使能信号OE等等。其中帧起始信号STV为一帧画面开始的起始信号。扫描方向控制信号L/R控制行扫描方向，例如从上到下、从下到上。使能信号OE用于控制扫描驱动信号的输出，例如当OE信号为高电平，扫描驱动信号输出，当OE信号变为低电平时，扫描驱动信号停止输出。通过驱动控制器输出的控制信号，来控制每个扫描信号输出电路120输出扫描驱动信号至对应的行信号线。
可选地，在一实施例中，参照图3，图3为本申请一实施例的显示驱动电路的逻辑结构示意图。上述信号输出控制电路121包括：
信号触发电路1211，包括两输入端口和一输出端口，所述两输入端口分别接收扫描驱动信号及第一控制信号，并在第一控制信号满足触发条件时，输出扫描驱动信号；
第一逻辑电路1212，包括两输入端口和一输出端口，一输入端口与信号触发电路的输出端口，另一输入端口接收第二控制信号，所述第一逻辑电路将信号触发电路输出的扫描驱动信号与所述第二控制信号进行逻辑运算后，输出运算后的扫描驱动信号。
具体地，该信号触发电路1211包括至少一触发集成电路，例如D触发器。该信号触发电路1211在接收到第一控制信号，且第一控制信号满足触发条件时，将接收到的扫描驱动信号输出。以D触发器为例，该D触发器的触发条件为上升沿触发，即当接收到第一控制信号，且第一控制信号处于上升沿的时候触发并将扫描驱动信号输出。可以替换的，该信号触发电路还可以包括实现相同功能的其他触发器，以及触发器可以采用其他的触发条件，例如下降沿触发等等。
第一逻辑电路1212包括至少一逻辑门电路，例如逻辑与门、逻辑或门、与非门、非门等等。通过逻辑门电路对接收到的扫描驱动信号和第二控制信号信号进行逻辑运算后并输出，从而控制扫描驱动信号的逻辑电平和输出时长。
进一步地，与预设行的行信号线连接的信号输出控制电路121中，第一逻辑电路1212为逻辑或门，与其余行的行信号线连接的信号输出控制电路121中，第一逻辑电路1212为逻辑与门。通过设置不同逻辑电路的第一逻辑电路，来控制扫描驱动信号的输出时长，使得无法进行预充电的预设行的行信号线上的显示像素可以延长充电时间，从而保证每一行行信号线上的显示像素的充电效果，进而实现画面显示均匀。
可选地，与首行的行信号线连接的信号输出控制电路121中，接收的扫描驱动信号为帧起始信号STV；其余行的行信号线连接的信号输出控制电路121中，接收的扫描驱动信号为前一信号输出控制电路121中信号触发电路1211输出的扫描驱动信号。通过如此设置，使得驱动控制器11只需要输出一扫描驱动信号，通过扫描驱动信号的移位传输，就实现了所有行的行信号线的扫描驱动，不但节省了驱动线路，而且还简化了驱动逻辑。
进一步地，上述预设行的行信号线为首行开始的预设数量的行信号线。一实施例中，该预设数量例如为4。当然，该预设数量可以为1，也可以为2，还可以为其他的数。该预设数量主要根据不能进行预充电的行信号线数量来设置。
结合参照图3和图4，图4是本申请一实施例的显示驱动电路进行行信号线扫描驱动的信号波形示意图。
驱动控制器11输出帧起始信号STV，通过帧起始信号STV来控制扫描驱动电路12进行行扫描。
当帧起始信号STV为高电平时，驱动控制器11控制扫描驱动电路12输出扫描驱动信号，从第1行开始逐行或隔行驱动行信号线上的开关器件启动工作，同时数据驱动电路13输出的充电信号通过启动工作的开关器件，对行信号线上的显示像素进行充电。另外，扫描驱动电路12对第1行行信号线上的显示像素进行充电的同时，由于扫描驱动信号还驱动第5行行信号线上的开关器件启动工作，因此数据驱动电路13输出的充电信号还对第5行行信号线上的显示像素进行预充电。以此类推，直到所有的行信号线上的显示像素均完成充电，完成一帧画面的扫描、刷新。
在扫描驱动电路12输出扫描驱动信号时，由于预设行的行信号线连接的信号输出控制电路121中，信号触发电路1211输出的扫描驱动信号与OE信号进行逻辑或的运算后，再输出运算后的扫描驱动信号。因此，预设行的行信号线连接的信号输出控制电路输出的扫描驱动信号中，其输出时长从时钟信号CKV的上升沿开始，持续到下一个时钟信号CKV的上升沿截止。例如，输出至首行的行信号线G1的扫描驱动信号的持续时长为t1。
与其他行的行信号线连接的信号输出控制电路121中，信号触发电路1211输出的扫描驱动信号与OE信号进行逻辑与的运算后，再输出运算后的扫描驱动信号。因此，其他行的行信号线连接的信号输出控制电路输出的扫描驱动信号中，其输出时长与OE信号的高电平持续时长一致。即，OE信号输出高电平，则输出扫描驱动信号；OE信号输出低电平，则停止输出扫描驱动信号。例如，输出至第5行的行信号线G5的扫描驱动信号的持续时长为t2。
另外，由于与其他行的行信号线连接的信号输出控制电路121中，信号触发电路1211输出的扫描驱动信号与OE信号进行逻辑或的运算后，再输出运算后的扫描驱动信号，因此在驱动控制器11控制扫描驱动电路12给其他行的行信号线进行扫描驱动，使得数据驱动电路13给其他行的行信号线进行预充电时，扫描驱动电路12输出的扫描驱动信号的输出时长与OE信号的高电平持续时长一致。例如，预充电时输出至第5行的行信号线G5的扫描驱动信号的持续时长为t3。
由上可知，由于预设行的行信号线无法进行预充电，因此通过本技术方案，使得预设行的行信号线上的开关器件的启动时长延长，从而延长了预设行的显示像素的充电时间，进而保证了所有的行信号线的显示像素的显示效果。
进一步地，参照图5，图5是本申请另一实施例的显示驱动电路的逻辑结构示意图。每一扫描信号输出电路120还包括第二逻辑电路122，该第二逻辑电路122接收第三控制信号和扫描驱动信号，并对第三控制信号和扫描驱动信号进行逻辑运算后，输出至信号触发电路1211。
具体地，该第二逻辑电路122包括至少一逻辑门电路，例如逻辑与门、逻辑或门、与非门、非门等等。第三控制信号为行扫描方向控制信号L/R。通过该行扫描控制信号来控制帧扫描开始时，从第一行开始扫描，还是从最后一行开始扫描。例如L/R为高电平时，从第一行开始扫描，L/R为低电平时，从最后一行开始扫描。
应当注意的是，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的部件或步骤。位于部件之前的单词“一”或“一个”不排除存在多个这样的部件。本申请可以借助于包括有若干不同部件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
尽管已描述了本申请的可选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括可选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (20)

  1. 一种显示驱动电路，其中，包括多个扫描信号输出电路，该多个扫描信号输出电路根据时序控制电路的控制信号，输出扫描驱动信号至对应的行信号线，来驱动行信号线上的显示单元；以及
    每一扫描信号输出电路均包括信号输出控制电路，且通过所述信号输出控制电路的控制，在为预设行的行信号线输出扫描驱动信号时，对该扫描驱动信号的输出时长进行延长。
  2. 如权利要求1所述的显示驱动电路，其中，所述预设行的行信号线为首行开始的预设数量的行信号线。
  3. 如权利要求1所述的显示驱动电路，其中，所述信号输出控制电路包括：
    信号触发电路，包括两输入端口和一输出端口，所述两输入端口分别接收扫描驱动信号及第一控制信号，并在第一控制信号满足触发条件时，输出扫描驱动信号；以及
    第一逻辑电路，包括两输入端口和一输出端口，一输入端口与所述信号触发电路的输出端口连接，另一输入端口接收第二控制信号，所述逻辑单元将所述信号触发电路输出的扫描驱动信号与所述第二控制信号进行逻辑运算后，输出运算后的扫描驱动信号。
  4. 如权利要求3所述的显示驱动电路，其中，与预设行的行信号线连接的信号输出控制电路中，第一逻辑电路为逻辑或门。
  5. 如权利要求4所述的显示驱动电路，其中，与其余行的行信号线连接的信号输出控制电路中，第一逻辑电路为逻辑与门。
  6. 如权利要求3所述的显示驱动电路，其中，所述信号触发电路包括至少一触发集成电路，所述触发集成电路在接收到第一控制信号，且第一控制信号为上升沿时，将接收到的扫描驱动信号输出。
  7. 如权利要求3所述的显示驱动电路，其中，所述信号触发电路为D触发器。
  8. 如权利要求3所述的显示驱动电路，其中，所述第二控制信号为使能信号，设置为控制扫描驱动信号的输出。
  9. 如权利要求3所述的显示驱动电路，其中，所述第一控制信号为时钟信号。
  10. 如权利要求3所述的显示驱动电路，其中，与首行的行信号线连接的信号输出控制电路中，接收的扫描驱动信号为帧起始信号；其余行的行信号线连接的信号输出控制电路中，接收的扫描驱动信号为前一信号输出控制电路中信号触发电路输出的扫描驱动信号。
  11. 如权利要求10所述的显示驱动电路，其中，所述每一扫描信号输出电路还包括第二逻辑电路，该第二逻辑电路接收第三控制信号和扫描驱动信号，并对第三控制信号和扫描驱动信号进行逻辑运算后，输出至信号触发电路。
  12. 如权利要求11所述的显示驱动电路，其中，所述第三控制信号为行扫描方向控制信号。
  13. 一种显示驱动电路，其中，包括多个扫描信号输出电路，该多个扫描信号输出电路根据时序控制电路的控制信号，输出扫描驱动信号至对应的行信号线，来驱动行信号线上的显示单元；所述多个扫描信号输出电路与行信号线对应连接，且与首行开始4行的行信号线连接的扫描信号输出电路为第一扫描信号输出电路，其余行的行信号线连接的扫描信号输出电路为第二扫描信号输出电路；以及
    每一扫描信号输出电路均包括信号输出控制电路，且通过所述信号输出控制电路的控制，在扫描信号输出电路对行信号线输出扫描驱动信号时，第一扫描信号输出电路输出的扫描驱动信号的时长比第二扫描信号输出电路输出的扫描驱动信号的时长更长。
  14. 如权利要求13所述的显示驱动电路，其中，所述信号输出控制电路包括：
    信号触发电路，包括两输入端口和一输出端口，所述两输入端口分别接收扫描驱动信号及第一控制信号，并在第一控制信号满足触发条件时，输出扫描驱动信号；以及
    第一逻辑电路，包括两输入端口和一输出端口，一输入端口与所述信号触发电路的输出端口连接，另一输入端口接收第二控制信号，所述第一逻辑电路将所述信号触发电路输出的扫描驱动信号与所述第二控制信号进行逻辑运算后，输出运算后的扫描驱动信号。
  15. 如权利要求14所述的显示驱动电路，其中，所述第一扫描信号输出电路中的信号输出控制电路中，第一逻辑电路为逻辑或门。
  16. 如权利要求14所述的显示驱动电路，其中，所述第二扫描信号输出电路中的信号输出控制电路中，第二逻辑电路为逻辑与门。
  17. 一种显示装置，其中，包括：
    基板，所述基板上形成显示区和非显示区，所述显示区内设置多个显示像素；以及
    显示驱动装置，设置为驱动所述显示像素进行显示，所述显示驱动装置包括多个扫描信号输出电路，该多个扫描信号输出电路根据时序控制电路的控制信号，输出扫描驱动信号至对应的行信号线，来驱动行信号线上的显示像素；每一扫描信号输出电路均包括信号输出控制电路，且通过所述信号输出控制电路的控制，在为预设行的行信号线输出扫描驱动信号时，对该扫描驱动信号的输出时长进行延长。
  18. 如权利要求17所述的显示装置，其中，所述显示驱动装置包括驱动控制器、扫描驱动电路、数据驱动电路，所述驱动控制器输出驱动控制信号，来控制扫描驱动电路和数据驱动电路输出对应的驱动信号，驱动所述显示像素工作。
  19. 如权利要求18所述的显示装置，其中，所述扫描驱动电路输出所述扫描驱动信号，并通过所述扫描信号输出电路输出至行信号线。
  20. 如权利要求19所述的显示装置，其中，所述驱动控制器输出控制信号，该输出控制信号输出至所述扫描信号输出电路，来控制扫描驱动信号的输出。
PCT/CN2018/115780 2018-11-05 2018-11-16 显示驱动电路以及显示装置 WO2020093434A1 (zh)

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