WO2020082446A1 - 一种电路板的差分走线及电路板 - Google Patents

一种电路板的差分走线及电路板 Download PDF

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Publication number
WO2020082446A1
WO2020082446A1 PCT/CN2018/115321 CN2018115321W WO2020082446A1 WO 2020082446 A1 WO2020082446 A1 WO 2020082446A1 CN 2018115321 W CN2018115321 W CN 2018115321W WO 2020082446 A1 WO2020082446 A1 WO 2020082446A1
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Prior art keywords
differential
circuit board
trace
differential trace
wiring
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Ceased
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PCT/CN2018/115321
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English (en)
French (fr)
Inventor
胡水秀
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HKC Co Ltd
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HKC Co Ltd
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Priority to US16/982,028 priority Critical patent/US11546985B2/en
Publication of WO2020082446A1 publication Critical patent/WO2020082446A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09672—Superposed layout, i.e. in different planes

Definitions

  • This solution relates to a circuit board, and more specifically, to a differential wiring of a circuit board and a circuit board.
  • Differential wiring is a pair of coupled transmission lines, widely used in computer buses and Ethernet devices.
  • Differential traces transmit differential signals, one of which carries a signal and the other carries its complementary signal. The receiving end judges the received signal by comparing the difference between the two signals. When differential signals are transmitted in differential traces, they are not easily disturbed by switching noise.
  • each pair of differential traces has two wires, and the two wires are arranged in parallel.
  • the differential wiring of the circuit board occupies a large area, the utilization rate of the circuit board is low, and the cost is high.
  • the present application provides a differential wiring of a circuit board and a circuit board, which reduces the occupied area of the differential wiring and improves the utilization rate of the circuit board.
  • the present application discloses a differential wiring of a circuit board.
  • the circuit board has at least two layers; the differential wiring has at least one pair and is provided on the circuit board; each pair of the differential wiring includes a first differential wiring A second differential trace; the first differential trace and the second differential trace are provided on different layers of the circuit board.
  • the first differential trace and the second differential trace are respectively disposed in two adjacent layers of the circuit board.
  • the first differential trace and the second differential trace are respectively disposed in two adjacent layers of the circuit board, and the first differential trace and the second differential trace are respectively disposed in two different layers of the circuit board
  • the distance between the first differential trace and the second differential trace is smaller, the coupling between the first differential trace and the second differential trace is stronger, and the possibility of electromagnetic interference (Electromagnetic Interference, EMI) is possible
  • EMI Electromagnetic Interference
  • the first differential trace is located directly below or directly above the second differential trace.
  • the circuit board has four layers, the first differential trace is provided on the second layer, and the second differential trace is provided on the third layer.
  • the routing paths of the first differential trace and the second differential trace are the same, and the distance between the first differential trace and the second differential trace is equal.
  • the traces of the first differential trace and the second differential trace are arranged in a straight line.
  • the circuit board has four layers, and there are multiple pairs of the differential traces.
  • Half of the differential traces have the first differential traces on the first layer and the second differential traces on the second layer.
  • the first differential trace is provided on the third layer, and the second differential trace is provided on the fourth layer.
  • the number of layers of the circuit board is a plurality of layers greater than four layers, and the first differential wiring and the second differential wiring are respectively provided in different layers of the plurality of layers of the circuit board.
  • the circuit board includes a control chip and a connector (Connector, CNT), one end of the first and second differential traces is connected to the control chip, and the other end is connected to a connector (Connector, CNT) Connection, the differential signal of the control chip is transmitted to the connector through the first differential wiring and the second differential wiring.
  • the control chip may include a timing controller (Timing Controller, TCON) and the like.
  • Another object of the present application is to provide a circuit board, the circuit board is a multilayer board, the circuit board includes a differential wiring, the differential wiring includes a first differential wiring, a second differential wiring; The first differential trace and the second differential trace are respectively arranged in two different layers on the circuit board.
  • Another object of the present application is to provide a differential wiring of a circuit board, the circuit board is a four-layer board; the circuit board includes a control chip, a connector and four pairs of differential wiring, each pair of the differential wiring It includes a first differential trace and a second differential trace; the first differential trace is provided on the second layer of the circuit board; the third differential trace is on the third layer; the first differential trace One end of the second differential wiring is connected to the control chip, and the other end is connected to the connector.
  • the differential signal of the control chip is transmitted to the connector through the first differential wiring and the second differential wiring.
  • the circuit board is a multi-layer board.
  • the circuit board includes a control chip, a differential wiring, and a connector.
  • the differential wiring includes a first differential wiring and a second differential Traces;
  • the manufacturing method includes:
  • One layer in the circuit board forms the first differential trace
  • Another layer in the circuit board forms a second differential trace
  • the control chip is formed on the circuit board
  • the first differential trace and the second differential trace are connected to the control chip and the connector.
  • the first differential trace and the second differential trace are arranged on the same layer.
  • the area occupied by the differential trace includes the area of the first differential trace and the second differential trace itself, the first differential trace and the first The area between two differential traces and the area between each pair of differential traces.
  • Such an arrangement occupies a large area, the circuit board utilization rate is low, and the cost is high.
  • placing the first differential trace and the second differential trace in two different layers of the circuit board can save the area between the first differential trace and the second differential trace, and can save half of the same The area between each two pairs of differential traces on the layer, thereby reducing the occupied area of the differential traces, improving the utilization rate of the circuit board, and reducing the cost.
  • FIG. 1 is a schematic structural diagram of an undisclosed differential trace
  • FIG. 2 is a schematic structural diagram of the first differential trace in the second layer of the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of the second differential trace in the third layer of the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a first differential trace and a second differential trace that are straight lines according to an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of the first differential trace in the third layer of the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a second differential trace at the fourth layer according to an embodiment of the present application.
  • FIG. 7 is a flowchart of manufacturing a circuit board according to an embodiment of the present application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • the term “including” and any variations thereof are intended to cover non-exclusive inclusions.
  • connection should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • this embodiment discloses a differential wiring of a circuit board, the circuit board 1 has at least two layers; the differential wiring 10 has at least one pair, and is provided on the circuit board 1; each The differential traces include a first differential trace 20 and a second differential trace 30; the first differential trace 20 and the second differential trace 30 are disposed on different layers of the circuit board 1.
  • the area occupied by the differential trace 10 includes the areas of the first differential trace 20 and the second differential trace 30 themselves 1.
  • disposing the first differential trace 20 and the second differential trace 30 in two different layers of the circuit board 1 can save the area between the first differential trace 20 and the second differential trace 30, In addition, half of the area between each pair of differential traces on the same layer can be saved, thereby reducing the occupied area of the differential trace 10, improving the utilization rate of the circuit board 1, and reducing costs.
  • the difference from the above embodiment is that the first differential trace 20 and the second differential trace 30 are respectively disposed in two adjacent layers of the circuit board 1.
  • the first differential trace 20 and the second differential trace 30 are respectively disposed in two adjacent layers of the circuit board 1, and the first differential trace 20 and the second differential trace 30 are respectively disposed in the circuit Two non-adjacent layers of board 1, the distance between the first differential trace 20 and the second differential trace 30 is smaller, and the coupling between the first differential trace 20 and the second differential trace 30 is stronger,
  • EMI Electromagnetic Interference
  • the first differential trace 20 is located directly below or directly above the second differential trace 30.
  • the circuit board 1 has four layers, the first differential trace 20 is provided on the second layer, and the second differential trace 30 is provided on the third layer.
  • the first differential trace 20 is located directly below or directly above the second differential trace 30, the distance between the first differential trace 20 and the second differential trace 30 is smaller, and the first differential trace 20
  • the coupling with the second differential trace 30 is stronger, the possibility of electromagnetic interference (Electromagnetic Interference, EMI) is less, and the immunity to noise is better.
  • EMI Electromagnetic Interference
  • the first differential trace 20 is provided on the second layer, and the second differential trace 30 is provided on the third layer.
  • the equivalent RC impedance (Equivalent RC) coupling of each pair of differential traces is substantially equal, while The utilization rate of the printed circuit board 1 is also improved.
  • the first differential trace 20 is disposed on the second layer, and the second differential trace 30 is disposed on the third layer.
  • the first differential trace 20 and the second differential trace 30 are not exposed on the surface and are not easily oxidized and aged.
  • the routing paths of the first differential trace 20 and the second differential trace 30 are the same, and the pitches of the first differential trace 20 and the second differential trace 30 are equal.
  • the traces of the first differential trace 20 and the second differential trace 30 are arranged in a straight line.
  • the routing paths of the first differential trace 20 and the second differential trace 30 are the same, the distance between the first differential trace 20 and the second differential trace 30 is equal, and the impedance is along the first differential trace 20 and The second differential trace 30 is continuous throughout and maintains a constant, and the first differential trace 20 and the second differential trace 30 have strong anti-interference capabilities.
  • the first differential trace 20 and the second differential trace 30 are arranged in a straight line.
  • the first differential trace 20 and the second differential trace 30 are not bent, and the trace is arranged Simple, the length error between the first differential trace 20 and the second differential trace 30 is small, the first differential trace 20 and the second differential trace 30 are closer to the same, and the impedance is easier to follow the first differential trace 20 and the second differential trace 30 are continuous throughout and maintain a constant, and the first differential trace 20 and the second differential trace 30 have strong anti-interference ability.
  • the circuit board 1 includes a control chip 40 (Timing Controller, TCON), one end of the first differential trace 20 and the second differential trace 30 is connected to the control chip 40, and the other end is connected to a connector 50 (Connector, CNT) connection, the differential signal of the control chip 40 is transmitted to the connector 50 via the first differential trace 20 and the second differential trace 30.
  • the control chip may include a timing controller (Timing Controller, TCON) and the like.
  • the first differential trace 20 and the second differential trace 30 are connected to the control chip 40, and the signals received by the first differential trace 20 and the second differential trace 30 are accurate; the control chip 40 is small and can further save The space of the circuit board 1 improves the utilization rate of the circuit board 1.
  • the difference from the above embodiment is that the circuit board 1 has four layers, the differential trace 10 has multiple pairs, and half of the differential trace 10 has the first The differential trace 20 is provided on the first layer, the second differential trace 30 is provided on the second layer, the other half of the differential trace 10 is provided with the first differential trace 20 on the third layer, and the second differential trace 30 is provided On the fourth floor.
  • the first differential trace 20 of half of the differential traces 10 is arranged on the first layer, and the second differential trace 30 is arranged on the second layer, and the other half of the differential traces 10
  • the first differential trace 20 of the trace is arranged on the third layer
  • the second differential trace 30 is arranged on the fourth layer
  • the differential trace 10 is more evenly distributed in each layer of the circuit board 1, each layer of the circuit board 1
  • the space utilization is more reasonable.
  • the differential traces 10 are not concentrated in two of the layers, resulting in a small remaining space on the two layers, while the space on the other two layers is not fully utilized.
  • the difference from the above embodiment is that the number of layers of the circuit board 1 is a plurality of layers greater than four layers, and the first differential trace 20 and the second differential trace 30 are respectively provided on the circuit board 1 In different layers of multiple layers.
  • the number of layers of the circuit board 1 is greater than four, and the number of layers of the circuit board 1 is large.
  • the circuit board 1 is a multilayer board.
  • the circuit board 1 includes a differential trace 10, and the differential trace 10 includes a A differential trace 20 and a second differential trace 30; the first differential trace 20 and the second differential trace 30 are respectively arranged in two different layers on the circuit board 1.
  • disposing the first differential trace 20 and the second differential trace 30 in two different layers of the circuit board 1 can save the area between the first differential trace 20 and the second differential trace 30, In addition, half of the area between each pair of differential traces on the same layer can be saved, thereby reducing the occupied area of the differential trace 10, improving the utilization rate of the circuit board 1, and reducing costs.
  • the circuit board 1 is a four-layer board; the circuit board 1 includes a control chip 40, a connector 50, and four pairs Differential trace 10, each pair of the differential trace 10 includes a first differential trace 20 and a second differential trace 30; the first differential trace 20 is provided on the second layer of the circuit board 1; the first On the third layer of the second differential trace 30; one end of the first differential trace 20 and the second differential trace 30 is connected to the control chip 40 and the other end is connected to the connector 50, and the differential signal of the control chip 40 passes The first differential trace 20 and the second differential trace 30 are transmitted to the connector 50.
  • the control chip may include a timing controller (Timing Controller, TCON), and so on.
  • TCON Timing Controller
  • the first differential trace 20 and the second differential trace 30 are respectively provided in the second layer and the third layer of the circuit board 1, which can save the area between the first differential trace 20 and the second differential trace 30, and can It saves half of the area between each pair of differential traces on the same layer, thereby reducing the occupied area of the differential trace 10, improving the utilization rate of the circuit board 1, and reducing the cost.
  • the first differential trace 20 and the second differential trace 30 are respectively disposed in the second layer and the third layer of the circuit board 1 to ensure that the equivalent RC (Resistance-Capacitance Circuits) coupling of each pair of differential traces is substantially equal, the first The coupling between the differential trace 20 and the second differential trace 30 is stronger, the possibility of EMI radiation is small, and the immunity to noise is better.
  • RC Resistance-Capacitance Circuits
  • the circuit board 1 is a multilayer board.
  • the circuit board 1 includes a control chip 40, a differential wiring 10, a connector 50, and a differential wiring 10 Including the first differential trace 20 and the second differential trace 30;
  • the manufacturing method includes:
  • S74 The first differential trace 20 and the second differential trace 30 are connected to the control chip 40 and the connector 50.
  • the first differential trace 20 and the first differential trace 20 can be arranged in different layers of the circuit board 1, which can save the area between the first differential trace 20 and the second differential trace 30, and can save Half the area between every two pairs of differential traces on the same layer, thereby reducing the occupied area of the differential traces, improving the utilization rate of the circuit board 1 and reducing the cost.
  • the circuit board 1 of the present application may include a printed circuit board (Printed Circuit Board, PCB), a flexible circuit board (Flexible Printed Circuit, FPC), etc., as long as applicable.
  • PCB printed circuit Board
  • FPC Flexible Printed Circuit

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

一种电路板（1）的差分走线（10）及电路板（1）。包括电路板（1），电路板（1）设置有差分走线（10）；差分走线（10）包括第一差分走线（20）和第二差分走线（30），设置在电路板（1）的不同层上。

Description

一种电路板的差分走线及电路板
本申请要求于2018年10月23日提交中国专利局、申请号为CN201811234265.2、发明名称为“一种电路板的差分走线及电路板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本方案涉及电路板，更具体的说，涉及一种电路板的差分走线及电路板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
差分走线是一对存在耦合的传输线，广泛应用于计算机总线和以太网设备中。差分走线传输的是差分信号，其中一根携带信号，另一根携带它的互补信号，接收端通过比较这两个信号的差值来判断接收的信号。差分信号在差分走线中传输时，不易受到开关噪声的干扰。
在面板行业中，电路板布局时，输出差分信号经过差分走线输出到后端，每一对差分走线有两根线，两根线并行排列。
电路板的差分走线占用面积大，电路板的利用率低，成本高。
技术解决方案
本申请提供一种电路板的差分走线及电路板，减小差分走线的占用面积，提高电路板利用率。
本申请的目的是通过以下技术方案来实现的：
本申请公开了一种电路板的差分走线，所述电路板至少有两层；所述差分走线至少有一对，并设置在电路板上；每对所述差分走线包括第一差分走线和第二差分走线；所述第一差分走线与第二差分走线设置在所述电路板的不同层上。
可选的，所述第一差分走线和第二差分走线分别设置在电路板的两个相邻层中。
本方案中，第一差分走线和第二差分走线分别设置在电路板的两个相邻层中，相对于第一差分走线和第二差分走线分别设置在电路板的两个不相邻层，第一差分走线和第二差分走线之间的距离更小，第一差分走线和第二差分走线之间的耦合更强，电磁干扰 (Electromagnetic Interference，EMI)的可能性小，对噪声的免疫性就更好。
可选的，所述第一差分走线位于第二差分走线的正下方或者正上方。
可选的，所述电路板为四层，所述第一差分走线设置在第二层，所述第二差分走线设置在第三层。
可选的，所述第一差分走线和第二差分走线的走线布置路径相同，所述第一差分走线和第二差分走线的间距相等。
可选的，所述第一差分走线和第二差分走线的走线布置为直线。
可选的，所述电路板为四层，所述差分走线有多对，一半所述差分走线的第一差分走线设置在第一层，第二差分走线设置在第二层，另一半所述差分走线的第一差分走线设置在第三层，第二差分走线设置在第四层。
可选的，所述电路板的层数为大于四层的复数层，所述第一差分走线和第二差分走线分别设置在电路板复数层的不同层中。
可选的，所述电路板包括有控制芯片和连接器(Connector，CNT)，所述第一差分走线和第二差分走线一端与控制芯片连接，另一端与连接器(Connector，CNT)连接,所述控制芯片的差分信号经过第一差分走线和第二差分走线输到连接器。所述控制芯片可以包括时序控制器(Timing Controller，TCON)等。
本申请的另一个目的在于提供一种电路板，所述电路板为多层板，所述电路板包括差分走线，所述差分走线包括第一差分走线、第二差分走线；所述第一差分走线和第二差分走线分别设置在电路板上不同的两层中。
本申请的另一个目的在于提供一种电路板的差分走线，所述电路板为四层板；所述电路板包括控制芯片、连接器和四对差分走线，每对所述差分走线包括第一差分走线和第二差分走线；所述第一差分走线设置在电路板的第二层上；所述第二差分走线的第三层上；所述第一差分走线和第二差分走线一端与控制芯片连接，另一端与连接器连接,所述控制芯片的差分信号经过第一差分走线和第二差分走线输到连接器。
本申请的另一个目的在于提供一种电路板的制作方法，电路板为多层板，电路板包括有控制芯片、差分走线、连接器，差分走线包括第一差分走线和第二差分走线；
所述制作方法包括：
电路板中的一层形成第一差分走线；
电路板中的另一层形成第二差分走线；
电路板上形成控制芯片；
第一差分走线和第二差分走线与控制芯片、连接器。
电路板中，第一差分走线和第二差分走线设置在同一层中，差分走线占用的面积包括第一差分走线和第二差分走线自身的面积、第一差分走线和第二差分走线之间的面积、每对差分走线之间的面积。这样的设置占用面积大，电路板利用率低，成本高。本方案中，将第一差分走线和第二差分走线设置在电路板的两个不同层中，可以节省第一差分走线和第二差分走线之间的面积，并且可以节省一半同一层每两对差分走线之间的面积，从而降低差分走线的占用面积，提高电路板的利用率，降低成本。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是未公开的差分走线的结构示意图；
图2是本申请实施例第一差分走线位于第二层的结构示意图；
图3是本申请实施例第二差分走线位于第三层的结构示意图；
图4是本申请实施例第一差分走线和第二差分走线为直线的结构示意图；
图5是本申请实施例第一差分走线位于第三层的结构示意图；
图6是本申请实施例第二差分走线位于第四层的结构示意图；
图7是本申请实施例电路板的制作的流程图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本 申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
下面参考图1至图7描述本申请一实施例中的一种占用面积小并提高电路板利用率的电路板的差分走线及电路板。
参考图2、图3，本实施方式公开了一种电路板的差分走线，所述电路板1至少有两层；所述差分走线10至少有一对，并设置在电路板1上；每对所述差分走线包括第一差分走线20和第二差分走线30；所述第一差分走线20与第二差分走线30设置在所述电路板1的不同层上。
在电路板1的第一差分走线20和第二差分走线30设置在同一层的方案中，差分走线10占用的面积包括第一差分走线20和第二差分走线30自身的面积、第一差分走线20和第二差分走线30之间的面积、每对差分走线之间的面积。这样的设置占用面积大，电路板1利用率低，成本高。本方案中，将第一差分走线20和第二差分走线30设置在电路板1的两个不同层中，可以节省第一差分走线20和第二差分走线30之间的面积，并且可以节省一半同一层每两对差分走线之间的面积，从而降低差分走线10的占用面积，提高电路板1的利用率，降低成本。
在一实施例中，参考图2、图3，与上述实施例不同的在于，所述第一差分走线20和第二差分走线30分别设置在电路板1的两个相邻层中。
本方案中，第一差分走线20和第二差分走线30分别设置在电路板1的两个相邻层中，相对于第一差分走线20和第二差分走线30分别设置在电路板1的两个不相邻层，第一差分走线20和第二差分走线30之间的距离更小，第一差分走线20和第二差分走线30之间的耦合更强，电磁干扰(Electromagnetic Interference，EMI)的可能性小，对噪声的免疫性就更好。
可选的，所述第一差分走线20位于第二差分走线30的正下方或者正上方。所述电路板1为四层，所述第一差分走线20设置在第二层，所述第二差分走线30设置在第三层。
本方案中，第一差分走线20位于第二差分走线30的正下方或者正上方，第一差分走线20和第二差分走线30之间的距离更小，第一差分走线20和第二差分走线30之间的耦合更强，电磁干扰(Electromagnetic Interference，EMI)的可能性小，对噪声的免疫性就更好。
本方案中，第一差分走线20设置在第二层，所述第二差分走线30设置在第三层，每对差分走线的等效RC阻抗(Equivalent RC impedance)耦合基本相等，同时也提高了印刷电路板1的利用率。第一差分走线20设置在第二层，所述第二差分走线30设置在第三层，第一差分走线20和第二差分走线30不暴露在表面，不容易氧化老化。
可选的，参考图4，所述第一差分走线20和第二差分走线30的走线布置路径相同，所述第一差分走线20和第二差分走线30的间距相等。第一差分走线20和第二差分走线30的走线布置为直线。
本方案中，第一差分走线20和第二差分走线30的走线布置路径相同，第一差分走线20和第二差分走线30的间距相等，阻抗沿第一差分走线20和第二差分走线30各处连续并且保持一个常数，第一差分走线20和第二差分走线30的抗干扰能力强。
本方案中，第一差分走线20和第二差分走线30的走线布置为直线，在布线的过程中，第一差分走线20和第二差分走线30不弯折，走线布置简单，第一差分走线20和第二差分走线30之间的长度误差较小，第一差分走线20和第二差分走线30更接近一致，阻抗更容易在沿第一差分走线20和第二差分走线30各处连续并且保持一个常数，第一差分走线20和第二差分走线30的抗干扰能力强。
可选的，参考图2，所述电路板1包括控制芯片40(TimingController，TCON)，所述第一差分走线20和第二差分走线30一端与控制芯片40连接，另一端与连接器50(Connector，CNT)连接,所述控制芯片40的差分信号经过第一差分走线20和第二差分走线30输到连接器50。所述控制芯片可以包括时序控制器(Timing Controller，TCON)等。
本方案中，第一差分走线20和第二差分走线30与控制芯片40连接，第一差分走线20和第二差分走线30接收的信号精准；控制芯片40体积小，可以进一步节省电路板1的空间，提高电路板1的利用率。
在一实施例中，参考图5、图6，与上述实施例不同的在于，所述电路板1为四层，所述差分走线10有多对，一半所述差分走线10的第一差分走线20设置在第一层，第二差分走线30设置在第二层，另一半所述差分走线10的第一差分走线20设置在第三层，第二差分走线30设置在第四层。
本方案中，差分走线10有多对，将其中一半的差分走线10的第一差分走线20设置在第一层，第二差分走线30设置在第二层，将另一半的差分走线的第一差分走线20设置在第三层，第二差分走线30设置在第四层，差分走线10较均匀分布设置在电路板1的每一层中，电路板1每层的空间利用更合理，差分走线10不集中在其中两层中，导致这两层的剩余空间小，而另外两层的空间未充分利用。
在一实施例中，与上述实施例不同的在于，所述电路板1的层数为大于四层的复数层，所述第一差分走线20和第二差分走线30分别设置在电路板1复数层的不同层中。
本方案中，电路板1的层数为大于四层，电路板1的层数较多，第一差分走线20和第二差分走线30的走线布置选择较多，走线布置更方便合理。
本申请另一实施方式公开了一种电路板1，参考图2、图3，所述电路板1为多层板，所述电路板1包括差分走线10，所述差分走线10包括第一差分走线20、第二差分走线30；所述第一差分走线20和第二差分走线30分别设置在电路板1上不同的两层中。
本方案中，将第一差分走线20和第二差分走线30设置在电路板1的两个不同层中，可以节省第一差分走线20和第二差分走线30之间的面积，并且可以节省一半同一层每两对差分走线之间的面积，从而降低差分走线10的占用面积，提高电路板1的利用率，降低成本。
本申请另一实施方式公开了一种电路板的差分走线，参考图2、图3，所述电路板1为四层板；所述电路板1包括控制芯片40、连接器50和四对差分走线10，每对所述差分走线10包括第一差分走线20和第二差分走线30；所述第一差分走线20设置在电路板1的第二层上；所述第二差分走线30的第三层上；所述第一差分走线20和第二差分走线30一端与控制芯片40连接，另一端与连接器50连接,所述控制芯片40的差分信号经过第一差分走线20和第二差分走线30传输到连接器50。
本方案中，所述控制芯片可以包括时序控制器(Timing Controller，TCON)等。第一差分走线20和第二差分走线30分别设置在电路板1第二层和第三层中，可以节省第一差分走线20和第二差分走线30之间的面积，并且可以节省一半同一层每两对差分走线之间的面积，从而降低差分走线10的占用面积，提高电路板1的利用率，降低成本。第一差分走线20和第二差分走线30分别设置在电路板1第二层和第三层中可以保证每对差分走线的等效RC(Resistance-Capacitance Circuits)耦合基本相等，第一差分走线20和第二差分走线30之间的耦合更强，EMI辐射的可能性小，对噪声的免疫性就更好。
本申请另一实施方式公开了一种电路板的制作方法，参考图7，电路板1为多层板，电路板1包括有控制芯片40、差分走线10、连接器50，差分走线10包括第一差分走线20和第二差分走线30；
所述制作方法包括：
S71:电路板1中的一层形成第一差分走线20；
S72:电路板1中的另一层形成第二差分走线30；
S73:电路板1上形成控制芯片40；
S74:第一差分走线20和第二差分走线30与控制芯片40、连接器50。
本方法可以将第一差分走线20、第一差分走线20设置在电路板1不同的层中，可以节省第一差分走线20和第二差分走线30之间的面积，并且可以节省一半同一层每两对差分走线之间的面积，从而降低差分走线的占用面积，提高电路板1的利用率，降低成本。
本申请的电路板1可以包括印制电路板(Printed Circuit Board，PCB)、柔性电路板(Flexible Printed Circuit，FPC)等，适用即可。
以上内容是结合具体的可选的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种电路板的差分走线，包括：
    电路板,至少有两层；
    至少一对差分走线，设置在电路板上；
    每对所述差分走线包括第一差分走线和第二差分走线；
    所述第一差分走线与第二差分走线设置在所述电路板的不同层上。
  2. 如权利要求1所述的一种电路板的差分走线，其中，所述第一差分走线和第二差分走线分别设置在电路板的两个相邻层中。
  3. 如权利要求2所述的一种电路板的差分走线，其中，所述第一差分走线位于第二差分走线的正下方。
  4. 如权利要求2所述的一种电路板的差分走线，其中所述第一差分走线位于第二差分走线的正上方。
  5. 如权利要求1所述的一种电路板的差分走线，其中，所述电路板为四层，所述第一差分走线设置在第二层，所述第二差分走线设置在第三层。
  6. 如权利要求1所述的一种电路板的差分走线，其中，所述第一差分走线和第二差分走线的走线布置路径相同。
  7. 如权利要求6所述的一种电路板的差分走线，其中，所述第一差分走线和第二差分走线的间距相等。
  8. 如权利要求7所述的一种电路板的差分走线，其中，所述第一差分走线和第二差分走线的走线布置为直线。
  9. 如权利要求1所述的一种电路板的差分走线，其中，所述电路板为四层，所述差分走线有多对，一半所述差分走线的第一差分走线设置在第一层，第二差分走线设置在第二层，另一半所述差分走线的第一差分走线设置在第三层，第二差分走线设置在第四层。
  10. 如权利要求2所述的一种电路板的差分走线，其中，所述电路板为四层，所述第一差分走线设置在第二层，所述第二差分走线设置在第三层。
  11. 如权利要求3所述的一种电路板的差分走线，其中，所述电路板为四层，所述第一差分走线设置在第二层，所述第二差分走线设置在第三层。
  12. 如权利要求1所述的一种电路板的差分走线，其中，所述电路板的层数为大于四层的复数层，所述第一差分走线和第二差分走线分别设置在电路板复数层的不同层中。
  13. 一种电路板的差分走线，包括：
    所述电路板为四层板；
    四对差分走线，设置在电路板上；
    每对所述差分走线包括第一差分走线和第二差分走线；
    每对所述第一差分走线设置在电路板的第二层上；每对所述第二差分走线的第三层上。
    控制芯片，设置在电路板上；
    连接器，设置在电路板上；
    所述第一差分走线和第二差分走线一端与控制芯片连接，另一端与连接器连接,所述控制芯片的差分信号经过第一差分走线和第二差分走线输到连接器。
  14. 如权利要求13所述的一种电路板的差分走线，其中，所述控制芯片为时序控制器。
  15. 一种电路板，所述电路板至少有两层，所述电路板包括：
    至少一对差分走线，设置在电路板上；
    每对所述差分走线包括第一差分走线和第二差分走线；
    所述第一差分走线与第二差分走线设置在所述电路板的不同层上。
  16. 如权利要求15所述的一种电路板，其中，所述第一差分走线和第二差分走线分别设置在电路板的两个相邻层中。
  17. 如权利要求15所述的一种电路板，其中，所述第一差分走线位于第二差分走线的正下方。
PCT/CN2018/115321 2018-10-23 2018-11-14 一种电路板的差分走线及电路板 Ceased WO2020082446A1 (zh)

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