WO2020078419A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2020078419A1
WO2020078419A1 PCT/CN2019/111661 CN2019111661W WO2020078419A1 WO 2020078419 A1 WO2020078419 A1 WO 2020078419A1 CN 2019111661 W CN2019111661 W CN 2019111661W WO 2020078419 A1 WO2020078419 A1 WO 2020078419A1
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Prior art keywords
layer
trench
source
forming
polysilicon
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English (en)
French (fr)
Inventor
肖魁
方冬
卞铮
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device structure and a manufacturing method thereof.
  • Trench VDMOS products are more widely used power devices.
  • the maturity of the trench process further reduces the size of the cell.
  • the trench area passes through the lowermost end of the P-type base region, the channel formed is located Between the source region and the drift region, the on-resistance is greatly reduced compared to the ordinary VDMOS eliminating the JFET region, so the trench VDMOS greatly improves the performance of the MOS power device.
  • the structure used today is that the polysilicon gate plane in the trench is lower than the silicon plane, the manufacturing process is etching trench, growing gate oxygen, polysilicon deposition, polysilicon etching, well region formation, NSD formation, hole Formation, metal electrode formation, back process.
  • the process setting when etching to the oxide layer above silicon increase a certain amount of etching, In order to ensure that all polysilicon above the silicon is completely etched. That is, the structure formed is that the polysilicon gate plane in the trench is lower than the silicon plane, which brings the problem that subsequent well region implantation and source region implantation will affect the channel, resulting in unstable threshold voltage.
  • the present invention proposes a semiconductor device structure and a manufacturing method thereof.
  • the polysilicon gate plane is higher than the silicon plane to solve the problem of unstable threshold voltage.
  • one aspect of the present invention provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; a polysilicon layer, the bottom of the polysilicon layer is located in the trench, so The polysilicon top height position is higher than the trench top height position.
  • Another aspect of the present invention provides a semiconductor manufacturing method, including: providing a semiconductor substrate; forming a trench in the semiconductor substrate; depositing a polysilicon layer with the bottom of the polysilicon layer in the trench; The layer is etched, and the top position of the etched polysilicon layer is higher than that of the trench.
  • a further aspect of the present invention provides a VDMOS device, including a semiconductor substrate; a trench formed in the semiconductor substrate; a gate formed of a polysilicon layer, the bottom of the polysilicon layer is located in the trench, and The polysilicon top height position is higher than the trench top height position, the gate plane is higher than the semiconductor substrate plane; it also includes contact layers formed above and below the semiconductor device and connected to the source and drain, respectively Thereby forming a cell structure.
  • the semiconductor device and the manufacturing method of the present invention can improve the threshold voltage stability under the premise that the manufacturing process is fully compatible without adding a mask or a process step.
  • FIG. 1A to 1K show schematic cross-sectional views of devices obtained by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIGS. 2A to 2K show schematic cross-sectional views of a device obtained by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 3 shows a schematic flowchart of an embodiment of the present invention.
  • Spatial relationship terms such as “below”, “below”, “below”, “above”, “above”, etc. It can be used here for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then elements or features described as “below” or “below” or “below” the elements will be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. In this way, a change from the illustrated shape due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted area shown as a rectangle generally has round or curved features and / or implant concentration gradients at its edges, rather than a binary change from the implanted area to the non-implanted area. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is proceeding. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.
  • the present invention provides a semiconductor device and a manufacturing method thereof, including: a semiconductor substrate; a trench formed in the semiconductor substrate; a polysilicon layer located in the trench and the top thereof The height position is higher than the height position of the top of the trench, and the semiconductor device and the manufacturing method of the present invention can improve the threshold voltage stability under the premise that the manufacturing process is fully compatible without adding a mask or a process step.
  • VDMOS The manufacturing process of the VDMOS will be described below with reference to the cross-sectional schematic diagrams of the devices obtained by the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention shown in FIGS. 1 to 1K.
  • Step 1 providing a silicon wafer 100 as a substrate, and forming a silicon epitaxial layer 101 on the silicon substrate, as shown in FIG. 1A;
  • Step 2 Form a first oxide layer 102, and form a first oxide layer 102 on the silicon epitaxial layer 101.
  • the first oxide layer 102 is a thermal oxide layer TOX, as shown in FIG. 1B;
  • Step 3 forming trenches, forming trenches in the first oxide layer 102 and the silicon epitaxial layer 101, as shown in FIG. 1C;
  • step 3 further includes: after forming the trench, removing the first oxide layer 102 above the silicon epitaxial layer 101;
  • Step 4 forming a second oxide layer 103, forming a second oxide layer 103 on the surface of the silicon epitaxial layer 101 and the trench, optionally, the second oxide layer is a gate oxide layer, as shown in FIG. 1D ;
  • Step 5 filling polysilicon 104, depositing polysilicon 104 on the surface of the gate oxide layer 103, and filling the trench and above the trench, as shown in FIG. 1E;
  • Step 6 The polysilicon layer 104 is etched, and the polysilicon layer 104 is etched.
  • the top position of the etched polysilicon layer 104 is lower than the top surface position of the groove, as shown in FIG. 1F;
  • Step 7 a well region 105 is formed, and a P well region is implanted into the silicon epitaxial layer, as shown in FIG. 1G;
  • Step 8 forming a first source / drain region 106, and implanting an N-type source / drain region NSD into the well region, as shown in FIG. 1H;
  • Step 9 forming an interlayer dielectric layer (ILD) 107, and forming an interlayer dielectric layer 107 above the trench and the first source / drain region 106, as shown in FIG. 1I;
  • ILD interlayer dielectric layer
  • a hole 108 is formed, and a CT contact hole 108 is formed on the interlayer dielectric layer.
  • the contact hole 108 extends from the top to the bottom of the interlayer dielectric layer 107, and the bottom of the contact hole 108 is lower than the The lower surface of the first source / drain region 106 and implanted through the contact hole 108 to form a second source / drain region 109, that is, a P-type source / drain PSD, as shown in FIG. 1J;
  • Step 11 forming a cell structure, forming contact layers 1101, 1102 above the interlayer dielectric layer 107 and below the silicon wafer 100 substrate, and forming leads through the contact layers 1101, 1102 respectively, connected to
  • the source (S) and drain (D) form a cell structure, as shown in Figure 1K.
  • the polysilicon 104 above the silicon is completely etched.
  • the implantation of the well region 105 and the implantation of the NSD 106 in steps 7 and 8 will affect the channel and thus the stability of the threshold voltage.
  • Step 1 providing a silicon wafer 200 as a substrate, and forming a silicon epitaxial layer 201 on the silicon substrate, as shown in FIG. 2A;
  • the semiconductor substrate includes the silicon wafer 200 and the silicon epitaxial layer 201;
  • the semiconductor substrate may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, and also include multiple layers composed of these semiconductors
  • the structure may be silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • Devices such as NMOS and / or PMOS may be formed on the semiconductor substrate.
  • a conductive member may also be formed in the semiconductor substrate, and the conductive member may be the gate, source, or drain of the transistor.
  • Step 2 Form a first oxide layer 202, and form a first oxide layer 202 on the silicon epitaxial layer 201.
  • the first oxide layer 202 is a thermal oxide layer TOX, as shown in FIG. 2B;
  • the first oxide layer 202 can be used for the first oxide layer 202, such as silicon dioxide.
  • the first oxide layer can be produced by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition) and the like.
  • Step 3 forming a trench, forming a trench in the first oxide layer 202 and the silicon epitaxial layer 201, as shown in FIG. 2C;
  • Step 4 forming a second oxide layer 203, forming a second oxide layer 203 in the trench, optionally, the second oxide layer 203 is a gate oxide layer, and the first oxide layer 202 remains in Above the silicon epitaxial layer 201, as shown in FIG. 2D;
  • the second oxide layer 203 may be made of various insulating materials, such as oxide, nitride, oxynitride, and the like.
  • the second oxide layer can be produced by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition) and the like.
  • the second oxide layer uses TEOS (ethyl orthosilicate, Si (OC 2 H 5 ) 4 ) oxide, that is, a silicon dioxide layer formed using TEOS.
  • TEOS ethyl orthosilicate, Si (OC 2 H 5 ) 4
  • the second insulating layer 304 is manufactured by a furnace tube process, the process temperature is 680 degrees exemplarily, and the thickness of the second insulating layer 304 is exemplarily
  • Step 5 filling polysilicon 204, depositing polysilicon 204 on the surfaces of the first oxide layer 202 and the second oxide layer 203, and filling the trenches and above the trenches, as shown in FIG. 2E;
  • Step 6 The polysilicon layer 204 is etched, and the polysilicon layer 204 is etched.
  • the height of the top of the etched polysilicon layer 204 is higher than the position of the top surface of the groove, as shown in FIG. 2F;
  • the polysilicon layer 204 is manufactured by methods such as furnace tube process, PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), etc., and is patterned by a photolithographic etching method commonly used in the art.
  • PVD Physical Vapor Deposition
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • other suitable materials may be used for the filling material in the trenches, which is not limited to polysilicon.
  • Step 7 forming a well region 205, and implanting a well region of a second doping type, such as a P well region 205, into the silicon epitaxial layer 201, as shown in FIG. 2G;
  • the well region 205 may also be a first doping type, such as an N-well region;
  • Step 8 forming a first source / drain region 206, and forming a first source / drain region 206 in the well region 205, where the first source / drain region 206 is of a first doping type, such as an N-type source / drain Area, as shown in Figure 2H;
  • the first source / drain region 206 may also be of a second doping type, such as a P-type source / drain region,
  • the source / drain region 206 is formed by implantation, and an ion implantation doping process may be used, which is to implant an ion beam accelerated to a certain high energy into the surface layer of a solid material to change the physical and chemical properties of the surface layer Craftsmanship.
  • Implanting corresponding impurity atoms into the semiconductor can change its surface conductivity or form a PN junction to form N-type source / drain regions, choose to implant phosphorus or arsenic into silicon
  • boron is implanted into silicon.
  • the choice of dopant is not limited to the above.
  • the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping
  • the hetero type is one of P type, low doped P-type, and high doped P + type
  • the second doped type is one of N type, low doped N- type, and high doped N + type.
  • the first doping type is one of N type, low doping N-type, and high doping N + type
  • the second doping type is P type, low doping P-type, and high doping P + type. one of them.
  • Step 9 forming an interlayer dielectric layer (ILD) 207, and forming an interlayer dielectric layer 207 above the trench and the first source / drain region 206, as shown in FIG. 2I;
  • ILD interlayer dielectric layer
  • the interlayer dielectric layer 207 is deposited between different layers to isolate the conductive layer to be deposited next.
  • the interlayer dielectric layer usually refers to the insulating layer between the semiconductor layer and the metal layer, which can be
  • the single-layer structure can be a multi-layer structure.
  • Step 10 a contact hole 208 is formed, and a CT contact hole 208 is formed on the interlayer dielectric layer 207.
  • the contact hole 208 extends from the top to the bottom of the interlayer dielectric layer 207, and the bottom of the contact hole 208 is lower than
  • the lower surface of the first source / drain region 206 and forming a second source / drain region 209 through the hole 208, the second source / drain region 209 is of a second doping type, such as a P-type source / drain region , As shown in Figure 2J;
  • the second source / drain region 209 may also be a first doping type, such as an N-type source / drain region, where the source / drain region is formed by implantation, and an ion implantation doping process may be used This process is to inject an ion beam accelerated to a certain high energy into the surface layer of a solid material to change the physical and chemical properties of the surface layer.
  • Implanting corresponding impurity atoms into the semiconductor can change its surface conductivity or form a PN junction to form N-type source / drain regions, choose to implant phosphorus or arsenic into silicon When forming P-type source / drain regions, choose to implant boron in silicon.
  • the choice of dopant is not limited to the above.
  • the first doping type and the second doping type generally refer to P-type or N-type, wherein the first doping type and the second doping type are opposite, such as the first doping
  • the hetero type is one of P type, low doped P-type, and high doped P + type
  • the second doped type is one of N type, low doped N- type, and high doped N + type.
  • the first doping type is one of N type, low doping N-type, and high doping N + type
  • the second doping type is P type, low doping P-type, and high doping P + type. one of them.
  • step 10 further includes the step of filling the CT contact hole 208;
  • Step 11 forming a cell structure, forming contact layers 2101,2102 above the interlayer dielectric layer 207 and below the silicon wafer 200 substrate, and forming leads through the contact layers 2101,2102 respectively, connected to
  • the source (S) and drain (D) form a cell structure, as shown in Figure 2K.
  • an etching method may be used, and the etching includes wet etching and / or dry ⁇ etched.
  • step 7 when performing the implantation operations in step 7, step 8, and step 10, respectively, a mask implantation method is used.
  • Step 3 to Step 4 Wet etching all the TOX oxide layer, while the embodiment of FIG. 2 retains the TOX oxide layer;
  • Step 5 to Step 6 Due to the relationship of the TOX oxide layer, the same etching method is used, and the embodiment of FIG. 2 obtains a structure in which the polysilicon gate plane is higher than the silicon plane;
  • the presence of the oxide layer makes the height of the top surface of the polysilicon layer higher than the height of the top surface of the silicon epitaxial layer, and the specific higher part can be determined by the thickness of the oxide layer.
  • the greater the thickness of the oxide layer, the top of the polysilicon layer is higher than the epitaxial layer The more the height, the height can be adjusted based on the existing process, compatible with the existing process;
  • the top of the polysilicon can block the implanted ions when the implantation step is performed. Therefore, the influence of the implantation step on the channel is reduced, thereby avoiding its influence on the threshold voltage.
  • the TOX oxide layer is retained to form a structure where the polysilicon gate plane is higher than the silicon plane when the polysilicon is etched.
  • the structure of the polysilicon gate plane higher than the silicon plane and the manufacturing method thereof proposed by the present invention solve the problem of unstable threshold voltage in mass production of devices. Compared with the current technology, the manufacturing process of the present invention does not add a mask or a new process step, and the manufacturing process is fully compatible.
  • the following refers to a schematic diagram of relevant steps of a method for manufacturing a VDMOS device according to an embodiment of the present invention shown in FIG. 3.
  • Step S101 providing a semiconductor substrate
  • Step S102 forming a trench in the semiconductor substrate
  • Step S103 depositing polysilicon in the trench
  • Step S104 the polysilicon layer is etched, and the top position of the etched polysilicon layer is higher than the top height position of the trench.
  • the present invention also provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; a polysilicon layer located in the trench at a top height position A position higher than the height of the top of the trench, optionally, further includes a well region formed in the semiconductor substrate.
  • a source / drain region is further included, and the source / drain region is formed in the well region.
  • the source / drain region includes a first source / drain region and a second source / drain region, and the first source / drain region and the second source / drain region have two doping types, wherein The doping type of the first source / drain is opposite to the doping type of the well region.
  • a contact layer is further formed, which is formed above and below the semiconductor device, respectively, connected to the source electrode and the drain electrode, thereby forming a cell structure.
  • the semiconductor device and the manufacturing method of the present invention can improve the threshold voltage stability under the premise that the manufacturing process is completely compatible without adding a mask or a process step.

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Abstract

一种半导体器件及其制造方法，包括：提供半导体衬底；在所述半导体衬底内形成沟槽；沉积多晶硅层，所述多晶硅层底部位于所述沟槽中；对所述多晶硅层进行刻蚀，刻蚀后的多晶硅层顶部高度位置高于所述沟槽的顶部高度位置。

Description

一种半导体器件及其制造方法 技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件结构及其制造方法。
背景技术
沟槽型VDMOS产品是较为广泛应用的功率器件，一方面，沟槽工艺的成熟使单元胞尺寸进一步下降，另一方面，由于沟槽区域穿过P型基区最下端，形成的沟道位于源区与漂移区之间，相比普通VDMOS消除JFET区，导通电阻大大减小，所以沟槽型VDMOS极大提高了MOS功率器件的性能。对于沟槽型VDMOS，如今采用的结构是沟槽内多晶硅栅平面低于硅平面，制造过程是刻蚀沟槽、生长栅氧、多晶硅淀积、多晶硅刻蚀、阱区形成、NSD形成、孔形成、金属电极形成、背面工艺。由于多晶硅刻蚀必须保证硅上方的多晶硅完全被刻蚀，否则器件将会存在如栅源短接等问题，所以，工艺设定当刻蚀到硅上方的氧化层时，增加一定刻蚀量，以保证所有硅上方的多晶硅完全被刻蚀。即形成的结构是沟槽内多晶硅栅平面低于硅平面，如此带来的问题是后继阱区注入与源区注入将会影响沟道，导致阈值电压不稳。
因此，本发明提出一种半导体器件结构及其制造方法，其多晶硅栅平面高于硅平面，解决阈值电压不稳的问题。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
针对的不足，本发明一方面提供一种一种半导体器件，包括：半导体衬底；沟槽，形成于所述半导体衬底中；多晶硅层，所述多晶硅层底部位于所述沟槽中，所述多晶硅顶部高度位置高于沟槽顶部高度位置。
本发明再一方面提供一种半导体制造方法，包括：提供半导体衬底；在 所述半导体衬底内形成沟槽；沉积多晶硅层，所述多晶硅层底部位于所述沟槽中；对所述多晶硅层进行刻蚀，刻蚀后的多晶硅层顶部高度位置高于所述沟槽的顶部高度位置。
本发明又一方面提供一种VDMOS器件，包括，半导体衬底；沟槽，形成于所述半导体衬底中；栅极，由多晶硅层构成，所述多晶硅层底部位于所述沟槽中，且其所述多晶硅顶部高度位置高于沟槽顶部高度位置，栅极平面高于半导体衬底平面；还包括接触层，分别形成于所述半导体器件的上方和下方，连接于源极和漏极，从而形成元胞结构。
本发明的半导体器件及其制造方法能够在制造工艺完全兼容且不增加掩模板或工艺步骤的前提下，提高阈值电压稳定性。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A至图1K示出了本发明一个实施方式的半导体器件的制造方法的相关步骤所获得的器件的剖面示意图；
图2A至图2K示出了本发明一个实施方式的半导体器件的制造方法的相关步骤所获得的器件的剖面示意图；
图3示出了本发明一个实施方式的流程示意图。
附图标记说明
100 200 硅片
101 201 硅外延层
102 202 第一氧化层
103 203 第二氧化层
104 204 多晶硅层
105 205 阱区
106 206 第一源/漏区
107 207 层间介电层
108 208 接触孔
109 209 第二源/漏区
1101 1102 2101 2102 接触层
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件 的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细步骤以及结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
为了解决前述的技术问题，本发明提供一种半导体器件及其制造方法，包括：半导体衬底；沟槽，形成于所述半导体衬底中；多晶硅层，位于所述沟槽中，且其顶部高度位置高于沟槽顶部高度位置，并且本发明的半导体器件及其制造方法能够在制造工艺完全兼容且不增加掩模板或工艺步骤的前提下，提高阈值电压稳定性。
下面参见图1至图1K所示出的本发明一个实施方式的半导体器件的制造方法的相关步骤所获得的器件的剖面示意图来说明VDMOS的制造过程。
步骤1，提供硅片100，作为基板，并在硅基板上形成硅外延层101，如图1A所示；
步骤2，形成第一氧化层102，在所述硅外延层101上形成第一氧化层102，可选地，所述第一氧化层102为热氧化层TOX，如图1B所示；
步骤3，形成沟槽，在所述第一氧化层102和所述硅外延层101内形成沟槽，如图1C所示；
可选择地，步骤3还包括：形成所述沟槽后，将所述硅外延层101上方的第一氧化层102去除；
步骤4，形成第二氧化层103，在所述硅外延层101的表面和沟槽内形成第二氧化层103，可选地，所述第二氧化层为栅氧化层，如图1D所示；
步骤5，填充多晶硅104，在所述栅氧化层103的表面沉积多晶硅104，对所述沟槽及沟槽上方进行填充，如图1E所示；
步骤6，刻蚀多晶硅104，对所述多晶硅层104进行刻蚀，刻蚀后的多晶硅层104顶部高度的位置低于所述凹槽的顶面位置，如图1F所示；
步骤7，形成阱区105，在所述硅外延层中注入形成P阱区，如图1G所示；
步骤8，形成第一源/漏区106，在所述阱区中注入形成N型源/漏区NSD，如图1H所示；
步骤9，形成层间介电层(ILD)107，在所述沟槽和第一源/漏区106上方形成层间介电层107，如图1I所示；
步骤10，形成孔108，在所述层间介电层上形成CT接触孔108，该接触孔108从层间介电层107的顶端向底部延伸，且该接触孔108的底部低于所述第一源/漏区106的下表面，并通过该接触孔108进行注入形成第二源/漏区109，即P型源/漏PSD，如图1J所示；
步骤11，形成元胞结构，在所述层间介电层107的上方和所述硅片100基板的下方形成接触层1101,1102，并且通过所述接触层1101,1102分别形成引线，连接于源极(S)和漏极(D)，从而形成元胞结构，如图1K所示。
前述实施方式的缺点如下：
制造过程中步骤5至步骤6过程中，使得硅上方的多晶硅104完全被刻蚀，如此，步骤7、8中阱区105注入与NSD106注入则会影响沟道，进而影响阈值电压的稳定性。
下面参见图2A至图2K所示出的本发明一个实施方式的VDMOS器件的制造方法的相关步骤所获得的器件的剖面示意图来说明VDMOS的又一制造过程。
步骤1，提供硅片200，作为基板，并在硅基板上形成硅外延层201，如图2A所示；
可选择地，半导体衬底包括所述硅片200和所述硅外延层201；
其中，半导体衬底可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。半导体衬底上可以形成有器件，例如NMOS和/或PMOS等。 同样，半导体衬底中还可以形成有导电构件，导电构件可以是晶体管的栅极、源极或漏极等等。
步骤2，形成第一氧化层202，在所述硅外延层201上形成第一氧化层202，可选地，所述第一氧化层202为热氧化层TOX，如图2B所示；
第一氧化层202可以采用各种氧化物，例如二氧化硅。第一氧化层可以通过诸如热氧化法、PVD(物理气相沉积)、CVD(化学气相沉积)、ALD(原子层沉积)等方法制作。
步骤3，形成沟槽，在所述第一氧化层202和所述硅外延层201内形成沟槽，如图2C所示；
步骤4，形成第二氧化层203，在所述沟槽内形成第二氧化层203，可选地，所述第二氧化层203为栅氧化层，所述第一氧化层202仍然保留在所述硅外延层201上方，如图2D所示；
第二氧化层203可以采用各种绝缘材料制作，例如氧化物、氮化物、氮氧化物等。第二氧化层可以通过诸如热氧化法、PVD(物理气相沉积)、CVD(化学气相沉积)、ALD(原子层沉积)等方法制作。
示例性地，第二氧化层采用TEOS(正硅酸乙酯，Si(OC 2H 5) 4)氧化物，即利用TEOS形成的二氧化硅层。示例性地，第二绝缘层304采用炉管工艺制作，工艺温度示例地为680度，第二绝缘层304厚度示例性地为
Figure PCTCN2019111661-appb-000001
步骤5，填充多晶硅204，在所述第一氧化层202和第二氧化层203的表面沉积多晶硅204，对所述沟槽及沟槽上方进行填充，如图2E所示；
步骤6，刻蚀多晶硅204，对所述多晶硅层204进行刻蚀，刻蚀后的多晶硅层204顶部高度的位置高于所述凹槽的顶面位置，如图2F所示；
所述多晶硅层204其通过诸如炉管工艺、PVD(物理气相沉积)、CVD(化学气相沉积)、ALD(原子层沉积)等方法制作，并通过本领域常用的光刻刻蚀方法图形化。当然，所述沟槽内的填充材料也可以采用其他合适的材料，而不限于多晶硅。
步骤7，形成阱区205，在所述硅外延层201中注入形成第二掺杂类型的阱区，比如P阱区205，如图2G所示；
可选地，该阱区205也可以是第一掺杂类型，比如N阱区；
步骤8，形成第一源/漏区206，在所述阱区205中形成第一源/漏区206，该第一源/漏区206为第一掺杂类型，比如，N型源/漏区，如图2H所示；
可选地，该第一源/漏区206也可以第二掺杂类型，比如P型源/漏区，
其中所述源/漏区206是通过注入方式形成的，可以采用离子注入掺杂工艺，该工艺是将加速到一定高能量的离子束注入固体材料表面层内，以改变表面层物理和化学性质的工艺。在半导体中注入相应的杂质原子(如在硅中注入硼、磷或砷等)，可改变其表面电导率或形成PN结，形成N型源/漏区时，选用在硅中注入磷或砷，而形成P型源/漏区时，选用在硅中注入硼，当然，掺杂剂的选择并不限于以上几种。
需要说明的是，本说明书中第一掺杂类型和第二掺杂类型泛指P型或N型，其中，所述第一掺杂类型和所述第二掺杂类型相反，比如第一掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一。
步骤9，形成层间介电层(ILD)207，在所述沟槽和第一源/漏区206上方形成层间介电层207，如图2I所示；
层间介电层207是沉积在不同层之间，用来和下一步要沉积的导电层做一隔离，层间介电层通常指位于半导体层和金属层之间的绝缘层，其可以为单层结构，可以为多层结构，通过对介电层自身参数的选择，比如介电系数，导热系数等，可以获得需要的导热性及RC延迟时间常数。
步骤10，形成接触孔208，在所述层间介电层207上形成CT接触孔208，该接触孔208从层间介电层207的顶端向底部延伸，且该接触孔208的底部低于所述第一源/漏区206的下表面，并通过该孔208进行形成第二源/漏区209，该第二源/漏区209为第二掺杂类型，比如P型源/漏区，如图2J所示；
可选地，该第二源/漏区209也可以是第一掺杂类型，比如N型源/漏区，其中所述源/漏区是通过注入方式形成的，可以采用离子注入掺杂工艺，该工艺是将加速到一定高能量的离子束注入固体材料表面层内，以改变表面层物理和化学性质的工艺。在半导体中注入相应的杂质原子(如在硅中注入硼、磷或砷等)，可改变其表面电导率或形成PN结，形成N型源/漏区时，选用在硅中注入磷或砷，而形成P型源/漏区时，选用在硅中注入硼，当然，掺杂剂的选择并不限于以上几种，
需要说明的是，本说明书中第一掺杂类型和第二掺杂类型泛指P型或N型，其中，所述第一掺杂类型和所述第二掺杂类型相反，比如第一掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二掺杂类型是N型，低掺 杂N-型，高掺杂N+型其中之一。或者相反地，第一掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一。
可选地，步骤10还包括CT接触孔208的填充步骤；
步骤11，形成元胞结构，在所述层间介电层207的上方和所述硅片200基板的下方形成接触层2101,2102，并且通过所述接触层2101,2102分别形成引线，连接于源极(S)和漏极(D)，从而形成元胞结构，如图2K所示。
可选择地，在步骤3，步骤6，步骤10中分别形成沟槽、多晶硅层的形成和/或接触孔的过程中，可以采用蚀刻的方法形成，所述蚀刻包括湿法蚀刻和/或干法蚀刻。
可选择地，在步骤7，步骤8，步骤10中分别执行注入操作时，采用掩膜注入的方式。
附图2所示的实施方式相较于附图1所示的实施方式而言，
1、步骤3到步骤4：为湿法刻蚀全部TOX氧化层，而附图2的实施方式保留TOX氧化层；
2、步骤5到步骤6：由于TOX氧化层存在的关系，采用相同刻蚀方式，附图2的实施方式得到多晶硅栅平面高于硅平面的结构；
氧化层的存在使得多晶硅顶部平面的高度高于硅外延层的顶面的高度，并且，其具体高出的部分可以由氧化层的厚度确定，氧化层的厚度越大，多晶硅顶部高于外延层的高度越多，因此，该高度可以在现有工艺的基础上得到调整，与现有工艺兼容；
3、步骤7、8注入过程将不会影响沟道，可使器件阈值电压稳定。
由于多晶硅顶部平面的高度相对较高，因此，在执行注入步骤时，所述多晶硅顶部能够对注入离子实现阻挡，因此，降低了注入步骤对沟道的影响，从而避免其对阈值电压的影响。
由此可见，采用保留TOX氧化层方式，在多晶硅刻蚀时，形成多晶硅栅平面高于硅平面的结构。本发明提出的多晶硅栅平面高于硅平面的结构及其制造方法解决器件量产制造中阈值电压不稳定的问题。并且本发明制造过程与当前技术相比，不增加掩模板或新的工艺步骤，制造工艺完全兼容。
下面参见图3所示出的本发明一个实施方式的VDMOS器件的制造方法的相关步骤示意图。
步骤S101，提供半导体衬底；
步骤S102，在所述半导体衬底内形成沟槽；
步骤S103，在所述沟槽内沉积多晶硅；
步骤S104，对所述多晶硅层进行刻蚀，刻蚀后的多晶硅层顶部高度位置高于所述沟槽的顶部高度位置。
在另一个实施例中，本发明还提供了一种半导体器件，包括：半导体衬底；沟槽，形成于所述半导体衬底中；多晶硅层，位于所述沟槽中，且其顶部高度位置高于沟槽顶部高度位置，可选地，还包括阱区，所述阱区形成于所述半导体衬底中。
可选地，还包括源/漏区，所述源/漏区形成于所述阱区中。
可选地，所述源/漏区包含第一源/漏区和第二源/漏区，所述第一源/漏区和第二源/漏区具有两种掺杂类型，其中，所述第一源/漏的掺杂类型与所述阱区的掺杂类型相反。
可选地，还包括接触层，分别形成于所述半导体器件的上方和下方，连接于源极和漏极，从而形成元胞结构。
并且本发明的半导体器件及其制造方法能够在制造工艺完全兼容且不增加掩模板或工艺步骤的前提下，提高阈值电压稳定性。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种半导体器件，包括：
    半导体衬底；
    沟槽，形成于所述半导体衬底中；
    多晶硅层，所述多晶硅层底部位于所述沟槽中，所述多晶硅顶部高度位置高于沟槽顶部高度位置。
  2. 如权利要求1所述的半导体器件，其中，还包括
    阱区，所述阱区形成于所述半导体衬底中。
  3. 如权利要求2所述的半导体器件，其中，还包括
    源/漏区，所述源/漏区形成于所述阱区中。
  4. 如权利要求3所述的半导体器件，其中，所述源/漏区包含第一源/漏区和第二源/漏区，所述第一源/漏区和第二源/漏区的掺杂类型相反，其中，所述第一源/漏的掺杂类型与所述阱区的掺杂类型相反。
  5. 如权利要求1-4任一项所述的半导体器件，其中，还包括接触层，分别形成于所述半导体器件的上方和下方，连接于源极和漏极，从而形成元胞结构。
  6. 一种半导体器件的制造方法，包括：
    提供半导体衬底；
    在所述半导体衬底内形成沟槽；
    沉积多晶硅层，所述多晶硅层底部位于所述沟槽中；
    对所述多晶硅层进行刻蚀，刻蚀后的多晶硅层顶部高度位置高于所述沟槽的顶部高度位置。
  7. 如权利要求6所述的制造方法，其中，还包括：在所述半导体衬底中形成阱区。
  8. 如权利要求7所述的制造方法，其中，还包括：在所述阱区中形成第一掺杂类型的源/漏区。
  9. 如权利要求8所述的制造方法，其中，
    还包括：在所述沟槽和所述第一源/漏区上方形成层间介电层。
  10. 如权利要求9所述的制造方法，其中，
    还包括：在所述层间介电层上形成接触孔，该接触孔从层间介电层的顶 端向底部延伸，且该接触孔的底部低于所述第一源/漏区的下表面，并通过该孔进行注入形成第二源/漏区，所述第二源/漏区的掺杂类型与第一源/漏区相反。
  11. 如权利要求10所述的制造方法，其中，还包括所述接触孔的填充步骤。
  12. 如权利要求9-11任一项所述的制造方法，其中，
    还包括：在所述层间介质层的上方和所述半导体衬底的下方形成接触层，并且通过所述接触层分别形成引线，连接于源极和漏极，从而形成元胞结构。
  13. 如权利要求6所述的制造方法，其中，所述在所述半导体衬底内形成沟槽的步骤之前还包括在所述衬底上形成第一氧化层的步骤；所述沉积多晶硅层的步骤包括在所述第一氧化层上沉积多晶硅层；所述对所述多晶硅层进行刻蚀的步骤包括刻蚀去除所述第一氧化层上的多晶硅，因第一氧化层高于沟槽从而刻蚀后在第一氧化层和沟槽之间留有多晶硅而使得多晶硅层顶部高度位置高于所述沟槽的顶部高度位置；所述对所述多晶硅层进行刻蚀的步骤之后还包括去除所述第一氧化层的步骤。
  14. 如权利要求13所述的制造方法，其中，还包括在所述沟槽内形成第二氧化层的步骤，所述沉积多晶硅层的步骤包括在所述第一氧化层和第二氧化层的表面沉积多晶硅。
  15. 一种VDMOS器件，包括：
    半导体衬底；
    沟槽，形成于所述半导体衬底中；
    栅极，由多晶硅层构成，所述多晶硅层底部位于所述沟槽中，且其所述多晶硅顶部高度位置高于沟槽顶部高度位置，栅极平面高于半导体衬底平面；
    还包括接触层，分别形成于所述半导体器件的上方和下方，连接于源极和漏极，从而形成元胞结构。
PCT/CN2019/111661 2018-10-18 2019-10-17 一种半导体器件及其制造方法 Ceased WO2020078419A1 (zh)

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US6031265A (en) * 1997-10-16 2000-02-29 Magepower Semiconductor Corp. Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area
US20120211826A1 (en) * 2011-02-22 2012-08-23 Yaojian Leng Trench DMOS Transistor with Reduced Gate-to-Drain Capacitance

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KR100791773B1 (ko) * 2006-12-27 2008-01-04 동부일렉트로닉스 주식회사 트랜치 게이트 모스 소자 제조 방법
CN206134689U (zh) * 2016-11-04 2017-04-26 无锡新洁能股份有限公司 高集成度的低压沟槽栅dmos器件

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Publication number Priority date Publication date Assignee Title
US5986304A (en) * 1997-01-13 1999-11-16 Megamos Corporation Punch-through prevention in trenched DMOS with poly-silicon layer covering trench corners
US6031265A (en) * 1997-10-16 2000-02-29 Magepower Semiconductor Corp. Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area
US20120211826A1 (en) * 2011-02-22 2012-08-23 Yaojian Leng Trench DMOS Transistor with Reduced Gate-to-Drain Capacitance

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