WO2020077897A1 - Goa 驱动电路及显示面板 - Google Patents

Goa 驱动电路及显示面板 Download PDF

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Publication number
WO2020077897A1
WO2020077897A1 PCT/CN2019/070903 CN2019070903W WO2020077897A1 WO 2020077897 A1 WO2020077897 A1 WO 2020077897A1 CN 2019070903 W CN2019070903 W CN 2019070903W WO 2020077897 A1 WO2020077897 A1 WO 2020077897A1
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Prior art keywords
transistor
pull
signal
goa
module
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Ceased
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PCT/CN2019/070903
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English (en)
French (fr)
Inventor
田新斌
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Publication of WO2020077897A1 publication Critical patent/WO2020077897A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • This application relates to the field of display technology, in particular to a GOA drive circuit and a display panel.
  • GOA Gate Driver On Array (array substrate row drive) technology is to integrate the TFT (Thin Film Transistor, thin film field effect transistor) in the GOA drive circuit on the array substrate, thereby eliminating the gate drive integrated circuit part that was originally arranged outside the array substrate. Reduce the cost of products from two aspects of material cost and process steps.
  • the GOA drive circuit In the existing GOA driving circuit, after the line scan signal of the current stage GOA unit is output, the low level of the line scan signal needs to be maintained for a period of time. However, due to the occurrence of abnormality in the GOA drive circuit, the GOA drive circuit cannot maintain the low level of the line scan signal after outputting the line scan signal of the current stage GOA unit, thereby affecting the operation of the GOA drive circuit.
  • An embodiment of the present application provides a GOA driving circuit and a display panel, which can enable the GOA driving circuit to maintain the low level of the line scanning signal after outputting the line scanning signal of the current stage GOA unit when the GOA circuit is abnormal.
  • the GOA driving circuit is composed of a cascade of multi-level GOA units. Each level of GOA units is used to drive a row of pixel units.
  • the current level of GOA units includes:
  • the pull-up control module is used to output a pull-up control signal according to the received line scan signal and stage transmission signal output by the upper-level GOA unit;
  • a pull-up module connected to the pull-up control module, for outputting the received high-frequency clock signal as the line scan signal of the current stage GOA unit according to the pull-up control signal;
  • a stage transmission module connected to the pull-up control module, is used to output the received high-frequency clock signal as a stage transmission signal of the current stage GOA unit according to the pull-up control signal;
  • a pull-down module connected to the pull-up control module and the pull-up module, is used to convert the pull-up control signal and the current-level GOA unit according to the received line scan signal output by the next-level GOA unit The line scan signal is pulled down to low level at the same time;
  • a pull-down maintenance module connected to the pull-up control module and the pull-up module, is used to maintain the pull-up control signal and the current line scan signal during the scan period of the pixel unit other than the current line At low level
  • An abnormality protection module connected to the pull-down maintenance module, is used to scan the pull-up control signal and the current line when the pull-up control signal is abnormal during the scan period of the pixel unit other than the current row The signal is pulled low again;
  • a bootstrap capacitor one end of the bootstrap capacitor is connected to the pull-up control signal, and the other end of the bootstrap capacitor is connected to the line scan signal of the current stage GOA unit;
  • the pull-up control module includes: a first transistor
  • the gate of the first transistor is connected to the cascade signal output by the upper-level GOA unit, the source of the first transistor is connected to the line scan signal output by the upper-level GOA unit, the first The drain of the transistor outputs the pull-up control signal;
  • the pull-up module includes: a second transistor
  • the gate of the second transistor is connected to the pull-up control signal, the source of the second transistor is connected to the high-frequency clock signal, and the drain of the second transistor is connected to output the row scan signal of the current stage GOA unit .
  • the stage transmission module includes: a third transistor
  • the gate of the third transistor is connected to the pull-up control signal, the source of the third transistor is connected to the high-frequency clock signal, and the drain of the third transistor is connected to output the staged signal of the current stage GOA unit .
  • the pull-down module includes: a fourth transistor and a fifth transistor;
  • the gate of the fourth transistor and the gate of the fifth transistor are both connected to the line scan signal output by the GOA unit of the next stage; the source of the fourth transistor and the source of the fifth transistor Both are connected to a low power signal; the drain of the fourth transistor is connected to the row scan signal of the current stage GOA unit, and the drain of the fifth transistor is connected to the pull-up control signal.
  • the pull-down maintenance module includes: a first pull-down maintenance unit and a second pull-down maintenance unit; the first pull-down maintenance unit and the second pull-down maintenance unit work alternately;
  • the first pull-down sustaining unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate, source, and source of the sixth transistor are all connected to a first high-frequency clock signal; the drain of the sixth transistor, the gate of the seventh transistor, and the first The drains of the eight transistors are connected to each other; the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor are all connected to the first pull-down Maintaining node connection; the gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-up control signal; the source of the eighth transistor, the source of the ninth transistor, all The source of the tenth transistor and the source of the eleventh transistor are both connected to a low power signal; the drain of the tenth transistor is connected to the line scan signal of the current stage GOA unit; the eleventh transistor The drain is connected to the pull-up control signal;
  • the second pull-down sustaining unit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor;
  • the gate and source of the twelfth transistor and the source of the thirteenth transistor are connected to the second high-frequency clock signal; the drain of the twelfth transistor and the gate of the thirteenth transistor And the drain of the fourteenth transistor are connected to each other; the drain of the thirteenth transistor, the drain of the fifteenth transistor, the gate of the sixteenth transistor, and the Both gates are connected to the second pull-down sustain node; the gates of the fourteenth transistor and the fifteenth transistor are both connected to the pull-up control signal; the source of the fourteenth transistor, The source of the fifteenth transistor, the source of the sixteenth transistor, and the source of the seventeenth transistor are all connected to a low power signal; the drain of the sixteenth transistor is connected to the current stage GOA The line scan signal of the cell; the drain of the seventeenth transistor is connected to the pull-up control signal;
  • the first low-frequency clock signal and the second low-frequency clock signal are two low-frequency signal sources with completely opposite phases.
  • the abnormality protection module includes: an eighteenth transistor;
  • the gate of the eighteenth transistor is connected to the line scan signals of all GOA cells after the current stage GOA cell, the source of the eighteenth transistor is connected to the pull-up control signal, and the seventeenth The drain of the transistor is connected to the first pull-down sustain node and the second pull-down sustain node.
  • the pull-up control module is further configured to output a pull-up control signal according to the received circuit start signal.
  • the pull-down module is further used to pull up the pull-up according to the received line scan signal of the second-level GOA unit
  • the control signal and the row scan signal of the GOA unit of the last stage are simultaneously pulled down to a low level.
  • An embodiment of the present application further provides a GOA driving circuit.
  • the GOA driving circuit is composed of a cascade of multi-level GOA units. Each level of GOA units is used to drive a row of pixel units.
  • the pull-up control module is used to output a pull-up control signal according to the received line scan signal and stage transmission signal output by the upper-level GOA unit;
  • a pull-up module connected to the pull-up control module, for outputting the received high-frequency clock signal as the line scan signal of the current stage GOA unit according to the pull-up control signal;
  • a stage transmission module connected to the pull-up control module, is used to output the received high-frequency clock signal as a stage transmission signal of the current stage GOA unit according to the pull-up control signal;
  • a pull-down module connected to the pull-up control module and the pull-up module, is used to convert the pull-up control signal and the current-level GOA unit according to the received line scan signal output by the next-level GOA unit The line scan signal is pulled down to low level at the same time;
  • a pull-down maintenance module connected to the pull-up control module and the pull-up module, is used to maintain the pull-up control signal and the current line scan signal during the scan period of the pixel unit other than the current line At low level
  • An abnormality protection module connected to the pull-down maintenance module, is used to scan the pull-up control signal and the current line when the pull-up control signal is abnormal during the scan period of the pixel unit other than the current row The signal is pulled low again;
  • a bootstrap capacitor one end of the bootstrap capacitor is connected to the pull-up control signal, and the other end of the bootstrap capacitor is connected to the line scan signal of the current stage GOA unit.
  • the pull-up control module includes: a first transistor
  • the gate of the first transistor is connected to the cascade signal output by the upper-level GOA unit, the source of the first transistor is connected to the line scan signal output by the upper-level GOA unit, the first The drain of the transistor outputs the pull-up control signal.
  • the pull-up module includes: a second transistor
  • the gate of the second transistor is connected to the pull-up control signal, the source of the second transistor is connected to the high-frequency clock signal, and the drain of the second transistor is connected to output the row scan signal of the current stage GOA unit .
  • the stage transmission module includes: a third transistor
  • the gate of the third transistor is connected to the pull-up control signal, the source of the third transistor is connected to the high-frequency clock signal, and the drain of the third transistor is connected to output the staged signal of the current stage GOA unit .
  • the pull-down module includes: a fourth transistor and a fifth transistor;
  • the gate of the fourth transistor and the gate of the fifth transistor are both connected to the line scan signal output by the GOA unit of the next stage; the source of the fourth transistor and the source of the fifth transistor Both are connected to a low power signal; the drain of the fourth transistor is connected to the row scan signal of the current stage GOA unit, and the drain of the fifth transistor is connected to the pull-up control signal.
  • the pull-down maintenance module includes: a first pull-down maintenance unit and a second pull-down maintenance unit; the first pull-down maintenance unit and the second pull-down maintenance unit work alternately;
  • the first pull-down sustaining unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate, source, and source of the sixth transistor are all connected to a first high-frequency clock signal; the drain of the sixth transistor, the gate of the seventh transistor, and the first The drains of the eight transistors are connected to each other; the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor are all connected to the first pull-down Maintaining node connection; the gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-up control signal; the source of the eighth transistor, the source of the ninth transistor, all The source of the tenth transistor and the source of the eleventh transistor are both connected to a low power signal; the drain of the tenth transistor is connected to the line scan signal of the current stage GOA unit; the eleventh transistor The drain is connected to the pull-up control signal;
  • the second pull-down sustaining unit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor;
  • the gate and source of the twelfth transistor and the source of the thirteenth transistor are connected to the second high-frequency clock signal; the drain of the twelfth transistor and the gate of the thirteenth transistor And the drain of the fourteenth transistor are connected to each other; the drain of the thirteenth transistor, the drain of the fifteenth transistor, the gate of the sixteenth transistor, and the Both gates are connected to the second pull-down sustain node; the gates of the fourteenth transistor and the fifteenth transistor are both connected to the pull-up control signal; the source of the fourteenth transistor, The source of the fifteenth transistor, the source of the sixteenth transistor, and the source of the seventeenth transistor are all connected to a low power signal; the drain of the sixteenth transistor is connected to the current stage GOA The line scan signal of the cell; the drain of the seventeenth transistor is connected to the pull-up control signal;
  • the first low-frequency clock signal and the second low-frequency clock signal are two low-frequency signal sources with completely opposite phases.
  • the abnormality protection module includes: a seventeenth transistor
  • the gate of the eighteenth transistor is connected to the line scan signals of all GOA cells after the current stage GOA cell, the source of the eighteenth transistor is connected to the pull-up control signal, and the seventeenth The drain of the transistor is connected to the first pull-down sustain node and the second pull-down sustain node.
  • the pull-up control module is further configured to output a pull-up control signal according to the received circuit start signal.
  • the pull-down module is further used to pull up the pull-up according to the received line scan signal of the second-level GOA unit
  • the control signal and the row scan signal of the GOA unit of the last stage are simultaneously pulled down to a low level.
  • An embodiment of the present application further provides a display panel, which includes a GOA driving circuit.
  • the GOA driving circuit is composed of a cascade of multi-level GOA units. Each level of GOA units is used to drive a row of pixel units.
  • the current level of GOA units includes:
  • the pull-up control module is used to output a pull-up control signal according to the received line scan signal and stage transmission signal output by the upper-level GOA unit;
  • a pull-up module connected to the pull-up control module, for outputting the received high-frequency clock signal as the line scan signal of the current stage GOA unit according to the pull-up control signal;
  • a stage transmission module connected to the pull-up control module, is used to output the received high-frequency clock signal as a stage transmission signal of the current stage GOA unit according to the pull-up control signal;
  • a pull-down module connected to the pull-up control module and the pull-up module, is used to convert the pull-up control signal and the current-level GOA unit according to the received line scan signal output by the next-level GOA unit The line scan signal is pulled down to low level at the same time;
  • a pull-down maintenance module connected to the pull-up control module and the pull-up module, is used to maintain the pull-up control signal and the current line scan signal during the scan period of the pixel unit other than the current line At low level
  • An abnormality protection module connected to the pull-down maintenance module, is used to scan the pull-up control signal and the current line when the pull-up control signal is abnormal during the scan period of the pixel unit other than the current row The signal is pulled low again;
  • a bootstrap capacitor one end of the bootstrap capacitor is connected to the pull-up control signal, and the other end of the bootstrap capacitor is connected to the line scan signal of the current stage GOA unit.
  • the pull-up control module includes: a first transistor
  • the gate of the first transistor is connected to the cascade signal output by the upper-level GOA unit, the source of the first transistor is connected to the line scan signal output by the upper-level GOA unit, the first The drain of the transistor outputs the pull-up control signal.
  • the pull-up module includes: a second transistor
  • the gate of the second transistor is connected to the pull-up control signal, the source of the second transistor is connected to the high-frequency clock signal, and the drain of the second transistor is connected to output the row scan signal of the current stage GOA unit .
  • the cascade transmission module includes: a third transistor
  • the gate of the third transistor is connected to the pull-up control signal, the source of the third transistor is connected to the high-frequency clock signal, and the drain of the third transistor is connected to output the staged signal of the current stage GOA unit .
  • the beneficial effects of the present invention are: the GOA driving circuit and the display panel provided by the present invention, by adding an abnormality protection module, in the scan period of the pixel unit other than the current row, when an abnormality occurs, the line of the current GOA unit can be scanned The signal and the pull-up control signal are maintained at a low level, thereby improving the stability of the GOA drive circuit.
  • FIG. 1 is a schematic structural diagram of a GOA driving circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a single-stage structure of a GOA driving circuit according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a single-stage circuit of the GOA driving circuit shown in FIG. 2;
  • FIG. 4 is a timing diagram of the single-stage circuit of the GOA driving circuit shown in FIG. 3;
  • FIG. 5 is a schematic diagram of the first-stage connection relationship of the single-stage architecture of the GOA driving circuit according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of the connection relationship of the last stage of the single-stage architecture of the GOA driving circuit according to an embodiment of the present application.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • FIG. 1 is a schematic structural diagram of a GOA driving circuit according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a single stage of a GOA driving circuit according to an embodiment of the present application.
  • the GOA driving circuit 10 of the embodiment of the present application is composed of a multi-level GOA unit stage 100, and each stage GOA unit 100 is used to drive a row of pixel units 200.
  • the current stage GOA unit 100 includes: The pull-up control module 101, the pull-up module 102, the stage transfer module 103, the pull-down module 104, the pull-down maintenance module 105, the abnormality protection module 106, and the bootstrap capacitor Cbt.
  • the pull-up control module 101 is used to output a pull-up control signal according to the received line scan signal G (N-1) and stage transmission signal ST (N-1) output by the upper-level GOA unit Q (N).
  • the pull-up module 102 is connected to the pull-up control module 101 for outputting the received high-frequency clock signal CK as the line scan signal G (N) of the current stage GOA unit according to the pull-up control signal Q (N).
  • the stage transmission module 103 is connected to the pull-up control module 101 and is used to output the received high-frequency clock signal CK as the stage transmission signal ST (N) of the current stage GOA unit according to the pull-up control signal Q (N).
  • the pull-down module 104 is connected to the pull-up control module 101 and the pull-up module 102, and is used to convert the pull-up control signal Q (N) and the pull-up control signal Q (N) according to the received line scan signal G (N-1) output by the next-level GOA unit.
  • the line scan signal G (N) of the GOA unit of the current stage is simultaneously pulled down to a low level.
  • the pull-down maintenance module 105 is connected to the pull-up control module 101 and the pull-up module 102, and is used to convert the pull-up control signal Q (N) and the current line scan signal G (N ) Maintained at a low level.
  • the abnormality protection module 106 is connected to the pull-down maintenance module 105, and is used to change the pull-up control signal Q (N) and the current stage when the pull-up control signal Q (N) is abnormal during the scan period of the pixel unit other than the current row.
  • the line scan signal G (N) is pulled down to the low level again.
  • One end of the bootstrap capacitor Cbt is connected to the pull-up control signal Q (N), and the other end of the bootstrap capacitor Cbt is connected to the line scan signal G (N) of the current stage GOA unit.
  • the pull-up control module 101 includes: a first transistor T1; a gate of the first transistor T1 is connected to a stage transmission signal ST (N-1) output by a previous stage GOA unit, and a The source is connected to the line scan signal G (N-1) output by the GOA unit at the previous stage, and the drain of the first transistor T1 outputs the pull-up control signal Q (N).
  • the pull-up module 102 includes: a second transistor T2; a gate of the second transistor T2 is connected to a pull-up control signal Q (N), a source of the second transistor T2 is connected to a high-frequency clock signal CK, and a drain of the second transistor T2
  • the line scan signal G (N) of the GOA unit of the current stage is continuously output.
  • the cascade transmission module 103 includes: a third transistor T3; a gate of the third transistor T3 is connected to the pull-up control signal Q (N), a source of the third transistor T3 is connected to the high-frequency clock signal CK, and a drain of the third transistor T3 Continuously output the cascade signal G (N) of the current stage GOA unit.
  • the pull-down module 104 includes: a fourth transistor T4 and a fifth transistor T5; both the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are connected to the line scan signal output by the next stage GOA unit; the fourth transistor T4 The source and the source of the fifth transistor T5 are both connected to the low power signal; the drain of the fourth transistor T4 is connected to the row scan signal of the current stage GOA unit, and the drain of the fifth transistor T5 is connected to the pull-up control signal.
  • the pull-down maintenance module 105 includes: a first pull-down maintenance unit 1051 and a second pull-down maintenance unit 1052; wherein,
  • the first pull-down sustaining unit 1051 includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11; a gate and a source of the sixth transistor T6 And the source of the seventh transistor T7 are connected to the first high-frequency clock signal LC1; the drain of the sixth transistor T6, the gate of the seventh transistor T7, and the drain of the eighth transistor T8 are connected to each other; the seventh transistor T7 The drain, the drain of the ninth transistor T9, the gate of the tenth transistor T10, and the gate of the eleventh transistor T11 are all connected to the first pull-down sustain node P (N); the gate of the eighth transistor T8 and the first The gates of the nine transistors T9 are connected to the pull-up control signal Q (N); the source of the eighth transistor T8, the source of the ninth transistor T9, the source of the tenth transistor T10, and the source of the eleventh transistor T11 Both are connected to the low power signal
  • the second pull-down sustaining unit 1052 includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17; a twelfth transistor T12
  • the gate, source and source of the thirteenth transistor T13 are connected to the second high-frequency clock signal LC2; the drain of the twelfth transistor T12, the gate of the thirteenth transistor T13 and the drain of the fourteenth transistor T14 Electrodes are connected to each other; the drain of the thirteenth transistor T13, the drain of the fifteenth transistor T15, the gate of the sixteenth transistor T16, and the gate of the seventeenth transistor T17 are all connected to the second pull-down sustain node K (N) Connection; the gate of the fourteenth transistor T14 and the gate of the fifteenth transistor T15 are connected to the pull-up control signal Q (N); the source of the fourteenth transistor T14, the source of the fifteenth transistor T15, the first
  • the abnormality protection module 106 includes: a seventeenth transistor T17; the gate of the seventeenth transistor T17 is connected to the line scan signals G (N + 1) / G (N + 2) / of all GOA units after the current stage GOA unit. ... / G (Last), the source of the eighteenth transistor T18 is connected to the pull-up control signal Q (N), and the drain of the eighteenth transistor T18 is connected to the first pull-down sustain node P (N) and the second pull-down Maintain node K (N).
  • FIG. 4 is a timing diagram of the single-stage circuit of the GOA driving circuit shown in FIG. 3.
  • the first A transistor T1 is turned on, and the scan signal G (N-1) of the GOA unit of the previous stage charges the bootstrap capacitor Cbt through the first transistor T1, so that the pull-up control signal Q (N) rises to a higher level.
  • stage signal ST (N-1) of the GOA unit in the upper stage turns to a low level
  • the first transistor T1 is turned off, and the pull-up control signal Q (N) maintains a higher level through the bootstrap capacitor Cbt.
  • the clock signal CK turns to a high level
  • the clock signal CK continues to charge the bootstrap capacitor Cbt through the second transistor T2, so that the pull-up control signal Q (N) reaches a higher level, the current stage of the GOA unit scan
  • the signal G (N) and the cascade signal ST (N) also turn high.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the constant voltage low level generated by the low power signal VSS pulls up the control signal Q (N ) Pulled low, the constant voltage low level generated by the low power signal VSS pulls the scan signal G (N) of the current stage GOA unit low.
  • the pull-up control signal Q (N) turns to low level
  • the seventh transistor T7 and the ninth transistor T9 are turned off, and at the same time, the high level generated by the first high-frequency clock signal LC1 causes the sixth transistor T6 and the eighth transistor T8 is turned on, the high level generated by the first high-frequency clock signal LC1 is transmitted to the first pull-down sustain node P (N), so that the tenth transistor T10 and the eleventh transistor T11 are turned on, and the constant voltage generated by the low power signal VSS is low
  • the level maintains the low level of the pull-up control signal Q (N) and the scan signal G (N) of the current stage GOA unit.
  • an abnormality protection module is added to maintain the line scan signal and the pull-up control signal of the current GOA unit at a low level when an abnormality occurs during the scan period of the pixel unit other than the current row, so that Improve the stability of the GOA drive circuit.
  • the pull-up control signal Q (N) transitions to a high level; as the GOA unit after the current stage GOA unit outputs a high level, the first Eighteen transistors are turned on, so that the high level of the pull-up control signal is transmitted to the first pull-down sustain node P (N), the tenth transistor T10 and the eleventh transistor T11 are turned on, and the pull-up control signal Q (N ) And the scan signal G (N) D level of the GOA unit of the current stage.
  • the first pull-down sustain unit 1051 and the second pull-down sustain unit 1052 work alternately, and the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are two low-frequency signal sources with completely opposite phases.
  • FIG. 5 is a schematic diagram of the first-stage connection relationship of the single-stage architecture of the GOA drive circuit according to an embodiment of the present application, that is, a schematic diagram of the GOA drive circuit connection relationship when N is 1.
  • the pull-up control module is also used to output a pull-up control signal according to the received circuit start signal; specifically, the gate and source of the first transistor are both connected to the circuit start signal.
  • FIG. 6 is a schematic diagram of the connection relationship of the last stage of the single-stage architecture of the GOA drive circuit according to an embodiment of the present application, that is, a schematic diagram of the connection relationship of the GOA drive circuit when N is the last stage of Last.
  • the pull-down module is also used to simultaneously pull down the pull-up control signal and the line scan signal of the last-level GOA unit to the low level according to the received line scan signal of the second-level GOA unit; specifically, the fourth The gate of the transistor and the gate of the fifth transistor are both connected to the line scan signal output by the second-stage GOA unit.
  • the GOA driving circuit is composed of a cascade of multi-level GOA units. Each level of GOA unit is used to drive a row of pixel units.
  • the current level of GOA unit includes: a pull-up control module, Pull module, level transmission module, pull-down module, pull-down maintenance module, abnormal protection module and bootstrap capacitor, by adding an abnormal protection module, in the scan cycle of the pixel unit other than the bank, when an abnormality occurs, the current level of GOA can be changed The row scanning signal and the pull-up control signal of the unit are maintained at a low level, thereby improving the stability of the GOA driving circuit.
  • the present application also provides a display panel including the GOA driving circuit described above.
  • a display panel including the GOA driving circuit described above.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种GOA驱动电路（10）及显示面板，其由多级GOA单元（100）级联构成，当前级GOA单元（100）包括：上拉控制模块（101）、上拉模块（102）、级传模块（103）、下拉模块（104）、下拉维持模块（105）、异常保护模块（106）以及自举电容（Cbt），通过增加一异常保护模块（106），在非本行像素单元的扫描周期内，当异常发生时，可以将当前级GOA单元（100）的行扫描信号（G(N)）以及上拉控制信号（Q(N)）维持在低电平。

Description

GOA驱动电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种GOA驱动电路及显示面板。
 背景技术
GOA(Gate Driver on Array，阵列基板行驱动) 技术是将GOA驱动电路中的TFT(Thin Film Transistor，薄膜场效应晶体管) 集成于阵列基板上，从而省掉原先设置在阵列基板外的栅极驱动集成电路部分，从材料成本和工艺步骤两个方面来降低产品的成本。
现有的GOA驱动电路中在输出当前级GOA单元的行扫描信号后，需在一段时间内维持行扫描信号的低电平。然而，由于GOA驱动电路中异常的发生，使得GOA驱动电路中在输出当前级GOA单元的行扫描信号后，不能维持行扫描信号的低电平，进而对GOA驱动电路的运作造成影响。
 技术问题
本申请实施例提供一种GOA驱动电路及显示面板，能够在GOA电路出现异常时，使得GOA驱动电路中在输出当前级GOA单元的行扫描信号后，维持行扫描信号的低电平。
 技术解决方案
本申请实施例提供一种GOA驱动电路，所述GOA驱动电路由多级GOA单元级联构成，每一级GOA单元用于驱动一行像素单元，当前级GOA单元包括：
上拉控制模块，用于根据接收到的由上一级GOA单元输出的行扫描信号与级传信号，输出上拉控制信号；
上拉模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将接收到的高频时钟信号输出为当前级GOA单元的行扫描信号；
级传模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将所述接收到的高频时钟信号输出为当前级GOA单元的级传信号；
下拉模块，与所述上拉控制模块以及所述上拉模块相连接，用于根据接收到的下一级GOA单元输出的行扫描信号，将所述上拉控制信号以及所述当前级GOA单元的行扫描信号同时下拉至低电平；
下拉维持模块，与所述上拉控制模块以及所述上拉模块相连接，用于在非本行像素单元的扫描周期内，将所述上拉控制信号以及所述当前级的行扫描信号维持在低电平；
异常保护模块，与所述下拉维持模块连接，用于在非本行像素单元的扫描周期内，当所述上拉控制信号异常时，将所述上拉控制信号以及所述当前级的行扫描信号再次下拉至低电平；以及
自举电容，所述自举电容的一端连接所述上拉控制信号，所述自举电容的另一端连接所述当前级GOA单元的行扫描信号；
所述上拉控制模块包括：第一晶体管；
所述第一晶体管的栅极连接由所述上一级GOA单元输出的级传信号，所述第一晶体管的源极连接由所述上一级GOA单元输出的行扫描信号，所述第一晶体管的漏极输出所述上拉控制信号；
所述上拉模块包括：第二晶体管；
所述第二晶体管的栅极连接所述上拉控制信号，所述第二晶体管的源极连接所述高频时钟信号，所述第二晶体管的漏极连输出当前级GOA单元的行扫描信号。
在本申请所述的GOA驱动电路中，所述级传模块包括：第三晶体管；
所述第三晶体管的栅极连接所述上拉控制信号，所述第三晶体管的源极连接所述高频时钟信号，所述第三晶体管的漏极连输出当前级GOA单元的级传信号。
在本申请所述的GOA驱动电路中，所述下拉模块包括：第四晶体管与第五晶体管；
所述第四晶体管的栅极与所述第五晶体管的栅极均连接由所述下一级GOA单元输出的行扫描信号；所述第四晶体管的源极与所述第五晶体管的源极均连接低电源信号；所述第四晶体管的漏极连接所述当前级GOA单元的行扫描信号，所述第五晶体管的漏极连接所述上拉控制信号。
在本申请所述的GOA驱动电路中，所述下拉维持模块包括：第一下拉维持单元与第二下拉维持单元；所述第一下拉维持单元与所述第二下拉维持单元交替工作；
所述第一下拉维持单元包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管；
所述第六晶体管的栅极、源极以及所述第七晶体管的源极均连接第一高频时钟信号；所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极相互连接；所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极以及所述第十一晶体管的栅极均与第一下拉维持节点连接；所述第八晶体管的栅极与所述第九晶体管的栅极均与所述上拉控制信号连接；所述第八晶体管的源极、所述第九晶体管的源极、所述第十晶体管的源极以及所述第十一晶体管的源极均连接低电源信号；所述第十晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十一晶体管的漏极连接所述上拉控制信号；
所述第二下拉维持单元包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管；
所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均连接第二高频时钟信号；所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十四晶体管的漏极相互连接；所述第十三晶体管的漏极、所述第十五晶体管的漏极、所述第十六晶体管的栅极以及所述第十七晶体管的栅极均与第二下拉维持节点连接；所述第十四晶体管的栅极与所述第十五晶体管的栅极均与所述上拉控制信号连接；所述第十四晶体管的源极、所述第十五晶体管的源极、所述第十六晶体管的源极以及所述第十七晶体管的源极均连接低电源信号；所述第十六晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十七晶体管的漏极连接所述上拉控制信号；
所述第一低频时钟信号与所述第二低频时钟信号是两个相位完全相反的低频信号源。
在本申请所述的GOA驱动电路中，所述异常保护模块包括：第十八晶体管；
所述第十八晶体管的栅极连接所述当前级GOA单元之后的所有GOA单元的行扫描信号，所述第十八晶体管的源极源极连接所述上拉控制信号，所述第十七晶体管的漏极连接所述第一下拉维持节点以及所述第二下拉维持节点。
在本申请所述的GOA驱动电路中，所述GOA驱动电路的第一级连接关系中，所述上拉控制模块接还用于根据接收到的电路启动信号，输出上拉控制信号。
在本申请所述的GOA驱动电路中，所述GOA驱动电路的最后一级连接关系中，所述下拉模块还用于根据接收到的第二级GOA单元的行扫描信号，将所述上拉控制信号以及所述最后一级GOA单元的行扫描信号同时下拉至低电平。
本申请实施例还提供一种GOA驱动电路，所述GOA驱动电路由多级GOA单元级联构成，每一级GOA单元用于驱动一行像素单元，当前级GOA单元包括：
上拉控制模块，用于根据接收到的由上一级GOA单元输出的行扫描信号与级传信号，输出上拉控制信号；
上拉模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将接收到的高频时钟信号输出为当前级GOA单元的行扫描信号；
级传模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将所述接收到的高频时钟信号输出为当前级GOA单元的级传信号；
下拉模块，与所述上拉控制模块以及所述上拉模块相连接，用于根据接收到的下一级GOA单元输出的行扫描信号，将所述上拉控制信号以及所述当前级GOA单元的行扫描信号同时下拉至低电平；
下拉维持模块，与所述上拉控制模块以及所述上拉模块相连接，用于在非本行像素单元的扫描周期内，将所述上拉控制信号以及所述当前级的行扫描信号维持在低电平；
异常保护模块，与所述下拉维持模块连接，用于在非本行像素单元的扫描周期内，当所述上拉控制信号异常时，将所述上拉控制信号以及所述当前级的行扫描信号再次下拉至低电平；以及
自举电容，所述自举电容的一端连接所述上拉控制信号，所述自举电容的另一端连接所述当前级GOA单元的行扫描信号。
在本申请所述的GOA驱动电路中，所述上拉控制模块包括：第一晶体管；
所述第一晶体管的栅极连接由所述上一级GOA单元输出的级传信号，所述第一晶体管的源极连接由所述上一级GOA单元输出的行扫描信号，所述第一晶体管的漏极输出所述上拉控制信号。
在本申请所述的GOA驱动电路中，所述上拉模块包括：第二晶体管；
所述第二晶体管的栅极连接所述上拉控制信号，所述第二晶体管的源极连接所述高频时钟信号，所述第二晶体管的漏极连输出当前级GOA单元的行扫描信号。
在本申请所述的GOA驱动电路中，所述级传模块包括：第三晶体管；
所述第三晶体管的栅极连接所述上拉控制信号，所述第三晶体管的源极连接所述高频时钟信号，所述第三晶体管的漏极连输出当前级GOA单元的级传信号。
在本申请所述的GOA驱动电路中，所述下拉模块包括：第四晶体管与第五晶体管；
所述第四晶体管的栅极与所述第五晶体管的栅极均连接由所述下一级GOA单元输出的行扫描信号；所述第四晶体管的源极与所述第五晶体管的源极均连接低电源信号；所述第四晶体管的漏极连接所述当前级GOA单元的行扫描信号，所述第五晶体管的漏极连接所述上拉控制信号。
在本申请所述的GOA驱动电路中，所述下拉维持模块包括：第一下拉维持单元与第二下拉维持单元；所述第一下拉维持单元与所述第二下拉维持单元交替工作；
所述第一下拉维持单元包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管；
所述第六晶体管的栅极、源极以及所述第七晶体管的源极均连接第一高频时钟信号；所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极相互连接；所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极以及所述第十一晶体管的栅极均与第一下拉维持节点连接；所述第八晶体管的栅极与所述第九晶体管的栅极均与所述上拉控制信号连接；所述第八晶体管的源极、所述第九晶体管的源极、所述第十晶体管的源极以及所述第十一晶体管的源极均连接低电源信号；所述第十晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十一晶体管的漏极连接所述上拉控制信号；
所述第二下拉维持单元包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管；
所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均连接第二高频时钟信号；所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十四晶体管的漏极相互连接；所述第十三晶体管的漏极、所述第十五晶体管的漏极、所述第十六晶体管的栅极以及所述第十七晶体管的栅极均与第二下拉维持节点连接；所述第十四晶体管的栅极与所述第十五晶体管的栅极均与所述上拉控制信号连接；所述第十四晶体管的源极、所述第十五晶体管的源极、所述第十六晶体管的源极以及所述第十七晶体管的源极均连接低电源信号；所述第十六晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十七晶体管的漏极连接所述上拉控制信号；
所述第一低频时钟信号与所述第二低频时钟信号是两个相位完全相反的低频信号源。
在本申请所述的GOA驱动电路中，所述异常保护模块包括：第十七晶体管；
所述第十八晶体管的栅极连接所述当前级GOA单元之后的所有GOA单元的行扫描信号，所述第十八晶体管的源极源极连接所述上拉控制信号，所述第十七晶体管的漏极连接所述第一下拉维持节点以及所述第二下拉维持节点。
在本申请所述的GOA驱动电路中，所述GOA驱动电路的第一级连接关系中，所述上拉控制模块接还用于根据接收到的电路启动信号，输出上拉控制信号。
在本申请所述的GOA驱动电路中，所述GOA驱动电路的最后一级连接关系中，所述下拉模块还用于根据接收到的第二级GOA单元的行扫描信号，将所述上拉控制信号以及所述最后一级GOA单元的行扫描信号同时下拉至低电平。
本申请实施例还提供一种显示面板，其包括GOA驱动电路，所述GOA驱动电路由多级GOA单元级联构成，每一级GOA单元用于驱动一行像素单元，当前级GOA单元包括：
上拉控制模块，用于根据接收到的由上一级GOA单元输出的行扫描信号与级传信号，输出上拉控制信号；
上拉模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将接收到的高频时钟信号输出为当前级GOA单元的行扫描信号；
级传模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将所述接收到的高频时钟信号输出为当前级GOA单元的级传信号；
下拉模块，与所述上拉控制模块以及所述上拉模块相连接，用于根据接收到的下一级GOA单元输出的行扫描信号，将所述上拉控制信号以及所述当前级GOA单元的行扫描信号同时下拉至低电平；
下拉维持模块，与所述上拉控制模块以及所述上拉模块相连接，用于在非本行像素单元的扫描周期内，将所述上拉控制信号以及所述当前级的行扫描信号维持在低电平；
异常保护模块，与所述下拉维持模块连接，用于在非本行像素单元的扫描周期内，当所述上拉控制信号异常时，将所述上拉控制信号以及所述当前级的行扫描信号再次下拉至低电平；以及
自举电容，所述自举电容的一端连接所述上拉控制信号，所述自举电容的另一端连接所述当前级GOA单元的行扫描信号。
在本申请所述的显示面板中，所述上拉控制模块包括：第一晶体管；
所述第一晶体管的栅极连接由所述上一级GOA单元输出的级传信号，所述第一晶体管的源极连接由所述上一级GOA单元输出的行扫描信号，所述第一晶体管的漏极输出所述上拉控制信号。
在本申请所述的显示面板中，所述上拉模块包括：第二晶体管；
所述第二晶体管的栅极连接所述上拉控制信号，所述第二晶体管的源极连接所述高频时钟信号，所述第二晶体管的漏极连输出当前级GOA单元的行扫描信号。
在本申请所述的显示面板中，所述级传模块包括：第三晶体管；
所述第三晶体管的栅极连接所述上拉控制信号，所述第三晶体管的源极连接所述高频时钟信号，所述第三晶体管的漏极连输出当前级GOA单元的级传信号。
 有益效果
本发明的有益效果为：本发明提供的GOA驱动电路及显示面板，通过增加一异常保护模块，在非本行像素单元的扫描周期内，当异常发生时，可以将当前级GOA单元的行扫描信号以及上拉控制信号维持在低电平，从而可以提高GOA驱动电路的稳定性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例的GOA驱动电路结构示意图；
图2为本申请实施例的GOA驱动电路的单级结构示意图；
图3为图2所示的GOA驱动电路的单级电路示意图；
图4为图3所示的GOA驱动电路的单级电路的时序示意图；
图5为本申请实施例的GOA驱动电路的单级架构第一级连接关系示意图；
图6为本申请实施例的GOA驱动电路的单级架构最后一级连接关系示意图。
 本发明的实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
请参阅图1、图2，图1为本申请实施例的GOA驱动电路结构示意图；图2为本申请实施例的GOA驱动电路的单级结构示意图。结合图1、图2所示，本申请实施例的GOA驱动电路10由多级GOA单元级100联构成，每一级GOA单元100用于驱动一行像素单元200，当前级GOA单元100包括：上拉控制模块101、上拉模块102、级传模块103、下拉模块104、下拉维持模块105、异常保护模块106以及自举电容Cbt。
请继续参阅图2，上拉控制模块101用于根据接收到的由上一级GOA单元输出的行扫描信G(N-1)与级传信号ST(N-1)，输出上拉控制信号Q(N)。
上拉模块102与上拉控制模块101相连接，用于根据上拉控制信号Q(N)，将接收到的高频时钟信号CK输出为当前级GOA单元的行扫描信号G(N)。
级传模块103与上拉控制模块101相连接，用于根据上拉控制信号Q(N)，将接收到的高频时钟信号CK输出为当前级GOA单元的级传信号ST(N)。
下拉模块104与上拉控制模块101以及上拉模块102相连接，用于根据接收到的下一级GOA单元输出的行扫描信号G(N-1)，将上拉控制信号Q(N)以及当前级GOA单元的行扫描信号G(N)同时下拉至低电平。
下拉维持模块105与上拉控制模块101以及上拉模块102相连接，用于在非本行像素单元的扫描周期内，将上拉控制信号Q(N)以及当前级的行扫描信号G(N)维持在低电平。
异常保护模块106，与下拉维持模块105连接，用于在非本行像素单元的扫描周期内，当上拉控制信号Q(N)异常时，将上拉控制信号Q(N)以及当前级的行扫描信号G(N)再次下拉至低电平。自举电容Cbt的一端连接上拉控制信号Q(N)，自举电容Cbt的另一端连接当前级GOA单元的行扫描信号G(N)。
进一步的，请参阅图3，图3为图2所示的GOA驱动电路的单级电路示意图。如图3所示，该上拉控制模块101包括：第一晶体管T1；第一晶体管T1的栅极连接由上一级GOA单元输出的级传信号ST(N-1)，第一晶体管T1的源极连接由上一级GOA单元输出的行扫描信号G(N-1)，第一晶体管T1的漏极输出上拉控制信号Q(N)。
该上拉模块102包括：第二晶体管T2；第二晶体管T2的栅极连接上拉控制信号Q(N)，第二晶体管T2的源极连接高频时钟信号CK，第二晶体管T2的漏极连输出当前级GOA单元的行扫描信号G(N)。
该级传模块103包括：第三晶体管T3；第三晶体管T3的栅极连接上拉控制信号Q(N)，第三晶体管T3的源极连接高频时钟信号CK，第三晶体管T3的漏极连输出当前级GOA单元的级传信号G(N)。
该下拉模块104包括：第四晶体管T4与第五晶体管T5；第四晶体管T4的栅极与第五晶体管T5的栅极均连接由下一级GOA单元输出的行扫描信号；第四晶体管T4的源极与第五晶体管T5的源极均连接低电源信号；第四晶体管T4的漏极连接当前级GOA单元的行扫描信号，第五晶体管T5的漏极连接上拉控制信号。
该下拉维持模块105包括：第一下拉维持单元1051与第二下拉维持单元1052；其中，
该第一下拉维持单元1051包括：第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11；第六晶体管T6的栅极、源极以及第七晶体管T7的源极均连接第一高频时钟信号LC1；第六晶体管T6的漏极、第七晶体管T7的栅极以及第八晶体管T8的漏极相互连接；第七晶体管T7的漏极、第九晶体管T9的漏极、第十晶体管T10的栅极以及第十一晶体管T11的栅极均与第一下拉维持节点P(N)连接；第八晶体管T8的栅极与第九晶体管T9的栅极均与上拉控制信号Q(N)连接；第八晶体管T8的源极、第九晶体管T9的源极、第十晶体管T10的源极以及第十一晶体管T11的源极均连接低电源信号VSS；第十晶体管T10的漏极连接当前级GOA单元的行扫描信号G(N)；第十一晶体管T11的漏极连接上拉控制信号Q(N)。
该第二下拉维持单元1052包括：第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17；第十二晶体管T12的栅极、源极以及第十三晶体管T13的源极均连接第二高频时钟信号LC2；第十二晶体管T12的漏极、第十三晶体管T13的栅极以及第十四晶体管T14的漏极相互连接；第十三晶体管T13的漏极、第十五晶体管T15的漏极、第十六晶体管T16的栅极以及第十七晶体管T17的栅极均与第二下拉维持节点K(N)连接；第十四晶体管T14的栅极与第十五晶体管T15的栅极均与上拉控制信号Q(N)连接；第十四晶体管T14的源极、第十五晶体管T15的源极、第十六晶体管T16的源极以及第十七晶体管T17的源极均连接低电源信号VSS；第十六晶体管T16的漏极连接当前级GOA单元的行扫描信号G(N)；第十七晶体管T17的漏极连接上拉控制信号Q(N)；
该异常保护模块106包括：第十七晶体管T17；第十七晶体管T17的栅极连接当前级GOA单元之后的所有GOA单元的行扫描信号G(N+1)/G(N+2)/……/G(Last)，第十八晶体管T18的源极源极连接上拉控制信号Q(N)，第十八晶体管T18的漏极连接第一下拉维持节点P(N)以及第二下拉维持节点K(N)。
请参阅图4，图4为图3所示的GOA驱动电路的单级电路的时序示意图。结合图3、图4所示，当上一级GOA单元的级传信号ST(N-1)为高电平，上一级GOA单元的扫描信号G(N-1)为高电平时，第一晶体管T1导通，上一级GOA单元的扫描信号G(N-1)通过第一晶体管T1给自举电容Cbt充电，使得上拉控制信号Q(N)上升到一较高的电平。
随后上一级GOA单元的级传信号ST(N-1)转为低电平，第一晶体管T1关闭，上拉控制信号Q(N)通过自举电容Cbt维持一较高的电平。同时，时钟信号CK转为高电平，时钟信号CK通过第二晶体管T2继续给自举电容Cbt充电，使得上拉控制信号Q(N)达到一更高的电平，当前级GOA单元的扫描信号G(N)和级传信号ST(N)也转为高电平。
当下一级GOA单元的扫描信号G(N+1)转为高电平时，第四晶体管T4和第五晶体管T5打开，低电源信号VSS产生的恒压低电平将上拉控制信号Q(N)拉低，低电源信号VSS产生的恒压低电平将当前级GOA单元的扫描信号G(N)拉低。
由于上拉控制信号Q(N)转为低电平，使得第七晶体管T7和第九晶体管T9关闭，同时，第一高频时钟信号LC1产生的高电平使得第六晶体管T6和第八晶体管T8打开，第一高频时钟信号LC1产生的高电平传至第一下拉维持节点P(N)，使得第十晶体管T10和第十一晶体管T11打开，低电源信号VSS产生的恒压低电平维持上拉控制信号Q(N)和当前级GOA单元的扫描信号G(N)的低电平。
然而，由于GOA驱动电路容易产生异常，也即，在非本行像素单元的扫描周期内，上拉控制信号Q（N）容易跳变至高电平，从而影响GOA驱动电路的正常运作。本申请实施例通过增加一异常保护模块，在非本行像素单元的扫描周期内，当异常发生时，可以将当前级GOA单元的行扫描信号以及上拉控制信号维持在低电平，从而可以提高GOA驱动电路的稳定性。
具体的，当异常产生，也即在非本行像素单元的扫描周期内，上拉控制信号Q(N)跳变至高电平；随着当前级GOA单元之后的GOA单元输出高电平，第十八晶体管打开，从而上拉控制信号的高电平传至第一下拉维持节点P(N),第十晶体管T10和第十一晶体管T11打开，进而可以继续维持上拉控制信号Q(N)和当前级GOA单元的扫描信号G(N)D第电平。
在一些实施例中，第一下拉维持单元1051与第二下拉维持单元1052交替工作，且，第一低频时钟信号LC1与第二低频时钟信号LC2是两个相位完全相反的低频信号源。
在一些实施例中，请参阅图5并结合图3，图5为本申请实施例的GOA驱动电路的单级架构第一级连接关系示意图，即N为1时的GOA驱动电路连接关系示意图。其中，该上拉控制模块接还用于根据接收到的电路启动信号，输出上拉控制信号；具体的，该第一晶体管的栅极、源极均连接电路启动信号。
请参阅图6并结合图3，图6为本申请实施例的GOA驱动电路的单级架构最后一级连接关系示意图，即N为最后一级Last时的GOA驱动电路连接关系示意图。其中，该下拉模块还用于根据接收到的第二级GOA单元的行扫描信号，将上拉控制信号以及最后一级GOA单元的行扫描信号同时下拉至低电平；具体的，该第四晶体管的栅极与第五晶体管的栅极均连接第二级GOA单元输出的行扫描信号。
本申请提供一种GOA驱动电路及显示面板，所述GOA驱动电路由多级GOA单元级联构成，每一级GOA单元用于驱动一行像素单元，当前级GOA单元包括：上拉控制模块、上拉模块、级传模块、下拉模块、下拉维持模块、异常保护模块以及自举电容，通过增加一异常保护模块，在非本行像素单元的扫描周期内，当异常发生时，可以将当前级GOA单元的行扫描信号以及上拉控制信号维持在低电平，从而可以提高GOA驱动电路的稳定性。
本申请还提供一种显示面板，该显示面板包括以上所述的GOA驱动电路，具体可参照以上，在此不做赘述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种GOA驱动电路，其中，所述GOA驱动电路由多级GOA单元级联构成，每一级GOA单元用于驱动一行像素单元，当前级GOA单元包括：
    上拉控制模块，用于根据接收到的由上一级GOA单元输出的行扫描信号与级传信号，输出上拉控制信号；
    上拉模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将接收到的高频时钟信号输出为当前级GOA单元的行扫描信号；
    级传模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将所述接收到的高频时钟信号输出为当前级GOA单元的级传信号；
    下拉模块，与所述上拉控制模块以及所述上拉模块相连接，用于根据接收到的下一级GOA单元输出的行扫描信号，将所述上拉控制信号以及所述当前级GOA单元的行扫描信号同时下拉至低电平；
    下拉维持模块，与所述上拉控制模块以及所述上拉模块相连接，用于在非本行像素单元的扫描周期内，将所述上拉控制信号以及所述当前级的行扫描信号维持在低电平；
    异常保护模块，与所述下拉维持模块连接，用于在非本行像素单元的扫描周期内，当所述上拉控制信号异常时，将所述上拉控制信号以及所述当前级的行扫描信号再次下拉至低电平；以及
    自举电容，所述自举电容的一端连接所述上拉控制信号，所述自举电容的另一端连接所述当前级GOA单元的行扫描信号；
    所述上拉控制模块包括：第一晶体管；
    所述第一晶体管的栅极连接由所述上一级GOA单元输出的级传信号，所述第一晶体管的源极连接由所述上一级GOA单元输出的行扫描信号，所述第一晶体管的漏极输出所述上拉控制信号；
    所述上拉模块包括：第二晶体管；
    所述第二晶体管的栅极连接所述上拉控制信号，所述第二晶体管的源极连接所述高频时钟信号，所述第二晶体管的漏极连输出当前级GOA单元的行扫描信号。
  2. 根据权利要求1所述的GOA驱动电路，其中，所述级传模块包括：第三晶体管；
    所述第三晶体管的栅极连接所述上拉控制信号，所述第三晶体管的源极连接所述高频时钟信号，所述第三晶体管的漏极连输出当前级GOA单元的级传信号。
  3. 根据权利要求1所述的GOA驱动电路，其中，所述下拉模块包括：第四晶体管与第五晶体管；
    所述第四晶体管的栅极与所述第五晶体管的栅极均连接由所述下一级GOA单元输出的行扫描信号；所述第四晶体管的源极与所述第五晶体管的源极均连接低电源信号；所述第四晶体管的漏极连接所述当前级GOA单元的行扫描信号，所述第五晶体管的漏极连接所述上拉控制信号。
  4. 根据权利要求1所述的GOA驱动电路，其中，所述下拉维持模块包括：第一下拉维持单元与第二下拉维持单元；所述第一下拉维持单元与所述第二下拉维持单元交替工作；
    所述第一下拉维持单元包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管；
    所述第六晶体管的栅极、源极以及所述第七晶体管的源极均连接第一高频时钟信号；所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极相互连接；所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极以及所述第十一晶体管的栅极均与第一下拉维持节点连接；所述第八晶体管的栅极与所述第九晶体管的栅极均与所述上拉控制信号连接；所述第八晶体管的源极、所述第九晶体管的源极、所述第十晶体管的源极以及所述第十一晶体管的源极均连接低电源信号；所述第十晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十一晶体管的漏极连接所述上拉控制信号；
    所述第二下拉维持单元包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管；
    所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均连接第二高频时钟信号；所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十四晶体管的漏极相互连接；所述第十三晶体管的漏极、所述第十五晶体管的漏极、所述第十六晶体管的栅极以及所述第十七晶体管的栅极均与第二下拉维持节点连接；所述第十四晶体管的栅极与所述第十五晶体管的栅极均与所述上拉控制信号连接；所述第十四晶体管的源极、所述第十五晶体管的源极、所述第十六晶体管的源极以及所述第十七晶体管的源极均连接低电源信号；所述第十六晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十七晶体管的漏极连接所述上拉控制信号；
    所述第一低频时钟信号与所述第二低频时钟信号是两个相位完全相反的低频信号源。
  5. 根据权利要求3所述的GOA驱动电路，其中，所述异常保护模块包括：第十八晶体管；
    所述第十八晶体管的栅极连接所述当前级GOA单元之后的所有GOA单元的行扫描信号，所述第十八晶体管的源极源极连接所述上拉控制信号，所述第十七晶体管的漏极连接所述第一下拉维持节点以及所述第二下拉维持节点。
  6. 根据权利要求5所述的GOA驱动电路，其中，所述GOA驱动电路的第一级连接关系中，所述上拉控制模块接还用于根据接收到的电路启动信号，输出上拉控制信号。
  7. 根据权利要求5所述的GOA驱动电路，其中，所述GOA驱动电路的最后一级连接关系中，所述下拉模块还用于根据接收到的第二级GOA单元的行扫描信号，将所述上拉控制信号以及所述最后一级GOA单元的行扫描信号同时下拉至低电平。
  8. 一种GOA驱动电路，其中，所述GOA驱动电路由多级GOA单元级联构成，每一级GOA单元用于驱动一行像素单元，当前级GOA单元包括：
    上拉控制模块，用于根据接收到的由上一级GOA单元输出的行扫描信号与级传信号，输出上拉控制信号；
    上拉模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将接收到的高频时钟信号输出为当前级GOA单元的行扫描信号；
    级传模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将所述接收到的高频时钟信号输出为当前级GOA单元的级传信号；
    下拉模块，与所述上拉控制模块以及所述上拉模块相连接，用于根据接收到的下一级GOA单元输出的行扫描信号，将所述上拉控制信号以及所述当前级GOA单元的行扫描信号同时下拉至低电平；
    下拉维持模块，与所述上拉控制模块以及所述上拉模块相连接，用于在非本行像素单元的扫描周期内，将所述上拉控制信号以及所述当前级的行扫描信号维持在低电平；
    异常保护模块，与所述下拉维持模块连接，用于在非本行像素单元的扫描周期内，当所述上拉控制信号异常时，将所述上拉控制信号以及所述当前级的行扫描信号再次下拉至低电平；以及
    自举电容，所述自举电容的一端连接所述上拉控制信号，所述自举电容的另一端连接所述当前级GOA单元的行扫描信号。
  9. 根据权利要求8所述的GOA驱动电路，其中，所述上拉控制模块包括：第一晶体管；
    所述第一晶体管的栅极连接由所述上一级GOA单元输出的级传信号，所述第一晶体管的源极连接由所述上一级GOA单元输出的行扫描信号，所述第一晶体管的漏极输出所述上拉控制信号。
  10. 根据权利要求8所述的GOA驱动电路，其中，所述上拉模块包括：第二晶体管；
    所述第二晶体管的栅极连接所述上拉控制信号，所述第二晶体管的源极连接所述高频时钟信号，所述第二晶体管的漏极连输出当前级GOA单元的行扫描信号。
  11. 根据权利要求8所述的GOA驱动电路，其中，所述级传模块包括：第三晶体管；
    所述第三晶体管的栅极连接所述上拉控制信号，所述第三晶体管的源极连接所述高频时钟信号，所述第三晶体管的漏极连输出当前级GOA单元的级传信号。
  12. 根据权利要求8所述的GOA驱动电路，其中，所述下拉模块包括：第四晶体管与第五晶体管；
    所述第四晶体管的栅极与所述第五晶体管的栅极均连接由所述下一级GOA单元输出的行扫描信号；所述第四晶体管的源极与所述第五晶体管的源极均连接低电源信号；所述第四晶体管的漏极连接所述当前级GOA单元的行扫描信号，所述第五晶体管的漏极连接所述上拉控制信号。
  13. 根据权利要求8所述的GOA驱动电路，其中，所述下拉维持模块包括：第一下拉维持单元与第二下拉维持单元；所述第一下拉维持单元与所述第二下拉维持单元交替工作；
    所述第一下拉维持单元包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管；
    所述第六晶体管的栅极、源极以及所述第七晶体管的源极均连接第一高频时钟信号；所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极相互连接；所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极以及所述第十一晶体管的栅极均与第一下拉维持节点连接；所述第八晶体管的栅极与所述第九晶体管的栅极均与所述上拉控制信号连接；所述第八晶体管的源极、所述第九晶体管的源极、所述第十晶体管的源极以及所述第十一晶体管的源极均连接低电源信号；所述第十晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十一晶体管的漏极连接所述上拉控制信号；
    所述第二下拉维持单元包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管；
    所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均连接第二高频时钟信号；所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十四晶体管的漏极相互连接；所述第十三晶体管的漏极、所述第十五晶体管的漏极、所述第十六晶体管的栅极以及所述第十七晶体管的栅极均与第二下拉维持节点连接；所述第十四晶体管的栅极与所述第十五晶体管的栅极均与所述上拉控制信号连接；所述第十四晶体管的源极、所述第十五晶体管的源极、所述第十六晶体管的源极以及所述第十七晶体管的源极均连接低电源信号；所述第十六晶体管的漏极连接所述当前级GOA单元的行扫描信号；所述第十七晶体管的漏极连接所述上拉控制信号；
    所述第一低频时钟信号与所述第二低频时钟信号是两个相位完全相反的低频信号源。
  14. 根据权利要求12所述的GOA驱动电路，其中，所述异常保护模块包括：第十八晶体管；
    所述第十八晶体管的栅极连接所述当前级GOA单元之后的所有GOA单元的行扫描信号，所述第十八晶体管的源极源极连接所述上拉控制信号，所述第十七晶体管的漏极连接所述第一下拉维持节点以及所述第二下拉维持节点。
  15. 根据权利要求14所述的GOA驱动电路，其中，所述GOA驱动电路的第一级连接关系中，所述上拉控制模块接还用于根据接收到的电路启动信号，输出上拉控制信号。
  16. 根据权利要求14所述的GOA驱动电路，其中，所述GOA驱动电路的最后一级连接关系中，所述下拉模块还用于根据接收到的第二级GOA单元的行扫描信号，将所述上拉控制信号以及所述最后一级GOA单元的行扫描信号同时下拉至低电平。
  17. 一种显示面板，其包括GOA驱动电路，所述GOA驱动电路由多级GOA单元级联构成，每一级GOA单元用于驱动一行像素单元，当前级GOA单元包括：
    上拉控制模块，用于根据接收到的由上一级GOA单元输出的行扫描信号与级传信号，输出上拉控制信号；
    上拉模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将接收到的高频时钟信号输出为当前级GOA单元的行扫描信号；
    级传模块，与所述上拉控制模块相连接，用于根据所述上拉控制信号，将所述接收到的高频时钟信号输出为当前级GOA单元的级传信号；
    下拉模块，与所述上拉控制模块以及所述上拉模块相连接，用于根据接收到的下一级GOA单元输出的行扫描信号，将所述上拉控制信号以及所述当前级GOA单元的行扫描信号同时下拉至低电平；
    下拉维持模块，与所述上拉控制模块以及所述上拉模块相连接，用于在非本行像素单元的扫描周期内，将所述上拉控制信号以及所述当前级的行扫描信号维持在低电平；
    异常保护模块，与所述下拉维持模块连接，用于在非本行像素单元的扫描周期内，当所述上拉控制信号异常时，将所述上拉控制信号以及所述当前级的行扫描信号再次下拉至低电平；以及
    自举电容，所述自举电容的一端连接所述上拉控制信号，所述自举电容的另一端连接所述当前级GOA单元的行扫描信号。
  18. 根据权利要求17所述的显示面板，其中，所述上拉控制模块包括：第一晶体管；
    所述第一晶体管的栅极连接由所述上一级GOA单元输出的级传信号，所述第一晶体管的源极连接由所述上一级GOA单元输出的行扫描信号，所述第一晶体管的漏极输出所述上拉控制信号。
  19. 根据权利要求17所述的显示面板，其中，所述上拉模块包括：第二晶体管；
    所述第二晶体管的栅极连接所述上拉控制信号，所述第二晶体管的源极连接所述高频时钟信号，所述第二晶体管的漏极连输出当前级GOA单元的行扫描信号。
  20. 根据权利要求17所述的显示面板，其中，所述级传模块包括：第三晶体管；
    所述第三晶体管的栅极连接所述上拉控制信号，所述第三晶体管的源极连接所述高频时钟信号，所述第三晶体管的漏极连输出当前级GOA单元的级传信号。
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