WO2020073456A1 - 导电层绝缘方法、导电层绝缘结构及显示装置 - Google Patents

导电层绝缘方法、导电层绝缘结构及显示装置 Download PDF

Info

Publication number
WO2020073456A1
WO2020073456A1 PCT/CN2018/118135 CN2018118135W WO2020073456A1 WO 2020073456 A1 WO2020073456 A1 WO 2020073456A1 CN 2018118135 W CN2018118135 W CN 2018118135W WO 2020073456 A1 WO2020073456 A1 WO 2020073456A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
conductive layer
insulating
conductive
Prior art date
Application number
PCT/CN2018/118135
Other languages
English (en)
French (fr)
Inventor
黄北洲
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Publication of WO2020073456A1 publication Critical patent/WO2020073456A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the technical field of liquid crystal display, in particular to a conductive layer insulation method, a conductive layer insulation structure, and a display device.
  • Thin-film transistor liquid crystal display has the advantages of high picture quality, thin and light, low power consumption, no radiation, etc., and has gradually become the mainstream of display devices.
  • TFT-LCD Thin-film transistor liquid crystal display
  • the quality requirements of wire manufacturing technology are becoming higher and higher during the production of thin-film transistor liquid crystal displays.
  • copper metal with lower resistance is generally used as the wire material instead of aluminum alloy or pure aluminum metal wires. Since copper ions have high activity and are easily oxidized, the problem of copper ion diffusion may occur, resulting in the active layer of the switching element in the array process being contaminated with copper ions, which may cause leakage of the device and result in product scrap.
  • the present application provides a method for insulating a conductive layer that prevents diffusion of ions, an insulating structure for a conductive layer, and a display device.
  • an embodiment of the present application provides a conductive layer insulation method, which is applied to a display panel.
  • the display panel includes at least a substrate, a plurality of switching elements, a plurality of data lines, and a plurality of scanning lines.
  • the method includes:
  • the conductive layer including the scanning line and the gate of the switching element
  • the density of the first insulating layer is greater than the density of the second insulating layer.
  • an embodiment of the present application provides a conductive layer insulation structure, which is applied to a display panel.
  • the display panel includes at least a substrate, a plurality of switching elements, a plurality of data lines, and a plurality of scanning lines.
  • the switching elements At least including the active layer and the gate,
  • the scanning line and the gate of the switching element are formed above the substrate and together serve as a conductive layer;
  • the conductive layer insulation structure includes:
  • a second insulating layer covering the first insulating layer, and the active layer is provided directly above a portion of the second insulating layer corresponding to the gate;
  • the density of the first insulating layer is greater than the density of the second insulating layer.
  • an embodiment of the present application provides a display device.
  • the display device includes a housing and a display panel.
  • the display panel includes:
  • the switching element includes at least an active layer and a gate, the scan line and the gate are formed above the substrate, and together serve as a conductive layer; the pixel unit and the switching element are disposed on the plurality of data The area surrounded by the line intersecting the multiple scanning lines at right angles;
  • the conductive layer insulation structure includes:
  • a second insulating layer covering the first insulating layer, and the active layer is provided directly above a portion of the second insulating layer corresponding to the gate;
  • the density of the first insulating layer is greater than the density of the second insulating layer.
  • Embodiments of the present application provide a conductive layer insulation method, a conductive layer insulation structure, and a display device.
  • the conductive layer insulation method includes: forming a conductive layer above the substrate; forming a first insulating layer to cover the conductive layer Forming the second insulating layer to cover the first insulating layer, the active layer is provided directly above the portion of the second insulating layer corresponding to the gate; wherein, the first insulating layer The density is greater than the density of the second insulating layer.
  • FIG. 1 is a schematic flowchart of a method for insulating a conductive layer in an embodiment of the present application
  • FIG. 2a is a schematic cross-sectional structural view of an insulating structure of a conductive layer in an embodiment of this application;
  • 2b is a schematic top view of an insulating structure of a conductive layer in an embodiment of this application;
  • FIG. 3 is a schematic structural diagram of an array substrate in an embodiment of the present application.
  • FIG. 4 is an enlarged schematic view of the area A of the array substrate in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a display device in an embodiment of the present application.
  • FIG. 1 is a schematic flowchart of a conductive layer insulation method in an embodiment of the present application.
  • the method is applied to a display panel.
  • the display panel includes at least a substrate, a plurality of switching elements, a plurality of data lines, and a plurality of scanning lines.
  • the switching element includes at least an active layer and a gate.
  • the method includes Steps S101-S103.
  • the display panel may include an array substrate, and the array substrate may include the substrate, a plurality of switching elements, a plurality of data lines, and a plurality of scan lines.
  • the substrate may be formed of a substrate such as a glass substrate or a plastic substrate.
  • the array substrate can be applied to display panels of various display devices.
  • the display panel may be a liquid crystal display panel in a thin film transistor liquid crystal display (TFT-LCD).
  • the array substrate may be a thin film transistor array substrate.
  • the switching element may be a thin film transistor.
  • the switching element may include a source electrode, a gate electrode, a drain electrode, an active layer, and the like.
  • the scanning line is electrically connected to the gate of the switching element, is formed above the substrate, and collectively serves as the conductive layer.
  • the conductive layer may be a copper metal conductive layer or a copper alloy conductive layer. If the conductive layer is a copper metal conductive layer, the formation of the conductive layer can be achieved by using a pure copper target and depositing a metal copper thin film on the substrate by sputtering. And through exposure, development and etching processes, the copper film is patterned into a conductive layer. S102, forming the first insulating layer to cover the conductive layer.
  • the method for forming the first insulating layer may be selected from, but not limited to, a DC vacuum magnetron sputtering method, a radio frequency vacuum magnetron sputtering method, and a reactive sputtering method.
  • the material of the first insulating layer may be silicon nitride.
  • the thickness of the first insulating layer is 150 angstroms to 250 angstroms.
  • the thickness of the first insulating layer may be 150 angstroms, 200 angstroms, or 250 angstroms.
  • the method for forming the second insulating layer may be selected from, but not limited to, a DC vacuum magnetron sputtering method, a radio frequency vacuum magnetron sputtering method, and a reactive sputtering method.
  • the material of the second insulating layer may be silicon nitride.
  • the forming speed of the first insulating layer is lower than the forming speed of the second insulating layer.
  • the density of the first insulating layer is greater than the density of the second insulating layer.
  • the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer is 1:20. For example, if the thickness of the first insulating layer is 200 angstroms; correspondingly, the thickness of the second insulating layer is 4000 angstroms. Or if the thickness of the first insulating layer is 150 Angstroms; correspondingly, the thickness of the second insulating layer is 3000 Angstroms. Or if the thickness of the first insulating layer is 250 Angstroms; correspondingly, the thickness of the second insulating layer is 5000 Angstroms.
  • the active layer may be a metal oxide semiconductor.
  • the active layer may be IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO: F, In 2 O 3 : Sn, In 2 O 3 : Mo, Cd 2 SnO 4 , ZnO: Al, TiO 2 : Nb or Cd-Sn-O etc.
  • the above layers can also be formed in other ways, such as chemical vapor deposition or physical deposition, etc., which will not be repeated here.
  • the metal ions in the conductive layer can be effectively prevented from diffusing to the active layer connected to the second insulating layer Layer, effectively avoiding leakage.
  • the method further includes: forming an adhesion layer between the substrate and the conductive layer, the adhesion layer may be a molybdenum alloy.
  • the molybdenum alloy includes, but is not limited to, any one or a mixture of two or more of MoNb, MoW, MoTi, and MoZr.
  • the adhesion layer may be formed on the substrate first, and then the conductive layer may be formed on the adhesion layer. For example, the substrate is provided first, and the substrate is washed with deionized water.
  • the adhesion layer is formed on the substrate by a sputtering process; then a copper thin film is formed on the adhesion layer by sputtering, and through exposure, development, and etching processes , Pattern the copper thin film into a conductive layer.
  • the adhesion between the conductive layer and the substrate can be enhanced by the adhesion layer, which is beneficial to enhance the stability of the overall structure.
  • the adhesion layer can also prevent the metal ions in the conductive layer from diffusing into the substrate, improving the reliability of the product.
  • FIGS. 2a and 2b are schematic top and cross-sectional structural views of an insulating structure of a conductive layer in an embodiment of the present application.
  • the conductive layer insulation structure 100 is applied to a display panel.
  • the display panel at least includes a substrate 210, a plurality of switching elements, a plurality of data lines, and a plurality of scan lines 240.
  • the switching element includes at least an active layer 140 and a gate 141, and may further include a source 142 and a drain 143.
  • the scan line 240 and the gate electrode 141 of the switching element are formed above the substrate 210 and are electrically connected and collectively serve as the conductive layer 110.
  • the conductive layer insulation structure 100 includes a first insulation layer 120 and a second insulation layer 130.
  • the active layer 140 is disposed directly above the portion of the second insulating layer 130 corresponding to the gate 141.
  • the source electrode 142 and the drain electrode 143 are respectively disposed at both ends of the active layer 140 and are electrically connected
  • the display panel includes an array substrate 200 including the substrate 210, a plurality of switching elements, a plurality of data lines, and a plurality of scan lines.
  • the substrate 210 may be formed of a substrate such as a glass substrate or a plastic substrate.
  • the array substrate 200 can be applied to display panels of various display devices.
  • the display panel may be a liquid crystal display panel in a thin film transistor liquid crystal display (TFT-LCD).
  • the array substrate may be a thin film transistor array substrate.
  • the switching element may be a thin film transistor.
  • the switching element includes a source electrode, a gate electrode, a drain electrode, an active layer, and the like.
  • the scan line is electrically connected to the gate of the switching element, is formed above the substrate, and collectively serves as the conductive layer 110.
  • the conductive layer 110 may be a copper metal conductive layer or a copper alloy conductive layer. If the conductive layer 110 is a copper metal conductive layer, the formation of the conductive layer 110 may be achieved by using a pure copper target and depositing a metal copper thin film on the substrate 210 by sputtering. And through exposure, development and etching processes, the copper thin film is patterned into the conductive layer 110.
  • the first insulating layer 120 covers the conductive layer 110.
  • the method for forming the first insulating layer 120 includes, but is not limited to: a DC vacuum magnetron sputtering method, a radio frequency vacuum magnetron sputtering method, and a reactive sputtering method.
  • the material of the first insulating layer 120 may be silicon nitride.
  • the thickness of the first insulating layer 120 is 150 angstroms to 250 angstroms.
  • the thickness of the first insulating layer 120 may be 150 angstroms, 200 angstroms, or 250 angstroms.
  • the second insulating layer 130 covers the first insulating layer 120, and the active layer 140 is disposed directly above a portion of the second insulating layer 130 corresponding to the gate.
  • the forming method of the second insulating layer 130 includes, but is not limited to, a DC vacuum magnetron sputtering method, a radio frequency vacuum magnetron sputtering method, and a reactive sputtering method.
  • the material of the second insulating layer 130 may be silicon nitride.
  • the forming speed of the first insulating layer 120 may be lower than the forming speed of the second insulating layer 130.
  • the density of the first insulating layer 120 may be greater than the density of the second insulating layer 130.
  • the ratio of the thickness of the first insulating layer 120 to the thickness of the second insulating layer 130 may be 1:20. For example, if the thickness of the first insulating layer 120 is 200 angstroms; correspondingly, the thickness of the second insulating layer 130 is 4000 angstroms. Or if the thickness of the first insulating layer 120 is 150 angstroms; correspondingly, the thickness of the second insulating layer 130 is 3,000 angstroms. Or, if the thickness of the first insulating layer 120 is 250 angstroms; correspondingly, the thickness of the second insulating layer 130 is 5,000 angstroms.
  • the material of the active layer 140 may be a metal oxide semiconductor.
  • the material of the active layer 140 may be IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO: F, In 2 O 3 : Sn, In 2 O 3 : Mo, Cd 2 SnO 4 , ZnO : Al, TiO 2 : Nb, Cd-Sn-O, etc.
  • the above layers can also be formed in other ways, such as chemical vapor deposition or physical deposition, etc., which will not be repeated here.
  • the metal ions in the conductive layer 110 can be effectively prevented from diffusing to the second insulating layer
  • the active layer 140 connected to the layer 130 effectively avoids the leakage phenomenon.
  • the conductive layer insulation structure 100 further includes an adhesion layer 150, which is disposed between the substrate 210 and the wire layer.
  • the adhesion layer 150 is a molybdenum alloy.
  • the molybdenum alloy includes but is not limited to any one or a mixture of two or more of MoNb, MoW, MoTi, and MoZr.
  • the adhesion layer 150 may be formed on the substrate 210 first, and then the conductive layer 110 may be formed on the adhesion layer 150.
  • the substrate 210 is provided first, and the substrate 210 is washed with deionized water.
  • the adhesion layer 150 is formed on the substrate 210 through a sputtering process; then a copper thin film is formed on the adhesion layer 150 by sputtering, and exposed, developed, and engraved Processes such as etching pattern the copper thin film into the conductive layer 110.
  • the adhesion layer 150 may be used to enhance the adhesion between the conductive layer 110 and the substrate 210, which is beneficial to enhance the stability of the overall structure. At the same time, the adhesion layer 150 can also prevent the metal ions in the conductive layer 110 from diffusing into the substrate 210, improving the reliability of the product.
  • FIG. 3 to FIG. 4 are a schematic structural diagram of an array substrate 200 and an enlarged schematic diagram of an area A of the array substrate 200 according to an embodiment of the present application.
  • the array substrate 200 includes a substrate 210, a plurality of data lines 230, and a plurality of scan lines 240.
  • the switching element 220 includes at least an active layer 140 and a gate 141.
  • the scan lines 240 and the gate 141 are formed on the A plurality of pixel units 250 and a plurality of switching elements 220 are disposed in a plurality of regions surrounded by the intersection of the data lines 230 and the scan lines 240.
  • One pixel unit 250 and one switching element 220 may be provided in each area surrounded by the data line 230 and the scan line 240 intersecting positively.
  • FIGS. 2 a and 2 b together.
  • a conductive layer insulation structure 100 is provided on the substrate 210.
  • the conductive layer insulation structure 100 includes a first insulation layer 120 and a second insulation layer 130.
  • the display panel includes an array substrate 200, and the array substrate 200 includes the substrate 210, a plurality of switching elements 220, a plurality of data lines, and a plurality of scan lines.
  • the substrate 210 may be formed of a substrate such as a glass substrate or a plastic substrate.
  • the array substrate 200 can be applied to display panels of various display devices.
  • the display panel may be a liquid crystal display panel in a thin film transistor liquid crystal display (TFT-LCD).
  • the array substrate 200 may be a thin film transistor array substrate.
  • the switching element 220 may be a thin film transistor.
  • the switching element 220 includes a source electrode, a gate electrode, a drain electrode, an active layer, and the like.
  • the scan line 240 is electrically connected to the gate 141 of the switching element 220 and is formed above the substrate 210 and collectively serves as the conductive layer 110.
  • the conductive layer 110 may be a copper metal conductive layer or a copper alloy conductive layer. If the conductive layer 110 is a copper metal conductive layer, the formation of the conductive layer 110 may be achieved by using a pure copper target and depositing a metal copper thin film on the substrate 210 by sputtering. And through exposure, development and etching processes, the copper thin film is patterned into the conductive layer 110.
  • the first insulating layer 120 covers the conductive layer 110.
  • the forming method of the first insulating layer 120 includes, but is not limited to: a DC vacuum magnetron sputtering method, a radio frequency vacuum magnetron sputtering method, and a reactive sputtering method.
  • the material of the first insulating layer 120 may be silicon nitride.
  • the thickness of the first insulating layer 120 is 150 angstroms to 250 angstroms.
  • the thickness of the first insulating layer 120 may be 150 angstroms, 200 angstroms, or 250 angstroms.
  • the second insulating layer 130 covers the first insulating layer 120, and the active layer 140 is disposed directly above a portion of the second insulating layer 130 corresponding to the gate 141.
  • the forming method of the second insulating layer 130 includes, but is not limited to: a DC vacuum magnetron sputtering method, a radio frequency vacuum magnetron sputtering method, and a reactive sputtering method.
  • the material of the second insulating layer 130 may be silicon nitride.
  • the forming speed of the first insulating layer 120 may be lower than the forming speed of the second insulating layer 130.
  • the density of the first insulating layer 120 may be greater than the density of the second insulating layer 130.
  • the ratio of the thickness of the first insulating layer 120 to the thickness of the second insulating layer 130 may be 1:20. For example, if the thickness of the first insulating layer 120 is 200 angstroms; correspondingly, the thickness of the second insulating layer 130 is 4,000 angstroms. Or if the thickness of the first insulating layer 120 is 150 angstroms; correspondingly, the thickness of the second insulating layer 130 is 3,000 angstroms. Or, if the thickness of the first insulating layer 120 is 250 angstroms; correspondingly, the thickness of the second insulating layer 130 is 5,000 angstroms.
  • the active layer 140 is a metal oxide semiconductor.
  • the active layer 140 may be IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO: F, In 2 O 3 : Sn, In 2 O 3 : Mo, Cd 2 SnO 4 , ZnO: Al , TiO 2 : Nb or Cd-Sn-O, etc.
  • the above layers can also be formed in other ways, such as chemical vapor deposition or physical deposition, etc., which will not be repeated here.
  • the metal ions in the conductive layer 110 can be effectively prevented from diffusing to the second insulating layer
  • the active layer 140 connected to the layer 130 effectively avoids the leakage phenomenon.
  • the conductive layer insulation structure 100 further includes an adhesion layer 150 disposed between the substrate 210 and the conductive layer 110.
  • the adhesion layer 150 is a molybdenum alloy.
  • the molybdenum alloy includes but is not limited to any one or a mixture of two or more of MoNb, MoW, MoTi, and MoZr.
  • the adhesion layer 150 may be formed on the substrate first, and then the conductive layer 110 may be formed on the adhesion layer 150.
  • the substrate 210 is provided first, and the substrate 210 is washed with deionized water.
  • the adhesion layer 150 is formed on the substrate 210 through a sputtering process; then a copper thin film is formed on the adhesion layer 150 by sputtering, and exposed, developed, and engraved Processes such as etching pattern the copper thin film into the conductive layer 110.
  • the adhesion layer 150 may be used to enhance the adhesion between the conductive layer 110 and the substrate 210, which is beneficial to enhance the stability of the overall structure. At the same time, the adhesion layer 150 can also prevent the metal ions in the conductive layer 110 from diffusing into the substrate 210, improving the reliability of the product.
  • FIG. 5 is a schematic structural diagram of a display device 300 according to an embodiment of the present application.
  • the display device 300 includes a housing 310 and a display panel 320.
  • the display panel 320 includes a substrate, a pixel unit, a switching element, a conductive layer insulation structure, a plurality of data lines and a plurality of scanning lines, and the switching element at least includes A source layer and a gate, the scan line and the gate are formed above the substrate, and together serve as a conductive layer; the pixel unit and the switching element are both plural, the pixel unit and the switching element It is arranged in a plurality of areas surrounded by the intersection of the plurality of data lines and the plurality of scan lines.
  • the conductive layer insulation structure is the conductive layer insulation structure 100 in the foregoing embodiment.
  • the conductive layer insulation structure 100 please refer to the foregoing embodiments, and no more details are provided here.
  • there is one conductive insulating structure and the conductive insulating structure integrally covers a plurality of the scanning lines and a plurality of the gates of the plurality of switching elements.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

本申请实施例提供了一种导电层绝缘方法、导电层绝缘结构及显示装置，所述方法包括：形成导电层于所述基板上方，所述导电层包括所述扫描线和所述开关元件的所述栅极；形成所述第一绝缘层以覆盖于所述导电层上方；形成所述第二绝缘层以覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层的正上方设置所述有源层；其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。

Description

导电层绝缘方法、导电层绝缘结构及显示装置
相关申请
本申请要求2018年10月8日申请的，申请号为2018111682252，名称为“一种导电层绝缘方法、导电层绝缘结构及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及液晶显示技术领域，具体涉及一种导电层绝缘方法、导电层绝缘结构及显示装置。
背景技术
薄膜晶体管液晶显示器(thin film transistor-liquid crystal display，TFT-LCD)具有高画质、轻薄、低消耗功率、无辐射等优势，已经逐渐成为显示设备的主流。随着薄膜晶体管液晶显示器往超大尺寸、高驱动频率、高分辨率等方面发展，薄膜晶体管液晶显示器在制作时，对导线制程技术的质量要求也越来越高。
为了满足未来高频率与高分辨率的液晶显示器规格的发展需求，通常以电阻较低的铜金属取代铝合金或纯铝金属导线作为导线材料。而由于铜离子的活性较高且易被氧化，因此会有铜离子扩散的问题发生，导致阵列工艺中开关元件的有源层受到铜离子污染，进而发生器件漏电现象，造成产品报废。
发明内容
有鉴于此，本申请提供了一种防止离子扩散的导电层绝缘方法、导电层绝缘结构及显示装置。
一方面，本申请实施例提供了一种导电层绝缘方法，应用于显示面板上，所述显示面板至少包括基板、多个开关元件、多条数据线和多条扫描线，所述开关元件至少包括有源层和栅极，所述方法包括：
形成导电层于所述基板上方，所述导电层包括所述扫描线和所述开关元件的所述栅极；
形成所述第一绝缘层以覆盖于所述导电层上方；以及
形成所述第二绝缘层以覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层的正上方设置所述有源层；
其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。
另一方面，本申请实施例提供了一种导电层绝缘结构，应用于显示面板上，所述显示面板至少包括基板、多个开关元件、多条数据线和多条扫描线，所述开关元件至少包括有源层和栅极，
所述扫描线和所述开关元件的所述栅极形成于所述基板上方，共同作为导电层；
所述导电层绝缘结构包括：
第一绝缘层，覆盖于所述导电层上方；以及
第二绝缘层，覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层正上方设置所述有源层；
其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。
再一方面，本申请实施例提供了一种显示装置，所述显示装置包括壳体和显示面板，所述显示面板包括：
基板；
像素单元；
开关元件；
导电层绝缘结构；以及
多条数据线和多条扫描线，
所述开关元件至少包括有源层和栅极，所述扫描线和所述栅极形成于所述基板上方，共同作为导电层；所述像素单元和所述开关元件设置在所述多条数据线与所述多条扫描线正相交所包围的区域内；
所述导电层绝缘结构包括：
第一绝缘层，覆盖于所述导电层上方；
第二绝缘层，覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层正上方设置所述有源层；
其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。
本申请实施例提供了一种导电层绝缘方法、导电层绝缘结构及显示装置，该导电层绝缘方法包括：形成导电层于所述基板上方；形成第一绝缘层以覆盖于所述导电层上方；形成所述第二绝缘层以覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层的正 上方设置所述有源层；其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。实施本申请实施例，可有效防止导电层中的金属离子扩散至与第二绝缘层连接的有源层，有效避免产生漏电现象。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例中一种导电层绝缘方法的流程示意图；
图2a为本申请一实施例中一种导电层绝缘结构的剖视结构示意图；
图2b为本申请一实施例中一种导电层绝缘结构的俯视结构示意图；
图3为本申请一实施例中一种阵列基板的结构示意图；
图4为图3中阵列基板A区域的放大示意图；
图5为本申请一实施例中一种显示装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下通过实施例，并结合附图，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
请参照图1，其为本申请实施例中一种导电层绝缘方法的流程示意图。该方法应用于显示面板上，所述显示面板至少包括基板、多个开关元件、多条数据线和多条扫描线，所述开关元件至少包括有源层和栅极，其中，所述方法包括步骤S101-S103。
S101，形成导电层于所述基板上方，所述导电层包括所述扫描线和所述开关元件的所述栅极。
具体实施中，所述显示面板可包括阵列基板，所述阵列基板可包括所述基板、多个开关元件、多条数据线和多条扫描线。所述基板可以由玻璃基板或者塑胶基板等基板形成。所述阵列基板可应用于各类显示装置的显示面板中。例如，所述显示面板可以为薄膜晶体管液晶显示器(thin film transistor-liquid crystal display，TFT-LCD)中的液晶显示面板。所述 阵列基板可以为薄膜晶体管阵列基板。所述开关元件可以是薄膜晶体管。所述开关元件可包括源极、栅极、漏极、有源层等。
其中，所述扫描线与所述开关元件的所述栅极电性连接，形成于所述基板上方，共同作为所述导电层。所述导电层可以为铜金属导电层或者铜合金导电层。若所述导电层为铜金属导电层，所述导电层的形成可通过如下方式实现：采用纯铜靶材，以溅镀法沉积金属铜薄膜于所述基板上方。并通过曝光、显影及刻蚀等工艺，将铜薄膜图案化成导电层。S102，形成所述第一绝缘层以覆盖于所述导电层上方。
具体实施中，所述第一绝缘层的形成方法可以选自但不限于：直流式真空磁控溅镀法、射频式真空磁控溅镀法及反应性溅镀法。
其中，所述第一绝缘层的材料可以为氮化硅。所述第一绝缘层的厚度为150埃米至250埃米，例如该第一绝缘层的厚度可以为150埃米、200埃米或者250埃米等等。
S103，形成所述第二绝缘层以覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层的正上方设置所述有源层。
具体实施中，所述第二绝缘层的形成方法可以选自但不限于：直流式真空磁控溅镀法、射频式真空磁控溅镀法及反应性溅镀法。所述第二绝缘层的材料可以为氮化硅。
其中，所述第一绝缘层的形成速度小于所述第二绝缘层的形成速度。所述第一绝缘层的密度大于所述第二绝缘层的密度。所述第一绝缘层的厚度与所述第二绝缘层的厚度的比值为1：20。例如，若所述第一绝缘层的厚度为200埃米；对应地，所述第二绝缘层的厚度为4000埃米。或者若所述第一绝缘层的厚度为150埃米；对应地，所述第二绝缘层的厚度为3000埃米。又或者若所述第一绝缘层的厚度为250埃米；对应地，所述第二绝缘层的厚度为5000埃米。
所述有源层可以为金属氧化物半导体。例如，所述有源层可以是IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In 2O 3:Sn、In 2O 3:Mo、Cd 2SnO 4、ZnO:Al、TiO 2:Nb或Cd-Sn-O等。
以上各层也可以采用其他方式形成，如化学蒸镀方式或物理沉积方式等，此处不再赘述。
实施本申请实施例，通过在第二绝缘层与导电层之间设置密度大于第二绝缘层的第一绝缘层，可有效防止导电层中的金属离子扩散至与第二绝缘层连接的有源层，有效避免产生漏电现象。
在一实施例中，所述方法还包括：在所述基板与所述导电层之间形成附着层，所述附着层可以为钼合金。所述钼合金包括但不限于是MoNb、MoW、MoTi和MoZr中的任意 一种或两种以上的混合物。具体实施中，可先在所述基板上形成所述附着层，再在所述附着层上形成所述导电层。例如，先提供基板，并通过去离子水对基板进行清洗。接着将钼合金作为溅射源通过溅射工艺，在所述基板上形成所述附着层；然后在所述附着层上以溅镀的方式形成铜薄膜，并通过曝光、显影及刻蚀等工艺，将铜薄膜图案化成导电层。
实施本申请实施例，可通过附着层增强所述导电层与所述基板之间的粘附性，有利于增强整体结构的稳定性。同时，所述附着层还可以防止导电层中的金属离子扩散到所述基板中，提高了产品的可靠性。
请参照图2a和图2b，其为本申请实施例中一种导电层绝缘结构的俯视和剖视结构示意图。其中，该导电层绝缘结构100应用于显示面板上，所述显示面板至少包括基板210、多个开关元件、多条数据线和多条扫描线240。所述开关元件至少包括有源层140和栅极141，并还可以包括源极142和漏极143。所述扫描线240和所述开关元件的所述栅极141形成于所述基板210上方，电性连接并共同作为导电层110。进一步地，所述导电层绝缘结构100包括第一绝缘层120以及第二绝缘层130。所述栅极141所对应的部分第二绝缘层130的正上方设置所述有源层140。所述源极142和漏极143分别设置在所述有源层140两端，并与所述有源层140电连接。
请一并参阅图3，在一具体实施中，所述显示面板包括阵列基板200，所述阵列基板200包括所述基板210、多个开关元件、多条数据线和多条扫描线。所述基板210可以由玻璃基板或者塑胶基板等基板形成。所述阵列基板200可应用于各类显示装置的显示面板中。例如，所述显示面板可以为薄膜晶体管液晶显示器(thin film transistor-liquid crystal display，TFT-LCD)中的液晶显示面板。所述阵列基板可以为薄膜晶体管阵列基板。所述开关元件可以是薄膜晶体管。所述开关元件包括源极、栅极、漏极、有源层等。
所述扫描线与所述开关元件的所述栅极电性连接，形成于所述基板上方，共同作为所述导电层110。所述导电层110可以为铜金属导电层或者铜合金导电层。若所述导电层110为铜金属导电层，所述导电层110的形成可通过如下方式实现：采用纯铜靶材，以溅镀法沉积金属铜薄膜于所述基板210上方。并通过曝光、显影及刻蚀等工艺，将铜薄膜图案化成导电层110。
所述第一绝缘层120覆盖于所述导电层110上方。
具体实施例中，所述第一绝缘层120的形成方法包括但不限于：直流式真空磁控溅镀法、射频式真空磁控溅镀法及反应性溅镀法。
其中，所述第一绝缘层120的材料可以为氮化硅。所述第一绝缘层120的厚度为150 埃米至250埃米，例如该第一绝缘层120的厚度可以为150埃米、200埃米或者250埃米等等。
所述第二绝缘层130覆盖于所述第一绝缘层120上方，所述栅极所对应的部分第二绝缘层130正上方设置所述有源层140。
具体实施例中，所述第二绝缘层130的形成方法包括但不限于：直流式真空磁控溅镀法、射频式真空磁控溅镀法及反应性溅镀法。所述第二绝缘层130的材料可以为氮化硅。
其中，所述第一绝缘层120的形成速度可小于所述第二绝缘层130的形成速度。所述第一绝缘层120的密度可大于所述第二绝缘层130的密度。所述第一绝缘层120的厚度与所述第二绝缘层130的厚度的比值可为1：20。例如，若所述第一绝缘层120的厚度为200埃米；对应地，所述第二绝缘层130的厚度为4000埃米。或者若所述第一绝缘层120的厚度为150埃米；对应地，所述第二绝缘层130的厚度为3000埃米。又或者若所述第一绝缘层120的厚度为250埃米；对应地，所述第二绝缘层130的厚度为5000埃米。
所述有源层140的材料可为金属氧化物半导体。例如，所述有源层140的材料可以是IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In 2O 3:Sn、In 2O 3:Mo、Cd 2SnO 4、ZnO:Al、TiO 2:Nb或Cd-Sn-O等。
以上各层也可以采用其他方式形成，如化学蒸镀方式或物理沉积方式等，此处不再赘述。
实施本申请实施例，通过在第二绝缘层130与导电层110之间设置密度大于第二绝缘层130的第一绝缘层120，可有效防止导电层110中的金属离子扩散至与第二绝缘层130连接的有源层140，有效避免产生漏电现象。
进一步地，所述导电层绝缘结构100还包括附着层150，所述附着层150设置于所述基板210以及所述导线层之间。所述附着层150为钼合金，所述钼合金包括但不限于是MoNb、MoW、MoTi和MoZr中的任意一种或两种以上的混合物。具体实施中，可先在所述基板210上形成所述附着层150，再在所述附着层150上形成所述导电层110。例如，先提供基板210，并通过去离子水对基板210进行清洗。接着将钼合金作为溅射源通过溅射工艺，在所述基板210上形成所述附着层150；然后在所述附着层150上以溅镀的方式形成铜薄膜，并通过曝光、显影及刻蚀等工艺，将铜薄膜图案化成导电层110。
实施本申请实施例，可通过附着层150增强所述导电层110与所述基板210之间的粘附性，有利于增强整体结构的稳定性。同时，所述附着层150还可以防止导电层110中的金属离子扩散到所述基板210中，提高了产品的可靠性。
请参照图3至图4，其为本申请一实施例中一种阵列基板200的结构示意图以及该阵 列基板200的A区域的放大示意图。该阵列基板200包括基板210、多条数据线230和多条扫描线240，所述开关元件220至少包括有源层140和栅极141，所述扫描线240和所述栅极141形成于所述基板210上方，共同作为导电层；所述多条数据线230与所述多条扫描线240正相交所包围的多个区域内设置多个像素单元250以及多个开关元件220。由所述数据线230与所述扫描线240正相交所包围形成的每个区域可设置一个像素单元250和一个开关元件220。具体请一并参照图2a和图2b，在所述基板210上设置导电层绝缘结构100，所述导电层绝缘结构100包括第一绝缘层120以及第二绝缘层130。
具体实施中，所述显示面板包括阵列基板200，所述阵列基板200包括所述基板210、多个开关元件220、多条数据线和多条扫描线。所述基板210可以由玻璃基板或者塑胶基板等基板形成。所述阵列基板200可应用于各类显示装置的显示面板中。例如，所述显示面板可以为薄膜晶体管液晶显示器(thin film transistor-liquid crystal display，TFT-LCD)中的液晶显示面板。所述阵列基板200可以为薄膜晶体管阵列基板。所述开关元件220可以是薄膜晶体管。所述开关元件220包括源极、栅极、漏极、有源层等。
其中，所述扫描线240与所述开关元件220的栅极141电性连接，形成于所述基板210上方，共同作为导电层110。所述导电层110可以为铜金属导电层或者铜合金导电层。若所述导电层110为铜金属导电层，所述导电层110的形成可通过如下方式实现：采用纯铜靶材，以溅镀法沉积金属铜薄膜于所述基板210上方。并通过曝光、显影及刻蚀等工艺，将铜薄膜图案化成导电层110。
所述第一绝缘层120覆盖于所述导电层110上方。
具体实施中，所述第一绝缘层120的形成方法包括但不限于：直流式真空磁控溅镀法、射频式真空磁控溅镀法及反应性溅镀法。
其中，所述第一绝缘层120的材料可以为氮化硅。所述第一绝缘层120的厚度为150埃米至250埃米，例如该第一绝缘层120的厚度可以为150埃米、200埃米或者250埃米等等。
所述第二绝缘层130覆盖于所述第一绝缘层120上方，所述栅极141所对应的部分第二绝缘层130正上方设置所述有源层140。
具体实施中，所述第二绝缘层130的形成方法包括但不限于：直流式真空磁控溅镀法、射频式真空磁控溅镀法及反应性溅镀法。所述第二绝缘层130的材料可以为氮化硅。
其中，所述第一绝缘层120的形成速度可小于所述第二绝缘层130的形成速度。所述第一绝缘层120的密度可大于所述第二绝缘层130的密度。所述第一绝缘层120的厚度与所述第二绝缘层130的厚度的比值可为1：20。例如，若所述第一绝缘层120的厚度为200 埃米；对应地，所述第二绝缘层130的厚度为4000埃米。或者若所述第一绝缘层120的厚度为150埃米；对应地，所述第二绝缘层130的厚度为3000埃米。又或者若所述第一绝缘层120的厚度为250埃米；对应地，所述第二绝缘层130的厚度为5000埃米。
所述有源层140为金属氧化物半导体。例如，所述有源层140可以是IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In 2O 3:Sn、In 2O 3:Mo、Cd 2SnO 4、ZnO:Al、TiO 2:Nb或Cd-Sn-O等。
以上各层也可以采用其他方式形成，如化学蒸镀方式或物理沉积方式等，此处不再赘述。
实施本申请实施例，通过在第二绝缘层130与导电层110之间设置密度大于第二绝缘层130的第一绝缘层120，可有效防止导电层110中的金属离子扩散至与第二绝缘层130连接的有源层140，有效避免产生漏电现象。
进一步地，所述导电层绝缘结构100还包括附着层150，所述附着层150设置于所述基板210以及所述导电层110之间。所述附着层150为钼合金，所述钼合金包括但不限于是MoNb、MoW、MoTi和MoZr中的任意一种或两种以上的混合物。具体实施中，可先在所述基板上形成所述附着层150，再在所述附着层150上形成所述导电层110。例如，先提供基板210，并通过去离子水对基板210进行清洗。接着将钼合金作为溅射源通过溅射工艺，在所述基板210上形成所述附着层150；然后在所述附着层150上以溅镀的方式形成铜薄膜，并通过曝光、显影及刻蚀等工艺，将铜薄膜图案化成导电层110。
实施本申请实施例，可通过附着层150增强所述导电层110与所述基板210之间的粘附性，有利于增强整体结构的稳定性。同时，所述附着层150还可以防止导电层110中的金属离子扩散到所述基板210中，提高了产品的可靠性。
请参照图5，其为本申请一实施例中一种显示装置300的结构示意图。所述显示装置300包括壳体310以及显示面板320，所述显示面板320包括基板、像素单元、开关元件、导电层绝缘结构、多条数据线和多条扫描线，所述开关元件至少包括有源层和栅极，所述扫描线和所述栅极形成于所述基板上方，共同作为导电层；所述像素单元和所述开关元件均为多个，所述像素单元和所述开关元件设置在所述多条数据线与所述多条扫描线正相交所包围的多个区域内。由所述数据线与所述扫描线正相交所包围形成的每个区域可设置一个像素单元和一个开关元件。所述导电层绝缘结构为前述实施例中的导电层绝缘结构100。该导电层绝缘结构100的具体描述请参见前述实施例，此处不再赘述。
在一实施例中，所述导电绝缘结构为多个，多个所述导电绝缘结构一一对应的覆盖多个所述扫描线和多个所述开关元件的多个所述栅极。
在另一实施例中，所述导电绝缘结构为一个，所述导电绝缘结构整体的覆盖多个所述扫描线和多个所述开关元件的多个所述栅极。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种导电层绝缘方法，应用于显示面板上，所述显示面板至少包括基板、多个开关元件、多条数据线和多条扫描线，所述开关元件至少包括有源层和栅极，其特征在于，所述方法包括：
    形成导电层于所述基板上方，所述导电层包括所述扫描线和所述开关元件的所述栅极；
    形成所述第一绝缘层以覆盖于所述导电层上方；以及
    形成所述第二绝缘层以覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层的正上方设置所述有源层；
    其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。
  2. 如权利要求1所述的方法，其特征在于，所述第一绝缘层的厚度为150埃米至250埃米。
  3. 如权利要求1所述的方法，其特征在于，所述第一绝缘层的形成速度小于所述第二绝缘层的形成速度。
  4. 如权利要求1所述的方法，其特征在于，所述第一绝缘层的厚度与所述第二绝缘层的厚度的比值为1：20。
  5. 如权利要求1所述的方法，其特征在于，所述第一绝缘层和/或所述第二绝缘层的材料包括氮化硅。
  6. 如权利要求1所述的方法，其特征在于，所述第一绝缘层或所述第二绝缘层的形成方法包括直流式真空磁控溅镀法、射频式真空磁控溅镀法、反应性溅镀法、化学蒸镀法或物理沉积法。
  7. 如权利要求1所述的方法，其特征在于，所述有源层的材料包括金属氧化物半导体。
  8. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    在所述基板与所述导电层之间形成附着层，所述附着层为钼合金。
  9. 一种导电层绝缘结构，应用于显示面板上，其特征在于，所述显示面板至少包括基板、多个开关元件、多条数据线和多条扫描线，所述开关元件至少包括有源层和栅极，所述扫描线和所述开关元件的所述栅极形成于所述基板上方，共同作为导电层，
    所述导电层绝缘结构包括：
    第一绝缘层，覆盖于所述导电层上方；以及
    第二绝缘层，覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层正上方设置所述有源层；
    其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。
  10. 如权利要求9所述的导电层绝缘结构，其特征在于，所述第一绝缘层的厚度为150埃米至250埃米。
  11. 如权利要求9所述的导电层绝缘结构，其特征在于，所述第一绝缘层的厚度与所述第二绝缘层的厚度的比值为1：20。
  12. 如权利要求9所述的导电层绝缘结构，其特征在于，所述第一绝缘层和/或所述第二绝缘层的材料包括氮化硅。
  13. 如权利要求9所述的导电层绝缘结构，其特征在于，所述有源层的材料包括金属半导体。
  14. 如权利要求9所述的导电层绝缘结构，其特征在于，所述导电层绝缘结构还包括附着层，所述附着层设置于所述导电层与所述基板之间，所述附着层为钼合金。
  15. 一种显示装置，所述显示装置包括壳体以及显示面板，其特征在于，所述显示面板包括：
    基板；
    像素单元；
    开关元件；
    导电层绝缘结构；以及
    多条数据线和多条扫描线，
    所述开关元件至少包括有源层和栅极，所述扫描线和所述栅极形成于所述基板上方，共同作为导电层；所述像素单元和所述开关元件设置在所述多条数据线与所述多条扫描线正相交所包围的区域内
    所述导电层绝缘结构包括：。
    第一绝缘层，覆盖于所述导电层上方；
    第二绝缘层，覆盖于所述第一绝缘层上方，所述栅极所对应的部分第二绝缘层正上方设置所述有源层；
    其中，所述第一绝缘层的密度大于所述第二绝缘层的密度。
  16. 如权利要求15所述的显示装置，其特征在于，所述第一绝缘层的厚度为150埃米至250埃米。
  17. 如权利要求15所述的显示装置，其特征在于，所述第一绝缘层的厚度与所述第二绝缘层的厚度的比值为1：20。
  18. 如权利要求15所述的显示装置，其特征在于，所述像素单元和所述开关元件均为多个。
  19. 如权利要求18所述的显示装置，其特征在于，所述导电绝缘结构为多个，多个所述导电绝缘结构一一对应的覆盖所述多个扫描线和所述多个开关元件的所述多个栅极。
  20. 如权利要求18所述的显示装置，其特征在于，所述导电绝缘结构为一个，所述导电绝缘结构整体的覆盖所述多个扫描线和所述多个开关元件的所述多个栅极。
PCT/CN2018/118135 2018-10-08 2018-11-29 导电层绝缘方法、导电层绝缘结构及显示装置 WO2020073456A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811168225.2 2018-10-08
CN201811168225.2A CN109143707A (zh) 2018-10-08 2018-10-08 一种导电层绝缘方法、导电层绝缘结构及显示装置

Publications (1)

Publication Number Publication Date
WO2020073456A1 true WO2020073456A1 (zh) 2020-04-16

Family

ID=64810430

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/118135 WO2020073456A1 (zh) 2018-10-08 2018-11-29 导电层绝缘方法、导电层绝缘结构及显示装置

Country Status (2)

Country Link
CN (1) CN109143707A (zh)
WO (1) WO2020073456A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553269A (zh) * 2003-12-03 2004-12-08 吉林北方彩晶数码电子有限公司 薄膜晶体管液晶显示器制造方法
CN102623434A (zh) * 2011-01-31 2012-08-01 北京泰龙电子技术有限公司 一种扩散阻挡层及其制备方法
CN103456738A (zh) * 2012-06-05 2013-12-18 群康科技(深圳)有限公司 薄膜晶体管基板以及显示器
JP2014138167A (ja) * 2013-01-18 2014-07-28 Sumitomo Electric Ind Ltd Ｍｅｓ構造トランジスタを作製する方法、ｍｅｓ構造トランジスタ
CN104064566A (zh) * 2013-03-19 2014-09-24 株式会社东芝 显示器件、薄膜晶体管、显示器件的制造方法、以及薄膜晶体管的制造方法
CN105097839A (zh) * 2015-07-20 2015-11-25 京东方科技集团股份有限公司 一种绝缘层、阵列基板及其制作方法、显示装置
CN106920836A (zh) * 2017-03-29 2017-07-04 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104064601B (zh) * 2014-06-30 2017-12-26 上海天马微电子有限公司 Tft、tft阵列基板及其制造方法、显示面板、显示装置
CN106292103A (zh) * 2016-08-22 2017-01-04 厦门天马微电子有限公司 一种阵列基板及其制作方法、显示面板、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553269A (zh) * 2003-12-03 2004-12-08 吉林北方彩晶数码电子有限公司 薄膜晶体管液晶显示器制造方法
CN102623434A (zh) * 2011-01-31 2012-08-01 北京泰龙电子技术有限公司 一种扩散阻挡层及其制备方法
CN103456738A (zh) * 2012-06-05 2013-12-18 群康科技(深圳)有限公司 薄膜晶体管基板以及显示器
JP2014138167A (ja) * 2013-01-18 2014-07-28 Sumitomo Electric Ind Ltd Ｍｅｓ構造トランジスタを作製する方法、ｍｅｓ構造トランジスタ
CN104064566A (zh) * 2013-03-19 2014-09-24 株式会社东芝 显示器件、薄膜晶体管、显示器件的制造方法、以及薄膜晶体管的制造方法
CN105097839A (zh) * 2015-07-20 2015-11-25 京东方科技集团股份有限公司 一种绝缘层、阵列基板及其制作方法、显示装置
CN106920836A (zh) * 2017-03-29 2017-07-04 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置

Also Published As

Publication number Publication date
CN109143707A (zh) 2019-01-04

Similar Documents

Publication Publication Date Title
JP6129312B2 (ja) アレイ基板の製造方法、アレイ基板及び表示装置
US6855957B1 (en) Semiconductor device and manufacturing method thereof
US9893206B2 (en) Thin film transistor, array substrate, their manufacturing methods, and display device
CN103646966A (zh) 一种薄膜晶体管、阵列基板及其制备方法、显示装置
CN106019751B (zh) 阵列基板及其制造方法、显示装置
CN107968097B (zh) 一种显示设备、显示基板及其制作方法
JP2015525000A (ja) 薄膜トランジスタ、アレイ基板及びその製作方法、ディスプレイ
WO2021022594A1 (zh) 阵列基板、显示面板及阵列基板的制作方法
TWI532154B (zh) 顯示面板及顯示裝置
CN110148601B (zh) 一种阵列基板、其制作方法及显示装置
CN103413812A (zh) 阵列基板及其制备方法、显示装置
WO2014187113A1 (zh) 阵列基板及制备方法、显示装置
CN105655359A (zh) Tft基板的制作方法
JP2008122923A (ja) 薄膜トランジスタアレイ基板およびその製造方法
WO2016177213A1 (zh) 阵列基板及其制造方法、显示装置
WO2015192595A1 (zh) 阵列基板及其制备方法、显示装置
WO2017140058A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
WO2020048291A1 (zh) 布线结构、显示基板、显示装置以及制作显示基板的方法
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
CN104133313A (zh) 阵列基板及其制备方法、液晶显示装置
EP2819155B1 (en) Thin film transistor array substrate and producing method thereof
WO2015143818A1 (zh) 阵列基板及其制造方法、显示装置
CN103545252A (zh) 阵列基板及其制备方法、液晶显示装置
JPS615577A (ja) 薄膜半導体装置
CN105140291A (zh) 薄膜晶体管及其制作方法、阵列基板以及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18936823

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 06.08.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18936823

Country of ref document: EP

Kind code of ref document: A1