WO2020073370A1 - 一种影像传感芯片的嵌入式封装结构和制作方法 - Google Patents

一种影像传感芯片的嵌入式封装结构和制作方法 Download PDF

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Publication number
WO2020073370A1
WO2020073370A1 PCT/CN2018/112617 CN2018112617W WO2020073370A1 WO 2020073370 A1 WO2020073370 A1 WO 2020073370A1 CN 2018112617 W CN2018112617 W CN 2018112617W WO 2020073370 A1 WO2020073370 A1 WO 2020073370A1
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Prior art keywords
substrate
image sensor
opening
sensor chip
packaging structure
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English (en)
French (fr)
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秦飞
赵帅
张理想
陈沛
安彤
代岩伟
肖智轶
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Beijing University of Technology
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Beijing University of Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/804—Containers or encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • the invention relates to a semiconductor chip packaging structure and manufacturing method, in particular to an image sensor chip packaging structure and manufacturing method, which belongs to the field of semiconductor packaging.
  • the image sensor chip is a semiconductor module, which is a device that converts an optical image into an electronic signal.
  • the electronic signal can be used for further processing or digitization for storage, or for transferring the image to a display device for display. It is widely used in digital cameras, mobile phones and other electronic optical devices.
  • Image sensor chips are mainly divided into two types: charge coupled device (CCD) and CMOS image sensor (CIS).
  • CCD image sensor is superior to the CMOS image sensor in terms of image quality and noise, the CMOS sensor can be manufactured using traditional semiconductor production technology, and the production cost is low.
  • CMOS image sensors have the advantages of low power consumption, low parasitic delay of capacitance and inductance.
  • the current impact sensor chip structure generally makes a cofferdam (polymer material) on the glass cover plate, and then bonds the functional surface of the chip with the periphery of the cofferdam through permanent bonding glue. At the same time, a certain distance needs to be left between the photosensitive region of the chip and the glass cover, which requires that the cofferdam must have a certain thickness.
  • the cofferdam due to the low strength and rigidity of the cofferdam currently used, and the poor thickness uniformity, it is not enough to ensure that there is sufficient distance between the photosensitive area of the chip and the glass cover, generally only 30-50 ⁇ m, and it will cause the chip and glass Problems such as poor flatness at the joint of the cover and uneven glass surface.
  • the interface between the cofferdam and other materials is prone to cracks, delamination and other problems caused by thermal stress, resulting in product failure.
  • the cofferdam contacts the functional surface of the chip, the probability of contamination in the functional area is increased, such as glue overflow.
  • the image sensor chip I / O ports are bound to increase. The increase in I / O port will lead to insufficient space for the ball, which is also a problem in the existing image sensor chip packaging structure.
  • the present invention proposes an embedded packaging structure and manufacturing method of an image sensor chip.
  • the image sensor chip is embedded in a substrate with a groove in a function-oriented manner, and the non-functional surface of the chip and the substrate are concave
  • the bottom of the groove is bonded, and then the glass cover plate is bonded to the substrate, and then the second surface of the substrate and the non-functional surface of the image sensor chip are provided with an opening exposing the pad of the functional surface of the image sensor chip, and formed in the opening to extend to
  • the conductive circuit on the back of the substrate electrically leads the pad to the back of the substrate.
  • the packaging is completed and cut to form an image sensor chip packaging structure.
  • an embedded packaging structure of an image sensor chip which includes at least a substrate, an image sensor chip, and a glass cover plate.
  • the substrate includes a first surface and a second surface opposite thereto. At least one groove extending toward the second surface is formed on the first surface of the substrate.
  • the image sensor chip includes a functional surface and a non-functional surface opposite thereto, and the functional surface includes a plurality of bonding pads and functional areas.
  • the non-functional surface is covered with a first adhesive layer.
  • the non-functional surface of the image sensor chip is bonded to the bottom surface of the groove through a first adhesive layer, and the first surface of the substrate is higher than the functional surface of the image sensor chip by 20 ⁇ m or more.
  • the size of the bottom surface of the groove is larger than the size of the non-functional surface that affects the sensor chip, so that there is a gap between the inner wall of the groove and the side surface of the image sensor chip.
  • the surface of the glass cover is bonded to the first surface of the substrate through a second bonding layer.
  • the second surface of the substrate has a second opening.
  • the first adhesive layer has a third opening, and a non-functional surface of the image sensor chip is provided with a fourth opening exposing each pad corresponding to the position of the pad.
  • the second opening of the second surface of the substrate and the third opening of the first adhesive layer correspond to the position of the fourth opening of the non-functional surface of the image sensor chip.
  • the second opening is connected to the third opening and the fourth opening to form a through hole.
  • the inner wall of the through hole and the second surface of the substrate are sequentially provided with a passivation layer, a metal wiring layer, a solder resist layer, and conductive bumps.
  • the embedded image sensor chip packaging structure is characterized in that the substrate is one of a silicon substrate, a glass substrate, a quartz substrate, and a ceramic substrate.
  • the embedded image sensor chip packaging structure is characterized in that the first surface of the substrate is 20-50 ⁇ m higher than the functional surface of the image sensor chip.
  • the embedded image sensor chip packaging structure is characterized in that there is a gap between the inner wall of the groove and the side of the image sensor chip, and the gap distance is 10- 20 ⁇ m.
  • the embedded image sensor chip packaging structure is characterized in that the packaging structure embeds an image chip on a substrate, or embeds more than two image chips of different structures at the same time On a substrate, a dual camera or array image sensor chip packaging structure is formed.
  • the embedded packaging structure of the image sensor chip is characterized in that the area surrounded by the conductive bumps and the metal wiring layer is not less than the functional surface or non-function of the image sensor chip The area of the surface.
  • step 1 a substrate is provided, the substrate including a first surface and a second surface opposite thereto.
  • Step 2 Coat a layer of photoresist on the first surface of the substrate to form a temporary adhesive layer
  • Step 3 Perform photolithography and development processes on the temporary adhesive layer to form at least one first opening
  • Step 4 Form a groove on the first surface of the substrate corresponding to the first opening, and remove the temporary adhesive layer;
  • Step 5 Provide at least one image sensor chip to be packaged.
  • the image sensor chip includes a functional surface and a non-functional surface opposite thereto, and the functional surface includes a plurality of bonding pads and functional areas.
  • Step 6 Coat a first adhesive layer on the image sensor chip to be packaged, and place at least one chip to be packaged in the groove through the patching process so that the first surface of the substrate is higher than A functional surface of the image sensor chip, there is a gap between the side surface of the image sensor chip and the side wall of the groove;
  • Step 7 providing a transparent glass cover plate, and bonding the glass cover plate and the first surface of the substrate with a second adhesive layer;
  • Step 8 Thin the second surface of the substrate
  • Step 9 forming a second opening in the second surface of the substrate
  • Step 10 forming a third opening and a fourth opening exposing each pad on the first adhesive layer and the non-functional surface of the image sensor chip, the second opening is formed with the third opening, and the fourth opening is formed Through hole
  • Step 11 forming a passivation layer on the inner wall of the through hole and the second surface of the substrate to expose each pad;
  • Step 12 forming a patterned metal wiring layer on the passivation layer
  • Step 13 forming a solder resist layer on the metal wiring layer, and forming a pad opening on the solder resist layer;
  • Step 14 forming conductive bumps on the pad openings
  • Step 15 The substrate and the glass cover are cut to form a single image sensor chip package.
  • the manufacturing method of the embedded packaging structure of the image sensor chip is characterized in that the manufacturing method of the groove of the substrate is dry etching or wet etching.
  • the manufacturing method of the embedded packaging structure of the image sensor chip is characterized in that, after step 6, a glass cover is bonded to the first surface of the substrate.
  • the manufacturing method of the embedded packaging structure of the image sensor chip is characterized in that the manufacturing method of the second opening is one of cutting, dry etching and wet etching Or a combination of several types, the manufacturing method of the third opening and the fourth opening is one or a combination of dry etching and wet etching.
  • the invention provides an embedded packaging structure and manufacturing method of an image sensor chip.
  • the invention does not require a polymer cofferdam, which reduces the reliability problem of excessive thermal stress due to a large thermal expansion coefficient of the polymer.
  • the glass cover is bonded to the substrate, and the image sensor chip is embedded in the cavity formed by the glass cover and the substrate. There is a gap between the inner wall of the cavity and the side wall of the image sensor chip to prevent the overflow of glue from contaminating the photosensitive area.
  • the electric signal is led to the second surface of the substrate through the through hole, which increases the space of the ball.
  • FIG. 1 is a schematic diagram of an image sensor chip embedded package structure according to an embodiment of the present invention.
  • step 1 is a schematic cross-sectional view of the package structure after step 1.
  • step 2 is a schematic cross-sectional view of the packaging structure after step 2.
  • step 3 is a schematic cross-sectional view of the package structure after step 3.
  • 5 is a schematic cross-sectional view of the package structure after step 4.
  • FIG. 6 is a schematic cross-sectional view of the package structure after step 5.
  • FIG. 7 is a schematic cross-sectional view of the packaging structure after step 6.
  • step 9 is a schematic cross-sectional view of the packaging structure after step 8.
  • FIG. 10 is a schematic cross-sectional view of the package structure after step 9.
  • 11 is a schematic cross-sectional view of the package structure after step 10.
  • step 12 is a schematic cross-sectional view of the packaging structure after step 11.
  • step 12 is a schematic cross-sectional view of the package structure after step 12.
  • step 14 is a schematic cross-sectional view of the package structure after step 13.
  • step 15 is a schematic cross-sectional view of the package structure after step 14.
  • 16 is a schematic cross-sectional view of the package structure after step 15.
  • the present invention discloses an embedded packaging structure of an image sensor chip, which includes at least a substrate (1), an image sensor chip (3), and a glass cover (5).
  • the substrate contains a first surface (101) and a second surface (102) opposite thereto.
  • the first surface (101) of the substrate is formed with at least one groove 103 extending toward the second surface (102).
  • the image sensor chip (3) includes a functional surface (301) and a non-functional surface (302) opposite thereto, and the functional surface includes a plurality of bonding pads (303) and functional areas (304).
  • the non-functional surface (302) is covered with a first adhesive layer (4).
  • the non-functional surface (302) of the image sensor chip (3) is bonded to the bottom surface of the groove (103) through the first adhesive layer (4), and the first surface (1) of the substrate (1) 101) 20 ⁇ m or more above the functional surface (301) of the image sensor chip (3).
  • the size of the bottom surface of the groove (103) is larger than the size of the non-functional surface (302) affecting the sensor chip (3), so that the inner wall (104) of the groove (103) and the image sensor There is a gap between the side surfaces (305) of the chip (3).
  • the surface of the glass cover (5) is bonded to the first surface (101) of the substrate (1) through a second adhesive layer (6).
  • the second surface (102) of the substrate (1) has a second opening (105).
  • the first adhesive layer (4) has a third opening (401), and the non-functional surface (302) of the image sensor chip (3) corresponds to the position of the solder pad (303) is provided with a third Four openings (306).
  • the second opening (105) of the second surface (102) of the substrate (1) and the third opening (401) of the first adhesive layer (4) correspond to the non-functional surface of the image sensor chip (3) (302) The position of the fourth opening (306).
  • the second opening (105) is connected to the third opening (401) and the fourth opening (306) to form a through hole.
  • the inner wall of the through hole and the second surface (102) of the substrate (1) are sequentially provided with a passivation layer (7), a metal wiring layer (8), a solder resist layer (9), and conductive bumps (10).
  • the substrate (1) is one of a silicon substrate, a glass substrate, a quartz substrate, and a ceramic substrate.
  • the first surface (101) of the substrate (1) is 20-50 ⁇ m higher than the functional surface (301) of the image sensor chip (3).
  • the gap distance is 10-20 ⁇ m.
  • the packaging structure embeds an image chip on a substrate, or embeds more than two image chips of different structures on a substrate at the same time to form a dual-camera or array image sensor chip package structure.
  • the area surrounded by the conductive bump (10) and the metal wiring layer (8) is not less than the area of the functional surface (303) or non-functional surface (304) of the image sensor chip (3).
  • FIGS. 2 to 16 are schematic diagrams of a method for manufacturing an image sensor chip according to an embodiment of the present invention.
  • a substrate (1) is provided.
  • the substrate includes a first surface (101) and a second surface (102) opposite thereto.
  • Step 2 as shown in FIG. 3, coating a layer of photoresist on the first surface (101) of the substrate (1) to form a temporary adhesive layer (2);
  • Step 3 as shown in FIG. 4, performing photolithography and development processes on the temporary adhesive layer (2) to form at least one first opening (201);
  • Step 4 as shown in FIG. 5, at the position of the first surface (101) of the substrate (1) corresponding to the first opening (201), a groove (103) is formed, and the temporary adhesive layer (2) is removed;
  • Step 5 at least one image sensor chip (3) to be packaged is provided.
  • the image sensor chip (3) includes a functional surface (301) and a non-functional surface (302) opposite thereto.
  • the functional surface (302) contains several pads (303) and functional areas (304).
  • Step 6 as shown in FIG. 7, coat the first adhesive layer (4) on the image sensor chip (3) to be packaged, and place at least one in the groove (103) through the patching process
  • the chip to be packaged makes the first surface (101) of the substrate (1) higher than the functional surface (301) of the image sensor chip, the side surface (305) of the image sensor chip and the groove There is a gap between the side walls (104) of (103);
  • Step 7 as shown in FIG. 8, providing a transparent glass cover plate (5), and bonding the glass cover plate and the first surface (101) of the substrate (1) with a second adhesive layer (6);
  • Step 8 as shown in FIG. 9, thin the second surface (102) of the substrate (1);
  • Step 9 as shown in FIG. 10, forming a second opening (105) on the second surface (103) of the substrate (1);
  • Step 10 as shown in FIG. 11, forming a third opening (302) exposing each pad (303) in the first adhesive layer (4) and the non-functional surface (302) of the image sensor chip (3) 401) and a fourth opening (306), the second opening (105) and the third opening (401), the fourth opening (306) form a through hole;
  • Step 11 as shown in FIG. 12, forming a passivation layer (7) on the inner wall of the through hole and the second surface (102) of the substrate to expose each pad (303)
  • Step 12 as shown in FIG. 13, forming a patterned metal wiring layer (8) on the passivation layer (7);
  • Step 13 as shown in FIG. 14, forming a solder resist layer (9) on the metal wiring layer (8), and forming a pad opening (901) on the solder resist layer;
  • Step 14 as shown in FIG. 15, forming conductive bumps (10) on the pad openings (901);
  • Step 15 as shown in FIG. 16, the substrate (1) and the glass cover (5) are cut to form a single image sensor chip package.
  • the manufacturing method of the groove (103) of the substrate (1) is dry etching or wet etching.
  • a glass cover (5) and the first surface (101) of the substrate (1) are bonded.
  • the manufacturing method of the second opening (105) is one or a combination of cutting, dry etching and wet etching, and the third opening (401) and the fourth opening (306) ) Is produced by one or a combination of dry etching and wet etching.

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Abstract

一种影像传感芯片（3）的嵌入式封装结构和制作方法，通过将影像传感芯片（3）以功能面（301）向上的方式嵌入带有的凹槽（103）的基板（1）中，芯片非功能面（302）和基板（1）的凹槽（103）的底部键合，再将玻璃盖板（5）与基板（1）键合，然后在基板（1）第二表面（102）与影像传感芯片（3）非功能面（302）设置暴露影像传感芯片（3）功能面（301）焊垫（303）的开口，并在开口内形成延伸到基板（1）背面的导电线路，将焊垫（303）电性引到基板（1）背面。该封装结构不需要聚合物围堰，缓解了结构的热失配，可靠性高，且减小了功能区污染的概率，提供了更大的布球空间。

Description

一种影像传感芯片的嵌入式封装结构和制作方法 技术领域
本发明涉及一种半导体芯片封装结构和制作方法，尤其涉及一种影像传感芯片封装结构和制作方法，属于半导体封装领域。
背景技术
影像传感芯片是一种半导体模块，是一种将光学影像转换成为电子信号的设备，电子信号可以用来进一步处理或数字化后进行存储，或用于将影像传递至显示装置进行显示等。它被广泛应用于数码相机，手机以及其他电子光学设备中。影像传感芯片主要分为电荷耦合器件(CCD)和CMOS影像传感器(CIS)两类。虽然CCD影像传感器在影像质量以及噪声等方面优于CMOS影像传感器，但是CMOS传感器可用传统的半导体生产技术制造，生产成本较低。同时由于所用的元件数相对较少以及信号传输距离短，CMOS影像传感器具备功耗低、电容、电感的寄生延迟低等优点。
随着各种先进封装技术的出现，影像传感芯片的封装形式也向着更轻、更薄、更便携的方向发展，同时也要求更高的性能、更快的速度以及更低的成本。
目前的影响传感芯片结构一般在玻璃盖板上制作围堰(高分子材料)，然后通过永久键合胶将芯片功能面与围堰的四周粘接在一起。同时需要在芯片感光区与玻璃盖板之间留有一定的距离，这就要求围堰必须具有一定的厚度。然而由于目前采用的围堰强度和刚度较小，且厚度均一性较差，不足以保证芯片感光区与玻璃盖板之间有足够的距离，一般仅有30～50μm，并且会造成芯片与玻璃盖板接合处平整度差和玻璃表面不平整等问题。而且，由于围堰材料与其他材料的热膨胀系数差异较大，使得围堰与其他材料的界面处容易发生由热应力引起的裂纹、分层等问题，从而导致产品失效。此外，由于围堰接触芯片功能面，就增大了功能区污染的概率，比如发生溢胶。随着对影像传感芯片的高性能需求的增大，影像传感芯片I/O口势必会增加。I/O口的增大将导致布球空间的不足，这也是现有的影像传感芯片封装结 构所存在的一个问题。
发明内容
为了改善上述问题，本发明提出一种影像传感芯片的嵌入式封装结构和制作方法，将影像传感芯片以功能面向上的方式嵌入带有凹槽的基板中，芯片非功能面和基板凹槽的底部键合，再将玻璃盖板与基板键合，然后在基板第二表面与影像传感芯片非功能面设置暴露影像传感芯片功能面焊垫的开口，并在开口内形成延伸到基板背面的导电线路，将焊垫电性引到基板背面。封装完毕切割形成影像传感芯片封装结构。
本发明的技术方案是这样实现的：
提供一种影像传感芯片的嵌入式封装结构，它包括至少一基板，一影像传感芯片，一玻璃盖板。所述基板含有第一表面和与其相对的第二表面。所述基板的第一表面上形成有至少一向所述第二表面延伸的凹槽。所述影像传感芯片含有功能面和与其相对的非功能面，所述功能面含有若干焊垫和功能区。所述非功能面覆盖有第一粘结层。所述影像传感芯片的非功能面)通过第一粘结层与所述凹槽的底面粘结，且所述基板的第一表面高于所述影像传感芯片的功能面20μm以上。所述凹槽的底面的尺寸大于所述影响传感芯片的非功能面的尺寸，使得所述凹槽的内壁和所述影像传感芯片的侧面之间存在间隙。所述玻璃盖板的表面通过第二粘结层与所述基板的第一表面粘结。所述基板的第二表面具有第二开口。所述第一粘结层具有第三开口，所述影像传感芯片的非功能面对应焊垫的位置设有暴露各个焊垫的第四开口。所述基板的第二表面的第二开口和第一粘结层的第三开口对应所述影像传感芯片的非功能面的第四开口的位置。所述第二开口与第三开口，第四开口连接形成通孔。所述通孔内壁及基板的第二表面依次设置有钝化层，金属布线层，阻焊层及导电凸点。
作为本发明的进一步改进，所述的嵌入式影像传感芯片封装结构，其特征在于，所述基板是硅基板，玻璃基板，石英基板，陶瓷基板的一种。
作为本发明的进一步改进，所述的嵌入式影像传感芯片封装结构，其特征在于，所述基板的第一表面比所述影像传感芯片的功能面高20-50μm。
作为本发明的进一步改进，所述的嵌入式影像传感芯片封装结构，其特征在于，所述凹槽的内壁和所述影像传感芯片的侧面之间存在间隙，所述间隙距离在10-20μm。
作为本发明的进一步改进，所述的嵌入式影像传感芯片封装结构，其特征在于，所述封装结构将一个影像芯片嵌入到一个基板上，或者将两个以上的不同结构的影像芯片同时嵌入到一个基板上，形成双摄或者阵列影像传感芯片封装结构。
作为本发明的进一步改进，所述影像传感芯片的嵌入式封装结构，其特征在于，所述导电凸点和金属布线层所围的面积不小于所述影像传感芯片的功能面或非功能面的面积。
提供一种影像传感芯片的嵌入式封装结构的制作方法，包括如下步骤：
步骤1，提供一基板，所述基板含有第一表面和与其相对的第二表面。
步骤2，在所述基板的第一表面涂布一层光刻胶，形成临时胶层；
步骤3，在所述临时胶层上进行光刻，显影工艺，形成至少一个第一开口；
步骤4，在所述基板的第一表面对应第一开口的位置，形成凹槽，并去除临时胶层；
步骤5，提供至少一待封装的影像传感芯片，所述影像传感芯片含有功能面和与其相对的非功能面，所述功能面含有若干焊垫和功能区。
步骤6，在待封装的影像传感芯片上涂布第一粘结层，并通过贴片工艺在所述凹槽内放置至少一颗待封装的芯片，使所述基板的第一表面高于所述影像传感芯片的功能面，所述影像传感芯片的侧面与所述凹槽的侧壁之间具有间隙；
步骤7，提供一透明玻璃盖板，并将玻璃盖板和所述基板的第一表面用第二粘结层粘结；
步骤8，对所述基板的第二表面减薄；
步骤9，于所述基板的第二表面形成第二开口；
步骤10，于所述第一粘结层和所述影像传感芯片的非功能面形成暴露各个焊垫的第三开口和第四开口，所述第二开口与第三开口，第四开口形成通孔；
步骤11，于所述通孔内壁和所述基板的第二表面形成暴露各个焊垫的钝化层；
步骤12，于所述钝化层上形成图形化的金属布线层；
步骤13，于所述金属布线层上形成阻焊层，所述阻焊层上形成有焊盘开口；
步骤14，于所述焊盘开口上形成导电凸点；
步骤15，将基板和玻璃盖板切割，形成单颗影像传感芯片封装体。
作为本发明的进一步改进，所述的影像传感芯片的嵌入式封装结构的制作方法，其特征在于，所述基板的凹槽的制作方法为干法刻蚀或湿法刻蚀。
作为本发明的进一步改进，所述的影像传感芯片的嵌入式封装结构的制作方法，其特征在于，在步骤6完成后将一玻璃盖板和基板的第一表面粘结。
作为本发明的进一步改进，所述的影像传感芯片的嵌入式封装结构的制作方法，其特征在于，所述第二开口的制作方法为切割，干法刻蚀和湿法刻蚀中的一种或几种的组合，所述第三开口和第四开口的制作方法为干法刻蚀和湿法刻蚀中的一种或两种的组合。
本发明的有益效果是：
本发明提供了一种影像传感芯片的嵌入式封装结构和制作方法。本发明不需要聚合物围堰，降低了因聚合物热膨胀系数较大产生的热应力过大的可靠性问题。玻璃盖板与基板粘结，影像传感芯片嵌入玻璃盖板与基板围成的空腔里。空腔的内壁与影像传感芯片的侧壁存在 间隙，避免了溢胶污染感光区。电信号由通孔引到基板的第二表面，增大了布球空间。
附图说明
图1为根据本发明实施例绘制的影像传感芯片嵌入式封装结构示意图。
图2为步骤1后的封装结构剖面示意图。
图3为步骤2后的封装结构剖面示意图。
图4为步骤3后的封装结构剖面示意图。
图5为步骤4后的封装结构剖面示意图。
图6为步骤5后的封装结构剖面示意图。
图7为步骤6后的封装结构剖面示意图。
图8为步骤7后的封装结构剖面示意图。
图9为步骤8后的封装结构剖面示意图。
图10为步骤9后的封装结构剖面示意图。
图11为步骤10后的封装结构剖面示意图。
图12为步骤11后的封装结构剖面示意图。
图13为步骤12后的封装结构剖面示意图。
图14为步骤13后的封装结构剖面示意图。
图15为步骤14后的封装结构剖面示意图。
图16为步骤15后的封装结构剖面示意图。
结合附图，作以下说明：
1-基板                 101-基板的第一表面
102-基板的第二表面     103-凹槽
104-凹槽内壁           105-第二开口
2-临时胶层             201-第一开口
3-影像传感芯片            301-影像传感芯片的功能面
302-影像传感芯片的非功能面303-焊垫
304-功能区             305-影像传感芯片的侧面
306-第四开口           4-粘结层
401-第三开口           5-玻璃盖板
6-粘结层               7-钝化层
8-金属布线层           9-阻焊层
901-阻焊层焊盘开口            10-导电凸点
具体实施方式
为使本发明能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细说明。为方便说明，实施例附图的结构中各组成部分未按正常比例缩放，故不代表实施例中各结果的实际相对大小。
如图1所示，本发明公开了一种影像传感芯片的嵌入式封装结构，它包括至少一基板(1)，一影像传感芯片(3)，一玻璃盖板(5)。所述基板含有第一表面(101)和与其相对的第二表面(102)。所述基板的第一表面(101)上形成有至少一向所述第二表面(102)延伸的凹槽103。所述影像传感芯片(3)含有功能面(301)和与其相对的非功能面(302)，所述功能面含有若干焊垫(303)和功能区(304)。所述非功能面(302)覆盖有第一粘结层(4)。所述影像传感芯片(3)的非功能面(302)通过第一粘结层(4)与所述凹槽(103)的底面粘结，且所述基板(1)的第一表面(101)高于所述影像传感芯片(3)的功能面(301)20μm以上。所述凹槽(103)的底面的尺寸大于所述影响传感芯片(3)的非功能面(302)的尺寸，使得所述凹槽(103)的内壁(104)和所述影像传感芯片(3)的侧面(305)之间存在间隙。所述玻璃盖板(5)的表面通过第二粘结层(6)与所述基板(1)的第一表面(101)粘结。所述基板(1)的第二表面(102)具有第二开口(105)。所述第一粘结层(4)具有第三开口(401)，所述影像传感芯片(3)的非功能面(302)对应焊垫(303)的位置设有暴露各个焊垫的第四开口(306)。所述基板(1)的第二表面(102)的第二开口(105)和第一粘结层(4)的第三开口(401)对应所述影像传感芯片(3)的非功能面(302)的第四开口(306)的位置。所述第二开口(105)与第三开口(401)，第四开口(306)连接形成通孔。所述通孔内壁及基板(1)的第二表面(102)依次设置有钝化层(7)，金属布线层(8)，阻焊层(9)及导电凸点(10)。
优选地，所述基板(1)是硅基板，玻璃基板，石英基板，陶瓷 基板的一种。
优选地，所述基板(1)的第一表面(101)比所述影像传感芯片(3)的功能面(301)高20-50μm。
优选地，所述凹槽(103)的内壁(104)和所述影像传感芯片(3)的侧面(305)之间存在间隙，所述间隙距离在10-20μm。
可选地，所述封装结构将一个影像芯片嵌入到一个基板上，或者将两个以上的不同结构的影像芯片同时嵌入到一个基板上，形成双摄或者阵列影像传感芯片封装结构。
优选地，所述导电凸点(10)和金属布线层(8)所围的面积不小于所述影像传感芯片(3)的功能面(303)或非功能面(304)的面积。
以下结合图2-16分别对一种影像传感芯片的嵌入式封装结构的制作方法进行介绍。
图2～图16为根据本发明实施例绘制的影像传感芯片制作方法示意图。
步骤1，如图2所示，提供一基板(1)，所述基板含有第一表面(101)和与其相对的第二表面(102)。
步骤2，如图3所示，在所述基板(1)的第一表面(101)涂布一层光刻胶，形成临时胶层(2)；
步骤3，如图4所示，在所述临时胶层(2)上进行光刻，显影工艺，形成至少一个第一开口(201)；
步骤4，如图5所示，在所述基板(1)的第一表面(101)对应第一开口(201)的位置，形成凹槽(103)，并去除临时胶层(2)；
步骤5，如图6所示，提供至少一待封装的影像传感芯片(3)，所述影像传感芯片(3)含有功能面(301)和与其相对的非功能面(302)，所述功能面(302)含有若干焊垫(303)和功能区(304)。
步骤6，如图7所示，在待封装的影像传感芯片(3)上涂布第一粘结层(4)，并通过贴片工艺在所述凹槽(103)内放置至少一颗待封装的芯片，使所述基板(1)的第一表面(101)高于所述影像传 感芯片的功能面(301)，所述影像传感芯片的侧面(305)与所述凹槽(103)的侧壁(104)之间具有间隙；
步骤7，如图8所示，提供一透明玻璃盖板(5)，并将玻璃盖板和所述基板(1)的第一表面(101)用第二粘结层(6)粘结；
步骤8，如图9所示，对所述基板(1)的第二表面(102)减薄；
步骤9，如图10所示，于所述基板(1)的第二表面(103)形成第二开口(105)；
步骤10，如图11所示，于所述第一粘结层(4)和所述影像传感芯片(3)的非功能面(302)形成暴露各个焊垫(303)的第三开口(401)和第四开口(306)，所述第二开口(105)与第三开口(401)，第四开口(306)形成通孔；
步骤11，如图12所示，于所述通孔内壁和所述基板的第二表面(102)形成暴露各个焊垫(303)的钝化层(7)；
步骤12，如图13所示，于所述钝化层(7)上形成图形化的金属布线层(8)；
步骤13，如图14所示，于所述金属布线层(8)上形成阻焊层(9)，所述阻焊层上形成有焊盘开口(901)；
步骤14，如图15所示，于所述焊盘开口(901)上形成导电凸点(10)；
步骤15，如图16所示，将基板(1)和玻璃盖板(5)切割，形成单颗影像传感芯片封装体。
优选的，所述基板(1)的凹槽(103)的制作方法为干法刻蚀或湿法刻蚀。
优选地，在步骤(6)完成后将一玻璃盖板(5)和基板(1)的第一表面(101)粘结。
优选地，所述第二开口(105)的制作方法为切割，干法刻蚀和湿法刻蚀中的一种或几种的组合，所述第三开口(401)和第四开口(306)的制作方法为干法刻蚀和湿法刻蚀中的一种或两种的组合。
以上实施例是参照附图，对本发明的优选实施例进行详细说明。本领域的技术人员通过对上述实施例进行各种形式上的修改或变更，但不背离本发明的实质的情况下，都落在本发明的保护范围之内。

Claims (9)

  1. 一种影像传感芯片的嵌入式封装结构，其特征在于，包括至少一基板(1)，一影像传感芯片(3)，一玻璃盖板(5)；所述基板含有第一表面(101)和与其相对的第二表面(102)；所述基板的第一表面(101)上形成有至少一向所述第二表面(102)延伸的凹槽(103)；所述影像传感芯片(3)含有功能面(301)和与其相对的非功能面(302)，所述功能面含有若干焊垫(303)和功能区(304)；所述非功能面(302)覆盖有第一粘结层(4)；所述影像传感芯片(3)的非功能面(302)通过第一粘结层(4)与所述凹槽(103)的底面粘结，且所述基板(1)的第一表面(101)高于所述影像传感芯片(3)的功能面(301)20μm以上；所述凹槽(103)的底面的尺寸大于所述影响传感芯片(3)的非功能面(302)的尺寸，使得所述凹槽(103)的内壁(104)和所述影像传感芯片(3)的侧面(305)之间存在间隙；所述玻璃盖板(5)的表面通过第二粘结层(6)与所述基板(1)的第一表面(101)粘结；所述基板(1)的第二表面(102)具有第二开口(105)；所述第一粘结层(4)具有第三开口(401)，所述影像传感芯片(3)的非功能面(302)对应焊垫(303)的位置设有暴露各个焊垫的第四开口(306)；所述基板(1)的第二表面(102)的第二开口(105)和第一粘结层(4)的第三开口(401)对应所述影像传感芯片(3)的非功能面(302)的第四开口(306)的位置；所述第二开口(105)与第三开口(401)，第四开口(306)连接形成通孔；所述通孔内壁及基板(1)的第二表面(102)依次设置有钝化层(7)，金属布线层(8)，阻焊层(9)及导电凸点(10)。
  2. 根据权利要求1所述的影像芯片的封装结构，其特征在于，所述基板(1)是硅基板，玻璃基板，石英基板，陶瓷基板的一种。
  3. 根据权利要求1所述的影像芯片的封装结构，其特征在于，所述基板(1)的第一表面(101)比所述影像传感芯片(3)的功能面(301)高20-50μm。
  4. 根据权利要求1所述的影像芯片的封装结构，其特征在于，所述凹槽(103)的内壁(104)和所述影像传感芯片(3)的侧面(305)之间存在的间隙在10-20μm。
  5. 根据权利要求1所述的影像芯片的封装结构，其特征在于， 所述封装结构将一个影像芯片嵌入到一个基板上，或者将两个以上的不同结构的影像芯片同时嵌入到一个基板上，形成双摄或者阵列影像传感芯片封装结构。
  6. 根据权利要求1所述的影像芯片的封装结构，其特征在于，所述导电凸点(10)和金属布线层(8)所围的面积不小于所述影像传感芯片(3)的功能面(303)或非功能面(304)的面积。
  7. 一种影像传感芯片的嵌入式封装结构的制作方法，其特征在于，包括如下步骤：
    步骤1，提供一基板(1)，所述基板含有第一表面(101)和与其相对的第二表面(102)；
    步骤2，在所述基板(1)的第一表面(101)涂布一层光刻胶，形成临时胶层(2)；
    步骤3，在所述临时胶层(2)上进行光刻，显影工艺，形成至少一个第一开口(201)；
    步骤4，在所述基板(1)的第一表面(101)对应第一开口(201)的位置，形成凹槽(103)，并去除临时胶层(2)；
    步骤5，提供至少一待封装的影像传感芯片(3)，所述影像传感芯片(3)含有功能面(301)和与其相对的非功能面(302)，所述功能面(302)含有若干焊垫(303)和功能区(304)；
    步骤6，在待封装的影像传感芯片(3)上涂布第一粘结层(4)，并通过贴片工艺在所述凹槽(103)内放置至少一颗待封装的芯片，使所述基板(1)的第一表面(101)高于所述影像传感芯片的功能面(301)，所述影像传感芯片的侧面(305)与所述凹槽(103)的侧壁(104)之间具有间隙；
    步骤7，提供一透明玻璃盖板(5)，并将玻璃盖板和所述基板(1)的第一表面(101)用第二粘结层(6)粘结；
    步骤8，对所述基板(1)的第二表面(102)减薄；
    步骤9，于所述基板(1)的第二表面(103)形成第二开口(105)；
    步骤10，于所述第一粘结层(4)和所述影像传感芯片(3)的非功能面(302)形成暴露各个焊垫(303)的第三开口(401)和第 四开口(306)，所述第二开口(105)与第三开口(401)，第四开口(306)形成通孔；
    步骤11，于所述通孔内壁和所述基板的第二表面(102)形成暴露各个焊垫(303)的钝化层(7)；
    步骤12，于所述钝化层(7)上形成图形化的金属布线层(8)；
    步骤13，于所述金属布线层(8)上形成阻焊层(9)，所述阻焊层上形成有焊盘开口(901)；
    步骤14，于所述焊盘开口(901)上形成导电凸点(10)；
    步骤15，将基板(1)和玻璃盖板(5)切割，形成单颗影像传感芯片封装体。
  8. 根据权利要求7所述的影像芯片封装结构的制作方法，其特征在于，所述基板(1)的凹槽(103)的制作方法为干法刻蚀或湿法刻蚀。
  9. 根据权利要求7所述的影像芯片封装结构的制作方法，其特征在于，所述第二开口(105)的制作方法为切割，干法刻蚀和湿法刻蚀中的一种或几种的组合，所述第三开口(401)和第四开口(306)的制作方法为干法刻蚀和湿法刻蚀中的一种或两种的组合。
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